commit ae88ae18fa1a120a9757432eaa296f3dd42204fd
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Mar 4 10:03:26 2020 +0100

    Bump BASE-VER to 8.4.1
    
    2020-03-04  Jakub Jelinek  <jakub@redhat.com>
    
            * BASE-VER: Set to 8.4.1.

diff --git a/gcc/BASE-VER b/gcc/BASE-VER
index a2f28f43be3..6da4de57dc6 100644
--- a/gcc/BASE-VER
+++ b/gcc/BASE-VER
@@ -1 +1 @@
-8.4.0
+8.4.1
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 142499c563c..6771ccc9019 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2020-03-04  Jakub Jelinek  <jakub@redhat.com>
+
+	* BASE-VER: Set to 8.4.1.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.

commit b8fc27379c134e2795717f26cc259b8e2028e96b
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Feb 27 09:38:12 2020 +0100

    maintainer-scripts: Speed up git clone in gcc_release
    
    When doing the 8.4-rc1, I've noticed (probably also because of the dying
    disk on sourceware) that git clone is extremely slow, and furthermore when
    all of us have some local snapshots, it is a waste of resources to download
    everything again.  Especially for the -f runs when we'll need to wait until
    git tag -s asks us for a gpg password interactively.
    
    The following patch adds an option through which one can point the script
    at a local gcc .git directory from which it can --dissociate --reference ...
    during cloning to speed it up.
    
    2020-02-27  Jakub Jelinek  <jakub@redhat.com>
    
            * gcc_release: Add support for -b local-git-repo argument.

diff --git a/maintainer-scripts/ChangeLog b/maintainer-scripts/ChangeLog
index 234aa502515..229b644a9d7 100644
--- a/maintainer-scripts/ChangeLog
+++ b/maintainer-scripts/ChangeLog
@@ -1,3 +1,7 @@
+2020-03-04  Jakub Jelinek  <jakub@redhat.com>
+
+	* gcc_release: Add support for -b local-git-repo argument.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/maintainer-scripts/gcc_release b/maintainer-scripts/gcc_release
index 8be870154f7..74cce1af18d 100755
--- a/maintainer-scripts/gcc_release
+++ b/maintainer-scripts/gcc_release
@@ -9,7 +9,7 @@
 # Contents:
 #   Script to create a GCC release.
 #
-# Copyright (c) 2001-2018 Free Software Foundation.
+# Copyright (c) 2001-2020 Free Software Foundation.
 #
 # This file is part of GCC.
 #
@@ -78,6 +78,7 @@ Options:
   -p previous-tarball  Location of a previous tarball (to generate diff files).
   -t tag               Tag to mark the release in git.
   -u username          Username for upload operations.
+  -b local-git-repo    Local git repository to speed up cloning.
 EOF
     exit 1
 }
@@ -103,8 +104,14 @@ build_sources() {
   changedir "${WORKING_DIRECTORY}"
 
   # Check out the sources.
-  ${GIT} clone -q -b "${GITBRANCH}" "${GITROOT}" "`basename ${SOURCE_DIRECTORY}`" || \
-      error "Could not check out release sources"
+  if [ -n "${GIT_REFERENCE}" ]; then
+    ${GIT} clone -q --dissociate --reference "${GIT_REFERENCE}" \
+		 -b "${GITBRANCH}" "${GITROOT}" "`basename ${SOURCE_DIRECTORY}`" || \
+        error "Could not check out release sources"
+  else
+    ${GIT} clone -q -b "${GITBRANCH}" "${GITROOT}" "`basename ${SOURCE_DIRECTORY}`" || \
+        error "Could not check out release sources"
+  fi
 
   # If this is a final release, make sure that the ChangeLogs
   # and version strings are updated.
@@ -567,6 +574,9 @@ TAG=""
 # The old tarballs from which to generate diffs.
 OLD_TARS=""
 
+# Local gcc git checkout to speed up git cloning.
+GIT_REFERENCE=""
+
 # The directory that will be used to construct the release.  The
 # release itself will be placed in a subdirectory of this directory.
 DESTINATION=${HOME}
@@ -613,7 +623,7 @@ TAR="${TAR:-tar}"
 ########################################################################
 
 # Parse the options.
-while getopts "d:fr:u:t:p:s:l" ARG; do
+while getopts "d:fr:u:t:p:s:lb:" ARG; do
     case $ARG in
     d)    DESTINATION="${OPTARG}";;
     r)    RELEASE="${OPTARG}";;
@@ -631,6 +641,7 @@ while getopts "d:fr:u:t:p:s:l" ARG; do
           if [ ! -f ${OPTARG} ]; then
 	    error "-p argument must name a tarball"
 	  fi;;
+    b)    GIT_REFERENCE="${OPTARG}";;
     \?)   usage;;
     esac
 done

commit f4e748747a6536dc49586c8202284bc2b7bf2c6c
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Mon Feb 10 07:58:45 2020 -0800

    i386: Properly pop restore token in signal frame
    
    Linux CET kernel places a restore token on shadow stack for signal
    handler to enhance security.  The restore token is 8 byte and aligned
    to 8 bytes.  It is usually transparent to user programs since kernel
    will pop the restore token when signal handler returns.  But when an
    exception is thrown from a signal handler, now we need to pop the
    restore token from shadow stack.  For x86-64, we just need to treat
    the signal frame as normal frame.  For i386, we need to search for
    the restore token to check if the original shadow stack is 8 byte
    aligned.  If the original shadow stack is 8 byte aligned, we just
    need to pop 2 slots, one restore token, from shadow stack.  Otherwise,
    we need to pop 3 slots, one restore token + 4 byte padding, from
    shadow stack.
    
    This patch also includes 2 tests, one has a restore token with 4 byte
    padding and one without.
    
    Tested on Linux/x86-64 CET machine with and without -m32.
    
    libgcc/
    
            Backport from mainline
            PR libgcc/85334
            * config/i386/shadow-stack-unwind.h (_Unwind_Frames_Increment):
            New.
    
    (cherry picked from commit bf6465d0461234ccd45ae34d5e2375a0bee0081d)

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index d0ac4295575..69f9f7ea863 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-03-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backport from mainline
+	2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR libgcc/85334
+	* config/i386/shadow-stack-unwind.h (_Unwind_Frames_Increment):
+	New.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/libgcc/config/i386/shadow-stack-unwind.h b/libgcc/config/i386/shadow-stack-unwind.h
index 40f48df2aec..c3ee8745cf6 100644
--- a/libgcc/config/i386/shadow-stack-unwind.h
+++ b/libgcc/config/i386/shadow-stack-unwind.h
@@ -49,3 +49,46 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 	}					\
     }						\
     while (0)
+
+/* Linux CET kernel places a restore token on shadow stack for signal
+   handler to enhance security.  The restore token is 8 byte and aligned
+   to 8 bytes.  It is usually transparent to user programs since kernel
+   will pop the restore token when signal handler returns.  But when an
+   exception is thrown from a signal handler, now we need to pop the
+   restore token from shadow stack.  For x86-64, we just need to treat
+   the signal frame as normal frame.  For i386, we need to search for
+   the restore token to check if the original shadow stack is 8 byte
+   aligned.  If the original shadow stack is 8 byte aligned, we just
+   need to pop 2 slots, one restore token, from shadow stack.  Otherwise,
+   we need to pop 3 slots, one restore token + 4 byte padding, from
+   shadow stack.  */
+#ifndef __x86_64__
+#undef _Unwind_Frames_Increment
+#define _Unwind_Frames_Increment(context, frames)	\
+  if (_Unwind_IsSignalFrame (context))			\
+    do							\
+      {							\
+	_Unwind_Word ssp, prev_ssp, token;		\
+	ssp = _get_ssp ();				\
+	if (ssp != 0)					\
+	  {						\
+	    /* Align shadow stack pointer to the next	\
+	       8 byte aligned boundary.  */		\
+	    ssp = (ssp + 4) & ~7;			\
+	    do						\
+	      {						\
+		/* Look for a restore token.  */	\
+		token = (*(_Unwind_Word *) (ssp - 8));	\
+		prev_ssp = token & ~7;			\
+		if (prev_ssp == ssp)			\
+		  break;				\
+		ssp += 8;				\
+	      }						\
+	    while (1);					\
+	    frames += (token & 0x4) ? 3 : 2;		\
+	  }						\
+      }							\
+    while (0);						\
+  else							\
+    frames++;
+#endif

commit 38296a44a0eae7c613647217858746e89c02438c
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Mon Mar 2 03:08:57 2020 -0800

    lto: Also copy .note.gnu.property section
    
    When generating the separate file with LTO debug sections, we should
    also copy .note.gnu.property section.
    
            PR lto/93966
            * simple-object.c (handle_lto_debug_sections): Also copy
            .note.gnu.property section.
    
    (cherry picked from commit 577350603a657590c4b54a4a966cb49497e2514c)

diff --git a/libiberty/ChangeLog b/libiberty/ChangeLog
index 227517e46c7..73e9717019c 100644
--- a/libiberty/ChangeLog
+++ b/libiberty/ChangeLog
@@ -1,3 +1,12 @@
+2020-03-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backport from master
+	2020-03-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR lto/93966
+	* simple-object.c (handle_lto_debug_sections): Also copy
+	.note.gnu.property section.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/libiberty/simple-object.c b/libiberty/simple-object.c
index d2465c6e13a..d08f9c6548c 100644
--- a/libiberty/simple-object.c
+++ b/libiberty/simple-object.c
@@ -288,6 +288,9 @@ handle_lto_debug_sections (const char *name)
   /* Copy over .note.GNU-stack section under the same name if present.  */
   else if (strcmp (name, ".note.GNU-stack") == 0)
     return strcpy (newname, name);
+  /* Copy over .note.gnu.property section under the same name if present.  */
+  else if (strcmp (name, ".note.gnu.property") == 0)
+    return strcpy (newname, name);
   /* Copy over .comment section under the same name if present.  Solaris
      ld uses them to relax its checking of ELF gABI access rules for
      COMDAT sections in objects produced by GCC.  */

commit 6352c50d06a8ca0157293ecb0ef1f8a6dc19148a
Author: Tobias Burnus <tobias@codesourcery.com>
Date:   Wed Mar 4 13:29:25 2020 +0100

    [Fortran] Disable front-end optimization for OpenACC atomic (PR93462)
    
            Backported from mainline
            2020-01-31  Tobias Burnus  <tobias@codesourcery.com>
    
            PR fortran/93462
            * frontend-passes.c (gfc_code_walker): For EXEC_OACC_ATOMIC, set
            in_omp_atomic to true prevent front-end optimization.
    
            PR fortran/93462
            * gfortran.dg/goacc/atomic-1.f90: New.

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index d3be7538ff7..d078dfb7533 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,12 @@
+2020-02-04  Tobias Burnus  <tobias@codesourcery.com>
+
+	Backported from mainline
+	2020-01-31  Tobias Burnus  <tobias@codesourcery.com>
+
+	PR fortran/93462
+	* frontend-passes.c (gfc_code_walker): For EXEC_OACC_ATOMIC, set
+	in_omp_atomic to true prevent front-end optimization.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/gcc/fortran/frontend-passes.c b/gcc/fortran/frontend-passes.c
index be0fd0f7e6c..e317c89ba5d 100644
--- a/gcc/fortran/frontend-passes.c
+++ b/gcc/fortran/frontend-passes.c
@@ -4766,6 +4766,7 @@ gfc_code_walker (gfc_code **c, walk_code_fn_t codefn, walk_expr_fn_t exprfn,
 	      WALK_SUBEXPR (co->ext.dt->extra_comma);
 	      break;
 
+	    case EXEC_OACC_ATOMIC:
 	    case EXEC_OMP_ATOMIC:
 	      in_omp_atomic = true;
 	      break;
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ab652ddc144..8a4be391de8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-02-04  Tobias Burnus  <tobias@codesourcery.com>
+
+	Backported from mainline
+	2020-01-31  Tobias Burnus  <tobias@codesourcery.com>
+
+	PR fortran/93462
+	* gfortran.dg/goacc/atomic-1.f90: New.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/gcc/testsuite/gfortran.dg/goacc/atomic-1.f90 b/gcc/testsuite/gfortran.dg/goacc/atomic-1.f90
new file mode 100644
index 00000000000..579f0494b78
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/goacc/atomic-1.f90
@@ -0,0 +1,17 @@
+! { dg-do compile }
+!
+! PR fortran/93462
+!
+! Contributed by G. Steinmetz
+!
+program p
+   integer :: n = 1
+   integer :: a
+!$acc atomic write
+   a = f(n) - f(n)
+contains
+   integer function f(x)
+      integer, intent(in) :: x
+      f = x
+   end
+end

commit a9e9ff7b8a4d10ccf54dd4a641dd55c1b1645e17
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Feb 27 10:45:30 2020 +0100

    gimplify: Don't optimize register const vars to static [PR93949]
    
    The following testcase is rejected, while it was accepted in 3.4 and earlier
    (before tree-ssa merge).
    The problem is that we decide to promote the const variable to TREE_STATIC,
    but TREE_STATIC DECL_REGISTER VAR_DECLs may only be the global register vars
    and so assemble_variable/make_decl_rtl diagnoses it.
    
    Either we do what the following patch does, where we could consider
    register as a hint the user doesn't want such optimization, because if
    something is forced static, it is not "register" anymore and register static
    is not valid in C either, or we could clear DECL_REGISTER instead, but would
    still need to punt at least on DECL_HARD_REGISTER cases.
    
    2020-02-27  Jakub Jelinek  <jakub@redhat.com>
    
            PR c/93949
            * gimplify.c (gimplify_init_constructor): Don't promote readonly
            DECL_REGISTER variables to TREE_STATIC.
    
            * gcc.c-torture/compile/pr93949.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6771ccc9019..22dcc34efec 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-02-27  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/93949
+	* gimplify.c (gimplify_init_constructor): Don't promote readonly
+	DECL_REGISTER variables to TREE_STATIC.
+
 2020-03-04  Jakub Jelinek  <jakub@redhat.com>
 
 	* BASE-VER: Set to 8.4.1.
diff --git a/gcc/gimplify.c b/gcc/gimplify.c
index cb5bdee2aac..a685dc87d7d 100644
--- a/gcc/gimplify.c
+++ b/gcc/gimplify.c
@@ -4814,6 +4814,7 @@ gimplify_init_constructor (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p,
 	    && num_nonzero_elements > 1
 	    && TREE_READONLY (object)
 	    && VAR_P (object)
+	    && !DECL_REGISTER (object)
 	    && (flag_merge_constants >= 2 || !TREE_ADDRESSABLE (object))
 	    /* For ctors that have many repeated nonzero elements
 	       represented through RANGE_EXPRs, prefer initializing
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8a4be391de8..b0c4d406fdf 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-27  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/93949
+	* gcc.c-torture/compile/pr93949.c: New test.
+
 2020-02-04  Tobias Burnus  <tobias@codesourcery.com>
 
 	Backported from mainline
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr93949.c b/gcc/testsuite/gcc.c-torture/compile/pr93949.c
new file mode 100644
index 00000000000..bbda0209802
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr93949.c
@@ -0,0 +1,7 @@
+/* PR c/93949 */
+
+void
+foo (void)
+{
+  register const double d[3] = { 0., 1., 2. };
+}

commit 7191ace5b8e96c6ed63ccdda25de978876c73ab1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Mar 5 00:17:29 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a75e50658cb..aa1008c6c0b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200304
+20200305

commit ce1281ffc193af8ef7c599bc84a91c320a9b18ed
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Mar 6 00:17:35 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index aa1008c6c0b..f54c682d2a0 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200305
+20200306

commit 932faa2ee1bf615c20e32cd8b703cc4490065f47
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Mar 7 00:17:29 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f54c682d2a0..94dc1073d95 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200306
+20200307

commit b4b9f03c3cc4d610681d6ded9fc91f11e75a7e20
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Mar 9 00:17:15 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 94dc1073d95..cfc79aab53c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200307
+20200309

commit 58ee464cbe58ad0c6006cfeddfd6e2ba36280918
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Mar 10 00:16:51 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index cfc79aab53c..966f032a1ba 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200309
+20200310

commit e6f7fb1872800656cdcf696fc4dc3e07547bd9fd
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Mar 11 00:16:49 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 966f032a1ba..6b5fa9106eb 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200310
+20200311

commit caba313a9a5bfd308f02afe3bdcbb9c267a875fa
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Mar 12 00:16:48 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6b5fa9106eb..e2b9f19d525 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200311
+20200312

commit 3d46f4875c6c50e8095294b6b700d6678a7e2f1e
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Fri Mar 6 10:04:51 2020 +0000

    arm: correct constraints on movsi_compare0 [PR91913]
    
    The peephole that detects a mov of one register to another followed by
    a comparison of the original register against zero is only used in Arm
    state; but the instruction that matches this is generic to all 32-bit
    compilation states.  That instruction lacks support for SP which is
    permitted in Arm state, but has restrictions in Thumb2 code.
    
    This patch fixes the problem by allowing SP when in ARM state for all
    registers; in Thumb state it allows SP only as a source when the
    register really is copied to another target.
    
    gcc/ChangeLog:
            PR target/91913
            Backport from master
            * config/arm/arm.md (movsi_compare0): Allow SP as a source register
            in Thumb state and also as a destination in Arm state.  Add T16
            variants.
    
    gcc/testsuite/ChangeLog:
            2020-02-10  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/91913
            Backport from master
            * gfortran.dg/pr91913.f90: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 22dcc34efec..9d9ad0e82e6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2020-03-12  Richard Earnshaw  <rearnsha@arm.com>
+
+	Backport from master
+	2020-02-10  Richard Earnshaw  <rearnsha@arm.com>
+
+	PR target/91913
+	* config/arm/arm.md (movsi_compare0): Allow SP as a source register
+	in Thumb state and also as a destination in Arm state.  Add T16
+	variants.
+
 2020-02-27  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c/93949
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index f78e1477eab..6d6b37719e0 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6312,16 +6312,21 @@
 
 (define_insn "*movsi_compare0"
   [(set (reg:CC CC_REGNUM)
-	(compare:CC (match_operand:SI 1 "s_register_operand" "0,r")
+	(compare:CC (match_operand:SI 1 "s_register_operand" "0,0,l,rk,rk")
 		    (const_int 0)))
-   (set (match_operand:SI 0 "s_register_operand" "=r,r")
+   (set (match_operand:SI 0 "s_register_operand" "=l,rk,l,r,rk")
 	(match_dup 1))]
   "TARGET_32BIT"
   "@
    cmp%?\\t%0, #0
+   cmp%?\\t%0, #0
+   subs%?\\t%0, %1, #0
+   subs%?\\t%0, %1, #0
    subs%?\\t%0, %1, #0"
   [(set_attr "conds" "set")
-   (set_attr "type" "alus_imm,alus_imm")]
+   (set_attr "arch" "t2,*,t2,t2,a")
+   (set_attr "type" "alus_imm")
+   (set_attr "length" "2,4,2,4,4")]
 )
 
 ;; Subroutine to store a half word from a register into memory.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b0c4d406fdf..e30299c0a19 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-03-12  Richard Earnshaw  <rearnsha@arm.com>
+
+	Backport from master
+	2020-02-10  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/91913
+	* gfortran.dg/pr91913.f90: New test.
+
 2020-02-27  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c/93949
diff --git a/gcc/testsuite/gfortran.dg/pr91913.f90 b/gcc/testsuite/gfortran.dg/pr91913.f90
new file mode 100644
index 00000000000..7d5477ac0c3
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr91913.f90
@@ -0,0 +1,5 @@
+! PR target/91913
+! { dg-do compile }
+! { dg-options "-std=legacy -Ofast --param max-cse-insns=0 -fno-schedule-insns -fsanitize=null" }
+
+include 'string_ctor_1.f90'

commit 6215083b9cdf97bb2886383ee309d1c9ce23a085
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Mar 13 00:16:49 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e2b9f19d525..a30f6fc9796 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200312
+20200313

commit 92902501c2ad030d56fd3347defd00e79187c51f
Author: Eric Botcazou <ebotcazou@gcc.gnu.org>
Date:   Fri Mar 13 09:58:44 2020 +0100

    Fix incorrect filling of delay slots in branchy code at -O2
    
    The issue is that relax_delay_slots can streamline the CFG in some cases,
    in particular remove BARRIERs, but removing BARRIERs changes the way the
    instructions are associated with (basic) blocks by the liveness analysis
    code in resource.c (find_basic_block) and thus can cause entries in the
    cache maintained by resource.c to become outdated, thus producing wrong
    answers downstream.
    
    The fix is to invalidate the cache entries affected by the removal of
    BARRIERs in relax_delay_slots, i.e. for the instructions down to the
    next BARRIER.
    
            PR rtl-optimization/94119
            * resource.h (clear_hashed_info_until_next_barrier): Declare.
            * resource.c (clear_hashed_info_until_next_barrier): New function.
            * reorg.c (add_to_delay_list): Fix formatting.
            (relax_delay_slots): Call clear_hashed_info_until_next_barrier on
            the next instruction after removing a BARRIER.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9d9ad0e82e6..9ed09c13c39 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2019-03-13  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR rtl-optimization/94119
+	* resource.h (clear_hashed_info_until_next_barrier): Declare.
+	* resource.c (clear_hashed_info_until_next_barrier): New function.
+	* reorg.c (add_to_delay_list): Fix formatting.
+	(relax_delay_slots): Call clear_hashed_info_until_next_barrier on
+	the next instruction after removing a BARRIER.
+
 2020-03-12  Richard Earnshaw  <rearnsha@arm.com>
 
 	Backport from master
diff --git a/gcc/reorg.c b/gcc/reorg.c
index 904d91ec9e8..f4d39b8dd6e 100644
--- a/gcc/reorg.c
+++ b/gcc/reorg.c
@@ -563,8 +563,9 @@ add_to_delay_list (rtx_insn *insn, vec<rtx_insn *> *delay_list)
 {
   /* If INSN has its block number recorded, clear it since we may
      be moving the insn to a new block.  */
-      clear_hashed_info_for_insn (insn);
-      delay_list->safe_push (insn);
+  clear_hashed_info_for_insn (insn);
+
+  delay_list->safe_push (insn);
 }
 
 /* Delete INSN from the delay slot of the insn that it is in, which may
@@ -3200,7 +3201,14 @@ relax_delay_slots (rtx_insn *first)
 
 	      if (invert_jump (jump_insn, label, 1))
 		{
-		  delete_related_insns (next);
+		  rtx_insn *from = delete_related_insns (next);
+
+		  /* We have just removed a BARRIER, which means that the block
+		     number of the next insns has effectively been changed (see
+		     find_basic_block in resource.c), so clear it.  */
+		  if (from)
+		    clear_hashed_info_until_next_barrier (from);
+
 		  next = jump_insn;
 		}
 
@@ -3473,18 +3481,22 @@ relax_delay_slots (rtx_insn *first)
 
 	      if (invert_jump (delay_jump_insn, label, 1))
 		{
-		  int i;
-
 		  /* Must update the INSN_FROM_TARGET_P bits now that
 		     the branch is reversed, so that mark_target_live_regs
 		     will handle the delay slot insn correctly.  */
-		  for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++)
+		  for (int i = 1; i < XVECLEN (PATTERN (insn), 0); i++)
 		    {
 		      rtx slot = XVECEXP (PATTERN (insn), 0, i);
 		      INSN_FROM_TARGET_P (slot) = ! INSN_FROM_TARGET_P (slot);
 		    }
 
-		  delete_related_insns (next);
+		  /* We have just removed a BARRIER, which means that the block
+		     number of the next insns has effectively been changed (see
+		     find_basic_block in resource.c), so clear it.  */
+		  rtx_insn *from = delete_related_insns (next);
+		  if (from)
+		    clear_hashed_info_until_next_barrier (from);
+
 		  next = insn;
 		}
 
diff --git a/gcc/resource.c b/gcc/resource.c
index caccce512c1..bcf30576eaa 100644
--- a/gcc/resource.c
+++ b/gcc/resource.c
@@ -1293,7 +1293,26 @@ clear_hashed_info_for_insn (rtx_insn *insn)
 	tinfo->block = -1;
     }
 }
-
+
+/* Clear any hashed information that we have stored for instructions
+   between INSN and the next BARRIER that follow a JUMP or a LABEL.  */
+
+void
+clear_hashed_info_until_next_barrier (rtx_insn *insn)
+{
+  while (insn && !BARRIER_P (insn))
+    {
+      if (JUMP_P (insn) || LABEL_P (insn))
+	{
+	  rtx_insn *next = next_active_insn (insn);
+	  if (next)
+	    clear_hashed_info_for_insn (next);
+	}
+
+      insn = next_nonnote_insn (insn);
+    }
+}
+
 /* Increment the tick count for the basic block that contains INSN.  */
 
 void
diff --git a/gcc/resource.h b/gcc/resource.h
index d9c66d42c26..0aa78a31411 100644
--- a/gcc/resource.h
+++ b/gcc/resource.h
@@ -46,6 +46,7 @@ extern void mark_set_resources (rtx, struct resources *, int,
 				enum mark_resource_type);
 extern void mark_referenced_resources (rtx, struct resources *, bool);
 extern void clear_hashed_info_for_insn (rtx_insn *);
+extern void clear_hashed_info_until_next_barrier (rtx_insn *);
 extern void incr_ticks_for_insn (rtx_insn *);
 extern void mark_end_of_function_resources (rtx, bool);
 extern void init_resource_info (rtx_insn *);

commit 8c55e44368d639849b28484f2c7842f4265b33c8
Author: Richard Biener <rguenther@suse.de>
Date:   Fri Mar 13 13:56:26 2020 +0100

    tree-optimization/94163 constrain alignment set by PRE
    
    This avoids HWI -> unsigned truncation to end up with zero alignment
    which set_ptr_info_alignment ICEs on.
    
    2020-03-13  Richard Biener  <rguenther@suse.de>
    
            PR tree-optimization/94163
            * tree-ssa-pre.c (create_expression_by_pieces): Check
            whether alignment would be zero.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9ed09c13c39..5af80f1a2d2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-13  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/94163
+	* tree-ssa-pre.c (create_expression_by_pieces): Check
+	whether alignment would be zero.
+
 2019-03-13  Eric Botcazou  <ebotcazou@adacore.com>
 
 	PR rtl-optimization/94119
diff --git a/gcc/tree-ssa-pre.c b/gcc/tree-ssa-pre.c
index 5f9dc50eef6..7f7e4173302 100644
--- a/gcc/tree-ssa-pre.c
+++ b/gcc/tree-ssa-pre.c
@@ -2797,7 +2797,8 @@ create_expression_by_pieces (basic_block block, pre_expr expr,
 	      unsigned HOST_WIDE_INT hmisalign
 		= args.length () == 3 ? tree_to_uhwi (args[2]) : 0;
 	      if ((halign & (halign - 1)) == 0
-		  && (hmisalign & ~(halign - 1)) == 0)
+		  && (hmisalign & ~(halign - 1)) == 0
+		  && (unsigned int)halign != 0)
 		set_ptr_info_alignment (get_ptr_info (forcedname),
 					halign, hmisalign);
 	    }

commit d72abee890682af7563541d4b174704db627b2a0
Author: Eric Botcazou <ebotcazou@gcc.gnu.org>
Date:   Fri Mar 13 18:04:41 2020 +0100

    Fix wrong year in ChangeLog.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5af80f1a2d2..471f17596a6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -4,7 +4,7 @@
 	* tree-ssa-pre.c (create_expression_by_pieces): Check
 	whether alignment would be zero.
 
-2019-03-13  Eric Botcazou  <ebotcazou@adacore.com>
+2020-03-13  Eric Botcazou  <ebotcazou@adacore.com>
 
 	PR rtl-optimization/94119
 	* resource.h (clear_hashed_info_until_next_barrier): Declare.

commit 91167c5739a5615e526a9673ccc413d5eca52a24
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Mar 14 00:17:04 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a30f6fc9796..3f10b5f6c1b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200313
+20200314

commit 88eae4fb59093df2311c24f44240eacc29279994
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Mar 15 00:16:51 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3f10b5f6c1b..d1f8c596469 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200314
+20200315

commit 23690790dd739f1cdd33a8249304b8f17e296c38
Author: Jason Merrill <jason@redhat.com>
Date:   Sat Mar 14 17:10:39 2020 -0400

    c++: Fix CTAD with multiple-arg ctor template [93248].
    
    When cp_unevaluated_operand is set, tsubst_decl thinks that if it sees a
    PARM_DECL that isn't already in local_specializations, we're in a decltype
    in a trailing return type or some such, and so we only want a substitution
    for a single PARM_DECL.  In this case, we want the whole chain, so make sure
    cp_unevaluated_operand is cleared.
    
    gcc/cp/ChangeLog
    2020-03-14  Jason Merrill  <jason@redhat.com>
    
            PR c++/93248
            * pt.c (build_deduction_guide): Clear cp_unevaluated_operand for
            substituting DECL_ARGUMENTS.

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index a525d4f4f9e..27b36eb7642 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-14  Jason Merrill  <jason@redhat.com>
+
+	PR c++/93248
+	* pt.c (build_deduction_guide): Clear cp_unevaluated_operand for
+	substituting DECL_ARGUMENTS.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index 409e86166c1..a2274f34725 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -26520,10 +26520,13 @@ build_deduction_guide (tree ctor, tree outer_args, tsubst_flags_t complain)
 				     complain, ctor);
 	  if (fparms == error_mark_node)
 	    ok = false;
-	  fargs = tsubst (fargs, tsubst_args, complain, ctor);
 	  if (ci)
 	    ci = tsubst_constraint_info (ci, tsubst_args, complain, ctor);
 
+	  /* Parms are to have DECL_CHAIN tsubsted, which would be skipped if
+	     cp_unevaluated_operand.  */
+	  temp_override<int> ev (cp_unevaluated_operand, 0);
+	  fargs = tsubst (fargs, tsubst_args, complain, ctor);
 	  current_template_parms = save_parms;
 	}
 
diff --git a/gcc/testsuite/g++.dg/cpp1z/class-deduction71.C b/gcc/testsuite/g++.dg/cpp1z/class-deduction71.C
new file mode 100644
index 00000000000..2fc71de8d95
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1z/class-deduction71.C
@@ -0,0 +1,6 @@
+// PR c++/93248
+// { dg-do compile { target c++17 } }
+
+template <typename T> struct S
+{ template <typename V> S (T, V, long = 0); };
+using U = decltype(S{0, 4u});

commit fed9ac72ee6c1b36d20a9550803835daaac174db
Author: Jason Merrill <jason@redhat.com>
Date:   Sat Mar 14 17:10:39 2020 -0400

    c++: Fix ICE-after-error on partial spec [92068]
    
    Here the template arguments for the partial specialization are valid
    arguments for the template, but not for a partial specialization, because
    'd' can never be deduced to anything other than an empty pack.
    
    gcc/cp/ChangeLog
    2020-03-14  Jason Merrill  <jason@redhat.com>
    
            PR c++/92068
            * pt.c (process_partial_specialization): Error rather than crash on
            extra pack expansion.

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 27b36eb7642..ed2405e6f33 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-14  Jason Merrill  <jason@redhat.com>
+
+	PR c++/92068
+	* pt.c (process_partial_specialization): Error rather than crash on
+	extra pack expansion.
+
 2020-03-14  Jason Merrill  <jason@redhat.com>
 
 	PR c++/93248
diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index a2274f34725..a7a5fa06d05 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -4919,6 +4919,14 @@ process_partial_specialization (tree decl)
       return decl;
     }
 
+  else if (nargs > DECL_NTPARMS (maintmpl))
+    {
+      error ("too many arguments for partial specialization %qT", type);
+      inform (DECL_SOURCE_LOCATION (maintmpl), "primary template here");
+      /* Avoid crash below.  */
+      return decl;
+    }
+
   /* If we aren't in a dependent class, we can actually try deduction.  */
   else if (tpd.level == 1
 	   /* FIXME we should be able to handle a partial specialization of a
@@ -4944,7 +4952,6 @@ process_partial_specialization (tree decl)
 
      Also, we verify that pack expansions only occur at the
      end of the argument list.  */
-  gcc_assert (nargs == DECL_NTPARMS (maintmpl));
   tpd2.parms = 0;
   for (i = 0; i < nargs; ++i)
     {
diff --git a/gcc/testsuite/g++.dg/cpp0x/variadic178.C b/gcc/testsuite/g++.dg/cpp0x/variadic178.C
new file mode 100644
index 00000000000..f0e65958de3
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/variadic178.C
@@ -0,0 +1,6 @@
+// PR c++/92068
+// { dg-do compile { target c++11 } }
+
+template <typename, typename> struct a;
+template <typename b, typename c, typename... d>
+struct a<b, c, d...> { };	// { dg-error "arguments" }

commit eee8f2161e072c1b9da4f334f882c385a27baa1f
Author: Jason Merrill <jason@redhat.com>
Date:   Sat Mar 14 17:10:39 2020 -0400

    c++: Find parameter pack in typedef in lambda [92909].
    
    find_parameter_packs_r doesn't look through typedefs, which is normally
    correct, but that means we need to handle their declarations specially.
    
    gcc/cp/ChangeLog
    2020-03-14  Jason Merrill  <jason@redhat.com>
    
            PR c++/92909
            * pt.c (find_parameter_packs_r): [DECL_EXPR]: Walk
            DECL_ORIGINAL_TYPE of a typedef.

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index ed2405e6f33..5668ce6a758 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-14  Jason Merrill  <jason@redhat.com>
+
+	PR c++/92909
+	* pt.c (find_parameter_packs_r): [DECL_EXPR]: Walk
+	DECL_ORIGINAL_TYPE of a typedef.
+
 2020-03-14  Jason Merrill  <jason@redhat.com>
 
 	PR c++/92068
diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index a7a5fa06d05..527d6f9f9b1 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -3814,10 +3814,18 @@ find_parameter_packs_r (tree *tp, int *walk_subtrees, void* data)
       return NULL_TREE;
 
     case DECL_EXPR:
-      /* Ignore the declaration of a capture proxy for a parameter pack.  */
-      if (is_capture_proxy (DECL_EXPR_DECL (t)))
-	*walk_subtrees = 0;
-      return NULL_TREE;
+      {
+	tree decl = DECL_EXPR_DECL (t);
+	/* Ignore the declaration of a capture proxy for a parameter pack.  */
+	if (is_capture_proxy (decl))
+	  *walk_subtrees = 0;
+	if (is_typedef_decl (decl) && TYPE_ALIAS_P (TREE_TYPE (decl)))
+	  /* Since we stop at aliases above, we need to look through them at
+	     the point of the DECL_EXPR.  */
+	  cp_walk_tree (&DECL_ORIGINAL_TYPE (decl),
+			&find_parameter_packs_r, ppd, ppd->visited);
+	return NULL_TREE;
+      }
 
     case RECORD_TYPE:
       if (TYPE_PTRMEMFUNC_P (t))
diff --git a/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C
new file mode 100644
index 00000000000..052283e6caa
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C
@@ -0,0 +1,12 @@
+// PR c++/92909
+// { dg-do compile { target c++11 } }
+
+template <class ... Ts>
+void foo()
+{
+    []
+    {
+        using T = Ts;
+    }();			// { dg-error "not expanded" }
+}
+template void foo<>();

commit 52955f5d4958b3fb33a4d76815a41a86f2e3ace0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Mar 16 00:16:53 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d1f8c596469..777d8efeebb 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200315
+20200316

commit b153804994b7234319acd6b2f32d72b26eb38848
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Mar 17 00:16:49 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 777d8efeebb..c73081a5a12 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200316
+20200317

commit 0636fd84c3515fd16e712871e12e1a987d000e8d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Mar 18 00:16:53 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c73081a5a12..584bf4bedcf 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200317
+20200318

commit 4d3efe374195c800abe97ad6574e07e2fc474c60
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Mar 19 00:16:57 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 584bf4bedcf..2cdfff05e89 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200318
+20200319

commit c8f84830a1bd275a62e226584b8ede40f0ce6760
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Thu Mar 19 15:33:02 2020 +0000

    doc: Note that some warnings depend on optimizations (PR 92757)
    
    Backport from mainline
    2020-01-13  Jonathan Wakely  <jwakely@redhat.com>
    
            PR driver/92757
            * doc/invoke.texi (Warning Options): Add caveat about some warnings
            depending on optimization settings.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 471f17596a6..b72e6a0512b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-03-19  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backport from mainline
+	2020-01-13  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR driver/92757
+	* doc/invoke.texi (Warning Options): Add caveat about some warnings
+	depending on optimization settings.
+
 2020-03-13  Richard Biener  <rguenther@suse.de>
 
 	PR tree-optimization/94163
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f3d7c5720b7..83c95892029 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -3859,6 +3859,11 @@ are being produced.  This allows the use of new @option{-Wno-} options
 with old compilers, but if something goes wrong, the compiler
 warns that an unrecognized option is present.
 
+The effectiveness of some warnings depends on optimizations also being
+enabled. For example @option{-Wsuggest-final-types} is more effective
+with link-time optimization and @option{-Wmaybe-uninitialized} will not
+warn at all unless optimization is enabled.
+
 @table @gcctabopt
 @item -Wpedantic
 @itemx -pedantic

commit 2cfe18b8376faaabec23490201d846c98045a386
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Mar 20 00:17:00 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2cdfff05e89..f4838bee578 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200319
+20200320

commit 7bbdeb3737beb5e4bd3f00aa2f09c9bb678ca761
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Mar 21 00:16:56 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f4838bee578..983af034e4c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200320
+20200321

commit 27aaa6a6ebd73cc6e1884bb6f304866bf5fc726a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Mar 22 12:51:42 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 983af034e4c..97182ea4df8 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200321
+20200322

commit 3c1be1b68cbbc7324ab6ac0c6c689dbf35600293
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Mar 23 00:16:55 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 97182ea4df8..2ce2bd47475 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200322
+20200323

commit 61ec6247a91954f6ed57e5c7fecde894acfce544
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Mar 24 00:17:01 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2ce2bd47475..a84a567c2e6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200323
+20200324

commit 0349bc70454e4de18d1cdf5eea0917646fdf79ae
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Tue Mar 24 15:00:44 2020 +0000

    AArch64: Break apart paradoxical subregs for VSTRUCT writes (PR target/94052)
    
    This works around an ICE in reload where from expand we get the following RTL
    generated for VSTRUCT mode writes:
    
    (insn 446 354 445 2 (set (reg:CI 383)
     (subreg:CI (reg:V4SI 291) 0)) "small.i":146:22 3408 {*aarch64_movci}
     (nil))
    
    This sequence is trying to say two things:
    
    1) liveliness: It's trying to say that eventually the whole CI reg will be
                   written to. It does this by generating the paradoxical subreg.
    2) write data: It's trying to in the same instruction also write the V4SI mode
                   component at offset 0 in the CI reg.
    
    This patch fixes it by in the backend when we see such a paradoxical
    construction breaking it apart and issuing a clobber to correct the liveliness
    information and then emitting a normal subreg write for the component that the
    paradoxical subreg was trying to write to.
    
    Concretely we generate this:
    
    (insn 42 41 43 (clobber (reg/v:CI 122 [ diD.5226 ])) "small.i":121:23 -1
         (nil))
    
    (insn 43 42 44 (set (subreg:V4SI (reg/v:CI 122 [ diD.5226 ]) 0)
            (reg:V4SI 136)) "small.i":121:23 -1
         (nil))
    
    gcc/ChangeLog:
    
            PR target/94052
            * config/aarch64/aarch64-simd.md (mov<mode>): Remove paradoxical
            subregs of VSTRUCT modes.
    
    gcc/testsuite/ChangeLog:
    
            * g++.target/aarch64/aarch64.exp: New file.
            * g++.target/aarch64/pr94052.C: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b72e6a0512b..82a2606280e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-24  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/94052
+	* config/aarch64/aarch64-simd.md (mov<mode>): Remove paradoxical
+	subregs of VSTRUCT modes.
+
 2020-03-19  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backport from mainline
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 1154fc3d58d..da664fc5d29 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5060,6 +5060,26 @@
       if (GET_CODE (operands[0]) != REG)
 	operands[1] = force_reg (<MODE>mode, operands[1]);
     }
+
+  /* If we have a paradoxical subreg trying to write to <MODE> from and the
+     registers don't overlap then we need to break it apart.  What it's trying
+     to do is give two kind of information at the same time.  It's trying to
+     convey liveness information by saying that the entire register will be
+     written to eventually, but it also only wants to write a single part of the
+     register.  Hence the paradoxical subreg.
+
+     Instead of allowing this we will split the two concerns.  The liveness
+     information will be conveyed using a clobber and then we break apart the
+     paradoxical subreg into just a normal write of the part that it wanted to
+     write originally.  */
+
+  if (REG_P (operands[0]) && paradoxical_subreg_p (operands[1]))
+    {
+      if (!reg_overlap_mentioned_p (operands[0], operands[1]))
+	emit_clobber (operands[0]);
+      operands[1] = SUBREG_REG (operands[1]);
+      operands[0] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
+    }
 })
 
 (define_insn "*aarch64_mov<mode>"
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e30299c0a19..683d76a0f90 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-03-24  Tamar Christina  <tamar.christina@arm.com>
+
+	* g++.target/aarch64/aarch64.exp: New file.
+	* g++.target/aarch64/pr94052.C: New test.
+
 2020-03-12  Richard Earnshaw  <rearnsha@arm.com>
 
 	Backport from master
diff --git a/gcc/testsuite/g++.target/aarch64/aarch64.exp b/gcc/testsuite/g++.target/aarch64/aarch64.exp
new file mode 100644
index 00000000000..22d804287df
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/aarch64.exp
@@ -0,0 +1,44 @@
+#  Specific regression driver for AArch64.
+#  Copyright (C) 2009-2019 Free Software Foundation, Inc.
+#
+#  This file is part of GCC.
+#
+#  GCC is free software; you can redistribute it and/or modify it
+#  under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; either version 3, or (at your option)
+#  any later version.
+#
+#  GCC is distributed in the hope that it will be useful, but
+#  WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with GCC; see the file COPYING3.  If not see
+#  <http://www.gnu.org/licenses/>.  */
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an AArch64 target.
+if {![istarget aarch64*-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib g++-dg.exp
+
+global DEFAULT_CXXFLAGS
+if ![info exists DEFAULT_CXXFLAGS] then {
+    set DEFAULT_CXXFLAGS " -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] \
+        "" $DEFAULT_CXXFLAGS
+
+# All done.
+dg-finish
+
diff --git a/gcc/testsuite/g++.target/aarch64/pr94052.C b/gcc/testsuite/g++.target/aarch64/pr94052.C
new file mode 100644
index 00000000000..d36c9bdc158
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/pr94052.C
@@ -0,0 +1,174 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -std=gnu++11 -w" } */
+
+namespace c {
+typedef int d;
+template <typename e> struct f { typedef e g; };
+template <bool, typename> struct h;
+template <typename e> e aa(typename f<e>::g i) { return i; }
+template <typename, typename> struct j {};
+template <d, typename> struct k;
+template <class l, class m> struct k<1, j<l, m>> { typedef m g; };
+template <d n, class l, class m> typename k<n, j<l, m>>::g ab(j<l, m>);
+} // namespace c
+typedef long d;
+typedef char o;
+typedef int p;
+typedef char q;
+typedef int r;
+namespace {
+struct s;
+constexpr d t = 6;
+template <typename> class ad {
+public:
+  static constexpr d u = t;
+  d v();
+  d x();
+  d y();
+};
+class z : ad<int> {};
+struct ae {
+  p af;
+};
+class ag {
+public:
+  ae ah();
+};
+} // namespace
+typedef __Int32x4_t ai;
+typedef struct {
+  ai aj[2];
+} ak;
+typedef int al;
+void am(p *a, ai b) { __builtin_aarch64_st1v4si(a, b); }
+namespace an {
+class ao {
+public:
+  bool operator==(ao);
+  d v();
+  d x();
+};
+class ap : public ad<r> {};
+class aq {
+public:
+  c::j<int, int> ar();
+  int as();
+  int at();
+};
+class au {
+public:
+  virtual d av(d);
+  virtual ap aw();
+  virtual ag ax();
+};
+class ay {};
+class az {
+  virtual void ba(const ay &, const s &);
+};
+using bb = az;
+class bc;
+class bd : bb {
+  void ba(const ay &, const s &);
+  bc *be;
+  bc *bf;
+  bc *bg;
+  aq bh;
+  int bi;
+  int bj;
+  ao bk;
+};
+namespace bl {
+namespace bm {
+namespace bn {
+class bo;
+}
+} // namespace bm
+} // namespace bl
+namespace bn {
+template <typename ac = c::h<0, bl::bm ::bn::bo>>
+ai bp(ac *, ac *, ac *, al, al, al, d, p);
+template <typename ac = c::h<0, bl::bm ::bn::bo>>
+ak bq(ac *br, ac *bs, ac *bt, al bu, al bv, al bw, d bx, int, int by) {
+  ak{bp(br, bs, bt, bu, bv, bw, bx, by), bp(br, bs, bt, bu, bv, bw, bx, by)};
+}
+template <typename ac = c::h<0, bl::bm ::bn::bo>>
+ak bz(ac *, ac *, ac *, al, al, al &, int, p);
+template <int> void ca(p *, const ak &);
+template <> void ca<1>(p *buffer, const ak &cb) {
+  am(buffer, cb.aj[0]);
+  am(buffer + 4, cb.aj[1]);
+}
+int cc(int, int);
+} // namespace bn
+class bc {
+public:
+  virtual au *cd();
+};
+class ce {
+public:
+  q *cf();
+};
+template <d> struct cg {
+  template <typename ch> static void ci(ay, z cj, ch ck) { ck(cj); }
+};
+template <typename ch> void cl(ay w, ch ck) {
+  z cj;
+  cg<z::u>::ci(w, cj, c::aa<ch>(ck));
+}
+namespace {
+template <typename T1, typename cm, int cn> class co {
+public:
+  static void convolve(ay, int cs, bc *cp, bc *cq, bc *cr, aq cw, int, ao ct) {
+    int by = cp->cd()->ax().ah().af;
+    int cu = cq->cd()->ax().ah().af;
+    cp->cd()->aw().v();
+    int cv = cp->cd()->aw().x();
+    cp->cd()->aw().y();
+    cp->cd()->aw();
+    int da = cr->cd()->aw().x();
+    int cx = cq->cd()->aw().x();
+    cq->cd()->aw().y();
+    int cy = cr->cd()->av(0);
+    int cz = cr->cd()->av(1);
+    bn::cc(cs, cn);
+    int de = c::ab<1>(cw.ar());
+    cw.as();
+    cw.at();
+    ay db;
+    ce dc;
+    ce dd;
+    ce w;
+    q *di = w.cf();
+    cl(db, [&](z) {
+      int df;
+      dc;
+      di;
+      cx;
+      auto dg(cu);
+      auto dh(cu);
+      auto dl(cu);
+      for (; cz; df += de) {
+        auto br = reinterpret_cast<T1 *>(cv);
+        auto bs = reinterpret_cast<T1 *>(cv);
+        auto bt = reinterpret_cast<T1 *>(df * ct.x());
+        auto dj = reinterpret_cast<cm *>(dd.cf() + da);
+        for (int dk; dk < cy; dk += cs, dj += cs)
+          if (ct == ao()) {
+            auto vres = bn::bz(br, bs, bt, dg, dh, dl, cn, by);
+            bn::ca<cn>(dj, vres);
+          } else
+            bn::bq(br, bs, bt, dg, dh, dl, ct.v(), cn, by);
+      }
+    });
+  }
+};
+template <typename T1, typename cm>
+void bz(ay dm, int cs, bc *cp, bc *cq, bc *cr, aq cw, int dn, ao ct) {
+  co<T1, cm, 1>::convolve(dm, cs, cp, cq, cr, cw, dn, ct);
+  co<T1, cm, 2>::convolve(dm, cs, cp, cq, cr, cw, dn, ct);
+}
+} // namespace
+void bd::ba(const ay &dm, const s &) {
+  bz<o, p>(dm, bi, be, bg, bf, bh, bj, bk);
+}
+} // namespace an

commit dc65052d2351aeb1f1968b6ac9f1244de6ed64e1
Author: John David Anglin <danglin@gcc.gnu.org>
Date:   Tue Mar 24 17:09:58 2020 +0000

    Define __BIG_ENDIAN__
    
            2020-03-24  John David Anglin  <danglin@gcc.gnu.org>
    
            PR lto/94249
            * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 82a2606280e..83587c9868a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-03-24  John David Anglin  <danglin@gcc.gnu.org>
+
+	PR lto/94249
+	* config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.
+
 2020-03-24  Tamar Christina  <tamar.christina@arm.com>
 
 	PR target/94052
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 232495bd719..383e8a9bb1a 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -171,6 +171,7 @@ do {								\
      builtin_assert("machine=hppa");				\
      builtin_define("__hppa");					\
      builtin_define("__hppa__");				\
+     builtin_define("__BIG_ENDIAN__");				\
      if (TARGET_PA_20)						\
        builtin_define("_PA_RISC2_0");				\
      else if (TARGET_PA_11)					\

commit e5acaad2bdd1297ea25067271da909163ec472e7
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Mar 25 00:16:52 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a84a567c2e6..4e2e6c730e5 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200324
+20200325

commit 2cc686897cc4d9935d4c8302af67565fa54c0aec
Author: Mark Eggleston <markeggleston@gcc.gnu.org>
Date:   Wed Mar 25 15:10:03 2020 +0000

    fortran: ICE using undeclared symbol in array constructor PR93484
    
    Using undeclared symbol k in an expression in the following
    array constructor results in an ICE:
    
        print *, [real(x(k))]
    
    If the call to the intrinsic is not in a constructor a no IMPLICIT
    type error is reported and the ICE does not occur.
    
    Matching on an expression instead of an initialisation express an
    and not converting a MATCH_ERROR return value into MATCH_NO results
    in the no IMPLICIT error and no ICE.
    
    Note: Steven G. Kargl  <kargl@gcc.gnu.org> is the author of the
    changes except for the test cases.
    
    gcc/fortran/ChangeLog:
    
            Backport from master
            2020-03-25  Mark Eggleston <markeggleston@gcc.gnu.org>
    
            PR fortran/93484
            * match.c (gfc_match_type_spec): Replace gfc_match_init_expr with
            gfc_match_expr. Return m if m is MATCH_NO or MATCH_ERROR.
    
    gcc/testsuite
    
            Backport from master
            2020-03-25  Mark Eggleston <markeggleston@gcc.gnu.org>
    
            PR fortran/93484
            * gfortran.dg/pr93484_1.f90: New test.
            * gfortran.dg/pr93484_2.f90: New test.

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index d078dfb7533..012286a1c72 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,12 @@
+2020-03-25  Mark Eggleston <markeggleston@gcc.gnu.org>
+
+	Backport from master
+	2020-03-25  Mark Eggleston <markeggleston@gcc.gnu.org>
+
+	PR fortran/93484
+	* match.c (gfc_match_type_spec): Replace gfc_match_init_expr with
+	gfc_match_expr. Return m if m is MATCH_NO or MATCH_ERROR.
+
 2020-02-04  Tobias Burnus  <tobias@codesourcery.com>
 
 	Backported from mainline
diff --git a/gcc/fortran/match.c b/gcc/fortran/match.c
index d0a4b53da6b..9b61f1f52ec 100644
--- a/gcc/fortran/match.c
+++ b/gcc/fortran/match.c
@@ -2183,9 +2183,9 @@ gfc_match_type_spec (gfc_typespec *ts)
 
 found:
 
-      m = gfc_match_init_expr (&e);
+      m = gfc_match_expr (&e);
       if (m == MATCH_NO || m == MATCH_ERROR)
-	return MATCH_NO;
+	return m;
 
       /* If a comma appears, it is an intrinsic subprogram. */
       gfc_gobble_whitespace ();
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 683d76a0f90..10d86b49843 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2020-03-25  Mark Eggleston <markeggleston@gcc.gnu.org>
+
+	Backport from master
+	2020-03-25  Mark Eggleston <markeggleston@gcc.gnu.org>
+
+	PR fortran/93484
+	* gfortran.dg/pr93484_1.f90: New test.
+	* gfortran.dg/pr93484_2.f90: New test.
+
 2020-03-24  Tamar Christina  <tamar.christina@arm.com>
 
 	* g++.target/aarch64/aarch64.exp: New file.
diff --git a/gcc/testsuite/gfortran.dg/pr93484_1.f90 b/gcc/testsuite/gfortran.dg/pr93484_1.f90
new file mode 100644
index 00000000000..3b6dbc9ad79
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr93484_1.f90
@@ -0,0 +1,8 @@
+! { dg-do compile }
+!
+program p
+  implicit none
+  integer :: x(4) = [1,2,3,4]
+  print *, [real(x(k))] ! { dg-error "Symbol 'k' at .1. has no IMPLICIT type" } 
+end
+
diff --git a/gcc/testsuite/gfortran.dg/pr93484_2.f90 b/gcc/testsuite/gfortran.dg/pr93484_2.f90
new file mode 100644
index 00000000000..4a7f4330ed9
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr93484_2.f90
@@ -0,0 +1,8 @@
+! { dg-do compile }
+!
+program p
+  implicit none
+  integer, parameter :: x(4) = [1,2,3,4]
+  print *, [real(x(k))] ! { dg-error "Symbol 'k' at .1. has no IMPLICIT type" }
+end
+

commit c072c70c29b51377905422e41575f01269b32506
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Mar 26 00:17:02 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4e2e6c730e5..2024abddc58 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200325
+20200326

commit 5dff17fb0d20807d73c41daa3f897faff13f7bac
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Mar 27 00:17:00 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2024abddc58..19a1a73d750 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200326
+20200327

commit 4c36b54de7ddbcb580f4b99936af4a0195db9d2f
Author: Nathan Sidwell <nathan@acm.org>
Date:   Fri Mar 27 13:24:27 2020 -0700

    c++: Fix ICE on popping local scope [pr84733]
    
            PR c++/84733
            * name-lookup.c (do_pushdecl): Look through cleanp levels.

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 5668ce6a758..7651d0e833f 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,8 @@
+2020-03-27  Nathan Sidwell  <nathan@acm.org>
+
+	PR c++/84733
+	* name-lookup.c (do_pushdecl): Look through cleanp levels.
+
 2020-03-14  Jason Merrill  <jason@redhat.com>
 
 	PR c++/92909
diff --git a/gcc/cp/name-lookup.c b/gcc/cp/name-lookup.c
index 3f8e4a0e3a8..f61e748e748 100644
--- a/gcc/cp/name-lookup.c
+++ b/gcc/cp/name-lookup.c
@@ -2971,7 +2971,8 @@ do_pushdecl (tree decl, bool is_friend)
   /* The binding level we will be pushing into.  During local class
      pushing, we want to push to the containing scope.  */
   cp_binding_level *level = current_binding_level;
-  while (level->kind == sk_class)
+  while (level->kind == sk_class
+	 || level->kind == sk_cleanup)
     level = level->level_chain;
 
   /* An anonymous namespace has a NULL DECL_NAME, but we still want to
diff --git a/gcc/testsuite/g++.dg/lookup/pr84733.C b/gcc/testsuite/g++.dg/lookup/pr84733.C
new file mode 100644
index 00000000000..d0394eab891
--- /dev/null
+++ b/gcc/testsuite/g++.dg/lookup/pr84733.C
@@ -0,0 +1,21 @@
+// { dg-do compile { target c++11 } }
+// PR c++/84733 ICE popping local binding after cleanup region
+
+struct c {
+  ~c();
+} b;
+
+void f() {
+#ifndef OK
+  try {
+  d:
+    ;
+  } catch (int) {
+  }
+#endif
+  decltype(b) a;
+  int e;
+  struct e { } f;
+  e = 5;
+  struct e j;
+}

commit 13e62dcdcd436a2a957698e56f5b48fb9594aaea
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Mar 28 00:16:56 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 19a1a73d750..46b44aa3286 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200327
+20200328

commit 3641821e2d6ee1064a9bdbfbb5bdb5977dcad97f
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Mar 29 00:16:54 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 46b44aa3286..70fbcbd8103 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200328
+20200329

commit bc23ea9c342cbdf5d364648d836a5f95d8ec596d
Author: Iain Sandoe <iain@sandoe.co.uk>
Date:   Sun Mar 29 10:04:03 2020 +0100

    Darwin: Fix i686 bootstrap when the assembler supports GOTOFF in data.
    
    When we use an assembler that supports " .long XX@GOTOFF", the current
    combination of configuration parameters and conditional compilation
    (when building an i686-darwin compiler with mdynamic-no-pic) assume that
    it's OK to put jump tables in the .const section.
    
    However, when we encounter a weak function with a jump table, this
    produces relocations that directly access the weak symbol section from
    the .const section - which is deemed illegal by the linker (since that
    would mean that the weak symbol could not be replaced).
    
    Arguably, this is a limitation (maybe even a bug) in the linker - but
    it seems that we'd have to change the ABI to fix it - since it would
    require some annotation (maybe just using a special section for the
    jump tables) to tell the linker that this specific circumstance is OK
    because the direct access to the weak symbol can only occur from that
    symbol itself.
    
    The fix is to force jump tables into the text section for all X86 Darwin
    versions (PIC code already had this change).
    
    We also need to backport 263764 'reorder MACHO and HAVE_GOTOFF_IN_DATA
    tests', since this causes us to emit @GOTOFF relocations which are not
    useable by the Darwin linker.
    
    gcc/ChangeLog:
    
    2020-03-29  Iain Sandoe  <iain@sandoe.co.uk>
    
            Backport from master.
            2018-08-22  Iain Sandoe  <iain@sandoe.co.uk>
    
            * config/i386/i386.c (ix86_output_addr_diff_elt): Move the MACH-O
            specific test before the one for HAVE_AS_GOTOFF_IN_DATA.
    
            Backport from master.
            2020-03-22  Iain Sandoe  <iain@sandoe.co.uk>
    
            * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
            references to Darwin.
            * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
            unconditionally and comment on why.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 83587c9868a..ec50bdc8ef0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2020-03-29  Iain Sandoe  <iain@sandoe.co.uk>
+
+	Backport from master.
+	2018-08-22  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* config/i386/i386.c (ix86_output_addr_diff_elt): Move the MACH-O
+	specific test before the one for HAVE_AS_GOTOFF_IN_DATA.
+
+	Backport from master.
+	2020-03-22  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
+	references to Darwin.
+	* config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
+	unconditionally and comment on why.
+
 2020-03-24  John David Anglin  <danglin@gcc.gnu.org>
 
 	PR lto/94249
diff --git a/gcc/config/i386/darwin.h b/gcc/config/i386/darwin.h
index 2d0dc1f2605..3a844a55cd6 100644
--- a/gcc/config/i386/darwin.h
+++ b/gcc/config/i386/darwin.h
@@ -236,6 +236,16 @@ along with GCC; see the file COPYING3.  If not see
 #undef TARGET_ASM_OUTPUT_IDENT
 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
 
+/* We always want jump tables in the text section:
+   * for PIC code, we need the subtracted symbol to be defined at
+     assembly-time.
+   * for mdynamic-no-pic, we cannot support jump tables in the .const
+     section for weak functions, this looks to ld64 like direct access
+     to the weak symbol from an anonymous atom.  */
+
+#undef JUMP_TABLES_IN_TEXT_SECTION
+#define JUMP_TABLES_IN_TEXT_SECTION 1
+
 /* Darwin profiling -- call mcount.  */
 #undef FUNCTION_PROFILER
 #define FUNCTION_PROFILER(FILE, LABELNO)				\
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 5d2e3945f6e..2fe0c8bc4f8 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -19922,8 +19922,6 @@ ix86_output_addr_diff_elt (FILE *file, int value, int rel)
   if (TARGET_64BIT || TARGET_VXWORKS_RTP)
     fprintf (file, "%s%s%d-%s%d\n",
 	     directive, LPREFIX, value, LPREFIX, rel);
-  else if (HAVE_AS_GOTOFF_IN_DATA)
-    fprintf (file, ASM_LONG "%s%d@GOTOFF\n", LPREFIX, value);
 #if TARGET_MACHO
   else if (TARGET_MACHO)
     {
@@ -19932,6 +19930,8 @@ ix86_output_addr_diff_elt (FILE *file, int value, int rel)
       putc ('\n', file);
     }
 #endif
+  else if (HAVE_AS_GOTOFF_IN_DATA)
+    fprintf (file, ASM_LONG "%s%d@GOTOFF\n", LPREFIX, value);
   else
     asm_fprintf (file, ASM_LONG "%U%s+[.-%s%d]\n",
 		 GOT_SYMBOL_NAME, LPREFIX, value);
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index aba63fb7a80..63a54558a65 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2254,11 +2254,10 @@ extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
 
 /* Under some conditions we need jump tables in the text section,
    because the assembler cannot handle label differences between
-   sections.  This is the case for x86_64 on Mach-O for example.  */
+   sections.  */
 
 #define JUMP_TABLES_IN_TEXT_SECTION \
-  (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
-   || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
+  (flag_pic && !(TARGET_64BIT || HAVE_AS_GOTOFF_IN_DATA))
 
 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
    and switch back.  For x86 we do this only to save a few bytes that

commit 40aa944391dfec4529fb6970b9e78d5805f88fc5
Author: Martin Liska <mliska@suse.cz>
Date:   Sun Mar 29 19:19:09 2020 +0200

    Backport 9297e013293e4d332fc7c40859ea4dd9616e0d88
    
            Backport from mainline
            2019-09-02  Martin Liska  <mliska@suse.cz>
    
            PR gcov-profile/91601
            * gcov.c (path_contains_zero_cycle_arc): Rename to ...
            (path_contains_zero_or_negative_cycle_arc): ... this and handle
            also negative edges.
            (circuit): Handle also negative edges as they can happen
            in some situations.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ec50bdc8ef0..44c4ae54b05 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2020-03-29  Martin Liska  <mliska@suse.cz>
+
+	Backport from mainline
+	2019-09-02  Martin Liska  <mliska@suse.cz>
+
+	PR gcov-profile/91601
+	* gcov.c (path_contains_zero_cycle_arc): Rename to ...
+	(path_contains_zero_or_negative_cycle_arc): ... this and handle
+	also negative edges.
+	(circuit): Handle also negative edges as they can happen
+	in some situations.
+
 2020-03-29  Iain Sandoe  <iain@sandoe.co.uk>
 
 	Backport from master.
diff --git a/gcc/gcov.c b/gcc/gcov.c
index a99802079dc..565530d4f73 100644
--- a/gcc/gcov.c
+++ b/gcc/gcov.c
@@ -653,10 +653,10 @@ unblock (const block_info *u, block_vector_t &blocked,
 /* Return true when PATH contains a zero cycle arc count.  */
 
 static bool
-path_contains_zero_cycle_arc (arc_vector_t &path)
+path_contains_zero_or_negative_cycle_arc (arc_vector_t &path)
 {
   for (unsigned i = 0; i < path.size (); i++)
-    if (path[i]->cs_count == 0)
+    if (path[i]->cs_count <= 0)
       return true;
   return false;
 }
@@ -682,7 +682,7 @@ circuit (block_info *v, arc_vector_t &path, block_info *start,
     {
       block_info *w = arc->dst;
       if (w < start
-	  || arc->cs_count == 0
+	  || arc->cs_count <= 0
 	  || !linfo.has_block (w))
 	continue;
 
@@ -693,7 +693,7 @@ circuit (block_info *v, arc_vector_t &path, block_info *start,
 	  handle_cycle (path, count);
 	  loop_found = true;
 	}
-      else if (!path_contains_zero_cycle_arc (path)
+      else if (!path_contains_zero_or_negative_cycle_arc (path)
 	       &&  find (blocked.begin (), blocked.end (), w) == blocked.end ())
 	loop_found |= circuit (w, path, start, blocked, block_lists, linfo,
 			       count);
@@ -708,7 +708,7 @@ circuit (block_info *v, arc_vector_t &path, block_info *start,
       {
 	block_info *w = arc->dst;
 	if (w < start
-	    || arc->cs_count == 0
+	    || arc->cs_count <= 0
 	    || !linfo.has_block (w))
 	  continue;
 

commit 2e50319ad2437e7b3a7691aa1351d522437d5b95
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Fri Dec 20 18:36:48 2019 +0100

    backport: re PR fortran/92775 (Incorrect expression in DW_AT_byte_stride on an array)
    
            Backported from mainline
            2019-12-06  Jakub Jelinek  <jakub@redhat.com>
    
            PR fortran/92775
            * trans.h (struct lang_type, struct lang_decl): Remove span member.
            (GFC_DECL_SPAN, GFC_TYPE_ARRAY_SPAN): Remove macros.
            * trans-array.h (gfc_get_descriptor_offsets_for_info): Add another
            argument.
            * trans-array.c (gfc_get_descriptor_offsets_for_info): Add SPAN_OFF
            argument and initialize *SPAN_OFF to the offset of span field.
            * trans-types.c (gfc_get_array_descr_info): Adjust
            gfc_get_descriptor_offsets_for_info caller.  Compute elem_size
            as base->span instead of TYPE_SIZE_UNIT (etype) constant.

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 012286a1c72..822381757f2 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,19 @@
+2020-03-30  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from mainline
+	2019-12-06  Jakub Jelinek  <jakub@redhat.com>
+
+	PR fortran/92775
+	* trans.h (struct lang_type, struct lang_decl): Remove span member.
+	(GFC_DECL_SPAN, GFC_TYPE_ARRAY_SPAN): Remove macros.
+	* trans-array.h (gfc_get_descriptor_offsets_for_info): Add another
+	argument.
+	* trans-array.c (gfc_get_descriptor_offsets_for_info): Add SPAN_OFF
+	argument and initialize *SPAN_OFF to the offset of span field.
+	* trans-types.c (gfc_get_array_descr_info): Adjust
+	gfc_get_descriptor_offsets_for_info caller.  Compute elem_size
+	as base->span instead of TYPE_SIZE_UNIT (etype) constant.
+
 2020-03-25  Mark Eggleston <markeggleston@gcc.gnu.org>
 
 	Backport from master
diff --git a/gcc/fortran/trans-array.c b/gcc/fortran/trans-array.c
index 9b898888e3d..52b46e22106 100644
--- a/gcc/fortran/trans-array.c
+++ b/gcc/fortran/trans-array.c
@@ -503,9 +503,10 @@ gfc_conv_shift_descriptor_lbound (stmtblock_t* block, tree desc,
 
 void
 gfc_get_descriptor_offsets_for_info (const_tree desc_type, tree *data_off,
-				     tree *dtype_off, tree *dim_off,
-				     tree *dim_size, tree *stride_suboff,
-				     tree *lower_suboff, tree *upper_suboff)
+				     tree *dtype_off, tree *span_off,
+				     tree *dim_off, tree *dim_size,
+				     tree *stride_suboff, tree *lower_suboff,
+				     tree *upper_suboff)
 {
   tree field;
   tree type;
@@ -515,6 +516,8 @@ gfc_get_descriptor_offsets_for_info (const_tree desc_type, tree *data_off,
   *data_off = byte_position (field);
   field = gfc_advance_chain (TYPE_FIELDS (type), DTYPE_FIELD);
   *dtype_off = byte_position (field);
+  field = gfc_advance_chain (TYPE_FIELDS (type), SPAN_FIELD);
+  *span_off = byte_position (field);
   field = gfc_advance_chain (TYPE_FIELDS (type), DIMENSION_FIELD);
   *dim_off = byte_position (field);
   type = TREE_TYPE (TREE_TYPE (field));
diff --git a/gcc/fortran/trans-array.h b/gcc/fortran/trans-array.h
index 5ef86565d8d..284f1791233 100644
--- a/gcc/fortran/trans-array.h
+++ b/gcc/fortran/trans-array.h
@@ -159,7 +159,7 @@ void gfc_trans_array_cobounds (tree, stmtblock_t *, const gfc_symbol *);
 
 /* Build expressions for accessing components of an array descriptor.  */
 void gfc_get_descriptor_offsets_for_info (const_tree, tree *, tree *, tree *, tree *,
-					  tree *, tree *, tree *);
+					  tree *, tree *, tree *, tree *);
 
 tree gfc_conv_descriptor_data_get (tree);
 tree gfc_conv_descriptor_data_addr (tree);
diff --git a/gcc/fortran/trans-types.c b/gcc/fortran/trans-types.c
index cc505aeb0bd..6b4a9e7d86b 100644
--- a/gcc/fortran/trans-types.c
+++ b/gcc/fortran/trans-types.c
@@ -3344,7 +3344,7 @@ gfc_get_array_descr_info (const_tree type, struct array_descr_info *info)
   int rank, dim;
   bool indirect = false;
   tree etype, ptype, t, base_decl;
-  tree data_off, dim_off, dtype_off, dim_size, elem_size;
+  tree data_off, span_off, dim_off, dtype_off, dim_size, elem_size;
   tree lower_suboff, upper_suboff, stride_suboff;
   tree dtype, field, rank_off;
 
@@ -3401,12 +3401,13 @@ gfc_get_array_descr_info (const_tree type, struct array_descr_info *info)
   if (indirect)
     base_decl = build1 (INDIRECT_REF, ptype, base_decl);
 
-  elem_size = fold_convert (gfc_array_index_type, TYPE_SIZE_UNIT (etype));
-
-  gfc_get_descriptor_offsets_for_info (type, &data_off, &dtype_off, &dim_off,
-				       &dim_size, &stride_suboff,
+  gfc_get_descriptor_offsets_for_info (type, &data_off, &dtype_off, &span_off,
+				       &dim_off, &dim_size, &stride_suboff,
 				       &lower_suboff, &upper_suboff);
 
+  t = fold_build_pointer_plus (base_decl, span_off);
+  elem_size = build1 (INDIRECT_REF, gfc_array_index_type, t);
+
   t = base_decl;
   if (!integer_zerop (data_off))
     t = fold_build_pointer_plus (t, data_off);
diff --git a/gcc/fortran/trans.h b/gcc/fortran/trans.h
index 103ad6787ad..78b3d7db764 100644
--- a/gcc/fortran/trans.h
+++ b/gcc/fortran/trans.h
@@ -953,7 +953,6 @@ struct GTY(())	lang_type	 {
   tree offset;
   tree dtype;
   tree dataptr_type;
-  tree span;
   tree base_decl[2];
   tree nonrestricted_type;
   tree caf_token;
@@ -969,7 +968,6 @@ struct GTY(()) lang_decl {
      address of target label.  */
   tree stringlen;
   tree addr;
-  tree span;
   /* For assumed-shape coarrays.  */
   tree token, caf_offset;
   unsigned int scalar_allocatable : 1;
@@ -979,7 +977,6 @@ struct GTY(()) lang_decl {
 
 #define GFC_DECL_ASSIGN_ADDR(node) DECL_LANG_SPECIFIC(node)->addr
 #define GFC_DECL_STRING_LEN(node) DECL_LANG_SPECIFIC(node)->stringlen
-#define GFC_DECL_SPAN(node) DECL_LANG_SPECIFIC(node)->span
 #define GFC_DECL_TOKEN(node) DECL_LANG_SPECIFIC(node)->token
 #define GFC_DECL_CAF_OFFSET(node) DECL_LANG_SPECIFIC(node)->caf_offset
 #define GFC_DECL_SAVED_DESCRIPTOR(node) \
@@ -1028,7 +1025,6 @@ struct GTY(()) lang_decl {
 #define GFC_TYPE_ARRAY_DTYPE(node) (TYPE_LANG_SPECIFIC(node)->dtype)
 #define GFC_TYPE_ARRAY_DATAPTR_TYPE(node) \
   (TYPE_LANG_SPECIFIC(node)->dataptr_type)
-#define GFC_TYPE_ARRAY_SPAN(node) (TYPE_LANG_SPECIFIC(node)->span)
 #define GFC_TYPE_ARRAY_BASE_DECL(node, internal) \
   (TYPE_LANG_SPECIFIC(node)->base_decl[(internal)])
 

commit 5a450ae4d1cee633d7edcf06451de94ff416027a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Mar 30 00:16:57 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 70fbcbd8103..e597618f32b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200329
+20200330

commit e9c115a0876d843a3649888bad7d3a5bda568685
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Mar 31 00:17:00 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e597618f32b..04484a25ecf 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200330
+20200331

commit bfb0e282e3dacb7c72f78b9b546b36a6fcc534e8
Author: Carl Love <carll@us.ibm.com>
Date:   Tue Mar 31 11:53:47 2020 -0500

    rs6000 Add command line and builtin compatibility check
    
    2020-03-31  Carl Love  <cel@us.ibm.com>
    
            backport of mainline commit
    
            commit 68dd57808f7c0147acdb5ca72c88ff655afcb0ce
            Author: Carl Love <carll@us.ibm.com>
            Date:   Fri Mar 20 18:15:05 2020 -0500
    
            whith change log typo fixed.
    
            PR target/87583
            * gcc/config/rs6000/rs6000.c (rs6000_option_override_internal):
            Add check for TARGET_FPRND for Power 7 or newer.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 44c4ae54b05..b88b67a1fea 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2020-03-31  Carl Love  <cel@us.ibm.com>
+
+	backport of mainline commit
+
+	commit 68dd57808f7c0147acdb5ca72c88ff655afcb0ce
+	Author: Carl Love <carll@us.ibm.com>
+	Date:   Fri Mar 20 18:15:05 2020 -0500
+
+	whith change log typo fixed.
+
+	PR target/87583
+	* gcc/config/rs6000/rs6000.c (rs6000_option_override_internal):
+	Add check for TARGET_FPRND for Power 7 or newer.
+
 2020-03-29  Martin Liska  <mliska@suse.cz>
 
 	Backport from mainline
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 8cf6bd54b2f..c868015dc9e 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4401,6 +4401,14 @@ rs6000_option_override_internal (bool global_init_p)
       rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
     }
 
+  if (!TARGET_FPRND && TARGET_VSX)
+    {
+      if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND)
+	/* TARGET_VSX = 1 implies Power 7 and newer */
+	error ("%qs requires %qs", "-mvsx", "-mfprnd");
+      rs6000_isa_flags &= ~OPTION_MASK_FPRND;
+    }
+
   if (TARGET_DIRECT_MOVE && !TARGET_VSX)
     {
       if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)

commit 9d9d5382765785afbd114e9b9f253a602871a047
Author: Carl Love <carll@us.ibm.com>
Date:   Tue Mar 31 12:45:34 2020 -0500

    rs6000: vec_rlnm fix to make builtin work according to ABI
    
            Backport from mainline:
              commit e97929e20b2f52e6cfc046c1302324d1b24d95e3
              Author: Carl Love <carll@us.ibm.com>
              Date:   Wed Mar 25 18:33:37 2020 -0500
    
            gcc/ChangeLog
    
            PR target/93819
                * gcc/config/rs6000/altivec.h:
                Fixed swapped arguments for vec_rlnm define.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b88b67a1fea..194ae71f4b0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-03-31  Carl Love  <cel@us.ibm.com>
+
+	Backport of:
+	  commit e97929e20b2f52e6cfc046c1302324d1b24d95e3
+	  Author: Carl Love <carll@us.ibm.com>
+	  Date:   Wed Mar 25 18:33:37 2020 -0500
+
+	PR target/93819
+        * gcc/config/rs6000/altivec.h:
+        Fixed swapped arguments for vec_rlnm define.
+
 2020-03-31  Carl Love  <cel@us.ibm.com>
 
 	backport of mainline commit
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 6c5757eadf5..9ae1a354fc5 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -180,7 +180,7 @@
 #define vec_recipdiv __builtin_vec_recipdiv
 #define vec_rlmi __builtin_vec_rlmi
 #define vec_vrlnm __builtin_vec_rlnm
-#define vec_rlnm(a,b,c) (__builtin_vec_rlnm((a),((b)<<8)|(c)))
+#define vec_rlnm(a,b,c) (__builtin_vec_rlnm((a),((c)<<8)|(b)))
 #define vec_rsqrt __builtin_vec_rsqrt
 #define vec_rsqrte __builtin_vec_rsqrte
 #define vec_signed __builtin_vec_vsigned

commit bfdb0a856a157dadfa127b77ac794d0d175c18c4
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Apr 1 00:17:16 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 04484a25ecf..724d468b408 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200331
+20200401

commit bca131fee1666e24549a0218de5b7258780462d3
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Apr 2 00:16:50 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 724d468b408..791b1d8bbc3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200401
+20200402

commit 26191cec3421a157f4bafa7760cfd1bc4f90f0e5
Author: Mark Eggleston <markeggleston@gcc.gnu.org>
Date:   Thu Apr 2 08:32:05 2020 +0100

    fortran: ICE equivalence with an element of an array PR94030
    
    Deferred size arrays can not be used in equivalance statements.
    
    gcc/fortran/ChangeLog:
    
            Backport from master
            2020-04-02  Mark Eggleston <markeggleston@gcc.gnu.org>
    
            PR fortran/94030
            * resolve.c (resolve_equivalence): Correct formatting
            around the label "identical_types".  Instead of using
            gfc_resolve_array_spec use is_non_constants_shape_array
            to determine whether the array can be used in a in an
            equivalence statement.
    
    gcc/testsuite/ChangeLog:
    
            Backport from master
            2020-04-02  Mark Eggleston <markeggleston@gcc.gnu.org>
    
            PR fortran/94030
            * gfortran.dg/pr94030_1.f90
            * gfortran.dg/pr94030_2.f90

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 822381757f2..801b1da81ea 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,13 @@
+2020-04-02  Mark Eggleston <markeggleston@gcc.gnu.org>
+
+	Backport from master
+	2020-04-02  Mark Eggleston <markeggleston@gcc.gnu.org>
+	Steven G. Kargl  <kargl@gcc.gnu.org>
+
+	PR fortran/94030
+	* gfortran.dg/pr94030_1.f90: New test.
+	* gfortran.dg/pr94030_2.f90: New test.
+
 2020-03-30  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from mainline
diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
index 8afc72350c1..69d877ed55b 100644
--- a/gcc/fortran/resolve.c
+++ b/gcc/fortran/resolve.c
@@ -16311,7 +16311,8 @@ resolve_equivalence (gfc_equiv *eq)
 	  && !gfc_notify_std (GFC_STD_GNU, msg, sym->name, &e->where))
 		continue;
 
-  identical_types:
+identical_types:
+
       last_ts =&sym->ts;
       last_where = &e->where;
 
@@ -16319,8 +16320,7 @@ resolve_equivalence (gfc_equiv *eq)
 	continue;
 
       /* Shall not be an automatic array.  */
-      if (e->ref->type == REF_ARRAY
-	  && !gfc_resolve_array_spec (e->ref->u.ar.as, 1))
+      if (e->ref->type == REF_ARRAY && is_non_constant_shape_array (sym))
 	{
 	  gfc_error ("Array %qs at %L with non-constant bounds cannot be "
 		     "an EQUIVALENCE object", sym->name, &e->where);
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 10d86b49843..e033b518c89 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2020-04-02  Mark Eggleston <markeggleston@gcc.gnu.org>
+
+	Backport from master
+	2020-04-02  Steven G. Kargl  <kargl@gcc.gnu.org>
+
+	PR fortran/94030
+	* resolve.c (resolve_equivalence): Correct formatting
+	around the label "identical_types".  Instead of using
+	gfc_resolve_array_spec use is_non_constants_shape_array
+	to determine whether the array can be used in a in an
+	equivalence statement.
+
 2020-03-25  Mark Eggleston <markeggleston@gcc.gnu.org>
 
 	Backport from master
diff --git a/gcc/testsuite/gfortran.dg/pr94030_1.f90 b/gcc/testsuite/gfortran.dg/pr94030_1.f90
new file mode 100644
index 00000000000..e63d3cc8da4
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr94030_1.f90
@@ -0,0 +1,11 @@
+! { dg-do compile }
+!
+
+subroutine f(n)
+  integer :: n
+  integer :: arr(n)
+  integer :: i
+  equivalence (i, arr(1))
+end
+
+! { dg-error "Array 'arr' at .1. with non-constant bounds cannot be an EQUIVALENCE object" " " { target *-*-* } 8 }
diff --git a/gcc/testsuite/gfortran.dg/pr94030_2.f90 b/gcc/testsuite/gfortran.dg/pr94030_2.f90
new file mode 100644
index 00000000000..84bfdeaa819
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr94030_2.f90
@@ -0,0 +1,33 @@
+! { dg-do compile }
+!
+! Provided by Steve Kargl.
+
+subroutine foo(n,m)
+  integer, intent(in) :: n, m
+  integer a(n)
+  real b(n)
+  equivalence(a,b)
+  if (m /= 2) then
+      a = 1
+      print *, a(1)
+  else
+      b = 42.
+      print *, b(1)
+   end if
+end subroutine 
+
+subroutine bar(m)
+  integer, intent(in) :: m
+  integer x(8)
+  real y(8)
+  equivalence(x,y)
+  if (m /= 2) then
+      x = 1
+      print *, x(1)
+  else
+      y = 42.
+      print *, y(1)
+   end if
+end subroutine 
+
+! { dg-error "Array '.' at .1. with non-constant bounds cannot be an EQUIVALENCE object" " " { target *-*-* } 9 }

commit f722c80a63cf0283acb7f7008c7a145293275d43
Author: Fritz Reese <foreese@gcc.gnu.org>
Date:   Thu Apr 2 13:50:11 2020 -0400

    Backport form master: Fix fortran/85982 ICE in resolve_component.
    
    2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
    
            Backport from master.
            2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
    
            PR fortran/85982
            * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
            attribute checking used by TYPE.
    
    2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
    
            Backport from master.
            2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
    
            PR fortran/85982
            * gfortran.dg/dec_structure_28.f90: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 194ae71f4b0..6509d0d3f9c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
+
+	PR fortran/85982
+	* fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
+	attribute checking used by TYPE.
+
 2020-03-31  Carl Love  <cel@us.ibm.com>
 
 	Backport of:
diff --git a/gcc/fortran/decl.c b/gcc/fortran/decl.c
index 13dd7352d27..8e7327dc568 100644
--- a/gcc/fortran/decl.c
+++ b/gcc/fortran/decl.c
@@ -5236,15 +5236,19 @@ match_attr_spec (void)
       if (d == DECL_STATIC && seen[DECL_SAVE])
 	continue;
 
-      if (gfc_current_state () == COMP_DERIVED
+      if (gfc_comp_struct (gfc_current_state ())
 	  && d != DECL_DIMENSION && d != DECL_CODIMENSION
 	  && d != DECL_POINTER   && d != DECL_PRIVATE
 	  && d != DECL_PUBLIC && d != DECL_CONTIGUOUS && d != DECL_NONE)
 	{
+	  bool is_derived = gfc_current_state () == COMP_DERIVED;
 	  if (d == DECL_ALLOCATABLE)
 	    {
-	      if (!gfc_notify_std (GFC_STD_F2003, "ALLOCATABLE "
-				   "attribute at %C in a TYPE definition"))
+	      if (!gfc_notify_std (GFC_STD_F2003, is_derived
+				   ? G_("ALLOCATABLE attribute at %C in a "
+					"TYPE definition")
+				   : G_("ALLOCATABLE attribute at %C in a "
+					"STRUCTURE definition")))
 		{
 		  m = MATCH_ERROR;
 		  goto cleanup;
@@ -5252,8 +5256,11 @@ match_attr_spec (void)
 	    }
 	  else if (d == DECL_KIND)
 	    {
-	      if (!gfc_notify_std (GFC_STD_F2003, "KIND "
-				   "attribute at %C in a TYPE definition"))
+	      if (!gfc_notify_std (GFC_STD_F2003, is_derived
+				   ? G_("KIND attribute at %C in a "
+					"TYPE definition")
+				   : G_("KIND attribute at %C in a "
+					"STRUCTURE definition")))
 		{
 		  m = MATCH_ERROR;
 		  goto cleanup;
@@ -5276,8 +5283,11 @@ match_attr_spec (void)
 	    }
 	  else if (d == DECL_LEN)
 	    {
-	      if (!gfc_notify_std (GFC_STD_F2003, "LEN "
-				   "attribute at %C in a TYPE definition"))
+	      if (!gfc_notify_std (GFC_STD_F2003, is_derived
+				   ? G_("LEN attribute at %C in a "
+					"TYPE definition")
+				   : G_("LEN attribute at %C in a "
+					"STRUCTURE definition")))
 		{
 		  m = MATCH_ERROR;
 		  goto cleanup;
@@ -5300,8 +5310,10 @@ match_attr_spec (void)
 	    }
 	  else
 	    {
-	      gfc_error ("Attribute at %L is not allowed in a TYPE definition",
-			 &seen_at[d]);
+	      gfc_error (is_derived ? G_("Attribute at %L is not allowed in a "
+					 "TYPE definition")
+				    : G_("Attribute at %L is not allowed in a "
+					 "STRUCTURE definition"), &seen_at[d]);
 	      m = MATCH_ERROR;
 	      goto cleanup;
 	    }
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e033b518c89..da114afcd58 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
+
+	PR fortran/85982
+	* gfortran.dg/dec_structure_28.f90: New test.
+
 2020-04-02  Mark Eggleston <markeggleston@gcc.gnu.org>
 
 	Backport from master
diff --git a/gcc/testsuite/gfortran.dg/dec_structure_28.f90 b/gcc/testsuite/gfortran.dg/dec_structure_28.f90
new file mode 100644
index 00000000000..bab08b2d5c3
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/dec_structure_28.f90
@@ -0,0 +1,35 @@
+! { dg-do compile }
+! { dg-options "-fdec-structure -fdec-static" }
+!
+! PR fortran/85982
+!
+! Test a regression wherein some component attributes were erroneously accepted
+! within a DEC structure.
+!
+
+structure /s/
+  integer :: a
+  integer, intent(in) :: b ! { dg-error "is not allowed" }
+  integer, intent(out) :: c ! { dg-error "is not allowed" }
+  integer, intent(inout) :: d ! { dg-error "is not allowed" }
+  integer, dimension(1,1) :: e ! OK
+  integer, external, pointer :: f ! { dg-error "is not allowed" }
+  integer, intrinsic :: f ! { dg-error "is not allowed" }
+  integer, optional :: g ! { dg-error "is not allowed" }
+  integer, parameter :: h ! { dg-error "is not allowed" }
+  integer, protected :: i ! { dg-error "is not allowed" }
+  integer, private :: j ! { dg-error "is not allowed" }
+  integer, static :: k ! { dg-error "is not allowed" }
+  integer, automatic :: l ! { dg-error "is not allowed" }
+  integer, public :: m ! { dg-error "is not allowed" }
+  integer, save :: n ! { dg-error "is not allowed" }
+  integer, target :: o ! { dg-error "is not allowed" }
+  integer, value :: p ! { dg-error "is not allowed" }
+  integer, volatile :: q ! { dg-error "is not allowed" }
+  integer, bind(c) :: r ! { dg-error "is not allowed" }
+  integer, asynchronous :: t ! { dg-error "is not allowed" }
+  character(len=3) :: v ! OK
+  integer(kind=4) :: w ! OK
+end structure
+
+end

commit f662909010de770ab6c29effb60b83d08abd61ad
Author: Fritz Reese <foreese@gcc.gnu.org>
Date:   Thu Apr 2 14:32:07 2020 -0400

    Indicate backport in changelogs from last commit.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6509d0d3f9c..d8405618b01 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
 
+	Backport from master.
+	2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
+
 	PR fortran/85982
 	* fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
 	attribute checking used by TYPE.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index da114afcd58..6de28943f5e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,8 @@
 2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
 
+	Backport from master.
+	2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
+
 	PR fortran/85982
 	* gfortran.dg/dec_structure_28.f90: New test.
 

commit 905d96d07e50171d986b11c95d98963632fd630f
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Apr 3 00:16:55 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 791b1d8bbc3..9d1fb19b175 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200402
+20200403

commit 33c5b217cbc7562238f96a29393f6ca8fb97482a
Author: Martin Liska <mliska@suse.cz>
Date:   Fri Apr 3 12:36:31 2020 +0200

    Backport 55a7380213a5c16120d5c674fb42b38a3d796b57
    
            Backport from mainline
            2020-04-03  Martin Liska  <mliska@suse.cz>
    
            PR ipa/94445
            * ipa-icf-gimple.c (func_checker::compare_gimple_call):
              Compare type attributes for gimple_call_fntypes.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d8405618b01..60d5efc0a84 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-03  Martin Liska  <mliska@suse.cz>
+
+	Backport from mainline
+	2020-04-03  Martin Liska  <mliska@suse.cz>
+
+	PR ipa/94445
+	* ipa-icf-gimple.c (func_checker::compare_gimple_call):
+	  Compare type attributes for gimple_call_fntypes.
+
 2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
 
 	Backport from master.
diff --git a/gcc/ipa-icf-gimple.c b/gcc/ipa-icf-gimple.c
index 37b9fe73b0a..60691bb5254 100644
--- a/gcc/ipa-icf-gimple.c
+++ b/gcc/ipa-icf-gimple.c
@@ -37,6 +37,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "ipa-utils.h"
 #include "tree-eh.h"
 #include "builtins.h"
+#include "attribs.h"
 
 #include "ipa-icf-gimple.h"
 
@@ -769,6 +770,9 @@ func_checker::compare_gimple_call (gcall *s1, gcall *s2)
       || (fntype1 && !types_compatible_p (fntype1, fntype2)))
     return return_false_with_msg ("call function types are not compatible");
 
+  if (fntype1 && fntype2 && comp_type_attributes (fntype1, fntype2) != 1)
+    return return_false_with_msg ("different fntype attributes");
+
   tree chain1 = gimple_call_chain (s1);
   tree chain2 = gimple_call_chain (s2);
   if ((chain1 && !chain2)

commit afae9879c28a2797c49bf2da51415da70cdd2b83
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Fri Apr 3 12:00:07 2020 +0100

    libstdc++: Fix std::to_address for debug iterators (PR 93960)
    
    It should be valid to use std::to_address on a past-the-end iterator,
    but the debug mode iterators do a check for dereferenceable in their
    operator->(). That check is generally useful, so rather than remove it
    this changes std::__to_address to identify a debug mode iterator and
    use base().operator->() to skip the check.
    
    Backport from mainline
    2020-04-03  Jonathan Wakely  <jwakely@redhat.com>
    
            PR libstdc++/93960
            * include/bits/ptr_traits.h (__to_address): Add special case for debug
            iterators, to avoid dereferenceable check.
            * testsuite/20_util/to_address/1_neg.cc: Adjust dg-error line number.
            * testsuite/20_util/to_address/debug.cc: New test.

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 1d6f972584a..495f6809729 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,14 @@
+2020-04-03  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backport from mainline
+	2020-04-03  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/93960
+	* include/bits/ptr_traits.h (__to_address): Add special case for debug
+	iterators, to avoid dereferenceable check.
+	* testsuite/20_util/to_address/1_neg.cc: Adjust dg-error line number.
+	* testsuite/20_util/to_address/debug.cc: New test.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/libstdc++-v3/include/bits/ptr_traits.h b/libstdc++-v3/include/bits/ptr_traits.h
index 11b6056370a..88261de02d6 100644
--- a/libstdc++-v3/include/bits/ptr_traits.h
+++ b/libstdc++-v3/include/bits/ptr_traits.h
@@ -34,6 +34,10 @@
 
 #include <bits/move.h>
 
+#if __cplusplus > 201703L
+namespace __gnu_debug { struct _Safe_iterator_base; }
+#endif
+
 namespace std _GLIBCXX_VISIBILITY(default)
 {
 _GLIBCXX_BEGIN_NAMESPACE_VERSION
@@ -169,7 +173,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   template<typename _Ptr, typename... _None>
     constexpr auto
     __to_address(const _Ptr& __ptr, _None...) noexcept
-    { return std::__to_address(__ptr.operator->()); }
+    {
+      if constexpr (is_base_of_v<__gnu_debug::_Safe_iterator_base, _Ptr>)
+	return std::__to_address(__ptr.base().operator->());
+      else
+	return std::__to_address(__ptr.operator->());
+    }
 
   /**
    * @brief Obtain address referenced by a pointer to an object
diff --git a/libstdc++-v3/testsuite/20_util/to_address/1_neg.cc b/libstdc++-v3/testsuite/20_util/to_address/1_neg.cc
index e5681de588f..3346253f2a8 100644
--- a/libstdc++-v3/testsuite/20_util/to_address/1_neg.cc
+++ b/libstdc++-v3/testsuite/20_util/to_address/1_neg.cc
@@ -17,7 +17,7 @@
 
 // { dg-options "-std=gnu++2a" }
 // { dg-do compile { target c++2a } }
-// { dg-error "not a function pointer" "" { target *-*-* } 153 }
+// { dg-error "not a function pointer" "" { target *-*-* } 157 }
 
 #include <memory>
 
diff --git a/libstdc++-v3/testsuite/20_util/to_address/debug.cc b/libstdc++-v3/testsuite/20_util/to_address/debug.cc
new file mode 100644
index 00000000000..4555284416d
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/to_address/debug.cc
@@ -0,0 +1,36 @@
+// Copyright (C) 2020 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-std=gnu++2a" }
+// { dg-do run { target c++2a } }
+
+#include <debug/vector>
+#include <testsuite_hooks.h>
+
+void
+test01()
+{
+  __gnu_debug::vector<int> v{1, 2, 3};
+  auto p = std::to_address(v.end());
+  VERIFY( p == v.data() + v.size() );
+}
+
+int
+main()
+{
+  test01();
+}

commit b445ceec81ba3f4afad8c3ead1e58f14f1c2e146
Author: Martin Jambor <mjambor@suse.cz>
Date:   Fri Apr 3 22:01:17 2020 +0200

    gcc-8 sra: Cap number of sub-access propagations with a param (PR 93435)
    
    This is non-trivial but rather straightforward backport of
    29f23ed79b60949fc60f6fdbbd931bd58090b241 from master.  See
    https://gcc.gnu.org/pipermail/gcc-patches/2020-March/542390.html for
    more information.
    
    Bootstrapped and tested on gcc-8 branch.
    
    2020-04-03  Martin Jambor  <mjambor@suse.cz>
    
            PR tree-optimization/93435
            * params.def (PARAM_SRA_MAX_PROPAGATIONS): New parameter.
            * tree-sra.c (propagation_budget): New variable.
            (budget_for_propagation_access): New function.
            (propagate_subaccesses_across_link): Use it.
            (propagate_all_subaccesses): Set up and destroy propagation_budget.
            * doc/invoke.texi (sra-max-propagations): New.
    
            testsuite/
            * gcc.dg/tree-ssa/pr93435.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 60d5efc0a84..c82e77a6ce9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2020-04-03  Martin Jambor  <mjambor@suse.cz>
+
+	PR tree-optimization/93435
+	* params.def (PARAM_SRA_MAX_PROPAGATIONS): New parameter.
+	* tree-sra.c (propagation_budget): New variable.
+	(budget_for_propagation_access): New function.
+	(propagate_subaccesses_across_link): Use it.
+	(propagate_all_subaccesses): Set up and destroy propagation_budget.
+	* doc/invoke.texi (sra-max-propagations): New.
+
 2020-04-03  Martin Liska  <mliska@suse.cz>
 
 	Backport from mainline
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 83c95892029..c138a0e84ce 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -10907,6 +10907,11 @@ speed
 (@option{sra-max-scalarization-size-Ospeed}) or size
 (@option{sra-max-scalarization-size-Osize}) respectively.
 
+@item sra-max-propagations
+The maximum number of artificial accesses that Scalar Replacement of
+Aggregates (SRA) will track, per one local variable, in order to
+facilitate copy propagation.
+
 @item tm-max-aggregate-size
 When making copies of thread-local variables in a transaction, this
 parameter specifies the size in bytes after which variables are
diff --git a/gcc/params.def b/gcc/params.def
index 74215f24a4f..e54483c4606 100644
--- a/gcc/params.def
+++ b/gcc/params.def
@@ -1017,6 +1017,13 @@ DEFPARAM (PARAM_SRA_MAX_SCALARIZATION_SIZE_SIZE,
 	  "considered for scalarization when compiling for size.",
 	  0, 0, 0)
 
+DEFPARAM (PARAM_SRA_MAX_PROPAGATIONS,
+	  "sra-max-propagations",
+	  "Maximum number of artificial accesses to enable forward propagation "
+	  "that Scalar Replacement of Aggregates will keep for one local "
+	  "variable.",
+	  32, 0, 0)
+
 DEFPARAM (PARAM_IPA_CP_VALUE_LIST_SIZE,
 	  "ipa-cp-value-list-size",
 	  "Maximum size of a list of values associated with each parameter for "
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6de28943f5e..dc0d4118255 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-03  Martin Jambor  <mjambor@suse.cz>
+
+	PR tree-optimization/93435
+	* gcc.dg/tree-ssa/pr93435.c: New test.
+
 2020-04-02  Fritz Reese  <foreese@gcc.gnu.org>
 
 	Backport from master.
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr93435.c b/gcc/testsuite/gcc.dg/tree-ssa/pr93435.c
new file mode 100644
index 00000000000..cb8e7495b15
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr93435.c
@@ -0,0 +1,159 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef signed char int8_T;
+typedef int int32_T;
+
+typedef struct {
+  int8_T a;
+} struct0_T;
+
+typedef struct {
+  struct0_T f10[4];
+} struct_T;
+
+typedef struct {
+  struct_T f9[4];
+} b_struct_T;
+
+typedef struct {
+  b_struct_T f8[4];
+} c_struct_T;
+
+typedef struct {
+  c_struct_T f7[4];
+} d_struct_T;
+
+typedef struct {
+  d_struct_T f6[4];
+} e_struct_T;
+
+typedef struct {
+  e_struct_T f5[4];
+} f_struct_T;
+
+typedef struct {
+  f_struct_T f4[4];
+} g_struct_T;
+
+typedef struct {
+  g_struct_T f3[4];
+} h_struct_T;
+
+typedef struct {
+  h_struct_T f2[4];
+} i_struct_T;
+
+typedef struct {
+  i_struct_T f1[4];
+} j_struct_T;
+
+typedef struct {
+  struct {
+    j_struct_T ds21[4];
+    i_struct_T ds20[4];
+    i_struct_T r9;
+  } f0;
+} deep_struct_arraysStackData;
+
+/* Function Definitions */
+void deep_struct_arrays(deep_struct_arraysStackData *SD,
+  int8_T in1, int8_T inCount, int8_T *out1, int8_T *out2, struct0_T out3[4])
+{
+  struct0_T r;
+  struct_T r1;
+  b_struct_T r2;
+  c_struct_T r3;
+  d_struct_T r4;
+  e_struct_T r5;
+  f_struct_T r6;
+  g_struct_T r7;
+  h_struct_T r8;
+  int32_T count;
+  int32_T i;
+
+  /*  Check properties of input in1 */
+  /*  Check properties of input inCount */
+  /*  Copyright 2006 The MathWorks, Inc. */
+  r.a = in1;
+  r1.f10[0] = r;
+  r1.f10[1] = r;
+  r1.f10[2] = r;
+  r1.f10[3] = r;
+  r2.f9[0] = r1;
+  r2.f9[1] = r1;
+  r2.f9[2] = r1;
+  r2.f9[3] = r1;
+  r3.f8[0] = r2;
+  r3.f8[1] = r2;
+  r3.f8[2] = r2;
+  r3.f8[3] = r2;
+  r4.f7[0] = r3;
+  r4.f7[1] = r3;
+  r4.f7[2] = r3;
+  r4.f7[3] = r3;
+  r5.f6[0] = r4;
+  r5.f6[1] = r4;
+  r5.f6[2] = r4;
+  r5.f6[3] = r4;
+  r6.f5[0] = r5;
+  r6.f5[1] = r5;
+  r6.f5[2] = r5;
+  r6.f5[3] = r5;
+  r7.f4[0] = r6;
+  r7.f4[1] = r6;
+  r7.f4[2] = r6;
+  r7.f4[3] = r6;
+  r8.f3[0] = r7;
+  r8.f3[1] = r7;
+  r8.f3[2] = r7;
+  r8.f3[3] = r7;
+  SD->f0.r9.f2[0] = r8;
+  SD->f0.r9.f2[1] = r8;
+  SD->f0.r9.f2[2] = r8;
+  SD->f0.r9.f2[3] = r8;
+  SD->f0.ds20[0] = SD->f0.r9;
+  SD->f0.ds20[3] = SD->f0.r9;
+  count = 0;
+  while (count < inCount) {
+    i = in1 + SD->f0.ds20[0].f2[0].f3[0].f4[0].f5[0].f6[0].f7[0].f8[0].f9[0]
+      .f10[0].a;
+    if (i > 127) {
+      i = 127;
+    } else {
+      if (i < -128) {
+        i = -128;
+      }
+    }
+
+    SD->f0.ds20[0].f2[0].f3[0].f4[0].f5[0].f6[0].f7[0].f8[0].f9[0].f10[0].a =
+      (int8_T)i;
+    i = SD->f0.ds20[3].f2[3].f3[3].f4[3].f5[3].f6[3].f7[3].f8[3].f9[3].f10[3].a
+      + 3;
+    if (i > 127) {
+      i = 127;
+    }
+
+    SD->f0.ds20[3].f2[3].f3[3].f4[3].f5[3].f6[3].f7[3].f8[3].f9[3].f10[3].a =
+      (int8_T)i;
+    count++;
+  }
+
+  if (inCount > 10) {
+    SD->f0.ds21[0].f1[1].f2[2].f3[3].f4[3].f5[3].f6[3].f7[3].f8[3].f9[3].f10[3].
+      a = 14;
+  } else {
+    SD->f0.ds21[0].f1[1].f2[2].f3[3].f4[3].f5[3].f6[3].f7[3].f8[3].f9[3].f10[3].
+      a = 16;
+  }
+
+  *out1 = SD->f0.ds20[0].f2[0].f3[0].f4[0].f5[0].f6[0].f7[0].f8[0].f9[0].f10[0].
+    a;
+  *out2 = SD->f0.ds20[3].f2[3].f3[3].f4[3].f5[3].f6[3].f7[3].f8[3].f9[3].f10[3].
+    a;
+  out3[0] = r;
+  out3[1] = r;
+  out3[2] = r;
+  out3[3] = SD->f0.ds21[0].f1[1].f2[2].f3[3].f4[3].f5[3].f6[3].f7[3].f8[3].f9[3]
+    .f10[3];
+}
diff --git a/gcc/tree-sra.c b/gcc/tree-sra.c
index e1ebdfaa225..264e1282c5a 100644
--- a/gcc/tree-sra.c
+++ b/gcc/tree-sra.c
@@ -291,6 +291,9 @@ static object_allocator<assign_link> assign_link_pool ("SRA links");
 /* Base (tree) -> Vector (vec<access_p> *) map.  */
 static hash_map<tree, auto_vec<access_p> > *base_access_vec;
 
+/* Hash to limit creation of artificial accesses */
+static hash_map<tree, unsigned> *propagation_budget;
+
 /* Candidate hash table helpers.  */
 
 struct uid_decl_hasher : nofree_ptr_hash <tree_node>
@@ -2665,6 +2668,32 @@ subtree_mark_written_and_enqueue (struct access *access)
     subtree_mark_written_and_enqueue (child);
 }
 
+/* If there is still budget to create a propagation access for DECL, return
+   true and decrement the budget.  Otherwise return false.  */
+
+static bool
+budget_for_propagation_access (tree decl)
+{
+  unsigned b, *p = propagation_budget->get (decl);
+  if (p)
+    b = *p;
+  else
+    b = PARAM_SRA_MAX_PROPAGATIONS;
+
+  if (b == 0)
+    return false;
+  b--;
+
+  if (b == 0 && dump_file && (dump_flags & TDF_DETAILS))
+    {
+      fprintf (dump_file, "The propagation budget of ");
+      print_generic_expr (dump_file, decl);
+      fprintf (dump_file, " (UID: %u) has been exhausted.\n", DECL_UID (decl));
+    }
+  propagation_budget->put (decl, b);
+  return true;
+}
+
 /* Propagate subaccesses and grp_write flags of RACC across an assignment link
    to LACC.  Enqueue sub-accesses as necessary so that the write flag is
    propagated transitively.  Return true if anything changed.  Additionally, if
@@ -2765,7 +2794,8 @@ propagate_subaccesses_across_link (struct access *lacc, struct access *racc)
 	  continue;
 	}
 
-      if (rchild->grp_unscalarizable_region)
+      if (rchild->grp_unscalarizable_region
+	  || !budget_for_propagation_access (lacc->base))
 	{
 	  if (rchild->grp_write && !lacc->grp_write)
 	    {
@@ -2795,6 +2825,7 @@ propagate_subaccesses_across_link (struct access *lacc, struct access *racc)
 static void
 propagate_all_subaccesses (void)
 {
+  propagation_budget = new hash_map<tree, unsigned>;
   while (work_queue_head)
     {
       struct access *racc = pop_access_from_work_queue ();
@@ -2833,6 +2864,7 @@ propagate_all_subaccesses (void)
 	    while (lacc);
 	}
     }
+  delete propagation_budget;
 }
 
 /* Go through all accesses collected throughout the (intraprocedural) analysis

commit fa63b36943448336219d8847278bb888e1ab1c09
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Apr 4 00:16:53 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 9d1fb19b175..860e4ad09fd 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200403
+20200404

commit c4f6911d39089c5f500977d9fc0e36c72f2018a7
Author: Jason Merrill <jason@redhat.com>
Date:   Thu Apr 2 23:40:46 2020 -0400

    c++: alias template and parameter packs (PR91966).
    
    In this testcase, when we do a pack expansion of count_better_mins<nums>,
    nums appears both in the definition of count_better_mins and as its template
    argument.  The intent is that we get a expansion over pairs of elements of
    the pack, i.e. less<2,2>, less<2,7>, less<7,2>, ....  But if we substitute
    into the definition of count_better_mins when parsing the template, we end
    up with sum<less<nums,nums>...>, which never gives us less<2,7>.  We could
    deal with this by somehow marking up the use of 'nums' as an argument for
    'num', but it's simpler to mark the alias as complex, so we need to
    instantiate it later with all its arguments rather than replace it early
    with its expansion.
    
    gcc/cp/ChangeLog
    2020-04-03  Jason Merrill  <jason@redhat.com>
    
            PR c++/91966
            * pt.c (complex_pack_expansion_r): New.
            (complex_alias_template_p): Use it.

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 7651d0e833f..e7a49b20082 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-03  Jason Merrill  <jason@redhat.com>
+
+	PR c++/91966
+	* pt.c (complex_pack_expansion_r): New.
+	(complex_alias_template_p): Use it.
+
 2020-03-27  Nathan Sidwell  <nathan@acm.org>
 
 	PR c++/84733
diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index 527d6f9f9b1..4673c27468e 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -6186,6 +6186,33 @@ uses_all_template_parms_r (tree t, void *data_)
   return 0;
 }
 
+/* for_each_template_parm any_fn callback for complex_alias_template_p.  */
+
+static int
+complex_pack_expansion_r (tree t, void *data_)
+{
+  /* An alias template with a pack expansion that expands a pack from the
+     enclosing class needs to be considered complex, to avoid confusion with
+     the same pack being used as an argument to the alias's own template
+     parameter (91966).  */
+  if (!PACK_EXPANSION_P (t))
+    return 0;
+  struct uses_all_template_parms_data &data
+    = *(struct uses_all_template_parms_data*)data_;
+  for (tree pack = PACK_EXPANSION_PARAMETER_PACKS (t); pack;
+       pack = TREE_CHAIN (pack))
+    {
+      tree parm_pack = TREE_VALUE (pack);
+      if (!TEMPLATE_PARM_P (parm_pack))
+	continue;
+      int idx, level;
+      template_parm_level_and_index (parm_pack, &level, &idx);
+      if (level < data.level)
+	return 1;
+    }
+  return 0;
+}
+
 static bool
 complex_alias_template_p (const_tree tmpl)
 {
@@ -6198,7 +6225,9 @@ complex_alias_template_p (const_tree tmpl)
   for (int i = 0; i < len; ++i)
     data.seen[i] = false;
 
-  for_each_template_parm (pat, uses_all_template_parms_r, &data, NULL, true);
+  if (for_each_template_parm (pat, uses_all_template_parms_r, &data,
+			      NULL, true, complex_pack_expansion_r))
+    return true;
   for (int i = 0; i < len; ++i)
     if (!data.seen[i])
       return true;
diff --git a/gcc/testsuite/g++.dg/cpp0x/variadic-alias2.C b/gcc/testsuite/g++.dg/cpp0x/variadic-alias2.C
new file mode 100644
index 00000000000..ab64866d35f
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/variadic-alias2.C
@@ -0,0 +1,103 @@
+// PR c++/91966
+// { dg-do compile { target c++11 } }
+
+// Reduced to this include-free example. Further reduction is hard: Either
+// the bug(?) disappears, or the program becomes meaningless.
+
+template<class...>
+struct list {};
+
+struct nil;
+
+////////////////////////////////////////////////////////////////////////////////
+
+template<int n>
+struct number {
+  constexpr /*implicit*/ operator int() const { return n; }
+  using type = number<n>;
+};
+
+using false_ = number<0>;
+using true_ = number<1>;
+
+static_assert(!false_{}, "");
+static_assert(true_{}, "");
+
+template<int... ns> using numbers = list<number<ns>...>;
+
+////////////////////////////////////////////////////////////////////////////////
+
+template<class lhs, class rhs>
+struct less_impl;
+
+template<int lhs, int rhs>
+struct less_impl<number<lhs>, number<rhs>>
+  : number<(lhs < rhs)> {};
+
+template<class lhs, class rhs> using less = typename less_impl<lhs, rhs>::type;
+
+////////////////////////////////////////////////////////////////////////////////
+
+template<class v0, class... vs>
+struct sum_impl {
+  static_assert(sizeof...(vs) == 0, "see specialization");
+  using type = v0;
+};
+
+template<int v0, int v1, class... vs>
+struct sum_impl<number<v0>, number<v1>, vs...>
+  : sum_impl<number<v0 + v1>, vs...> {};
+
+template<class... nums> using sum = typename sum_impl<nums...>::type;
+
+////////////////////////////////////////////////////////////////////////////////
+
+template<class num>
+struct conditional_impl {
+  static_assert(num{}, "see specialization");
+
+  template<class T, class F>
+  using type = T;
+};
+
+template<>
+struct conditional_impl<false_> {
+  template<class T, class F>
+  using type = F;
+};
+
+template<class num, class T, class F>
+using conditional = typename conditional_impl<num>::template type<T, F>;
+
+////////////////////////////////////////////////////////////////////////////////
+
+template<class seq>
+struct min_filter_impl;
+
+template<class... nums>
+struct min_filter_impl<list<nums...>> {
+  template<class num>
+  using count_better_mins = sum<less<nums, num>...>;
+
+  using type = list<conditional<count_better_mins<nums>, nil, nums>...>;
+
+//using debug = list<conditional<count_better_mins<nums>, nil, void>...>;
+
+// error: expansion pattern 'conditional<typename sum_impl<less<nums, nums>...>::type, nil, void>' contains no parameter packs
+
+};
+
+template<class seq> using min_filter = typename min_filter_impl<seq>::type;
+
+////////////////////////////////////////////////////////////////////////////////
+
+void test_min_filter() {
+  using computed = min_filter<numbers<2, 7, 2>>;
+  using expected = list<number<2>, nil, number<2>>;
+  (void)(computed{} = expected{});// compiles for identical types
+
+// error: no match for 'operator=' (operand types are 'computed' {aka 'list<number<2>, number<7>, number<2> >'} and 'expected' {aka 'list<number<2>, nil, number<2> >'})
+
+}
+
+int main() {}

commit e42d142f421c132ceeee3aca3a5b3f0176bd363d
Author: Jason Merrill <jason@redhat.com>
Date:   Sat Apr 4 11:45:41 2020 -0400

    c++: Mangling of dependent conversions [PR91377]
    
    We skip over other conversion codes when mangling expressions, we should do
    the same with IMPLICIT_CONV_EXPR.
    
    gcc/cp/ChangeLog
    2020-04-04  Jason Merrill  <jason@redhat.com>
    
            PR c++/91377
            * mangle.c (write_expression): Skip IMPLICIT_CONV_EXPR.

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index e7a49b20082..d1d829a8bca 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-04  Jason Merrill  <jason@redhat.com>
+
+	PR c++/91377
+	* mangle.c (write_expression): Skip IMPLICIT_CONV_EXPR.
+
 2020-04-03  Jason Merrill  <jason@redhat.com>
 
 	PR c++/91966
diff --git a/gcc/cp/mangle.c b/gcc/cp/mangle.c
index ac90e47fc94..a95eab4ba69 100644
--- a/gcc/cp/mangle.c
+++ b/gcc/cp/mangle.c
@@ -2902,6 +2902,7 @@ write_expression (tree expr)
   /* Skip NOP_EXPR and CONVERT_EXPR.  They can occur when (say) a pointer
      argument is converted (via qualification conversions) to another type.  */
   while (CONVERT_EXPR_CODE_P (code)
+	 || code == IMPLICIT_CONV_EXPR
 	 || location_wrapper_p (expr)
 	 /* Parentheses aren't mangled.  */
 	 || code == PAREN_EXPR
diff --git a/gcc/testsuite/g++.dg/abi/mangle75.C b/gcc/testsuite/g++.dg/abi/mangle75.C
new file mode 100644
index 00000000000..f2661997a33
--- /dev/null
+++ b/gcc/testsuite/g++.dg/abi/mangle75.C
@@ -0,0 +1,13 @@
+// PR c++/91377
+// { dg-do compile { target c++11 } }
+
+struct f {
+  static constexpr int d = 3;
+  typedef int e;
+};
+template <int a> struct x { };
+template <typename g, g j, g m> using n = x<j + m>;
+template <typename ac> auto v() -> n<typename ac::e, 0, ac::d>;
+void af() { v<f>(); }
+
+// { dg-final { scan-assembler "_Z1vI1fE1xIXplLi0EsrT_1dEEv" } }

commit 15abbf3f217f516729d03863e6673bb0b74f6639
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Apr 5 00:16:52 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 860e4ad09fd..4620826ac97 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200404
+20200405

commit 2b9d5e0e59dfe5beb71e42d312650ec0cae35f3c
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Apr 6 00:16:49 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4620826ac97..e17e404e8b2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200405
+20200406

commit 6bdef867e21eb667be537c4987bda965dcb61b9c
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Apr 7 00:16:57 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e17e404e8b2..ea8a4ef5088 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200406
+20200407

commit 11b19dfc082607e5049f72f1ef954fda7b42e8d4
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 7 08:27:49 2020 +0200

    i386: Fix emit_reduc_half on V{64Q,32H}Imode [PR94500]
    
    The following testcase is miscompiled in 8.x, because emit_reduc_half is
    prepared to handle for 512-bit modes only i equal to 512, 256, 128 and 64.
    V32HImode also needs i equal to 32 and V64QImode i equal to 32 and 16,
    but emit_reduc_half in that case performs a redundant permutation exactly
    like i == 32.  In 9+ the testcase works because Richard in r9-3393
    changed the reduc_* expanders so that they actually don't call
    ix86_expand_reduc on 512-bit modes, but only 128-bit ones.
    
    The patch fixes emit_reduc_half to handle also i of 32 and 16 similarly to
    how V32QImode/V16HImode are handled for AVX2.  I think it shouldn't hurt
    to fix the function even on the trunk and 9 branch even when nothing uses
    it ATM.
    
    2020-04-07  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94500
            * config/i386/i386.c (emit_reduc_half): For V{64QI,32HI}mode
            handle i < 64 using avx512bw_lshrv4ti3.  Formatting fixes.
    
            * gcc.target/i386/avx512bw-pr94500.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c82e77a6ce9..046cc261e4b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94500
+	* config/i386/i386.c (emit_reduc_half): For V{64QI,32HI}mode
+	handle i < 64 using avx512bw_lshrv4ti3.  Formatting fixes.
+
 2020-04-03  Martin Jambor  <mjambor@suse.cz>
 
 	PR tree-optimization/93435
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 2fe0c8bc4f8..13943ebf800 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -44528,43 +44528,51 @@ emit_reduc_half (rtx dest, rtx src, int i)
       break;
     case E_V64QImode:
     case E_V32HImode:
+      if (i < 64)
+	{
+	  d = gen_reg_rtx (V4TImode);
+	  tem = gen_avx512bw_lshrv4ti3 (d, gen_lowpart (V4TImode, src),
+					GEN_INT (i / 2));
+	  break;
+	}
+      /* FALLTHRU */
     case E_V16SImode:
     case E_V16SFmode:
     case E_V8DImode:
     case E_V8DFmode:
       if (i > 128)
 	tem = gen_avx512f_shuf_i32x4_1 (gen_lowpart (V16SImode, dest),
-				      gen_lowpart (V16SImode, src),
-				      gen_lowpart (V16SImode, src),
-				      GEN_INT (0x4 + (i == 512 ? 4 : 0)),
-				      GEN_INT (0x5 + (i == 512 ? 4 : 0)),
-				      GEN_INT (0x6 + (i == 512 ? 4 : 0)),
-				      GEN_INT (0x7 + (i == 512 ? 4 : 0)),
-				      GEN_INT (0xC), GEN_INT (0xD),
-				      GEN_INT (0xE), GEN_INT (0xF),
-				      GEN_INT (0x10), GEN_INT (0x11),
-				      GEN_INT (0x12), GEN_INT (0x13),
-				      GEN_INT (0x14), GEN_INT (0x15),
-				      GEN_INT (0x16), GEN_INT (0x17));
+					gen_lowpart (V16SImode, src),
+					gen_lowpart (V16SImode, src),
+					GEN_INT (0x4 + (i == 512 ? 4 : 0)),
+					GEN_INT (0x5 + (i == 512 ? 4 : 0)),
+					GEN_INT (0x6 + (i == 512 ? 4 : 0)),
+					GEN_INT (0x7 + (i == 512 ? 4 : 0)),
+					GEN_INT (0xC), GEN_INT (0xD),
+					GEN_INT (0xE), GEN_INT (0xF),
+					GEN_INT (0x10), GEN_INT (0x11),
+					GEN_INT (0x12), GEN_INT (0x13),
+					GEN_INT (0x14), GEN_INT (0x15),
+					GEN_INT (0x16), GEN_INT (0x17));
       else
 	tem = gen_avx512f_pshufd_1 (gen_lowpart (V16SImode, dest),
-				   gen_lowpart (V16SImode, src),
-				   GEN_INT (i == 128 ? 0x2 : 0x1),
-				   GEN_INT (0x3),
-				   GEN_INT (0x3),
-				   GEN_INT (0x3),
-				   GEN_INT (i == 128 ? 0x6 : 0x5),
-				   GEN_INT (0x7),
-				   GEN_INT (0x7),
-				   GEN_INT (0x7),
-				   GEN_INT (i == 128 ? 0xA : 0x9),
-				   GEN_INT (0xB),
-				   GEN_INT (0xB),
-				   GEN_INT (0xB),
-				   GEN_INT (i == 128 ? 0xE : 0xD),
-				   GEN_INT (0xF),
-				   GEN_INT (0xF),
-				   GEN_INT (0xF));
+				    gen_lowpart (V16SImode, src),
+				    GEN_INT (i == 128 ? 0x2 : 0x1),
+				    GEN_INT (0x3),
+				    GEN_INT (0x3),
+				    GEN_INT (0x3),
+				    GEN_INT (i == 128 ? 0x6 : 0x5),
+				    GEN_INT (0x7),
+				    GEN_INT (0x7),
+				    GEN_INT (0x7),
+				    GEN_INT (i == 128 ? 0xA : 0x9),
+				    GEN_INT (0xB),
+				    GEN_INT (0xB),
+				    GEN_INT (0xB),
+				    GEN_INT (i == 128 ? 0xE : 0xD),
+				    GEN_INT (0xF),
+				    GEN_INT (0xF),
+				    GEN_INT (0xF));
       break;
     default:
       gcc_unreachable ();
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index dc0d4118255..6de08c83f0d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94500
+	* gcc.target/i386/avx512bw-pr94500.c: New test.
+
 2020-04-03  Martin Jambor  <mjambor@suse.cz>
 
 	PR tree-optimization/93435
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-pr94500.c b/gcc/testsuite/gcc.target/i386/avx512bw-pr94500.c
new file mode 100644
index 00000000000..7effdac5a17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-pr94500.c
@@ -0,0 +1,28 @@
+/* PR target/94500 */
+/* { dg-do run { target avx512bw } } */
+/* { dg-options "-O3 -mavx512bw -mprefer-vector-width=512" } */
+
+#define AVX512BW
+#include "avx512f-helper.h"
+
+__attribute__((noipa)) signed char
+foo (signed char *p)
+{
+  signed char r = 0;
+  int i;
+  for (i = 0; i < 256; i++)
+    if (p[i] > r) r = p[i];
+  return r;
+}
+
+signed char buf[256];
+
+static void
+TEST (void)
+{
+  int i;
+  for (i = 0; i < 256; i++)
+    buf[i] = i - 128;
+  if (foo (buf) != 127)
+    abort ();
+}

commit 09f2293fac1785681f8ceaf6ae6d2d5cfe519b08
Author: Will Schmidt <will_schmidt@vnet.ibm.com>
Date:   Tue Apr 7 16:32:39 2020 -0500

    rs6000 pragma fix backport from mainline to gcc-8
    
        2020-04-07  Will Schmidt  <will_schmidt@vnet.ibm.com>
    
        Backport from mainline.
            2020-03-23  Will Schmidt  <will_schmidt@vnet.ibm.com>
    
            * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove
            code to skip defining builtins based on builtin_mask.
    
            * gcc.target/powerpc/pragma_power6.c: New.
            * gcc.target/powerpc/pragma_power7.c: New.
            * gcc.target/powerpc/pragma_power8.c: New.
            * gcc.target/powerpc/pragma_power9.c: New.
            * gcc.target/powerpc/pragma_misc9.c: New.
            * gcc.target/powerpc/vsu/pragma_misc9.c: New.
            * gcc.target/powerpc/vsu/vec-all-nez-7.c: Update.
            * gcc.target/powerpc/vsu/vec-any-eqz-7.c: Update.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 046cc261e4b..7d52e3d2ddf 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-04-07  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	Backport from mainline.
+	2020-03-23  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* config/rs6000/rs6000-call.c altivec_init_builtins(): Remove
+	code to skip defining builtins based on builtin_mask.
+
 2020-04-07  Jakub Jelinek  <jakub@redhat.com>
 
 	PR target/94500
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index c868015dc9e..95643c01b5a 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -17622,7 +17622,6 @@ altivec_init_builtins (void)
   size_t i;
   tree ftype;
   tree decl;
-  HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
 
   tree pvoid_type_node = build_pointer_type (void_type_node);
 
@@ -17984,17 +17983,8 @@ altivec_init_builtins (void)
   d = bdesc_dst;
   for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
     {
-      HOST_WIDE_INT mask = d->mask;
-
       /* It is expected that these dst built-in functions may have
 	 d->icode equal to CODE_FOR_nothing.  */
-      if ((mask & builtin_mask) != mask)
-	{
-	  if (TARGET_DEBUG_BUILTIN)
-	    fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
-		     d->name);
-	  continue;
-	}
       def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
     }
 
@@ -18004,15 +17994,6 @@ altivec_init_builtins (void)
     {
       machine_mode mode1;
       tree type;
-      HOST_WIDE_INT mask = d->mask;
-
-      if ((mask & builtin_mask) != mask)
-	{
-	  if (TARGET_DEBUG_BUILTIN)
-	    fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
-		     d->name);
-	  continue;
-	}
 
       if (rs6000_overloaded_builtin_p (d->code))
 	mode1 = VOIDmode;
@@ -18059,15 +18040,6 @@ altivec_init_builtins (void)
     {
       machine_mode mode0;
       tree type;
-      HOST_WIDE_INT mask = d->mask;
-
-      if ((mask & builtin_mask) != mask)
-	{
-	  if (TARGET_DEBUG_BUILTIN)
-	    fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
-		     d->name);
-	  continue;
-	}
 
       /* Cannot define builtin if the instruction is disabled.  */
       gcc_assert (d->icode != CODE_FOR_nothing);
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6de08c83f0d..59c802200a9 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2020-04-07  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	Backport from mainline.
+	2020-03-23  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* gcc.target/powerpc/pragma_power6.c: New.
+	* gcc.target/powerpc/pragma_power7.c: New.
+	* gcc.target/powerpc/pragma_power8.c: New.
+	* gcc.target/powerpc/pragma_power9.c: New.
+	* gcc.target/powerpc/pragma_misc9.c: New.
+	* gcc.target/powerpc/vsu/pragma_misc9.c: New.
+	* gcc.target/powerpc/vsu/vec-all-nez-7.c: Update.
+	* gcc.target/powerpc/vsu/vec-any-eqz-7.c: Update.
+
 2020-04-07  Jakub Jelinek  <jakub@redhat.com>
 
 	PR target/94500
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
new file mode 100644
index 00000000000..605c61a0d94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mcpu=power9 -maltivec -O2" } */
+
+/* Ensure that if we set a pragma gcc target for an
+   older processor, we do not compile builtins that
+   the older target does not support.  */
+
+#include <altivec.h>
+
+vector bool int
+test1 (vector signed int a, vector signed int b)
+{
+  return vec_cmpnez (a, b);
+}
+
+#pragma GCC target ("cpu=power8")
+vector bool int
+test2 (vector signed int a, vector signed int b)
+{
+  return vec_cmpnez (a, b);
+  /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */
+}
+
+#pragma GCC target ("cpu=power7")
+vector signed int
+test3 (vector signed int a, vector signed int b)
+{
+  return vec_mergee (a, b);
+  /* { dg-error "'__builtin_altivec_vmrgew_v4si' requires the '-mpower8-vector' option" "" { target *-*-* } .-1 } */
+}
+
+#pragma GCC target ("cpu=power6")
+vector signed int
+test4 (vector int a, vector int b)
+{
+  return vec_sldw (a, b, 2);
+  /* { dg-error "'__builtin_vsx_xxsldwi_4si' requires the '-mvsx' option" "" { target *-*-* } .-1 } */
+}
+
+vector int
+test5 (vector int a, vector int b)
+{
+  return vec_add (a, b);
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_power6.c b/gcc/testsuite/gcc.target/powerpc/pragma_power6.c
new file mode 100644
index 00000000000..7bd13491dd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_power6.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-mcpu=power6 -maltivec -O2" } */
+
+#include <altivec.h>
+
+#pragma GCC target ("cpu=power6,altivec")
+#ifdef _ARCH_PWR6
+vector int
+isa_2_05 (vector int a, vector int b)
+{
+  return vec_add (a, b);
+}
+#else
+#error failed power6 pragma target
+#endif
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_power7.c b/gcc/testsuite/gcc.target/powerpc/pragma_power7.c
new file mode 100644
index 00000000000..06a7793baf6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_power7.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mcpu=power6 -maltivec -O2" } */
+
+#include <altivec.h>
+
+#pragma GCC target ("cpu=power6,altivec")
+#ifdef _ARCH_PWR6
+vector int
+test1 (vector int a, vector int b)
+{
+  return vec_add (a, b);
+}
+#else
+#error failed power6 pragma target
+#endif
+
+#pragma GCC target ("cpu=power7")
+/* Force a re-read of altivec.h with new cpu target. */
+#undef _ALTIVEC_H
+#include <altivec.h>
+#ifdef _ARCH_PWR7
+vector signed int
+test2 (vector signed int a, vector signed int b)
+{
+  return vec_sldw (a, b, 3);
+}
+#else
+#error failed to set power7 pragma target
+#endif
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_power8.c b/gcc/testsuite/gcc.target/powerpc/pragma_power8.c
new file mode 100644
index 00000000000..1922890bdbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_power8.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power6 -maltivec -O2" } */
+
+#include <altivec.h>
+
+#pragma GCC target ("cpu=power6,altivec")
+#ifdef _ARCH_PWR6
+vector int
+test1 (vector int a, vector int b)
+{
+  return vec_add (a, b);
+}
+#else
+#error failed power6 pragma target
+#endif
+
+#pragma GCC target ("cpu=power7")
+/* Force a re-read of altivec.h with new cpu target. */
+#undef _ALTIVEC_H
+#include <altivec.h>
+#ifdef _ARCH_PWR7
+vector signed int
+test2 (vector signed int a, vector signed int b)
+{
+  return vec_sldw (a, b, 3);
+}
+#else
+#error failed to set power7 pragma target
+#endif
+
+#pragma GCC target ("cpu=power8")
+/* Force a re-read of altivec.h with new cpu target. */
+#undef _ALTIVEC_H
+#include <altivec.h>
+#ifdef _ARCH_PWR8
+vector int
+test3 (vector int a, vector int b)
+{
+  return vec_mergee (a, b);
+}
+typedef __attribute__((altivec(vector__))) long vec_t;
+int
+test3b (vec_t a, vec_t b)
+{
+  return __builtin_vec_vcmpeq_p (2, a, b);
+}
+#else
+#error failed to set power8 pragma target.
+#endif
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_power9.c b/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
new file mode 100644
index 00000000000..1b14ee5ec3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pragma_power9.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mcpu=power6 -maltivec -O2" } */
+
+#include <altivec.h>
+
+#ifdef _ARCH_PWR6
+vector int
+test1 (vector int a, vector int b)
+{
+  return vec_add (a, b);
+}
+#else
+#error failed on default power6 pragma target
+#endif
+
+#pragma GCC target ("cpu=power7")
+#undef _ALTIVEC_H
+#include <altivec.h>
+#ifdef _ARCH_PWR7
+vector signed int
+test2 (vector signed int a, vector signed int b)
+{
+  return vec_sldw (a, b, 3);
+}
+#else
+#error failed to set power7 pragma target
+#endif
+
+#pragma GCC target ("cpu=power8")
+#undef _ALTIVEC_H
+#include <altivec.h>
+#ifdef _ARCH_PWR8
+vector int
+test3 (vector int a, vector int b)
+{
+  return vec_mergee (a, b);
+}
+
+typedef __attribute__((altivec(vector__))) long vec_t;
+int
+test3b (vec_t a, vec_t b)
+{
+  return __builtin_vec_vcmpeq_p (2, a, b);
+}
+#else
+#error failed to set power8 pragma target.
+#endif
+
+#pragma GCC target ("cpu=power9,power9-vector")
+#undef _ALTIVEC_H
+#include <altivec.h>
+#ifdef _ARCH_PWR9
+vector bool int
+test4 (vector signed int a, vector signed int b)
+{
+  return vec_cmpnez (a, b);
+}
+#else
+#error Failed to set cpu=power9 pragma target.
+#endif
+
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c
index 0628a85aefe..06b27e66f11 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c
@@ -12,5 +12,6 @@ test_all_not_equal_and_not_zero (vector unsigned short *arg1_p,
   vector unsigned short arg_1 = *arg1_p;
   vector unsigned short arg_2 = *arg2_p;
 
-  return __builtin_vec_vcmpnez_p (__CR6_LT, arg_1, arg_2);	/* { dg-error "builtin function '__builtin_vec_vcmpnez_p' not supported in this compiler configuration" } */
+  return __builtin_vec_vcmpnez_p (__CR6_LT, arg_1, arg_2);
+  /* { dg-error "'__builtin_altivec_vcmpnezh_p' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */
 }
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c
index f81ad21a205..983d33dd3f1 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c
@@ -11,5 +11,6 @@ test_any_equal (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
   vector unsigned int arg_1 = *arg1_p;
   vector unsigned int arg_2 = *arg2_p;
 
-  return __builtin_vec_vcmpnez_p (__CR6_LT_REV, arg_1, arg_2);	/* { dg-error "builtin function '__builtin_vec_vcmpnez_p' not supported in this compiler configuration" } */
+  return __builtin_vec_vcmpnez_p (__CR6_LT_REV, arg_1, arg_2);
+  /* { dg-error "'__builtin_altivec_vcmpnezw_p' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */
 }

commit 5913ca399ca0f4fb4fc1d33bf48c99702fd359b0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Apr 8 00:16:56 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ea8a4ef5088..24b62cfe093 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200407
+20200408

commit ca49ba6ab92328c48a9b84fce43cfa12ae5bfe04
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Apr 9 00:16:57 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 24b62cfe093..ef1034d79a9 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200408
+20200409

commit c4f7e2bee23afa4c6b5b39cc5cb19c767cdf123a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Apr 10 00:16:58 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ef1034d79a9..475ee88e9ae 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200409
+20200410

commit 6f9fa50688ee33f836751ada1d407048e0bb28d8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Apr 11 00:16:52 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 475ee88e9ae..c729be36d0c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200410
+20200411

commit 295b1a5d2d95a486195973d8f9c4bb13090a5ce4
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Apr 12 00:16:52 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c729be36d0c..446679853bd 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200411
+20200412

commit 3efeae5e1147c831e96896b3a15b68ab8546e45d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Apr 13 00:16:57 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 446679853bd..4b34a2006ee 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200412
+20200413

commit 0be6e988cbd251e0897d3cff15e0e2f446b3a221
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Apr 14 00:16:58 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4b34a2006ee..f266ebb42e9 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200413
+20200414

commit 5e67ee3aa084a54f59c0848c32c17faddbb04c4c
Author: Thomas König <tkoenig@gcc.gnu.org>
Date:   Tue Apr 14 18:45:59 2020 +0200

    Backport from trunk of the fix for PR 94270.
    
    2020-04-14  Thomas Koenig  <tkoenig@gcc.gnu.org>
    
            Backport from trunk.
            PR fortran/94270
            * trans-decl.c (generate_local_decl): Do not warn if the
            symbol is artifical.
    
    2020-04-14  Thomas Koenig  <tkoenig@gcc.gnu.org>
    
            Backport from trunk
            PR fortran/94270
            * gfortran.dg/warn_unused_dummy_argument_6.f90: New test.

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 801b1da81ea..9104f16a847 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,10 @@
+2020-04-14  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	Backport from trunk.
+	PR fortran/94270
+	* trans-decl.c (generate_local_decl): Do not warn if the
+	symbol is artifical.
+
 2020-04-02  Mark Eggleston <markeggleston@gcc.gnu.org>
 
 	Backport from master
diff --git a/gcc/fortran/trans-decl.c b/gcc/fortran/trans-decl.c
index 2dc350fbb5a..30ed449e12f 100644
--- a/gcc/fortran/trans-decl.c
+++ b/gcc/fortran/trans-decl.c
@@ -5873,7 +5873,7 @@ generate_local_decl (gfc_symbol * sym)
       /* Unused procedure passed as dummy argument.  */
       if (sym->attr.flavor == FL_PROCEDURE)
 	{
-	  if (!sym->attr.referenced)
+	  if (!sym->attr.referenced && !sym->attr.artificial)
 	    {
 	      if (warn_unused_dummy_argument)
 		gfc_warning (OPT_Wunused_dummy_argument,
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 59c802200a9..5062d974b97 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-14  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	Backport from trunk
+	PR fortran/94270
+	* gfortran.dg/warn_unused_dummy_argument_6.f90: New test.
+
 2020-04-07  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	Backport from mainline.
diff --git a/gcc/testsuite/gfortran.dg/warn_unused_dummy_argument_6.f90 b/gcc/testsuite/gfortran.dg/warn_unused_dummy_argument_6.f90
new file mode 100644
index 00000000000..72f6d5c0857
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/warn_unused_dummy_argument_6.f90
@@ -0,0 +1,13 @@
+! { dg-do compile }
+! { dg-options "-Wall" }
+! PR 94270 - this used to give a bogus warning.
+! Test case by Ignacio Fernández Galván.
+subroutine foo()
+external bar
+call meh(bar)
+call foo_internal()
+contains
+  subroutine foo_internal()
+    call meh(bar)
+  end subroutine foo_internal
+end subroutine foo

commit 1cbbd75bb5f6a07d0ec777b9a5da714230d1d2e6
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Apr 15 00:17:00 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f266ebb42e9..02d9a4f0c70 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200414
+20200415

commit 87c1bfebcdda50ff8964a07c9963823de43de65a
Author: Max Filippov <jcmvbkbc@gmail.com>
Date:   Thu Sep 26 20:51:27 2019 +0000

    xtensa: backport fix for PR target/91880
    
    Xtensa hwloop_optimize segfaults when zero overhead loop is about to be
    inserted as the first instruction of the function.
    Insert zero overhead loop instruction into new basic block before the
    loop when basic block that precedes the loop is empty.
    
    2020-04-15  Max Filippov  <jcmvbkbc@gmail.com>
    gcc/
            * config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead
            loop instruction into new basic block before the loop when basic
            block that precedes the loop is empty.
    
    gcc/testsuite/
            * gcc.target/xtensa/pr91880.c: New test case.
            * gcc.target/xtensa/xtensa.exp: New test suite.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7d52e3d2ddf..e647f30190a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-15  Max Filippov  <jcmvbkbc@gmail.com>
+
+	Backport from mainline.
+	2019-09-26  Max Filippov  <jcmvbkbc@gmail.com>
+
+	* config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead
+	loop instruction into new basic block before the loop when basic
+	block that precedes the loop is empty.
+
 2020-04-07  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 08f9f7c7a8f..de206527810 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -4232,7 +4232,9 @@ hwloop_optimize (hwloop_info loop)
 
   seq = get_insns ();
 
-  if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1)
+  entry_after = BB_END (entry_bb);
+  if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1
+      || !entry_after)
     {
       basic_block new_bb;
       edge e;
@@ -4253,7 +4255,6 @@ hwloop_optimize (hwloop_info loop)
     }
   else
     {
-      entry_after = BB_END (entry_bb);
       while (DEBUG_INSN_P (entry_after)
              || (NOTE_P (entry_after)
 		 && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK))
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5062d974b97..ee3b133fd4d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-04-15  Max Filippov  <jcmvbkbc@gmail.com>
+
+	Backport from mainline.
+	2019-09-26  Max Filippov  <jcmvbkbc@gmail.com>
+
+	* gcc.target/xtensa/pr91880.c: New test case.
+	* gcc.target/xtensa/xtensa.exp: New test suite.
+
 2020-04-14  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	Backport from trunk
diff --git a/gcc/testsuite/gcc.target/xtensa/pr91880.c b/gcc/testsuite/gcc.target/xtensa/pr91880.c
new file mode 100644
index 00000000000..f4895a1bb8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/xtensa/pr91880.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fomit-frame-pointer -fno-tree-vectorize" } */
+
+void foo (unsigned int n, char *a, char *b)
+{
+  int i;
+
+  for (i = 0; i <= n - 1; ++i)
+    a[i] = b[i];
+}
diff --git a/gcc/testsuite/gcc.target/xtensa/xtensa.exp b/gcc/testsuite/gcc.target/xtensa/xtensa.exp
new file mode 100644
index 00000000000..8720327f526
--- /dev/null
+++ b/gcc/testsuite/gcc.target/xtensa/xtensa.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2019 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an Xtensa target.
+if ![istarget xtensa*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish

commit f45b87f786809997d2f8d418ab10de6640149422
Author: Max Filippov <jcmvbkbc@gmail.com>
Date:   Mon Apr 13 13:26:04 2020 -0700

    xtensa: backport fix for PR target/94584
    
    Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can
    load value from memory, but they don't treat volatile memory correctly.
    Add %v1 before load instructions to emit 'memw' instruction when
    -mserialize-volatile is in effect.
    
    2020-04-15  Max Filippov  <jcmvbkbc@gmail.com>
    gcc/
            * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
            (extendhisi2_internal): Add %v1 before the load instructions.
    
    gcc/testsuite/
            * gcc.target/xtensa/pr94584.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e647f30190a..a060c850ed2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-15  Max Filippov  <jcmvbkbc@gmail.com>
+
+	Backport from mainline.
+	2020-04-14  Max Filippov  <jcmvbkbc@gmail.com>
+
+	PR target/94584
+	* config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
+	(extendhisi2_internal): Add %v1 before the load instructions.
+
 2020-04-15  Max Filippov  <jcmvbkbc@gmail.com>
 
 	Backport from mainline.
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 209f839cfb0..9b911e30900 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -538,7 +538,7 @@
   ""
   "@
    extui\t%0, %1, 0, 16
-   l16ui\t%0, %1"
+   %v1l16ui\t%0, %1"
   [(set_attr "type"	"arith,load")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
@@ -549,7 +549,7 @@
   ""
   "@
    extui\t%0, %1, 0, 8
-   l8ui\t%0, %1"
+   %v1l8ui\t%0, %1"
   [(set_attr "type"	"arith,load")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
@@ -575,7 +575,7 @@
   ""
   "@
    sext\t%0, %1, 15
-   l16si\t%0, %1"
+   %v1l16si\t%0, %1"
   [(set_attr "type"	"arith,load")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ee3b133fd4d..ffd37f1229a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-04-15  Max Filippov  <jcmvbkbc@gmail.com>
+
+	Backport from mainline.
+	2020-04-13  Max Filippov  <jcmvbkbc@gmail.com>
+
+	PR target/94584
+	* gcc.target/xtensa/pr94584.c: New test.
+
 2020-04-15  Max Filippov  <jcmvbkbc@gmail.com>
 
 	Backport from mainline.
diff --git a/gcc/testsuite/gcc.target/xtensa/pr94584.c b/gcc/testsuite/gcc.target/xtensa/pr94584.c
new file mode 100644
index 00000000000..1577285b8a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/xtensa/pr94584.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mserialize-volatile" } */
+
+unsigned long load32 (volatile unsigned long *s)
+{
+  return *s;
+}
+
+short load16s (volatile short *s)
+{
+  return *s;
+}
+
+unsigned short load16u (volatile unsigned short *s)
+{
+  return *s;
+}
+
+unsigned char load8 (volatile unsigned char *s)
+{
+  return *s;
+}
+
+/* { dg-final { scan-assembler-times "memw" 4 } } */

commit 06d6120b7a5621d584bd0c861bc94096cc8b60b7
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Wed Apr 15 23:25:27 2020 +0200

    i386: Require OPTION_MASK_ISA_SSE2 for __builtin_ia32_movq128 [PR94603]
    
            PR target/94603
            * config/i386/i386-builtin.def (__builtin_ia32_movq128):
            Require OPTION_MASK_ISA_SSE2.
    
    testsuite/ChangeLog:
    
            PR target/94603
            * gcc.target/i386/pr94603.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a060c850ed2..4cf6f64b017 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-15  Uroš Bizjak  <ubizjak@gmail.com>
+
+	PR target/94603
+	* config/i386/i386-builtin.def (__builtin_ia32_movq128):
+	Require OPTION_MASK_ISA_SSE2.
+
 2020-04-15  Max Filippov  <jcmvbkbc@gmail.com>
 
 	Backport from mainline.
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index fe23ab0b829..35bd8add04a 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -787,7 +787,7 @@ BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX
 
 BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE)
 
-BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI)
+BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI)
 
 /* SSE2 MMX */
 BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ffd37f1229a..7e60625fdc7 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-15  Uroš Bizjak  <ubizjak@gmail.com>
+
+	PR target/94603
+	* gcc.target/i386/pr94603.c: New test.
+
 2020-04-15  Max Filippov  <jcmvbkbc@gmail.com>
 
 	Backport from mainline.
diff --git a/gcc/testsuite/gcc.target/i386/pr94603.c b/gcc/testsuite/gcc.target/i386/pr94603.c
new file mode 100644
index 00000000000..34a1e069eac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr94603.c
@@ -0,0 +1,11 @@
+/* PR target/94603 */
+/* { dg-do compile } */
+/* { dg-options "-Wno-implicit-function-declaration -msse -mno-sse2" } */
+
+typedef long long __attribute__ ((__vector_size__ (16))) V;
+
+V
+foo (V v)
+{
+  return __builtin_ia32_movq128 (v);  /* { dg-error "" } */
+}

commit 9ba334bab33fbb68cadbe0d65b471bdb8420c676
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Apr 16 00:17:01 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 02d9a4f0c70..6cfb1fe3b70 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200415
+20200416

commit 23f24c89039bd775fd27ab1d2a084d83801a594a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Apr 17 00:17:00 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6cfb1fe3b70..b2b78b6f5b9 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200416
+20200417

commit 99ddb11c0840f68466a14fd583dd4d3a558d4961
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Fri Apr 17 15:23:27 2020 -0700

    x86: Insert ENDBR if function will be called indirectly
    
    Since constant_call_address_operand has
    
    ;; Test for a pc-relative call operand
    (define_predicate "constant_call_address_operand"
      (match_code "symbol_ref")
    {
      if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC
          || flag_force_indirect_call)
        return false;
      if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
        return false;
      return true;
    })
    
    even if cgraph_node::get (cfun->decl)->only_called_directly_p () returns
    false, the fuction may still be called indirectly.  Copy the logic from
    constant_call_address_operand to rest_of_insert_endbranch to insert ENDBR
    at function entry if function will be called indirectly.
    
    NB: gcc.target/i386/pr94417-2.c is updated to expect 4 ENDBRs, instead
    of 2, since only GCC 10 has the fix for PR target/89355 not to insert
    ENDBR after NOTE_INSN_DELETED_LABEL.
    
    gcc/
    
            Backport from master
            PR target/94417
            * config/i386/i386.c (rest_of_insert_endbranch): Insert ENDBR at
            function entry if function will be called indirectly.
    
    gcc/testsuite/
    
            Backport from master
            PR target/94417
            * gcc.target/i386/pr94417-1.c: New test.
            * gcc.target/i386/pr94417-2.c: Likewise.
            * gcc.target/i386/pr94417-3.c: Likewise.
    
    (cherry picked from commit c5f379653964a1d2c7037b2de3e947a48370a198)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4cf6f64b017..c758e9a40c7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backport from master
+	2020-04-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/94417
+	* config/i386/i386.c (rest_of_insert_endbranch): Insert ENDBR at
+	function entry if function will be called indirectly.
+
 2020-04-15  Uroš Bizjak  <ubizjak@gmail.com>
 
 	PR target/94603
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 13943ebf800..89a38f25470 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2498,7 +2498,12 @@ rest_of_insert_endbranch (void)
 
   if (!lookup_attribute ("nocf_check",
 			 TYPE_ATTRIBUTES (TREE_TYPE (cfun->decl)))
-      && !cgraph_node::get (cfun->decl)->only_called_directly_p ())
+      && (!cgraph_node::get (cfun->decl)->only_called_directly_p ()
+	  || ix86_cmodel == CM_LARGE
+	  || ix86_cmodel == CM_LARGE_PIC
+	  || flag_force_indirect_call
+	  || (TARGET_DLLIMPORT_DECL_ATTRIBUTES
+	      && DECL_DLLIMPORT_P (cfun->decl))))
     {
       /* Queue ENDBR insertion to x86_function_profiler.  */
       if (crtl->profile && flag_fentry)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7e60625fdc7..939aceed460 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2020-04-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backport from master
+	2020-04-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/94417
+	* gcc.target/i386/pr94417-1.c: New test.
+	* gcc.target/i386/pr94417-2.c: Likewise.
+	* gcc.target/i386/pr94417-3.c: Likewise.
+
 2020-04-15  Uroš Bizjak  <ubizjak@gmail.com>
 
 	PR target/94603
diff --git a/gcc/testsuite/gcc.target/i386/pr94417-1.c b/gcc/testsuite/gcc.target/i386/pr94417-1.c
new file mode 100644
index 00000000000..5bbe057fa8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr94417-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -fcf-protection -mcmodel=large" } */
+/* { dg-final { scan-assembler-times {\mendbr} 2 } } */
+
+extern void ext (void);
+
+__attribute((noclone, noinline))
+static
+void
+foo (void)
+{
+  ext ();
+}
+
+void
+bar (void)
+{
+  foo ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr94417-2.c b/gcc/testsuite/gcc.target/i386/pr94417-2.c
new file mode 100644
index 00000000000..9e9c277e07f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr94417-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -fpic -mcmodel=large -fcf-protection" } */
+/* { dg-final { scan-assembler-times {\mendbr} 4 } } */
+
+extern void ext (void);
+
+__attribute((noclone, noinline))
+static
+void
+foo (void)
+{
+  ext ();
+}
+
+void
+bar (void)
+{
+  foo ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr94417-3.c b/gcc/testsuite/gcc.target/i386/pr94417-3.c
new file mode 100644
index 00000000000..07c451796c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr94417-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fcf-protection -mforce-indirect-call" } */
+/* { dg-final { scan-assembler-times {\mendbr} 2 } } */
+
+extern void ext (void);
+
+__attribute((noclone, noinline))
+static
+void
+foo (void)
+{
+  ext ();
+}
+
+void
+bar (void)
+{
+  foo ();
+}

commit 24a2c2d015f20679d055ae38f4e37864cced705f
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Apr 18 00:16:56 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b2b78b6f5b9..50a74e38312 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200417
+20200418

commit a79b2bcb2e9af1a80f980105a052f21f8af79095
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Apr 19 00:16:57 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 50a74e38312..affc41ecfe5 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200418
+20200419

commit 1737e76b253f7412ac6635e7c9dc1398efbffad9
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Sun Apr 19 16:30:13 2020 +0200

    i386: Remove unneeded assignments when triggering SSE exceptions
    
    According to "Intel 64 and IA32 Arch SDM, Vol. 3":
    
    "Because SIMD floating-point exceptions are precise and occur immediately,
    the situation does not arise where an x87 FPU instruction, a WAIT/FWAIT
    instruction, or another SSE/SSE2/SSE3 instruction will catch a pending
    unmasked SIMD floating-point exception."
    
    Remove unneeded assignments to volatile memory.
    
    libgcc/ChangeLog:
    
            * config/i386/sfp-exceptions.c (__sfp_handle_exceptions) [__SSE_MATH__]:
            Remove unneeded assignments to volatile memory.
    
    libatomic/ChangeLog:
    
            * config/x86/fenv.c (__atomic_feraiseexcept) [__SSE_MATH__]:
            Remove unneeded assignments to volatile memory.
    
    libgfortran/ChangeLog:
    
            * config/fpu-387.h (local_feraiseexcept) [__SSE_MATH__]:
            Remove unneeded assignments to volatile memory.

diff --git a/libatomic/ChangeLog b/libatomic/ChangeLog
index 59fc1952792..5f89d6aade8 100644
--- a/libatomic/ChangeLog
+++ b/libatomic/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-19  Uroš Bizjak  <ubizjak@gmail.com>
+
+	* config/x86/fenv.c (__atomic_feraiseexcept) [__SSE_MATH__]:
+	Remove unneeded assignments to volatile memory.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/libatomic/config/x86/fenv.c b/libatomic/config/x86/fenv.c
index 36d86f369fe..f8d678744db 100644
--- a/libatomic/config/x86/fenv.c
+++ b/libatomic/config/x86/fenv.c
@@ -57,9 +57,7 @@ __atomic_feraiseexcept (int excepts)
     {
       float f = 0.0f;
 #ifdef __SSE_MATH__
-      volatile float r __attribute__ ((unused));
       asm volatile ("%vdivss\t{%0, %d0|%d0, %0}" : "+x" (f));
-      r = f; /* Needed to trigger exception.   */
 #else
       asm volatile ("fdiv\t{%y0, %0|%0, %y0}" : "+t" (f));
       /* No need for fwait, exception is triggered by emitted fstp.  */
@@ -77,9 +75,7 @@ __atomic_feraiseexcept (int excepts)
     {
       float f = 1.0f, g = 0.0f;
 #ifdef __SSE_MATH__
-      volatile float r __attribute__ ((unused));
       asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));
-      r = f; /* Needed to trigger exception.   */
 #else
       asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g));
       /* No need for fwait, exception is triggered by emitted fstp.  */
@@ -105,9 +101,7 @@ __atomic_feraiseexcept (int excepts)
     {
       float f = 1.0f, g = 3.0f;
 #ifdef __SSE_MATH__
-      volatile float r __attribute__ ((unused));
       asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));
-      r = f; /* Needed to trigger exception.   */
 #else
       asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g));
       /* No need for fwait, exception is triggered by emitted fstp.  */
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 69f9f7ea863..2a43d9c0c8e 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-19  Uroš Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/sfp-exceptions.c (__sfp_handle_exceptions) [__SSE_MATH__]:
+	Remove unneeded assignments to volatile memory.
+
 2020-03-04  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from mainline
diff --git a/libgcc/config/i386/sfp-exceptions.c b/libgcc/config/i386/sfp-exceptions.c
index 9d7d88d643b..8446b55f1ba 100644
--- a/libgcc/config/i386/sfp-exceptions.c
+++ b/libgcc/config/i386/sfp-exceptions.c
@@ -48,9 +48,7 @@ __sfp_handle_exceptions (int _fex)
     {
       float f = 0.0f;
 #ifdef __SSE_MATH__
-      volatile float r __attribute__ ((unused));
       asm volatile ("%vdivss\t{%0, %d0|%d0, %0}" : "+x" (f));
-      r = f; /* Needed to trigger exception.   */
 #else
       asm volatile ("fdiv\t{%y0, %0|%0, %y0}" : "+t" (f));
       /* No need for fwait, exception is triggered by emitted fstp.  */
@@ -68,9 +66,7 @@ __sfp_handle_exceptions (int _fex)
     {
       float f = 1.0f, g = 0.0f;
 #ifdef __SSE_MATH__
-      volatile float r __attribute__ ((unused));
       asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));
-      r = f; /* Needed to trigger exception.   */
 #else
       asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g));
       /* No need for fwait, exception is triggered by emitted fstp.  */
@@ -96,9 +92,7 @@ __sfp_handle_exceptions (int _fex)
     {
       float f = 1.0f, g = 3.0f;
 #ifdef __SSE_MATH__
-      volatile float r __attribute__ ((unused));
       asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));
-      r = f; /* Needed to trigger exception.   */
 #else
       asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g));
       /* No need for fwait, exception is triggered by emitted fstp.  */
diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog
index 60d9b434ad1..b4825c78c45 100644
--- a/libgfortran/ChangeLog
+++ b/libgfortran/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-19  Uroš Bizjak  <ubizjak@gmail.com>
+
+	* config/fpu-387.h (local_feraiseexcept) [__SSE_MATH__]:
+	Remove unneeded assignments to volatile memory.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/libgfortran/config/fpu-387.h b/libgfortran/config/fpu-387.h
index c6cb873fc0e..9a3cb9a2efa 100644
--- a/libgfortran/config/fpu-387.h
+++ b/libgfortran/config/fpu-387.h
@@ -103,9 +103,7 @@ local_feraiseexcept (int excepts)
     {
       float f = 0.0f;
 #ifdef __SSE_MATH__
-      volatile float r __attribute__ ((unused));
       __asm__ __volatile__ ("%vdivss\t{%0, %d0|%d0, %0}" : "+x" (f));
-      r = f; /* Needed to trigger exception.   */
 #else
       __asm__ __volatile__ ("fdiv\t{%y0, %0|%0, %y0}" : "+t" (f));
       /* No need for fwait, exception is triggered by emitted fstp.  */
@@ -123,9 +121,7 @@ local_feraiseexcept (int excepts)
     {
       float f = 1.0f, g = 0.0f;
 #ifdef __SSE_MATH__
-      volatile float r __attribute__ ((unused));
       __asm__ __volatile__ ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));
-      r = f; /* Needed to trigger exception.   */
 #else
       __asm__ __volatile__ ("fdivs\t%1" : "+t" (f) : "m" (g));
       /* No need for fwait, exception is triggered by emitted fstp.  */
@@ -151,9 +147,7 @@ local_feraiseexcept (int excepts)
     {
       float f = 1.0f, g = 3.0f;
 #ifdef __SSE_MATH__
-      volatile float r __attribute__ ((unused));
       __asm__ __volatile__ ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));
-      r = f; /* Needed to trigger exception.   */
 #else
       __asm__ __volatile__ ("fdivs\t%1" : "+t" (f) : "m" (g));
       /* No need for fwait, exception is triggered by emitted fstp.  */

commit b3e5d33b380a161bbfb854f47077a5c32684a39e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Apr 20 00:16:56 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index affc41ecfe5..d99538f2a38 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200419
+20200420

commit b262ef0ed1628d88aa7a899fb3f93bcf3e51998e
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Mon Apr 20 11:46:38 2020 +0100

    AArch64: Fix options canonicanization for assembler
    
    It is currently impossible to use fp16 on any architecture higher than Armv8.3-a
    due to a bug in options canonization.  This bug results in the fp16 flag not
    being emitted in the assembly when it should have been.
    
    This is caused by a complicated architectural requirement at Armv8.4-a.  On
    Armv8.2-a and Armv8.3-a fp16fml is an optional extension and turning it on turns
    on both fp and fp16.  However starting with Armv8.4-a fp16fml is mandatory if
    fp16 is available, otherwise it's optional.
    
    In short this means that to enable fp16fml the smallest option that needs to
    passed to the assembler is Armv8.4-a+fp16.
    
    The fix in this patch takes into account that an option may be on by default in
    an architecture, but that not all the bits required to use it are on by default
    in an architecture.  In such cases the difference between the two are still
    emitted to the assembler.
    
    gcc/ChangeLog:
    
            PR target/94396
            * common/config/aarch64/aarch64-common.c
            (aarch64_get_extension_string_for_isa_flags): Handle default flags.
    
    gcc/testsuite/ChangeLog:
    
            PR target/94396
            * gcc.target/aarch64/options_set_11.c: New test.
            * gcc.target/aarch64/options_set_12.c: New test.
            * gcc.target/aarch64/options_set_13.c: New test.
            * gcc.target/aarch64/options_set_14.c: New test.
            * gcc.target/aarch64/options_set_15.c: New test.
            * gcc.target/aarch64/options_set_16.c: New test.
            * gcc.target/aarch64/options_set_17.c: New test.
            * gcc.target/aarch64/options_set_18.c: New test.
            * gcc.target/aarch64/options_set_19.c: New test.
            * gcc.target/aarch64/options_set_20.c: New test.
            * gcc.target/aarch64/options_set_21.c: New test.
            * gcc.target/aarch64/options_set_22.c: New test.
            * gcc.target/aarch64/options_set_23.c: New test.
            * gcc.target/aarch64/options_set_24.c: New test.
            * gcc.target/aarch64/options_set_25.c: New test.
            * gcc.target/aarch64/options_set_26.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c758e9a40c7..87d76a84118 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-20  Tamar Christina  <tamar.christina@arm.com>
+
+	Backport from mainline.
+	2020-04-03  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/94396
+	* common/config/aarch64/aarch64-common.c
+	(aarch64_get_extension_string_for_isa_flags): Handle default flags.
+
 2020-04-17  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from master
diff --git a/gcc/common/config/aarch64/aarch64-common.c b/gcc/common/config/aarch64/aarch64-common.c
index 4bd61e8be1f..d500ae53cc0 100644
--- a/gcc/common/config/aarch64/aarch64-common.c
+++ b/gcc/common/config/aarch64/aarch64-common.c
@@ -367,7 +367,22 @@ aarch64_get_extension_string_for_isa_flags (unsigned long isa_flags,
 	/* We remove all the dependent bits, to prevent them from being turned
 	   on twice.  This only works because we assume that all there are
 	   individual options to set all bits standalone.  */
-	isa_flag_bits &= ~opt->flags_on;
+
+	/* PR target/94396.
+
+	   For flags which would already imply a bit that's on by default (e.g
+	   fp16fml which implies +fp,+fp16) we must emit the flags that are not
+	   on by default.  i.e. in Armv8.4-a +fp16fml is default if +fp16.  So
+	   if a user passes armv8.4-a+fp16 (or +fp16fml) then we need to emit
+	   +fp16.  But if +fp16fml is used in an architecture where it is
+	   completely optional we only have to emit the canonical flag.  */
+	uint64_t toggle_bits = opt->flags_on & default_arch_flags;
+	/* Now check to see if the canonical flag is on by default.  If it
+	   is not then enabling it will enable all bits in flags_on.  */
+	if ((opt->flag_canonical & default_arch_flags) == 0)
+	  toggle_bits = opt->flags_on;
+
+	isa_flag_bits &= ~toggle_bits;
 	isa_flag_bits |= opt->flag_canonical;
       }
     }
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 939aceed460..874df4046a3 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,26 @@
+2020-04-20  Tamar Christina  <tamar.christina@arm.com>
+
+	Backport from mainline.
+	2020-04-03  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/94396
+	* gcc.target/aarch64/options_set_11.c: New test.
+	* gcc.target/aarch64/options_set_12.c: New test.
+	* gcc.target/aarch64/options_set_13.c: New test.
+	* gcc.target/aarch64/options_set_14.c: New test.
+	* gcc.target/aarch64/options_set_15.c: New test.
+	* gcc.target/aarch64/options_set_16.c: New test.
+	* gcc.target/aarch64/options_set_17.c: New test.
+	* gcc.target/aarch64/options_set_18.c: New test.
+	* gcc.target/aarch64/options_set_19.c: New test.
+	* gcc.target/aarch64/options_set_20.c: New test.
+	* gcc.target/aarch64/options_set_21.c: New test.
+	* gcc.target/aarch64/options_set_22.c: New test.
+	* gcc.target/aarch64/options_set_23.c: New test.
+	* gcc.target/aarch64/options_set_24.c: New test.
+	* gcc.target/aarch64/options_set_25.c: New test.
+	* gcc.target/aarch64/options_set_26.c: New test.
+
 2020-04-17  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from master
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_11.c b/gcc/testsuite/gcc.target/aarch64/options_set_11.c
new file mode 100644
index 00000000000..d083bfdbd5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_11.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a+fp" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.2-a\+crc} } } */
+
+ /* FP is default on, no need to pass on to assembler.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_12.c b/gcc/testsuite/gcc.target/aarch64/options_set_12.c
new file mode 100644
index 00000000000..58a09fda2c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_12.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a+fp16" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.2-a\+crc\+fp16} } } */
+
+ /* fp16 not default, should be emitted.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_13.c b/gcc/testsuite/gcc.target/aarch64/options_set_13.c
new file mode 100644
index 00000000000..2a517ecb58f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_13.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a+fp16+fp" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.2-a\+crc\+fp16} } } */
+
+ /* FP is part of FP16, don't emit it.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_14.c b/gcc/testsuite/gcc.target/aarch64/options_set_14.c
new file mode 100644
index 00000000000..c192bf6cb63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_14.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a+fp16fml" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.2-a\+crc\+fp16fml} } } */
+
+ /* fmp16fml is smallest option to emit.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_15.c b/gcc/testsuite/gcc.target/aarch64/options_set_15.c
new file mode 100644
index 00000000000..32ec3ea4643
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_15.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a+fp16fml+fp" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.2-a\+crc\+fp16fml*} } } */
+
+ /* fp included in fp16fml, only emit latter.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_16.c b/gcc/testsuite/gcc.target/aarch64/options_set_16.c
new file mode 100644
index 00000000000..b45c01a915b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_16.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a+fp16fml+fp16+fp" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.2-a\+crc\+fp16fml} } } */
+
+ /* fp16fml is smallest options to emit.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_17.c b/gcc/testsuite/gcc.target/aarch64/options_set_17.c
new file mode 100644
index 00000000000..c490e1f47a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_17.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a+dotprod" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.2-a\+crc\+dotprod} } } */
+
+ /* dotprod needs to be emitted pre armv8.4.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_18.c b/gcc/testsuite/gcc.target/aarch64/options_set_18.c
new file mode 100644
index 00000000000..61587dbbd63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_18.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.4-a+dotprod" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.4-a\+crc} } } */
+
+ /* dotprod is default in armv8.4-a, don't emit.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_19.c b/gcc/testsuite/gcc.target/aarch64/options_set_19.c
new file mode 100644
index 00000000000..72b58126182
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_19.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.4-a+fp" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.4-a\+crc} } } */
+
+ /* fp default, don't emit.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_20.c b/gcc/testsuite/gcc.target/aarch64/options_set_20.c
new file mode 100644
index 00000000000..b383e0aced2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_20.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.4-a+fp16" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.4-a\+crc\+fp16} } } */
+
+ /* fp16 smallest set to emit.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_21.c b/gcc/testsuite/gcc.target/aarch64/options_set_21.c
new file mode 100644
index 00000000000..19fcd6fda6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_21.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.4-a+fp16+fp" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.4-a\+crc\+fp16} } } */
+
+ /* fp16 smallest set to emit.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_22.c b/gcc/testsuite/gcc.target/aarch64/options_set_22.c
new file mode 100644
index 00000000000..77ae4089f39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_22.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.4-a+fp16fml" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.4-a\+crc\+fp16} } } */
+
+ /* fp16 smallest set to emit.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_23.c b/gcc/testsuite/gcc.target/aarch64/options_set_23.c
new file mode 100644
index 00000000000..dee637c5d2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_23.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.4-a+fp16fml+fp" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.4-a\+crc\+fp16} } } */
+
+ /* fp16 smallest set to emit.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_24.c b/gcc/testsuite/gcc.target/aarch64/options_set_24.c
new file mode 100644
index 00000000000..54b0e3d4a83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_24.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.4-a+fp16fml+fp16" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.4-a\+crc\+fp16} } } */
+
+ /* fp16 smallest set to emit.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_25.c b/gcc/testsuite/gcc.target/aarch64/options_set_25.c
new file mode 100644
index 00000000000..a3b2d63c06e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_25.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.4-a+fp16fml+fp+fp16" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.4-a\+crc\+fp16} } } */
+
+ /* fp16 smallest set to emit.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_26.c b/gcc/testsuite/gcc.target/aarch64/options_set_26.c
new file mode 100644
index 00000000000..b383e0aced2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/options_set_26.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.4-a+fp16" } */
+
+int main ()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8\.4-a\+crc\+fp16} } } */
+
+ /* fp16 smallest set to emit.  */

commit 472c004fcd13e429dad7d1b829d21e26d24e39a4
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Mon Apr 20 05:51:29 2020 -0700

    x86: Restore the frame pointer in word_mode
    
    We must restore the frame pointer in word_mode for eh_return epilogues
    since the upper 32 bits of RBP register can have any values.
    
    Tested on Linux/x32 and Linux/x86-64.
    
            Backport from master
            PR target/94556
            * config/i386/i386.c (ix86_expand_epilogue): Restore the frame
            pointer in word_mode for eh_return epilogues.
    
    (cherry picked from commit efc1f3577f38bb213b313661c025ac965baee953)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 87d76a84118..a14aaec61db 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backport from master
+	2020-04-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/94556
+	* config/i386/i386.c (ix86_expand_epilogue): Restore the frame
+	pointer in word_mode for eh_return epilogues.
+
 2020-04-20  Tamar Christina  <tamar.christina@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 89a38f25470..f1baecda28e 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -14601,8 +14601,13 @@ ix86_expand_epilogue (int style)
 	      t = plus_constant (Pmode, t, m->fs.fp_offset - UNITS_PER_WORD);
 	      emit_insn (gen_rtx_SET (sa, t));
 
-	      t = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
-	      insn = emit_move_insn (hard_frame_pointer_rtx, t);
+	      /* NB: eh_return epilogues must restore the frame pointer
+		 in word_mode since the upper 32 bits of RBP register
+		 can have any values.  */
+	      t = gen_frame_mem (word_mode, hard_frame_pointer_rtx);
+	      rtx frame_reg = gen_rtx_REG (word_mode,
+					   HARD_FRAME_POINTER_REGNUM);
+	      insn = emit_move_insn (frame_reg, t);
 
 	      /* Note that we use SA as a temporary CFA, as the return
 		 address is at the proper place relative to it.  We
@@ -14617,7 +14622,7 @@ ix86_expand_epilogue (int style)
 	      add_reg_note (insn, REG_CFA_DEF_CFA,
 			    plus_constant (Pmode, sa, UNITS_PER_WORD));
 	      ix86_add_queued_cfa_restore_notes (insn);
-	      add_reg_note (insn, REG_CFA_RESTORE, hard_frame_pointer_rtx);
+	      add_reg_note (insn, REG_CFA_RESTORE, frame_reg);
 	      RTX_FRAME_RELATED_P (insn) = 1;
 
 	      m->fs.cfa_reg = sa;

commit 7539c2a680c99c90b7d1a47acf659cdd259b4650
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Apr 21 00:16:54 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d99538f2a38..c1a6cf0b925 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200420
+20200421

commit b463ced59535fddeff90d697f869d58e444568fa
Author: Martin Jambor <mjambor@suse.cz>
Date:   Tue Apr 21 17:41:01 2020 +0200

    sra-8: Fix sra_modify_expr handling of partial writes (PR 94482)
    
    This is a fairly straightforward backport of the mainline fix for PR 94482.
    
    When sra_modify_expr is invoked on an expression that modifies only
    part of the underlying replacement, such as a BIT_FIELD_REF on a LHS
    of an assignment and the SRA replacement's type is not compatible with
    what is being replaced (0th operand of the B_F_R in the above
    example), it does not work properly, basically throwing away the part
    of the expr that should have stayed intact.
    
    This is fixed in two ways.  For BIT_FIELD_REFs, which operate on the
    binary image of the replacement (and so in a way serve as a
    VIEW_CONVERT_EXPR) we just do not bother with converting.  For
    REALPART_EXPRs and IMAGPART_EXPRs, if the replacement is not a
    register, we insert a VIEW_CONVERT_EXPR under
    the complex partial access expression, which is always OK, for loads
    from registers we take the extra step of converting it to a temporary.
    
    This revealed a bug in fwprop which is fixed with the hunk from Richi.
    This is the only difference from the mainline patch which has two
    hunks, but the code handling BIT_FIELD_REF is not present in gcc-8.
    
    Oh, and the testcase options were changed to what Jakub put there on
    the mainline to suppress all vector ABI warnings.
    
    Bootstrapped and tested on x86_64-linux.
    
    2020-04-21  Martin Jambor  <mjambor@suse.cz>
    
            Backport from master
            2020-04-09  Martin Jambor  <mjambor@suse.cz>
                        Richard Biener  <rguenther@suse.de>
    
            PR tree-optimization/94482
            * tree-sra.c (create_access_replacement): Dump new replacement with
            TDF_UID.
            (sra_modify_expr): Fix handling of cases when the original EXPR writes
            to only part of the replacement.
            * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
            the first operand of combinations into REAL/IMAGPART_EXPR and
            BIT_FIELD_REF.
    
            testsuite/
            * gcc.dg/torture/pr94482.c: New test.
            * gcc.dg/tree-ssa/pr94482-2.c: Likewise.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a14aaec61db..2d410b25d3f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2020-04-21  Martin Jambor  <mjambor@suse.cz>
+
+	Backport from master
+	2020-04-09  Martin Jambor  <mjambor@suse.cz>
+	            Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/94482
+	* tree-sra.c (create_access_replacement): Dump new replacement with
+	TDF_UID.
+	(sra_modify_expr): Fix handling of cases when the original EXPR writes
+	to only part of the replacement.
+	* tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
+	the first operand of combinations into REAL/IMAGPART_EXPR and
+	BIT_FIELD_REF.
+
 2020-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from master
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 874df4046a3..58bbd2ed205 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-21  Martin Jambor  <mjambor@suse.cz>
+
+	Backport from master
+	2020-04-09  Martin Jambor  <mjambor@suse.cz>
+
+	PR tree-optimization/94482
+	* gcc.dg/torture/pr94482.c: New test.
+	* gcc.dg/tree-ssa/pr94482-2.c: Likewise.
+
 2020-04-20  Tamar Christina  <tamar.christina@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/testsuite/gcc.dg/torture/pr94482.c b/gcc/testsuite/gcc.dg/torture/pr94482.c
new file mode 100644
index 00000000000..9264842e349
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr94482.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-additional-options "-Wno-psabi -w" } */
+/* { dg-additional-options "-msse2" { target sse2_runtime } } */
+
+typedef unsigned V __attribute__ ((__vector_size__ (16)));
+union U
+{
+  V j;
+  unsigned long long i __attribute__ ((__vector_size__ (16)));
+};
+
+static inline __attribute__((always_inline)) V
+foo (unsigned long long a)
+{
+  union U z = { .j = (V) {} };
+  for (unsigned long i = 0; i < 1; i++)
+    z.i[i] = a;
+  return z.j;
+}
+
+static inline __attribute__((always_inline)) V
+bar (V a, unsigned long long i, int q)
+{
+  union U z = { .j = a };
+  z.i[q] = i;
+  return z.j;
+}
+
+int
+main ()
+{
+  union U z = { .j = bar (foo (1729), 2, 1) };
+  if (z.i[0] != 1729)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr94482-2.c b/gcc/testsuite/gcc.dg/tree-ssa/pr94482-2.c
new file mode 100644
index 00000000000..fcac9d5e439
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr94482-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O1" } */
+
+typedef unsigned long V __attribute__ ((__vector_size__ (8)));
+typedef _Complex int Ci;
+typedef _Complex float Cf;
+
+union U
+{
+  Ci ci;
+  Cf cf;
+};
+
+volatile Ci vgi;
+
+Cf foo (Cf c)
+{
+  __real c = 0x1ffp10;
+  return c;
+}
+
+Ci ioo (Ci c)
+{
+  __real c = 50;
+  return c;
+}
+
+
+int main (int argc, char *argv[])
+{
+  union U u;
+
+  __real u.ci = 500;
+  __imag u.ci = 1000;
+  vgi = u.ci;
+
+  u.ci = ioo (u.ci);
+  __imag u.ci = 100;
+
+  if (__real u.ci != 50 || __imag u.ci != 100)
+    __builtin_abort();
+
+  u.cf = foo (u.cf);
+  __imag u.cf = 0x1p3;
+
+  if (__real u.cf != 0x1ffp10 || __imag u.cf != 0x1p3)
+    __builtin_abort();
+
+  return 0;
+}
diff --git a/gcc/tree-sra.c b/gcc/tree-sra.c
index 264e1282c5a..143cd06a541 100644
--- a/gcc/tree-sra.c
+++ b/gcc/tree-sra.c
@@ -2324,7 +2324,7 @@ create_access_replacement (struct access *access)
 	  print_generic_expr (dump_file, access->base);
 	  fprintf (dump_file, " offset: %u, size: %u: ",
 		   (unsigned) access->offset, (unsigned) access->size);
-	  print_generic_expr (dump_file, repl);
+	  print_generic_expr (dump_file, repl, TDF_UID);
 	  fprintf (dump_file, "\n");
 	}
     }
@@ -3182,6 +3182,7 @@ sra_modify_expr (tree *expr, gimple_stmt_iterator *gsi, bool write)
   location_t loc;
   struct access *access;
   tree type, bfr, orig_expr;
+  bool partial_cplx_access = false;
 
   if (TREE_CODE (*expr) == BIT_FIELD_REF)
     {
@@ -3192,7 +3193,10 @@ sra_modify_expr (tree *expr, gimple_stmt_iterator *gsi, bool write)
     bfr = NULL_TREE;
 
   if (TREE_CODE (*expr) == REALPART_EXPR || TREE_CODE (*expr) == IMAGPART_EXPR)
-    expr = &TREE_OPERAND (*expr, 0);
+    {
+      expr = &TREE_OPERAND (*expr, 0);
+      partial_cplx_access = true;
+    }
   access = get_access_for_expr (*expr);
   if (!access)
     return false;
@@ -3220,13 +3224,32 @@ sra_modify_expr (tree *expr, gimple_stmt_iterator *gsi, bool write)
          be accessed as a different type too, potentially creating a need for
          type conversion (see PR42196) and when scalarized unions are involved
          in assembler statements (see PR42398).  */
-      if (!useless_type_conversion_p (type, access->type))
+      if (!bfr && !useless_type_conversion_p (type, access->type))
 	{
 	  tree ref;
 
 	  ref = build_ref_for_model (loc, orig_expr, 0, access, gsi, false);
 
-	  if (write)
+	  if (partial_cplx_access)
+	    {
+	    /* VIEW_CONVERT_EXPRs in partial complex access are always fine in
+	       the case of a write because in such case the replacement cannot
+	       be a gimple register.  In the case of a load, we have to
+	       differentiate in between a register an non-register
+	       replacement.  */
+	      tree t = build1 (VIEW_CONVERT_EXPR, type, repl);
+	      gcc_checking_assert (!write || access->grp_partial_lhs);
+	      if (!access->grp_partial_lhs)
+		{
+		  tree tmp = make_ssa_name (type);
+		  gassign *stmt = gimple_build_assign (tmp, t);
+		  /* This is always a read. */
+		  gsi_insert_before (gsi, stmt, GSI_SAME_STMT);
+		  t = tmp;
+		}
+	      *expr = t;
+	    }
+	  else if (write)
 	    {
 	      gassign *stmt;
 
diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c
index 91741894aec..287a45c38a8 100644
--- a/gcc/tree-ssa-forwprop.c
+++ b/gcc/tree-ssa-forwprop.c
@@ -2342,7 +2342,8 @@ pass_forwprop::execute (function *fun)
 		    continue;
 		  if (!is_gimple_assign (use_stmt)
 		      || (gimple_assign_rhs_code (use_stmt) != REALPART_EXPR
-			  && gimple_assign_rhs_code (use_stmt) != IMAGPART_EXPR))
+			  && gimple_assign_rhs_code (use_stmt) != IMAGPART_EXPR)
+		      || TREE_OPERAND (gimple_assign_rhs1 (use_stmt), 0) != lhs)
 		    {
 		      rewrite = false;
 		      break;

commit 08a6420c7b017bbb78abfbd315944147492280da
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Tue Apr 21 17:26:52 2020 +0100

    libstdc++: Document correct feature test macro, __cpp_lib_is_invocable
    
    The std::is_callable trait was renamed to is_invocable, but I never
    updated the manual to reflect the updated feature test macro.
    
            * doc/xml/manual/status_cxx2017.xml: Fix name of feature test macro.
            * doc/html/*: Regenerate.

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 495f6809729..8d3f7f9b185 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-21  Jonathan Wakely  <jwakely@redhat.com>
+
+	* doc/xml/manual/status_cxx2017.xml: Fix name of feature test macro.
+	* doc/html/*: Regenerate.
+
 2020-04-03  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backport from mainline
diff --git a/libstdc++-v3/doc/html/manual/status.html b/libstdc++-v3/doc/html/manual/status.html
index 970c73d992b..189b4e5eda2 100644
--- a/libstdc++-v3/doc/html/manual/status.html
+++ b/libstdc++-v3/doc/html/manual/status.html
@@ -689,7 +689,7 @@ Feature-testing recommendations for C++</a>.
 	<a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0077r2.html" target="_top">
 	P0077R2
 	</a>
-      </td><td align="center"> 7.1 </td><td align="left"><code class="code"> __cpp_lib_is_callable &gt;= 201603 </code></td></tr><tr><td align="left"> has_unique_object_representations </td><td align="left">
+      </td><td align="center"> 7.1 </td><td align="left"><code class="code"> __cpp_lib_is_invocable &gt;= 201703 </code></td></tr><tr><td align="left"> has_unique_object_representations </td><td align="left">
 	<a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0258r2.html" target="_top">
 	P0258R2
 	</a>
diff --git a/libstdc++-v3/doc/xml/manual/status_cxx2017.xml b/libstdc++-v3/doc/xml/manual/status_cxx2017.xml
index 7b5b4c41209..3931a7a71f9 100644
--- a/libstdc++-v3/doc/xml/manual/status_cxx2017.xml
+++ b/libstdc++-v3/doc/xml/manual/status_cxx2017.xml
@@ -458,7 +458,7 @@ Feature-testing recommendations for C++</link>.
 	</link>
       </entry>
       <entry align="center"> 7.1 </entry>
-      <entry><code> __cpp_lib_is_callable >= 201603 </code></entry>
+      <entry><code> __cpp_lib_is_invocable >= 201703 </code></entry>
     </row>
 
     <row>

commit b6295ad4c9ea45781341f0f31bc7e91e517d1a86
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Apr 22 00:16:56 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c1a6cf0b925..dd5a95e4f6b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200421
+20200422

commit 512b0ffab3bc4f334cbb36c598192c1da2abe330
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:07 2020 +0100

    aarch64: Add early clobber for aarch64_store_exclusive.
    
    gcc/ChangeLog:
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2018-07-16  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
    
            * config/aarch64/atomics.md (aarch64_store_execlusive<mode>): Add
            early clobber.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2d410b25d3f..446a5a8f759 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline.
+	2018-07-16  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	* config/aarch64/atomics.md (aarch64_store_execlusive<mode>): Add
+	early clobber.
+
 2020-04-21  Martin Jambor  <mjambor@suse.cz>
 
 	Backport from master
@@ -40,6 +48,7 @@
 	* config/i386/i386.c (rest_of_insert_endbranch): Insert ENDBR at
 	function entry if function will be called indirectly.
 
+
 2020-04-15  Uroš Bizjak  <ubizjak@gmail.com>
 
 	PR target/94603
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index 686e39ff2ee..fba5ec6db58 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -530,7 +530,7 @@
 )
 
 (define_insn "aarch64_store_exclusive<mode>"
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "=&r")
     (unspec_volatile:SI [(const_int 0)] UNSPECV_SX))
    (set (match_operand:ALLI 1 "aarch64_sync_memory_operand" "=Q")
     (unspec_volatile:ALLI

commit 1bf932b1ab9002089ddd79d64532186d7320d6b5
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:08 2020 +0100

    aarch64: Simplify LSE cas generation
    
    The cas insn is a single insn, and if expanded properly need not
    be split after reload.  Use the proper inputs for the insn.
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/aarch64.c (aarch64_expand_compare_and_swap):
            Force oldval into the rval register for TARGET_LSE; emit the compare
            during initial expansion so that it may be deleted if unused.
            (aarch64_gen_atomic_cas): Remove.
            * config/aarch64/atomics.md (aarch64_compare_and_swap<SHORT>_lse):
            Change =&r to +r for operand 0; use match_dup for operand 2;
            remove is_weak and mod_f operands as unused.  Drop the split
            and merge with...
            (aarch64_atomic_cas<SHORT>): ... this pattern's output; remove.
            (aarch64_compare_and_swap<GPI>_lse): Similarly.
            (aarch64_atomic_cas<GPI>): Similarly.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 446a5a8f759..8b356f7e651 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline.
+	2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/aarch64.c (aarch64_expand_compare_and_swap):
+	Force oldval into the rval register for TARGET_LSE; emit the compare
+	during initial expansion so that it may be deleted if unused.
+	(aarch64_gen_atomic_cas): Remove.
+	* config/aarch64/atomics.md (aarch64_compare_and_swap<SHORT>_lse):
+	Change =&r to +r for operand 0; use match_dup for operand 2;
+	remove is_weak and mod_f operands as unused.  Drop the split
+	and merge with...
+	(aarch64_atomic_cas<SHORT>): ... this pattern's output; remove.
+	(aarch64_compare_and_swap<GPI>_lse): Similarly.
+	(aarch64_atomic_cas<GPI>): Similarly.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index cda2895d28e..a03565c3b4e 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -496,7 +496,6 @@ rtx aarch64_load_tp (rtx);
 
 void aarch64_expand_compare_and_swap (rtx op[]);
 void aarch64_split_compare_and_swap (rtx op[]);
-void aarch64_gen_atomic_cas (rtx, rtx, rtx, rtx, rtx);
 
 bool aarch64_atomic_ldop_supported_p (enum rtx_code);
 void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 20761578fb6..c83a9f7ae78 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -14169,17 +14169,19 @@ aarch64_expand_compare_and_swap (rtx operands[])
 {
   rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x;
   machine_mode mode, cmp_mode;
-  typedef rtx (*gen_cas_fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+  typedef rtx (*gen_split_cas_fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+  typedef rtx (*gen_atomic_cas_fn) (rtx, rtx, rtx, rtx);
   int idx;
-  gen_cas_fn gen;
-  const gen_cas_fn split_cas[] =
+  gen_split_cas_fn split_gen;
+  gen_atomic_cas_fn atomic_gen;
+  const gen_split_cas_fn split_cas[] =
   {
     gen_aarch64_compare_and_swapqi,
     gen_aarch64_compare_and_swaphi,
     gen_aarch64_compare_and_swapsi,
     gen_aarch64_compare_and_swapdi
   };
-  const gen_cas_fn atomic_cas[] =
+  const gen_atomic_cas_fn atomic_cas[] =
   {
     gen_aarch64_compare_and_swapqi_lse,
     gen_aarch64_compare_and_swaphi_lse,
@@ -14238,14 +14240,29 @@ aarch64_expand_compare_and_swap (rtx operands[])
       gcc_unreachable ();
     }
   if (TARGET_LSE)
-    gen = atomic_cas[idx];
+    {
+      atomic_gen = atomic_cas[idx];
+      /* The CAS insn requires oldval and rval overlap, but we need to
+	 have a copy of oldval saved across the operation to tell if
+	 the operation is successful.  */
+      if (mode == QImode || mode == HImode)
+	rval = copy_to_mode_reg (SImode, gen_lowpart (SImode, oldval));
+      else if (reg_overlap_mentioned_p (rval, oldval))
+        rval = copy_to_mode_reg (mode, oldval);
+      else
+	emit_move_insn (rval, oldval);
+      emit_insn (atomic_gen (rval, mem, newval, mod_s));
+      aarch64_gen_compare_reg (EQ, rval, oldval);
+    }
   else
-    gen = split_cas[idx];
-
-  emit_insn (gen (rval, mem, oldval, newval, is_weak, mod_s, mod_f));
+    {
+      split_gen = split_cas[idx];
+      emit_insn (split_gen (rval, mem, oldval, newval, is_weak, mod_s, mod_f));
+    }
 
   if (mode == QImode || mode == HImode)
-    emit_move_insn (operands[1], gen_lowpart (mode, rval));
+    rval = gen_lowpart (mode, rval);
+  emit_move_insn (operands[1], rval);
 
   x = gen_rtx_REG (CCmode, CC_REGNUM);
   x = gen_rtx_EQ (SImode, x, const0_rtx);
@@ -14295,42 +14312,6 @@ aarch64_emit_post_barrier (enum memmodel model)
     }
 }
 
-/* Emit an atomic compare-and-swap operation.  RVAL is the destination register
-   for the data in memory.  EXPECTED is the value expected to be in memory.
-   DESIRED is the value to store to memory.  MEM is the memory location.  MODEL
-   is the memory ordering to use.  */
-
-void
-aarch64_gen_atomic_cas (rtx rval, rtx mem,
-			rtx expected, rtx desired,
-			rtx model)
-{
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-  machine_mode mode;
-
-  mode = GET_MODE (mem);
-
-  switch (mode)
-    {
-    case E_QImode: gen = gen_aarch64_atomic_casqi; break;
-    case E_HImode: gen = gen_aarch64_atomic_cashi; break;
-    case E_SImode: gen = gen_aarch64_atomic_cassi; break;
-    case E_DImode: gen = gen_aarch64_atomic_casdi; break;
-    default:
-      gcc_unreachable ();
-    }
-
-  /* Move the expected value into the CAS destination register.  */
-  emit_insn (gen_rtx_SET (rval, expected));
-
-  /* Emit the CAS.  */
-  emit_insn (gen (rval, mem, desired, model));
-
-  /* Compare the expected value with the value loaded by the CAS, to establish
-     whether the swap was made.  */
-  aarch64_gen_compare_reg (EQ, rval, expected);
-}
-
 /* Split a compare and swap pattern.  */
 
 void
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index fba5ec6db58..be970d105ff 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -85,56 +85,50 @@
   }
 )
 
-(define_insn_and_split "aarch64_compare_and_swap<mode>_lse"
-  [(set (reg:CC CC_REGNUM)					;; bool out
-    (unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
-   (set (match_operand:SI 0 "register_operand" "=&r")		;; val out
+(define_insn "aarch64_compare_and_swap<mode>_lse"
+  [(set (match_operand:SI 0 "register_operand" "+r")		;; val out
     (zero_extend:SI
-      (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
+     (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
    (set (match_dup 1)
     (unspec_volatile:SHORT
-      [(match_operand:SI 2 "aarch64_plus_operand" "rI")	;; expected
-       (match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ")	;; desired
-       (match_operand:SI 4 "const_int_operand")		;; is_weak
-       (match_operand:SI 5 "const_int_operand")		;; mod_s
-       (match_operand:SI 6 "const_int_operand")]	;; mod_f
+      [(match_dup 0)						;; expected
+       (match_operand:SHORT 2 "aarch64_reg_or_zero" "rZ")	;; desired
+       (match_operand:SI 3 "const_int_operand")]		;; mod_s
       UNSPECV_ATOMIC_CMPSW))]
   "TARGET_LSE"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-  {
-    aarch64_gen_atomic_cas (operands[0], operands[1],
-			    operands[2], operands[3],
-			    operands[5]);
-    DONE;
-  }
-)
+{
+  enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
+  if (is_mm_relaxed (model))
+    return "cas<atomic_sfx>\t%<w>0, %<w>2, %1";
+  else if (is_mm_acquire (model) || is_mm_consume (model))
+    return "casa<atomic_sfx>\t%<w>0, %<w>2, %1";
+  else if (is_mm_release (model))
+    return "casl<atomic_sfx>\t%<w>0, %<w>2, %1";
+  else
+    return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
+})
 
-(define_insn_and_split "aarch64_compare_and_swap<mode>_lse"
-  [(set (reg:CC CC_REGNUM)					;; bool out
-    (unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
-   (set (match_operand:GPI 0 "register_operand" "=&r")		;; val out
+(define_insn "aarch64_compare_and_swap<mode>_lse"
+  [(set (match_operand:GPI 0 "register_operand" "+r")		;; val out
     (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q"))   ;; memory
    (set (match_dup 1)
     (unspec_volatile:GPI
-      [(match_operand:GPI 2 "aarch64_plus_operand" "rI")	;; expect
-       (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")		;; desired
-       (match_operand:SI 4 "const_int_operand")			;; is_weak
-       (match_operand:SI 5 "const_int_operand")			;; mod_s
-       (match_operand:SI 6 "const_int_operand")]		;; mod_f
+      [(match_dup 0)						;; expected
+       (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")		;; desired
+       (match_operand:SI 3 "const_int_operand")]		;; mod_s
       UNSPECV_ATOMIC_CMPSW))]
   "TARGET_LSE"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-  {
-    aarch64_gen_atomic_cas (operands[0], operands[1],
-			    operands[2], operands[3],
-			    operands[5]);
-    DONE;
-  }
-)
+{
+  enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
+  if (is_mm_relaxed (model))
+    return "cas<atomic_sfx>\t%<w>0, %<w>2, %1";
+  else if (is_mm_acquire (model) || is_mm_consume (model))
+    return "casa<atomic_sfx>\t%<w>0, %<w>2, %1";
+  else if (is_mm_release (model))
+    return "casl<atomic_sfx>\t%<w>0, %<w>2, %1";
+  else
+    return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
+})
 
 (define_expand "atomic_exchange<mode>"
  [(match_operand:ALLI 0 "register_operand" "")
@@ -607,55 +601,6 @@
       return "swpal<atomic_sfx>\t%<w>2, %<w>0, %1";
   })
 
-;; Atomic compare-and-swap: HI and smaller modes.
-
-(define_insn "aarch64_atomic_cas<mode>"
- [(set (match_operand:SI 0 "register_operand" "+&r")		  ;; out
-   (zero_extend:SI
-    (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q")))  ;; memory.
-  (set (match_dup 1)
-   (unspec_volatile:SHORT
-    [(match_dup 0)
-     (match_operand:SHORT 2 "aarch64_reg_or_zero" "rZ")	;; value.
-     (match_operand:SI 3 "const_int_operand" "")]	;; model.
-    UNSPECV_ATOMIC_CAS))]
- "TARGET_LSE && reload_completed"
-{
-  enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
-  if (is_mm_relaxed (model))
-    return "cas<atomic_sfx>\t%<w>0, %<w>2, %1";
-  else if (is_mm_acquire (model) || is_mm_consume (model))
-    return "casa<atomic_sfx>\t%<w>0, %<w>2, %1";
-  else if (is_mm_release (model))
-    return "casl<atomic_sfx>\t%<w>0, %<w>2, %1";
-  else
-    return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
-})
-
-;; Atomic compare-and-swap: SI and larger modes.
-
-(define_insn "aarch64_atomic_cas<mode>"
- [(set (match_operand:GPI 0 "register_operand" "+&r")	      ;; out
-   (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q"))  ;; memory.
-  (set (match_dup 1)
-   (unspec_volatile:GPI
-    [(match_dup 0)
-     (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")	;; value.
-     (match_operand:SI 3 "const_int_operand" "")]	;; model.
-    UNSPECV_ATOMIC_CAS))]
-  "TARGET_LSE && reload_completed"
-{
-    enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
-    if (is_mm_relaxed (model))
-      return "cas<atomic_sfx>\t%<w>0, %<w>2, %1";
-    else if (is_mm_acquire (model) || is_mm_consume (model))
-      return "casa<atomic_sfx>\t%<w>0, %<w>2, %1";
-    else if (is_mm_release (model))
-      return "casl<atomic_sfx>\t%<w>0, %<w>2, %1";
-    else
-      return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
-})
-
 ;; Atomic load-op: Load data, operate, store result, keep data.
 
 (define_insn "aarch64_atomic_load<atomic_ldop><mode>"

commit 369a4d6dd2df645f1870506d8dd6a5a265955b34
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:09 2020 +0100

    aarch64: Improve cas generation
    
    Do not zero-extend the input to the cas for subword operations;
    instead, use the appropriate zero-extending compare insns.
    Correct the predicates and constraints for immediate expected operand.
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): New.
            (aarch64_split_compare_and_swap): Use it.
            (aarch64_expand_compare_and_swap): Likewise.  Remove convert_modes;
            test oldval against the proper predicate.
            * config/aarch64/atomics.md (atomic_compare_and_swap<ALLI>):
            Use nonmemory_operand for expected.
            (cas_short_expected_pred): New.
            (aarch64_compare_and_swap<SHORT>): Use it; use "rn" not "rI" to match.
            (aarch64_compare_and_swap<GPI>): Use "rn" not "rI" for expected.
            * config/aarch64/predicates.md (aarch64_plushi_immediate): New.
            (aarch64_plushi_operand): New.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8b356f7e651..231cf8a38c2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline.
+	2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): New.
+	(aarch64_split_compare_and_swap): Use it.
+	(aarch64_expand_compare_and_swap): Likewise.  Remove convert_modes;
+	test oldval against the proper predicate.
+	* config/aarch64/atomics.md (atomic_compare_and_swap<ALLI>):
+	Use nonmemory_operand for expected.
+	(cas_short_expected_pred): New.
+	(aarch64_compare_and_swap<SHORT>): Use it; use "rn" not "rI" to match.
+	(aarch64_compare_and_swap<GPI>): Use "rn" not "rI" for expected.
+	* config/aarch64/predicates.md (aarch64_plushi_immediate): New.
+	(aarch64_plushi_operand): New.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index c83a9f7ae78..b6a6e314153 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1524,6 +1524,33 @@ aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y)
   return cc_reg;
 }
 
+/* Similarly, but maybe zero-extend Y if Y_MODE < SImode.  */
+
+static rtx
+aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x, rtx y,
+                                  machine_mode y_mode)
+{
+  if (y_mode == E_QImode || y_mode == E_HImode)
+    {
+      if (CONST_INT_P (y))
+	y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode));
+      else
+	{
+	  rtx t, cc_reg;
+	  machine_mode cc_mode;
+
+	  t = gen_rtx_ZERO_EXTEND (SImode, y);
+	  t = gen_rtx_COMPARE (CC_SWPmode, t, x);
+	  cc_mode = CC_SWPmode;
+	  cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM);
+	  emit_set_insn (cc_reg, t);
+	  return cc_reg;
+	}
+    }
+
+  return aarch64_gen_compare_reg (code, x, y);
+}
+
 /* Build the SYMBOL_REF for __tls_get_addr.  */
 
 static GTY(()) rtx tls_get_addr_libfunc;
@@ -14167,20 +14194,11 @@ aarch64_emit_unlikely_jump (rtx insn)
 void
 aarch64_expand_compare_and_swap (rtx operands[])
 {
-  rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x;
-  machine_mode mode, cmp_mode;
-  typedef rtx (*gen_split_cas_fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+  rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x, cc_reg;
+  machine_mode mode, r_mode;
   typedef rtx (*gen_atomic_cas_fn) (rtx, rtx, rtx, rtx);
   int idx;
-  gen_split_cas_fn split_gen;
   gen_atomic_cas_fn atomic_gen;
-  const gen_split_cas_fn split_cas[] =
-  {
-    gen_aarch64_compare_and_swapqi,
-    gen_aarch64_compare_and_swaphi,
-    gen_aarch64_compare_and_swapsi,
-    gen_aarch64_compare_and_swapdi
-  };
   const gen_atomic_cas_fn atomic_cas[] =
   {
     gen_aarch64_compare_and_swapqi_lse,
@@ -14198,36 +14216,19 @@ aarch64_expand_compare_and_swap (rtx operands[])
   mod_s = operands[6];
   mod_f = operands[7];
   mode = GET_MODE (mem);
-  cmp_mode = mode;
 
   /* Normally the succ memory model must be stronger than fail, but in the
      unlikely event of fail being ACQUIRE and succ being RELEASE we need to
      promote succ to ACQ_REL so that we don't lose the acquire semantics.  */
-
   if (is_mm_acquire (memmodel_from_int (INTVAL (mod_f)))
       && is_mm_release (memmodel_from_int (INTVAL (mod_s))))
     mod_s = GEN_INT (MEMMODEL_ACQ_REL);
 
-  switch (mode)
+  r_mode = mode;
+  if (mode == QImode || mode == HImode)
     {
-    case E_QImode:
-    case E_HImode:
-      /* For short modes, we're going to perform the comparison in SImode,
-	 so do the zero-extension now.  */
-      cmp_mode = SImode;
-      rval = gen_reg_rtx (SImode);
-      oldval = convert_modes (SImode, mode, oldval, true);
-      /* Fall through.  */
-
-    case E_SImode:
-    case E_DImode:
-      /* Force the value into a register if needed.  */
-      if (!aarch64_plus_operand (oldval, mode))
-	oldval = force_reg (cmp_mode, oldval);
-      break;
-
-    default:
-      gcc_unreachable ();
+      r_mode = SImode;
+      rval = gen_reg_rtx (r_mode);
     }
 
   switch (mode)
@@ -14245,27 +14246,49 @@ aarch64_expand_compare_and_swap (rtx operands[])
       /* The CAS insn requires oldval and rval overlap, but we need to
 	 have a copy of oldval saved across the operation to tell if
 	 the operation is successful.  */
-      if (mode == QImode || mode == HImode)
-	rval = copy_to_mode_reg (SImode, gen_lowpart (SImode, oldval));
-      else if (reg_overlap_mentioned_p (rval, oldval))
-        rval = copy_to_mode_reg (mode, oldval);
+      if (reg_overlap_mentioned_p (rval, oldval))
+        rval = copy_to_mode_reg (r_mode, oldval);
       else
-	emit_move_insn (rval, oldval);
+	emit_move_insn (rval, gen_lowpart (r_mode, oldval));
+
       emit_insn (atomic_gen (rval, mem, newval, mod_s));
-      aarch64_gen_compare_reg (EQ, rval, oldval);
+
+      cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
     }
   else
     {
-      split_gen = split_cas[idx];
-      emit_insn (split_gen (rval, mem, oldval, newval, is_weak, mod_s, mod_f));
+      /* The oldval predicate varies by mode.  Test it and force to reg.  */
+      insn_code code;
+      switch (mode)
+	{
+	  case E_QImode:
+	    code = CODE_FOR_aarch64_compare_and_swapqi;
+	    break;
+	  case E_HImode:
+	    code = CODE_FOR_aarch64_compare_and_swaphi;
+	    break;
+	  case E_SImode:
+	    code = CODE_FOR_aarch64_compare_and_swapsi;
+	    break;
+	  case E_DImode:
+	    code = CODE_FOR_aarch64_compare_and_swapdi;
+	    break;
+	  default:
+	    gcc_unreachable ();
+	}
+      if (!insn_data[code].operand[2].predicate (oldval, mode))
+	oldval = force_reg (mode, oldval);
+
+      emit_insn (GEN_FCN (code) (rval, mem, oldval, newval,
+				 is_weak, mod_s, mod_f));
+      cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
     }
 
-  if (mode == QImode || mode == HImode)
+  if (r_mode != mode)
     rval = gen_lowpart (mode, rval);
   emit_move_insn (operands[1], rval);
 
-  x = gen_rtx_REG (CCmode, CC_REGNUM);
-  x = gen_rtx_EQ (SImode, x, const0_rtx);
+  x = gen_rtx_EQ (SImode, cc_reg, const0_rtx);
   emit_insn (gen_rtx_SET (bval, x));
 }
 
@@ -14374,10 +14397,10 @@ aarch64_split_compare_and_swap (rtx operands[])
     }
   else
     {
-      cond = aarch64_gen_compare_reg (NE, rval, oldval);
+      cond = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
       x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
       x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
-				 gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
+				gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
       aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
     }
 
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index be970d105ff..b0e84b8addd 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -24,8 +24,8 @@
   [(match_operand:SI 0 "register_operand" "")			;; bool out
    (match_operand:ALLI 1 "register_operand" "")			;; val out
    (match_operand:ALLI 2 "aarch64_sync_memory_operand" "")	;; memory
-   (match_operand:ALLI 3 "general_operand" "")			;; expected
-   (match_operand:ALLI 4 "aarch64_reg_or_zero" "")			;; desired
+   (match_operand:ALLI 3 "nonmemory_operand" "")		;; expected
+   (match_operand:ALLI 4 "aarch64_reg_or_zero" "")		;; desired
    (match_operand:SI 5 "const_int_operand")			;; is_weak
    (match_operand:SI 6 "const_int_operand")			;; mod_s
    (match_operand:SI 7 "const_int_operand")]			;; mod_f
@@ -36,19 +36,22 @@
   }
 )
 
+(define_mode_attr cas_short_expected_pred
+  [(QI "aarch64_reg_or_imm") (HI "aarch64_plushi_operand")])
+
 (define_insn_and_split "aarch64_compare_and_swap<mode>"
   [(set (reg:CC CC_REGNUM)					;; bool out
     (unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
-   (set (match_operand:SI 0 "register_operand" "=&r")	   ;; val out
+   (set (match_operand:SI 0 "register_operand" "=&r")		;; val out
     (zero_extend:SI
       (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
    (set (match_dup 1)
     (unspec_volatile:SHORT
-      [(match_operand:SI 2 "aarch64_plus_operand" "rI")	;; expected
+      [(match_operand:SHORT 2 "<cas_short_expected_pred>" "rn")	;; expected
        (match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ")	;; desired
-       (match_operand:SI 4 "const_int_operand")		;; is_weak
-       (match_operand:SI 5 "const_int_operand")		;; mod_s
-       (match_operand:SI 6 "const_int_operand")]	;; mod_f
+       (match_operand:SI 4 "const_int_operand")			;; is_weak
+       (match_operand:SI 5 "const_int_operand")			;; mod_s
+       (match_operand:SI 6 "const_int_operand")]		;; mod_f
       UNSPECV_ATOMIC_CMPSW))
    (clobber (match_scratch:SI 7 "=&r"))]
   ""
@@ -68,7 +71,7 @@
     (match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q"))   ;; memory
    (set (match_dup 1)
     (unspec_volatile:GPI
-      [(match_operand:GPI 2 "aarch64_plus_operand" "rI")	;; expect
+      [(match_operand:GPI 2 "aarch64_plus_operand" "rn")	;; expect
        (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")		;; desired
        (match_operand:SI 4 "const_int_operand")			;; is_weak
        (match_operand:SI 5 "const_int_operand")			;; mod_s
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 5d41d435040..7b0565a00b1 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -110,6 +110,18 @@
   (ior (match_operand 0 "register_operand")
        (match_operand 0 "aarch64_plus_immediate")))
 
+(define_predicate "aarch64_plushi_immediate"
+  (match_code "const_int")
+{
+  HOST_WIDE_INT val = INTVAL (op);
+  /* The HImode value must be zero-extendable to an SImode plus_operand.  */
+  return ((val & 0xfff) == val || sext_hwi (val & 0xf000, 16) == val);
+})
+
+(define_predicate "aarch64_plushi_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_operand 0 "aarch64_plushi_immediate")))
+
 (define_predicate "aarch64_pluslong_immediate"
   (and (match_code "const_int")
        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))

commit 5d8ff6f1ff2cef121dc33d954535fc4cf5648cb6
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:09 2020 +0100

    aarch64: Improve swp generation
    
    Allow zero as an input; fix constraints; avoid unnecessary split.
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/aarch64.c (aarch64_emit_atomic_swap): Remove.
            (aarch64_gen_atomic_ldop): Don't call it.
            * config/aarch64/atomics.md (atomic_exchange<ALLI>):
            Use aarch64_reg_or_zero.
            (aarch64_atomic_exchange<ALLI>): Likewise.
            (aarch64_atomic_exchange<ALLI>_lse): Remove split; remove & from
            operand 0; use aarch64_reg_or_zero for input; merge ...
            (aarch64_atomic_swp<ALLI>): ... this and remove.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 231cf8a38c2..2d8a8ea6b0c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline.
+	2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/aarch64.c (aarch64_emit_atomic_swap): Remove.
+	(aarch64_gen_atomic_ldop): Don't call it.
+	* config/aarch64/atomics.md (atomic_exchange<ALLI>):
+	Use aarch64_reg_or_zero.
+	(aarch64_atomic_exchange<ALLI>): Likewise.
+	(aarch64_atomic_exchange<ALLI>_lse): Remove split; remove & from
+	operand 0; use aarch64_reg_or_zero for input; merge ...
+	(aarch64_atomic_swp<ALLI>): ... this and remove.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index b6a6e314153..bac69474598 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -14454,27 +14454,6 @@ aarch64_emit_bic (machine_mode mode, rtx dst, rtx s1, rtx s2, int shift)
   emit_insn (gen (dst, s2, shift_rtx, s1));
 }
 
-/* Emit an atomic swap.  */
-
-static void
-aarch64_emit_atomic_swap (machine_mode mode, rtx dst, rtx value,
-			  rtx mem, rtx model)
-{
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-
-  switch (mode)
-    {
-    case E_QImode: gen = gen_aarch64_atomic_swpqi; break;
-    case E_HImode: gen = gen_aarch64_atomic_swphi; break;
-    case E_SImode: gen = gen_aarch64_atomic_swpsi; break;
-    case E_DImode: gen = gen_aarch64_atomic_swpdi; break;
-    default:
-      gcc_unreachable ();
-    }
-
-  emit_insn (gen (dst, mem, value, model));
-}
-
 /* Operations supported by aarch64_emit_atomic_load_op.  */
 
 enum aarch64_atomic_load_op_code
@@ -14587,10 +14566,6 @@ aarch64_gen_atomic_ldop (enum rtx_code code, rtx out_data, rtx out_result,
      a SET then emit a swap instruction and finish.  */
   switch (code)
     {
-    case SET:
-      aarch64_emit_atomic_swap (mode, out_data, src, mem, model_rtx);
-      return;
-
     case MINUS:
       /* Negate the value and treat it as a PLUS.  */
       {
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index b0e84b8addd..6cc14fbf6c1 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -136,7 +136,7 @@
 (define_expand "atomic_exchange<mode>"
  [(match_operand:ALLI 0 "register_operand" "")
   (match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
-  (match_operand:ALLI 2 "register_operand" "")
+  (match_operand:ALLI 2 "aarch64_reg_or_zero" "")
   (match_operand:SI 3 "const_int_operand" "")]
   ""
   {
@@ -156,10 +156,10 @@
 
 (define_insn_and_split "aarch64_atomic_exchange<mode>"
   [(set (match_operand:ALLI 0 "register_operand" "=&r")		;; output
-    (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
+    (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))	;; memory
    (set (match_dup 1)
     (unspec_volatile:ALLI
-      [(match_operand:ALLI 2 "register_operand" "r")	;; input
+      [(match_operand:ALLI 2 "aarch64_reg_or_zero" "rZ")	;; input
        (match_operand:SI 3 "const_int_operand" "")]		;; model
       UNSPECV_ATOMIC_EXCHG))
    (clobber (reg:CC CC_REGNUM))
@@ -175,22 +175,25 @@
   }
 )
 
-(define_insn_and_split "aarch64_atomic_exchange<mode>_lse"
-  [(set (match_operand:ALLI 0 "register_operand" "=&r")
+(define_insn "aarch64_atomic_exchange<mode>_lse"
+  [(set (match_operand:ALLI 0 "register_operand" "=r")
     (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
    (set (match_dup 1)
     (unspec_volatile:ALLI
-      [(match_operand:ALLI 2 "register_operand" "r")
+      [(match_operand:ALLI 2 "aarch64_reg_or_zero" "rZ")
        (match_operand:SI 3 "const_int_operand" "")]
       UNSPECV_ATOMIC_EXCHG))]
   "TARGET_LSE"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
   {
-    aarch64_gen_atomic_ldop (SET, operands[0], NULL, operands[1],
-			     operands[2], operands[3]);
-    DONE;
+    enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
+    if (is_mm_relaxed (model))
+      return "swp<atomic_sfx>\t%<w>2, %<w>0, %1";
+    else if (is_mm_acquire (model) || is_mm_consume (model))
+      return "swpa<atomic_sfx>\t%<w>2, %<w>0, %1";
+    else if (is_mm_release (model))
+      return "swpl<atomic_sfx>\t%<w>2, %<w>0, %1";
+    else
+      return "swpal<atomic_sfx>\t%<w>2, %<w>0, %1";
   }
 )
 
@@ -582,28 +585,6 @@
 
 ;; ARMv8.1-A LSE instructions.
 
-;; Atomic swap with memory.
-(define_insn "aarch64_atomic_swp<mode>"
- [(set (match_operand:ALLI 0 "register_operand" "+&r")
-   (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
-  (set (match_dup 1)
-   (unspec_volatile:ALLI
-    [(match_operand:ALLI 2 "register_operand" "r")
-     (match_operand:SI 3 "const_int_operand" "")]
-    UNSPECV_ATOMIC_SWP))]
-  "TARGET_LSE && reload_completed"
-  {
-    enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
-    if (is_mm_relaxed (model))
-      return "swp<atomic_sfx>\t%<w>2, %<w>0, %1";
-    else if (is_mm_acquire (model) || is_mm_consume (model))
-      return "swpa<atomic_sfx>\t%<w>2, %<w>0, %1";
-    else if (is_mm_release (model))
-      return "swpl<atomic_sfx>\t%<w>2, %<w>0, %1";
-    else
-      return "swpal<atomic_sfx>\t%<w>2, %<w>0, %1";
-  })
-
 ;; Atomic load-op: Load data, operate, store result, keep data.
 
 (define_insn "aarch64_atomic_load<atomic_ldop><mode>"

commit f557aa1a836377d49fdbd4e7cecb2eede55b1dd2
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:10 2020 +0100

    aarch64: Improve atomic-op lse generation
    
    Fix constraints; avoid unnecessary split.  Drop the use of the atomic_op
    iterator in favor of the ATOMIC_LDOP iterator; this is simplier and more
    logical for ldclr aka bic.
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/aarch64.c (aarch64_emit_bic): Remove.
            (aarch64_atomic_ldop_supported_p): Remove.
            (aarch64_gen_atomic_ldop): Remove.
            * config/aarch64/atomic.md (atomic_<atomic_optab><ALLI>):
            Fully expand LSE operations here.
            (atomic_fetch_<atomic_optab><ALLI>): Likewise.
            (atomic_<atomic_optab>_fetch<ALLI>): Likewise.
            (aarch64_atomic_<ATOMIC_LDOP><ALLI>_lse): Drop atomic_op iterator
            and use ATOMIC_LDOP instead; use register_operand for the input;
            drop the split and emit insns directly.
            (aarch64_atomic_fetch_<ATOMIC_LDOP><ALLI>_lse): Likewise.
            (aarch64_atomic_<atomic_op>_fetch<ALLI>_lse): Remove.
            (aarch64_atomic_load<ATOMIC_LDOP><ALLI>): Remove.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2d8a8ea6b0c..cb5489a4587 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline.
+	2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/aarch64.c (aarch64_emit_bic): Remove.
+	(aarch64_atomic_ldop_supported_p): Remove.
+	(aarch64_gen_atomic_ldop): Remove.
+	* config/aarch64/atomic.md (atomic_<atomic_optab><ALLI>):
+	Fully expand LSE operations here.
+	(atomic_fetch_<atomic_optab><ALLI>): Likewise.
+	(atomic_<atomic_optab>_fetch<ALLI>): Likewise.
+	(aarch64_atomic_<ATOMIC_LDOP><ALLI>_lse): Drop atomic_op iterator
+	and use ATOMIC_LDOP instead; use register_operand for the input;
+	drop the split and emit insns directly.
+	(aarch64_atomic_fetch_<ATOMIC_LDOP><ALLI>_lse): Likewise.
+	(aarch64_atomic_<atomic_op>_fetch<ALLI>_lse): Remove.
+	(aarch64_atomic_load<ATOMIC_LDOP><ALLI>): Remove.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index a03565c3b4e..da68ce0e7d0 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -497,8 +497,6 @@ rtx aarch64_load_tp (rtx);
 void aarch64_expand_compare_and_swap (rtx op[]);
 void aarch64_split_compare_and_swap (rtx op[]);
 
-bool aarch64_atomic_ldop_supported_p (enum rtx_code);
-void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
 
 bool aarch64_gen_adjusted_ldpstp (rtx *, bool, scalar_mode, RTX_CODE);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index bac69474598..1068cfd899a 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -14292,32 +14292,6 @@ aarch64_expand_compare_and_swap (rtx operands[])
   emit_insn (gen_rtx_SET (bval, x));
 }
 
-/* Test whether the target supports using a atomic load-operate instruction.
-   CODE is the operation and AFTER is TRUE if the data in memory after the
-   operation should be returned and FALSE if the data before the operation
-   should be returned.  Returns FALSE if the operation isn't supported by the
-   architecture.  */
-
-bool
-aarch64_atomic_ldop_supported_p (enum rtx_code code)
-{
-  if (!TARGET_LSE)
-    return false;
-
-  switch (code)
-    {
-    case SET:
-    case AND:
-    case IOR:
-    case XOR:
-    case MINUS:
-    case PLUS:
-      return true;
-    default:
-      return false;
-    }
-}
-
 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
    sequence implementing an atomic operation.  */
 
@@ -14435,227 +14409,6 @@ aarch64_split_compare_and_swap (rtx operands[])
     aarch64_emit_post_barrier (model);
 }
 
-/* Emit a BIC instruction.  */
-
-static void
-aarch64_emit_bic (machine_mode mode, rtx dst, rtx s1, rtx s2, int shift)
-{
-  rtx shift_rtx = GEN_INT (shift);
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-
-  switch (mode)
-    {
-    case E_SImode: gen = gen_and_one_cmpl_lshrsi3; break;
-    case E_DImode: gen = gen_and_one_cmpl_lshrdi3; break;
-    default:
-      gcc_unreachable ();
-    }
-
-  emit_insn (gen (dst, s2, shift_rtx, s1));
-}
-
-/* Operations supported by aarch64_emit_atomic_load_op.  */
-
-enum aarch64_atomic_load_op_code
-{
-  AARCH64_LDOP_PLUS,	/* A + B  */
-  AARCH64_LDOP_XOR,	/* A ^ B  */
-  AARCH64_LDOP_OR,	/* A | B  */
-  AARCH64_LDOP_BIC	/* A & ~B  */
-};
-
-/* Emit an atomic load-operate.  */
-
-static void
-aarch64_emit_atomic_load_op (enum aarch64_atomic_load_op_code code,
-			     machine_mode mode, rtx dst, rtx src,
-			     rtx mem, rtx model)
-{
-  typedef rtx (*aarch64_atomic_load_op_fn) (rtx, rtx, rtx, rtx);
-  const aarch64_atomic_load_op_fn plus[] =
-  {
-    gen_aarch64_atomic_loadaddqi,
-    gen_aarch64_atomic_loadaddhi,
-    gen_aarch64_atomic_loadaddsi,
-    gen_aarch64_atomic_loadadddi
-  };
-  const aarch64_atomic_load_op_fn eor[] =
-  {
-    gen_aarch64_atomic_loadeorqi,
-    gen_aarch64_atomic_loadeorhi,
-    gen_aarch64_atomic_loadeorsi,
-    gen_aarch64_atomic_loadeordi
-  };
-  const aarch64_atomic_load_op_fn ior[] =
-  {
-    gen_aarch64_atomic_loadsetqi,
-    gen_aarch64_atomic_loadsethi,
-    gen_aarch64_atomic_loadsetsi,
-    gen_aarch64_atomic_loadsetdi
-  };
-  const aarch64_atomic_load_op_fn bic[] =
-  {
-    gen_aarch64_atomic_loadclrqi,
-    gen_aarch64_atomic_loadclrhi,
-    gen_aarch64_atomic_loadclrsi,
-    gen_aarch64_atomic_loadclrdi
-  };
-  aarch64_atomic_load_op_fn gen;
-  int idx = 0;
-
-  switch (mode)
-    {
-    case E_QImode: idx = 0; break;
-    case E_HImode: idx = 1; break;
-    case E_SImode: idx = 2; break;
-    case E_DImode: idx = 3; break;
-    default:
-      gcc_unreachable ();
-    }
-
-  switch (code)
-    {
-    case AARCH64_LDOP_PLUS: gen = plus[idx]; break;
-    case AARCH64_LDOP_XOR: gen = eor[idx]; break;
-    case AARCH64_LDOP_OR: gen = ior[idx]; break;
-    case AARCH64_LDOP_BIC: gen = bic[idx]; break;
-    default:
-      gcc_unreachable ();
-    }
-
-  emit_insn (gen (dst, mem, src, model));
-}
-
-/* Emit an atomic load+operate.  CODE is the operation.  OUT_DATA is the
-   location to store the data read from memory.  OUT_RESULT is the location to
-   store the result of the operation.  MEM is the memory location to read and
-   modify.  MODEL_RTX is the memory ordering to use.  VALUE is the second
-   operand for the operation.  Either OUT_DATA or OUT_RESULT, but not both, can
-   be NULL.  */
-
-void
-aarch64_gen_atomic_ldop (enum rtx_code code, rtx out_data, rtx out_result,
-			 rtx mem, rtx value, rtx model_rtx)
-{
-  machine_mode mode = GET_MODE (mem);
-  machine_mode wmode = (mode == DImode ? DImode : SImode);
-  const bool short_mode = (mode < SImode);
-  aarch64_atomic_load_op_code ldop_code;
-  rtx src;
-  rtx x;
-
-  if (out_data)
-    out_data = gen_lowpart (mode, out_data);
-
-  if (out_result)
-    out_result = gen_lowpart (mode, out_result);
-
-  /* Make sure the value is in a register, putting it into a destination
-     register if it needs to be manipulated.  */
-  if (!register_operand (value, mode)
-      || code == AND || code == MINUS)
-    {
-      src = out_result ? out_result : out_data;
-      emit_move_insn (src, gen_lowpart (mode, value));
-    }
-  else
-    src = value;
-  gcc_assert (register_operand (src, mode));
-
-  /* Preprocess the data for the operation as necessary.  If the operation is
-     a SET then emit a swap instruction and finish.  */
-  switch (code)
-    {
-    case MINUS:
-      /* Negate the value and treat it as a PLUS.  */
-      {
-	rtx neg_src;
-
-	/* Resize the value if necessary.  */
-	if (short_mode)
-	  src = gen_lowpart (wmode, src);
-
-	neg_src = gen_rtx_NEG (wmode, src);
-	emit_insn (gen_rtx_SET (src, neg_src));
-
-	if (short_mode)
-	  src = gen_lowpart (mode, src);
-      }
-      /* Fall-through.  */
-    case PLUS:
-      ldop_code = AARCH64_LDOP_PLUS;
-      break;
-
-    case IOR:
-      ldop_code = AARCH64_LDOP_OR;
-      break;
-
-    case XOR:
-      ldop_code = AARCH64_LDOP_XOR;
-      break;
-
-    case AND:
-      {
-	rtx not_src;
-
-	/* Resize the value if necessary.  */
-	if (short_mode)
-	  src = gen_lowpart (wmode, src);
-
-	not_src = gen_rtx_NOT (wmode, src);
-	emit_insn (gen_rtx_SET (src, not_src));
-
-	if (short_mode)
-	  src = gen_lowpart (mode, src);
-      }
-      ldop_code = AARCH64_LDOP_BIC;
-      break;
-
-    default:
-      /* The operation can't be done with atomic instructions.  */
-      gcc_unreachable ();
-    }
-
-  aarch64_emit_atomic_load_op (ldop_code, mode, out_data, src, mem, model_rtx);
-
-  /* If necessary, calculate the data in memory after the update by redoing the
-     operation from values in registers.  */
-  if (!out_result)
-    return;
-
-  if (short_mode)
-    {
-      src = gen_lowpart (wmode, src);
-      out_data = gen_lowpart (wmode, out_data);
-      out_result = gen_lowpart (wmode, out_result);
-    }
-
-  x = NULL_RTX;
-
-  switch (code)
-    {
-    case MINUS:
-    case PLUS:
-      x = gen_rtx_PLUS (wmode, out_data, src);
-      break;
-    case IOR:
-      x = gen_rtx_IOR (wmode, out_data, src);
-      break;
-    case XOR:
-      x = gen_rtx_XOR (wmode, out_data, src);
-      break;
-    case AND:
-      aarch64_emit_bic (wmode, out_result, out_data, src, 0);
-      return;
-    default:
-      gcc_unreachable ();
-    }
-
-  emit_set_insn (out_result, x);
-
-  return;
-}
-
 /* Split an atomic operation.  */
 
 void
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index 6cc14fbf6c1..47a8a40c5b8 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -207,13 +207,37 @@
     rtx (*gen) (rtx, rtx, rtx);
 
     /* Use an atomic load-operate instruction when possible.  */
-    if (aarch64_atomic_ldop_supported_p (<CODE>))
-      gen = gen_aarch64_atomic_<atomic_optab><mode>_lse;
+    if (TARGET_LSE)
+      {
+	switch (<CODE>)
+	  {
+	  case MINUS:
+	    operands[1] = expand_simple_unop (<MODE>mode, NEG, operands[1],
+					      NULL, 1);
+	    /* fallthru */
+	  case PLUS:
+	    gen = gen_aarch64_atomic_add<mode>_lse;
+	    break;
+	  case IOR:
+	    gen = gen_aarch64_atomic_ior<mode>_lse;
+	    break;
+	  case XOR:
+	    gen = gen_aarch64_atomic_xor<mode>_lse;
+	    break;
+	  case AND:
+	    operands[1] = expand_simple_unop (<MODE>mode, NOT, operands[1],
+					      NULL, 1);
+	    gen = gen_aarch64_atomic_bic<mode>_lse;
+	    break;
+	  default:
+	    gcc_unreachable ();
+	  }
+	operands[1] = force_reg (<MODE>mode, operands[1]);
+      }
     else
       gen = gen_aarch64_atomic_<atomic_optab><mode>;
 
     emit_insn (gen (operands[0], operands[1], operands[2]));
-
     DONE;
   }
 )
@@ -239,22 +263,25 @@
   }
 )
 
-(define_insn_and_split "aarch64_atomic_<atomic_optab><mode>_lse"
+(define_insn "aarch64_atomic_<atomic_ldoptab><mode>_lse"
   [(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q")
-    (unspec_volatile:ALLI
-      [(atomic_op:ALLI (match_dup 0)
-	(match_operand:ALLI 1 "<atomic_op_operand>" "r<const_atomic>"))
-       (match_operand:SI 2 "const_int_operand")]
-      UNSPECV_ATOMIC_OP))
+	(unspec_volatile:ALLI
+	  [(match_dup 0)
+	   (match_operand:ALLI 1 "register_operand" "r")
+	   (match_operand:SI 2 "const_int_operand")]
+      ATOMIC_LDOP))
    (clobber (match_scratch:ALLI 3 "=&r"))]
   "TARGET_LSE"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
   {
-    aarch64_gen_atomic_ldop (<CODE>, operands[3], NULL, operands[0],
-			     operands[1], operands[2]);
-    DONE;
+   enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
+   if (is_mm_relaxed (model))
+     return "ld<atomic_ldop><atomic_sfx>\t%<w>1, %<w>3, %0";
+   else if (is_mm_release (model))
+     return "ld<atomic_ldop>l<atomic_sfx>\t%<w>1, %<w>3, %0";
+   else if (is_mm_acquire (model) || is_mm_consume (model))
+     return "ld<atomic_ldop>a<atomic_sfx>\t%<w>1, %<w>3, %0";
+   else
+     return "ld<atomic_ldop>al<atomic_sfx>\t%<w>1, %<w>3, %0";
   }
 )
 
@@ -280,7 +307,7 @@
   }
 )
 
-;; Load-operate-store, returning the updated memory data.
+;; Load-operate-store, returning the original memory data.
 
 (define_expand "atomic_fetch_<atomic_optab><mode>"
  [(match_operand:ALLI 0 "register_operand" "")
@@ -293,13 +320,37 @@
   rtx (*gen) (rtx, rtx, rtx, rtx);
 
   /* Use an atomic load-operate instruction when possible.  */
-  if (aarch64_atomic_ldop_supported_p (<CODE>))
-    gen = gen_aarch64_atomic_fetch_<atomic_optab><mode>_lse;
+  if (TARGET_LSE)
+    {
+      switch (<CODE>)
+        {
+	case MINUS:
+	  operands[2] = expand_simple_unop (<MODE>mode, NEG, operands[2],
+					    NULL, 1);
+	  /* fallthru */
+	case PLUS:
+	  gen = gen_aarch64_atomic_fetch_add<mode>_lse;
+	  break;
+	case IOR:
+	  gen = gen_aarch64_atomic_fetch_ior<mode>_lse;
+	  break;
+	case XOR:
+	  gen = gen_aarch64_atomic_fetch_xor<mode>_lse;
+	  break;
+	case AND:
+	  operands[2] = expand_simple_unop (<MODE>mode, NOT, operands[2],
+					    NULL, 1);
+	  gen = gen_aarch64_atomic_fetch_bic<mode>_lse;
+	  break;
+	default:
+	  gcc_unreachable ();
+	}
+      operands[2] = force_reg (<MODE>mode, operands[2]);
+    }
   else
     gen = gen_aarch64_atomic_fetch_<atomic_optab><mode>;
 
   emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
-
   DONE;
 })
 
@@ -326,23 +377,26 @@
   }
 )
 
-(define_insn_and_split "aarch64_atomic_fetch_<atomic_optab><mode>_lse"
-  [(set (match_operand:ALLI 0 "register_operand" "=&r")
-    (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
+(define_insn "aarch64_atomic_fetch_<atomic_ldoptab><mode>_lse"
+  [(set (match_operand:ALLI 0 "register_operand" "=r")
+	(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
    (set (match_dup 1)
-    (unspec_volatile:ALLI
-      [(atomic_op:ALLI (match_dup 1)
-	(match_operand:ALLI 2 "<atomic_op_operand>" "r<const_atomic>"))
-       (match_operand:SI 3 "const_int_operand")]
-      UNSPECV_ATOMIC_LDOP))]
+	(unspec_volatile:ALLI
+	  [(match_dup 1)
+	   (match_operand:ALLI 2 "register_operand" "r")
+	   (match_operand:SI 3 "const_int_operand")]
+	  ATOMIC_LDOP))]
   "TARGET_LSE"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
   {
-    aarch64_gen_atomic_ldop (<CODE>, operands[0], NULL, operands[1],
-			     operands[2], operands[3]);
-    DONE;
+   enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
+   if (is_mm_relaxed (model))
+     return "ld<atomic_ldop><atomic_sfx>\t%<w>2, %<w>0, %1";
+   else if (is_mm_acquire (model) || is_mm_consume (model))
+     return "ld<atomic_ldop>a<atomic_sfx>\t%<w>2, %<w>0, %1";
+   else if (is_mm_release (model))
+     return "ld<atomic_ldop>l<atomic_sfx>\t%<w>2, %<w>0, %1";
+   else
+     return "ld<atomic_ldop>al<atomic_sfx>\t%<w>2, %<w>0, %1";
   }
 )
 
@@ -370,7 +424,7 @@
   }
 )
 
-;; Load-operate-store, returning the original memory data.
+;; Load-operate-store, returning the updated memory data.
 
 (define_expand "atomic_<atomic_optab>_fetch<mode>"
  [(match_operand:ALLI 0 "register_operand" "")
@@ -380,17 +434,23 @@
   (match_operand:SI 3 "const_int_operand")]
  ""
 {
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-  rtx value = operands[2];
-
-  /* Use an atomic load-operate instruction when possible.  */
-  if (aarch64_atomic_ldop_supported_p (<CODE>))
-    gen = gen_aarch64_atomic_<atomic_optab>_fetch<mode>_lse;
+  /* Use an atomic load-operate instruction when possible.  In this case
+     we will re-compute the result from the original mem value. */
+  if (TARGET_LSE)
+    {
+      rtx tmp = gen_reg_rtx (<MODE>mode);
+      operands[2] = force_reg (<MODE>mode, operands[2]);
+      emit_insn (gen_atomic_fetch_<atomic_optab><mode>
+                 (tmp, operands[1], operands[2], operands[3]));
+      tmp = expand_simple_binop (<MODE>mode, <CODE>, tmp, operands[2],
+				 operands[0], 1, OPTAB_WIDEN);
+      emit_move_insn (operands[0], tmp);
+    }
   else
-    gen = gen_aarch64_atomic_<atomic_optab>_fetch<mode>;
-
-  emit_insn (gen (operands[0], operands[1], value, operands[3]));
-
+    {
+      emit_insn (gen_aarch64_atomic_<atomic_optab>_fetch<mode>
+                 (operands[0], operands[1], operands[2], operands[3]));
+    }
   DONE;
 })
 
@@ -417,29 +477,6 @@
   }
 )
 
-(define_insn_and_split "aarch64_atomic_<atomic_optab>_fetch<mode>_lse"
-  [(set (match_operand:ALLI 0 "register_operand" "=&r")
-    (atomic_op:ALLI
-     (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")
-     (match_operand:ALLI 2 "<atomic_op_operand>" "r<const_atomic>")))
-   (set (match_dup 1)
-    (unspec_volatile:ALLI
-      [(match_dup 1)
-       (match_dup 2)
-       (match_operand:SI 3 "const_int_operand")]
-      UNSPECV_ATOMIC_LDOP))
-     (clobber (match_scratch:ALLI 4 "=&r"))]
-  "TARGET_LSE"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-  {
-    aarch64_gen_atomic_ldop (<CODE>, operands[4], operands[0], operands[1],
-			     operands[2], operands[3]);
-    DONE;
-  }
-)
-
 (define_insn_and_split "atomic_nand_fetch<mode>"
   [(set (match_operand:ALLI 0 "register_operand" "=&r")
     (not:ALLI
@@ -582,29 +619,3 @@
       return "dmb\\tish";
   }
 )
-
-;; ARMv8.1-A LSE instructions.
-
-;; Atomic load-op: Load data, operate, store result, keep data.
-
-(define_insn "aarch64_atomic_load<atomic_ldop><mode>"
- [(set (match_operand:ALLI 0 "register_operand" "=r")
-   (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
-  (set (match_dup 1)
-   (unspec_volatile:ALLI
-    [(match_dup 1)
-     (match_operand:ALLI 2 "register_operand")
-     (match_operand:SI 3 "const_int_operand")]
-    ATOMIC_LDOP))]
- "TARGET_LSE && reload_completed"
- {
-   enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
-   if (is_mm_relaxed (model))
-     return "ld<atomic_ldop><atomic_sfx>\t%<w>2, %<w>0, %1";
-   else if (is_mm_acquire (model) || is_mm_consume (model))
-     return "ld<atomic_ldop>a<atomic_sfx>\t%<w>2, %<w>0, %1";
-   else if (is_mm_release (model))
-     return "ld<atomic_ldop>l<atomic_sfx>\t%<w>2, %<w>0, %1";
-   else
-     return "ld<atomic_ldop>al<atomic_sfx>\t%<w>2, %<w>0, %1";
- })
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 21d66d36f82..8f999d5248d 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -479,7 +479,6 @@
     UNSPECV_ATOMIC_CAS		; Represent an atomic CAS.
     UNSPECV_ATOMIC_SWP		; Represent an atomic SWP.
     UNSPECV_ATOMIC_OP		; Represent an atomic operation.
-    UNSPECV_ATOMIC_LDOP		; Represent an atomic load-operation
     UNSPECV_ATOMIC_LDOP_OR	; Represent an atomic load-or
     UNSPECV_ATOMIC_LDOP_BIC	; Represent an atomic load-bic
     UNSPECV_ATOMIC_LDOP_XOR	; Represent an atomic load-xor
@@ -1504,6 +1503,10 @@
  [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
   (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
 
+(define_int_attr atomic_ldoptab
+ [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic")
+  (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
+
 ;; -------------------------------------------------------------------
 ;; Int Iterators Attributes.
 ;; -------------------------------------------------------------------

commit 5497bc389dca6a992aaa063df308959f23409c3f
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:11 2020 +0100

    aarch64: Remove early clobber from ATOMIC_LDOP scratch
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/atomics.md (aarch64_atomic_<ATOMIC_LDOP><ALLI>_lse):
            scratch register need not be early-clobber.  Document the reason
            why we cannot use ST<OP>.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cb5489a4587..791296d15da 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline.
+	2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/atomics.md (aarch64_atomic_<ATOMIC_LDOP><ALLI>_lse):
+	scratch register need not be early-clobber.  Document the reason
+	why we cannot use ST<OP>.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index 47a8a40c5b8..d740f4a100b 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -263,6 +263,18 @@
   }
 )
 
+;; It is tempting to want to use ST<OP> for relaxed and release
+;; memory models here.  However, that is incompatible with the
+;; C++ memory model for the following case:
+;;
+;;	atomic_fetch_add(ptr, 1, memory_order_relaxed);
+;;	atomic_thread_fence(memory_order_acquire);
+;;
+;; The problem is that the architecture says that ST<OP> (and LD<OP>
+;; insns where the destination is XZR) are not regarded as a read.
+;; However we also implement the acquire memory barrier with DMB LD,
+;; and so the ST<OP> is not blocked by the barrier.
+
 (define_insn "aarch64_atomic_<atomic_ldoptab><mode>_lse"
   [(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q")
 	(unspec_volatile:ALLI
@@ -270,7 +282,7 @@
 	   (match_operand:ALLI 1 "register_operand" "r")
 	   (match_operand:SI 2 "const_int_operand")]
       ATOMIC_LDOP))
-   (clobber (match_scratch:ALLI 3 "=&r"))]
+   (clobber (match_scratch:ALLI 3 "=r"))]
   "TARGET_LSE"
   {
    enum memmodel model = memmodel_from_int (INTVAL (operands[2]));

commit c7ae64412b6c9c7b966f3c0ab8eaa51c220ea39c
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:11 2020 +0100

    aarch64: Extend %R for integer registers
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/aarch64.c (aarch64_print_operand): Allow integer
            registers with %R.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 791296d15da..e32e00b6f6a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline.
+	2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/aarch64.c (aarch64_print_operand): Allow integer
+	registers with %R.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 1068cfd899a..317571e018c 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -6627,7 +6627,7 @@ sizetochar (int size)
      'S/T/U/V':		Print a FP/SIMD register name for a register list.
 			The register printed is the FP/SIMD register name
 			of X + 0/1/2/3 for S/T/U/V.
-     'R':		Print a scalar FP/SIMD register name + 1.
+     'R':		Print a scalar Integer/FP/SIMD register name + 1.
      'X':		Print bottom 16 bits of integer constant in hex.
      'w/x':		Print a general register name or the zero register
 			(32-bit or 64-bit).
@@ -6813,12 +6813,13 @@ aarch64_print_operand (FILE *f, rtx x, int code)
       break;
 
     case 'R':
-      if (!REG_P (x) || !FP_REGNUM_P (REGNO (x)))
-	{
-	  output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
-	  return;
-	}
-      asm_fprintf (f, "q%d", REGNO (x) - V0_REGNUM + 1);
+      if (REG_P (x) && FP_REGNUM_P (REGNO (x)))
+	asm_fprintf (f, "q%d", REGNO (x) - V0_REGNUM + 1);
+      else if (REG_P (x) && GP_REGNUM_P (REGNO (x)))
+	asm_fprintf (f, "x%d", REGNO (x) - R0_REGNUM + 1);
+      else
+	output_operand_lossage ("incompatible register operand for '%%%c'",
+				code);
       break;
 
     case 'X':

commit 1101198f3d099af0555d7202a2a00c96d39ee4e2
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:12 2020 +0100

    aarch64: Implement TImode compare-and-swap
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Add support
            for NE comparison of TImode values.
            (aarch64_emit_load_exclusive): Add support for TImode.
            (aarch64_emit_store_exclusive): Likewise.
            (aarch64_split_compare_and_swap): Disable strong_zero_p for TImode.
            * config/aarch64/atomics.md (atomic_compare_and_swapti):
            Change iterator from ALLI to ALLI_TI.
            (atomic_compare_and_swapti): New.
            (atomic_compare_and_swapti: New.
            (aarch64_load_exclusive_pair): New.
            (aarch64_store_exclusive_pair): New.
            * config/aarch64/iterators.md (ALLI_TI): New iterator.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e32e00b6f6a..9785585a48d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,21 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline.
+	2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/aarch64.c (aarch64_gen_compare_reg): Add support
+	for NE comparison of TImode values.
+	(aarch64_emit_load_exclusive): Add support for TImode.
+	(aarch64_emit_store_exclusive): Likewise.
+	(aarch64_split_compare_and_swap): Disable strong_zero_p for TImode.
+	* config/aarch64/atomics.md (atomic_compare_and_swapti):
+	Change iterator from ALLI to ALLI_TI.
+	(atomic_compare_and_swapti): New.
+	(atomic_compare_and_swapti: New.
+	(aarch64_load_exclusive_pair): New.
+	(aarch64_store_exclusive_pair): New.
+	* config/aarch64/iterators.md (ALLI_TI): New iterator.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 317571e018c..09e78313489 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1517,10 +1517,33 @@ emit_set_insn (rtx x, rtx y)
 rtx
 aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y)
 {
-  machine_mode mode = SELECT_CC_MODE (code, x, y);
-  rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
+  machine_mode cmp_mode = GET_MODE (x);
+  machine_mode cc_mode;
+  rtx cc_reg;
 
-  emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
+  if (cmp_mode == TImode)
+    {
+      gcc_assert (code == NE);
+
+      cc_mode = CCmode;
+      cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM);
+
+      rtx x_lo = operand_subword (x, 0, 0, TImode);
+      rtx y_lo = operand_subword (y, 0, 0, TImode);
+      emit_set_insn (cc_reg, gen_rtx_COMPARE (cc_mode, x_lo, y_lo));
+
+      rtx x_hi = operand_subword (x, 1, 0, TImode);
+      rtx y_hi = operand_subword (y, 1, 0, TImode);
+      emit_insn (gen_ccmpdi (cc_reg, cc_reg, x_hi, y_hi,
+			     gen_rtx_EQ (cc_mode, cc_reg, const0_rtx),
+			     GEN_INT (AARCH64_EQ)));
+    }
+  else
+    {
+      cc_mode = SELECT_CC_MODE (code, x, y);
+      cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM);
+      emit_set_insn (cc_reg, gen_rtx_COMPARE (cc_mode, x, y));
+    }
   return cc_reg;
 }
 
@@ -14145,40 +14168,54 @@ static void
 aarch64_emit_load_exclusive (machine_mode mode, rtx rval,
 			     rtx mem, rtx model_rtx)
 {
-  rtx (*gen) (rtx, rtx, rtx);
-
-  switch (mode)
+  if (mode == TImode)
+    emit_insn (gen_aarch64_load_exclusive_pair (gen_lowpart (DImode, rval),
+						gen_highpart (DImode, rval),
+						mem, model_rtx));
+  else
     {
-    case E_QImode: gen = gen_aarch64_load_exclusiveqi; break;
-    case E_HImode: gen = gen_aarch64_load_exclusivehi; break;
-    case E_SImode: gen = gen_aarch64_load_exclusivesi; break;
-    case E_DImode: gen = gen_aarch64_load_exclusivedi; break;
-    default:
-      gcc_unreachable ();
-    }
+      rtx (*gen) (rtx, rtx, rtx);
+
+      switch (mode)
+	{
+	case E_QImode: gen = gen_aarch64_load_exclusiveqi; break;
+	case E_HImode: gen = gen_aarch64_load_exclusivehi; break;
+	case E_SImode: gen = gen_aarch64_load_exclusivesi; break;
+	case E_DImode: gen = gen_aarch64_load_exclusivedi; break;
+	default:
+	  gcc_unreachable ();
+	}
 
-  emit_insn (gen (rval, mem, model_rtx));
+      emit_insn (gen (rval, mem, model_rtx));
+    }
 }
 
 /* Emit store exclusive.  */
 
 static void
 aarch64_emit_store_exclusive (machine_mode mode, rtx bval,
-			      rtx rval, rtx mem, rtx model_rtx)
+			      rtx mem, rtx rval, rtx model_rtx)
 {
-  rtx (*gen) (rtx, rtx, rtx, rtx);
-
-  switch (mode)
+  if (mode == TImode)
+    emit_insn (gen_aarch64_store_exclusive_pair
+	       (bval, mem, operand_subword (rval, 0, 0, TImode),
+		operand_subword (rval, 1, 0, TImode), model_rtx));
+  else
     {
-    case E_QImode: gen = gen_aarch64_store_exclusiveqi; break;
-    case E_HImode: gen = gen_aarch64_store_exclusivehi; break;
-    case E_SImode: gen = gen_aarch64_store_exclusivesi; break;
-    case E_DImode: gen = gen_aarch64_store_exclusivedi; break;
-    default:
-      gcc_unreachable ();
-    }
+      rtx (*gen) (rtx, rtx, rtx, rtx);
+
+      switch (mode)
+	{
+	case E_QImode: gen = gen_aarch64_store_exclusiveqi; break;
+	case E_HImode: gen = gen_aarch64_store_exclusivehi; break;
+	case E_SImode: gen = gen_aarch64_store_exclusivesi; break;
+	case E_DImode: gen = gen_aarch64_store_exclusivedi; break;
+	default:
+	  gcc_unreachable ();
+	}
 
-  emit_insn (gen (bval, rval, mem, model_rtx));
+      emit_insn (gen (bval, mem, rval, model_rtx));
+    }
 }
 
 /* Mark the previous jump instruction as unlikely.  */
@@ -14197,16 +14234,6 @@ aarch64_expand_compare_and_swap (rtx operands[])
 {
   rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x, cc_reg;
   machine_mode mode, r_mode;
-  typedef rtx (*gen_atomic_cas_fn) (rtx, rtx, rtx, rtx);
-  int idx;
-  gen_atomic_cas_fn atomic_gen;
-  const gen_atomic_cas_fn atomic_cas[] =
-  {
-    gen_aarch64_compare_and_swapqi_lse,
-    gen_aarch64_compare_and_swaphi_lse,
-    gen_aarch64_compare_and_swapsi_lse,
-    gen_aarch64_compare_and_swapdi_lse
-  };
 
   bval = operands[0];
   rval = operands[1];
@@ -14232,18 +14259,29 @@ aarch64_expand_compare_and_swap (rtx operands[])
       rval = gen_reg_rtx (r_mode);
     }
 
-  switch (mode)
-    {
-    case E_QImode: idx = 0; break;
-    case E_HImode: idx = 1; break;
-    case E_SImode: idx = 2; break;
-    case E_DImode: idx = 3; break;
-    default:
-      gcc_unreachable ();
-    }
   if (TARGET_LSE)
     {
-      atomic_gen = atomic_cas[idx];
+      insn_code code;
+      switch (mode)
+	{
+	case E_QImode:
+	 code = CODE_FOR_aarch64_compare_and_swapqi_lse;
+	 break;
+	case E_HImode:
+	 code = CODE_FOR_aarch64_compare_and_swaphi_lse;
+	 break;
+	case E_SImode:
+	 code = CODE_FOR_aarch64_compare_and_swapsi_lse;
+	 break;
+	case E_DImode:
+	 code = CODE_FOR_aarch64_compare_and_swapdi_lse;
+	 break;
+	case E_TImode:
+	 code = CODE_FOR_aarch64_compare_and_swapti_lse;
+	 break;
+	default:
+	  gcc_unreachable ();
+	}
       /* The CAS insn requires oldval and rval overlap, but we need to
 	 have a copy of oldval saved across the operation to tell if
 	 the operation is successful.  */
@@ -14252,7 +14290,7 @@ aarch64_expand_compare_and_swap (rtx operands[])
       else
 	emit_move_insn (rval, gen_lowpart (r_mode, oldval));
 
-      emit_insn (atomic_gen (rval, mem, newval, mod_s));
+      emit_insn (GEN_FCN (code) (rval, mem, newval, mod_s));
 
       cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
     }
@@ -14274,6 +14312,9 @@ aarch64_expand_compare_and_swap (rtx operands[])
 	  case E_DImode:
 	    code = CODE_FOR_aarch64_compare_and_swapdi;
 	    break;
+	  case E_TImode:
+	    code = CODE_FOR_aarch64_compare_and_swapti;
+	    break;
 	  default:
 	    gcc_unreachable ();
 	}
@@ -14345,7 +14386,7 @@ aarch64_split_compare_and_swap (rtx operands[])
 	CBNZ	scratch, .label1
     .label2:
 	CMP	rval, 0.  */
-  bool strong_zero_p = !is_weak && oldval == const0_rtx;
+  bool strong_zero_p = !is_weak && oldval == const0_rtx && mode != TImode;
 
   label1 = NULL;
   if (!is_weak)
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index d740f4a100b..d79c1896321 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -22,10 +22,10 @@
 
 (define_expand "atomic_compare_and_swap<mode>"
   [(match_operand:SI 0 "register_operand" "")			;; bool out
-   (match_operand:ALLI 1 "register_operand" "")			;; val out
-   (match_operand:ALLI 2 "aarch64_sync_memory_operand" "")	;; memory
-   (match_operand:ALLI 3 "nonmemory_operand" "")		;; expected
-   (match_operand:ALLI 4 "aarch64_reg_or_zero" "")		;; desired
+   (match_operand:ALLI_TI 1 "register_operand" "")		;; val out
+   (match_operand:ALLI_TI 2 "aarch64_sync_memory_operand" "")	;; memory
+   (match_operand:ALLI_TI 3 "nonmemory_operand" "")		;; expected
+   (match_operand:ALLI_TI 4 "aarch64_reg_or_zero" "")		;; desired
    (match_operand:SI 5 "const_int_operand")			;; is_weak
    (match_operand:SI 6 "const_int_operand")			;; mod_s
    (match_operand:SI 7 "const_int_operand")]			;; mod_f
@@ -88,6 +88,30 @@
   }
 )
 
+(define_insn_and_split "aarch64_compare_and_swapti"
+  [(set (reg:CC CC_REGNUM)					;; bool out
+    (unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
+   (set (match_operand:TI 0 "register_operand" "=&r")	;; val out
+    (match_operand:TI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
+   (set (match_dup 1)
+    (unspec_volatile:TI
+      [(match_operand:TI 2 "aarch64_reg_or_zero" "rZ")	;; expect
+       (match_operand:TI 3 "aarch64_reg_or_zero" "rZ")	;; desired
+       (match_operand:SI 4 "const_int_operand")			;; is_weak
+       (match_operand:SI 5 "const_int_operand")			;; mod_s
+       (match_operand:SI 6 "const_int_operand")]		;; mod_f
+      UNSPECV_ATOMIC_CMPSW))
+   (clobber (match_scratch:SI 7 "=&r"))]
+  ""
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  {
+    aarch64_split_compare_and_swap (operands);
+    DONE;
+  }
+)
+
 (define_insn "aarch64_compare_and_swap<mode>_lse"
   [(set (match_operand:SI 0 "register_operand" "+r")		;; val out
     (zero_extend:SI
@@ -133,6 +157,28 @@
     return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
 })
 
+(define_insn "aarch64_compare_and_swapti_lse"
+  [(set (match_operand:TI 0 "register_operand" "+r")	;; val out
+    (match_operand:TI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
+   (set (match_dup 1)
+    (unspec_volatile:TI
+      [(match_dup 0)						;; expect
+       (match_operand:TI 2 "register_operand" "r")		;; desired
+       (match_operand:SI 3 "const_int_operand")]		;; mod_s
+      UNSPECV_ATOMIC_CMPSW))]
+  "TARGET_LSE"
+{
+  enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
+  if (is_mm_relaxed (model))
+    return "casp\t%0, %R0, %2, %R2, %1";
+  else if (is_mm_acquire (model) || is_mm_consume (model))
+    return "caspa\t%0, %R0, %2, %R2, %1";
+  else if (is_mm_release (model))
+    return "caspl\t%0, %R0, %2, %R2, %1";
+  else
+    return "caspal\t%0, %R0, %2, %R2, %1";
+})
+
 (define_expand "atomic_exchange<mode>"
  [(match_operand:ALLI 0 "register_operand" "")
   (match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
@@ -578,6 +624,24 @@
   }
 )
 
+(define_insn "aarch64_load_exclusive_pair"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec_volatile:DI
+	  [(match_operand:TI 2 "aarch64_sync_memory_operand" "Q")
+	   (match_operand:SI 3 "const_int_operand")]
+	  UNSPECV_LX))
+   (set (match_operand:DI 1 "register_operand" "=r")
+	(unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LX))]
+  ""
+  {
+    enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
+    if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model))
+      return "ldxp\t%0, %1, %2";
+    else
+      return "ldaxp\t%0, %1, %2";
+  }
+)
+
 (define_insn "aarch64_store_exclusive<mode>"
   [(set (match_operand:SI 0 "register_operand" "=&r")
     (unspec_volatile:SI [(const_int 0)] UNSPECV_SX))
@@ -596,6 +660,25 @@
   }
 )
 
+(define_insn "aarch64_store_exclusive_pair"
+  [(set (match_operand:SI 0 "register_operand" "=&r")
+	(unspec_volatile:SI [(const_int 0)] UNSPECV_SX))
+   (set (match_operand:TI 1 "aarch64_sync_memory_operand" "=Q")
+	(unspec_volatile:TI
+	  [(match_operand:DI 2 "aarch64_reg_or_zero" "rZ")
+	   (match_operand:DI 3 "aarch64_reg_or_zero" "rZ")
+	   (match_operand:SI 4 "const_int_operand")]
+	  UNSPECV_SX))]
+  ""
+  {
+    enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
+    if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
+      return "stxp\t%w0, %x2, %x3, %1";
+    else
+      return "stlxp\t%w0, %x2, %x3, %1";
+  }
+)
+
 (define_expand "mem_thread_fence"
   [(match_operand:SI 0 "const_int_operand" "")]
   ""
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 8f999d5248d..914a30aa77c 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -35,6 +35,9 @@
 ;; Iterator for all integer modes (up to 64-bit)
 (define_mode_iterator ALLI [QI HI SI DI])
 
+;; Iterator for all integer modes (up to 128-bit)
+(define_mode_iterator ALLI_TI [QI HI SI DI TI])
+
 ;; Iterator for all integer modes that can be extended (up to 64-bit)
 (define_mode_iterator ALLX [QI HI SI])
 

commit 0b65e477890b7fe7f47a3dd85975ab7ee09b0609
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:15 2020 +0100

    Aarch64: Fix shrinkwrapping interactions with atomics (PR92692)
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline
            2020-01-17  Wilco Dijkstra  <wdijkstr@arm.com>
    
            PR target/92692
            * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
            Use epilogue_completed rather than reload_completed.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9785585a48d..3a578f6f8bd 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2020-01-17  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	PR target/92692
+	* config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
+	Use epilogue_completed rather than reload_completed.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index d79c1896321..4984a08680e 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -104,7 +104,7 @@
    (clobber (match_scratch:SI 7 "=&r"))]
   ""
   "#"
-  "&& reload_completed"
+  "&& epilogue_completed"
   [(const_int 0)]
   {
     aarch64_split_compare_and_swap (operands);

commit eccc28184d58dc27232d6710dc44eb2c91c01060
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:13 2020 +0100

    aarch64: Tidy aarch64_split_compare_and_swap
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/aarch64 (aarch64_split_compare_and_swap): Disable
            strong_zero_p for aarch64_track_speculation; unify some code paths;
            use aarch64_gen_compare_reg instead of open-coding.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3a578f6f8bd..52012bb730d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline.
+	2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/aarch64 (aarch64_split_compare_and_swap): Disable
+	strong_zero_p for aarch64_track_speculation; unify some code paths;
+	use aarch64_gen_compare_reg instead of open-coding.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
@@ -9,7 +18,7 @@
 
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
-	Backport from mainline.
+	Backport from mainline
 	2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
 
 	* config/aarch64/aarch64.c (aarch64_gen_compare_reg): Add support
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 09e78313489..2df5bf3db97 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -14359,13 +14359,11 @@ aarch64_split_compare_and_swap (rtx operands[])
   /* Split after prolog/epilog to avoid interactions with shrinkwrapping.  */
   gcc_assert (epilogue_completed);
 
-  rtx rval, mem, oldval, newval, scratch;
+  rtx rval, mem, oldval, newval, scratch, x, model_rtx;
   machine_mode mode;
   bool is_weak;
   rtx_code_label *label1, *label2;
-  rtx x, cond;
   enum memmodel model;
-  rtx model_rtx;
 
   rval = operands[0];
   mem = operands[1];
@@ -14386,7 +14384,7 @@ aarch64_split_compare_and_swap (rtx operands[])
 	CBNZ	scratch, .label1
     .label2:
 	CMP	rval, 0.  */
-  bool strong_zero_p = !is_weak && oldval == const0_rtx && mode != TImode;
+  bool strong_zero_p = (!is_weak && oldval == const0_rtx && mode != TImode);
 
   label1 = NULL;
   if (!is_weak)
@@ -14399,26 +14397,20 @@ aarch64_split_compare_and_swap (rtx operands[])
   /* The initial load can be relaxed for a __sync operation since a final
      barrier will be emitted to stop code hoisting.  */
   if (is_mm_sync (model))
-    aarch64_emit_load_exclusive (mode, rval, mem,
-				 GEN_INT (MEMMODEL_RELAXED));
+    aarch64_emit_load_exclusive (mode, rval, mem, GEN_INT (MEMMODEL_RELAXED));
   else
     aarch64_emit_load_exclusive (mode, rval, mem, model_rtx);
 
   if (strong_zero_p)
-    {
-      x = gen_rtx_NE (VOIDmode, rval, const0_rtx);
-      x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
-				gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
-      aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
-    }
+    x = gen_rtx_NE (VOIDmode, rval, const0_rtx);
   else
     {
-      cond = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
-      x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
-      x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
-				gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
-      aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
+      rtx cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
+      x = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
     }
+  x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
+			    gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
+  aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
 
   aarch64_emit_store_exclusive (mode, scratch, mem, newval, model_rtx);
 
@@ -14430,22 +14422,16 @@ aarch64_split_compare_and_swap (rtx operands[])
       aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
     }
   else
-    {
-      cond = gen_rtx_REG (CCmode, CC_REGNUM);
-      x = gen_rtx_COMPARE (CCmode, scratch, const0_rtx);
-      emit_insn (gen_rtx_SET (cond, x));
-    }
+    aarch64_gen_compare_reg (NE, scratch, const0_rtx);
 
   emit_label (label2);
+
   /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
      to set the condition flags.  If this is not used it will be removed by
      later passes.  */
   if (strong_zero_p)
-    {
-      cond = gen_rtx_REG (CCmode, CC_REGNUM);
-      x = gen_rtx_COMPARE (CCmode, rval, const0_rtx);
-      emit_insn (gen_rtx_SET (cond, x));
-    }
+    aarch64_gen_compare_reg (NE, rval, const0_rtx);
+
   /* Emit any final barrier needed for a __sync operation.  */
   if (is_mm_sync (model))
     aarch64_emit_post_barrier (model);

commit 06f8058a8368f79e2cbf4659db53b941895f271a
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:13 2020 +0100

    aarch64: Add out-of-line functions for LSE atomics
    
    This is the libgcc part of the interface -- providing the functions.
    Rationale is provided at the top of libgcc/config/aarch64/lse.S.
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline
            2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/lse-init.c: New file.
            * config/aarch64/lse.S: New file.
            * config/aarch64/t-lse: New file.
            * config.host: Add t-lse to all aarch64 tuples.

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 2a43d9c0c8e..32e609b1a86 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,13 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/lse-init.c: New file.
+	* config/aarch64/lse.S: New file.
+	* config/aarch64/t-lse: New file.
+	* config.host: Add t-lse to all aarch64 tuples.
+
 2020-04-19  Uroš Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/sfp-exceptions.c (__sfp_handle_exceptions) [__SSE_MATH__]:
diff --git a/libgcc/config.host b/libgcc/config.host
index b12c86267da..e436ade1a68 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -337,23 +337,27 @@ aarch64*-*-elf | aarch64*-*-rtems*)
 	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
 	extra_parts="$extra_parts crtfastmath.o"
 	tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+	tmake_file="${tmake_file} ${cpu_type}/t-lse t-slibgcc-libgcc"
 	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp t-crtfm"
 	md_unwind_header=aarch64/aarch64-unwind.h
 	;;
 aarch64*-*-freebsd*)
 	extra_parts="$extra_parts crtfastmath.o"
 	tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+	tmake_file="${tmake_file} ${cpu_type}/t-lse t-slibgcc-libgcc"
 	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp t-crtfm"
 	md_unwind_header=aarch64/freebsd-unwind.h
 	;;
 aarch64*-*-fuchsia*)
 	tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+	tmake_file="${tmake_file} ${cpu_type}/t-lse t-slibgcc-libgcc"
 	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
 	;;
 aarch64*-*-linux*)
 	extra_parts="$extra_parts crtfastmath.o"
 	md_unwind_header=aarch64/linux-unwind.h
 	tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+	tmake_file="${tmake_file} ${cpu_type}/t-lse t-slibgcc-libgcc"
 	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp t-crtfm"
 	;;
 alpha*-*-linux*)
diff --git a/libgcc/config/aarch64/lse-init.c b/libgcc/config/aarch64/lse-init.c
new file mode 100644
index 00000000000..33d29147479
--- /dev/null
+++ b/libgcc/config/aarch64/lse-init.c
@@ -0,0 +1,45 @@
+/* Out-of-line LSE atomics for AArch64 architecture, Init.
+   Copyright (C) 2019 Free Software Foundation, Inc.
+   Contributed by Linaro Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+/* Define the symbol gating the LSE implementations.  */
+_Bool __aarch64_have_lse_atomics
+  __attribute__((visibility("hidden"), nocommon));
+
+/* Disable initialization of __aarch64_have_lse_atomics during bootstrap.  */
+#ifndef inhibit_libc
+# include <sys/auxv.h>
+
+/* Disable initialization if the system headers are too old.  */
+# if defined(AT_HWCAP) && defined(HWCAP_ATOMICS)
+
+static void __attribute__((constructor))
+init_have_lse_atomics (void)
+{
+  unsigned long hwcap = getauxval (AT_HWCAP);
+  __aarch64_have_lse_atomics = (hwcap & HWCAP_ATOMICS) != 0;
+}
+
+# endif /* HWCAP */
+#endif /* inhibit_libc */
diff --git a/libgcc/config/aarch64/lse.S b/libgcc/config/aarch64/lse.S
new file mode 100644
index 00000000000..a5f6673596c
--- /dev/null
+++ b/libgcc/config/aarch64/lse.S
@@ -0,0 +1,235 @@
+/* Out-of-line LSE atomics for AArch64 architecture.
+   Copyright (C) 2019 Free Software Foundation, Inc.
+   Contributed by Linaro Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+/*
+ * The problem that we are trying to solve is operating system deployment
+ * of ARMv8.1-Atomics, also known as Large System Exensions (LSE).
+ *
+ * There are a number of potential solutions for this problem which have
+ * been proposed and rejected for various reasons.  To recap:
+ *
+ * (1) Multiple builds.  The dynamic linker will examine /lib64/atomics/
+ * if HWCAP_ATOMICS is set, allowing entire libraries to be overwritten.
+ * However, not all Linux distributions are happy with multiple builds,
+ * and anyway it has no effect on main applications.
+ *
+ * (2) IFUNC.  We could put these functions into libgcc_s.so, and have
+ * a single copy of each function for all DSOs.  However, ARM is concerned
+ * that the branch-to-indirect-branch that is implied by using a PLT,
+ * as required by IFUNC, is too much overhead for smaller cpus.
+ *
+ * (3) Statically predicted direct branches.  This is the approach that
+ * is taken here.  These functions are linked into every DSO that uses them.
+ * All of the symbols are hidden, so that the functions are called via a
+ * direct branch.  The choice of LSE vs non-LSE is done via one byte load
+ * followed by a well-predicted direct branch.  The functions are compiled
+ * separately to minimize code size.
+ */
+
+/* Tell the assembler to accept LSE instructions.  */
+	.arch armv8-a+lse
+
+/* Declare the symbol gating the LSE implementations.  */
+	.hidden	__aarch64_have_lse_atomics
+
+/* Turn size and memory model defines into mnemonic fragments.  */
+#if SIZE == 1
+# define S     b
+# define UXT   uxtb
+#elif SIZE == 2
+# define S     h
+# define UXT   uxth
+#elif SIZE == 4 || SIZE == 8 || SIZE == 16
+# define S
+# define UXT   mov
+#else
+# error
+#endif
+
+#if MODEL == 1
+# define SUFF  _relax
+# define A
+# define L
+#elif MODEL == 2
+# define SUFF  _acq
+# define A     a
+# define L
+#elif MODEL == 3
+# define SUFF  _rel
+# define A
+# define L     l
+#elif MODEL == 4
+# define SUFF  _acq_rel
+# define A     a
+# define L     l
+#else
+# error
+#endif
+
+/* Concatenate symbols.  */
+#define glue2_(A, B)		A ## B
+#define glue2(A, B)		glue2_(A, B)
+#define glue3_(A, B, C)		A ## B ## C
+#define glue3(A, B, C)		glue3_(A, B, C)
+#define glue4_(A, B, C, D)	A ## B ## C ## D
+#define glue4(A, B, C, D)	glue4_(A, B, C, D)
+
+/* Select the size of a register, given a regno.  */
+#define x(N)			glue2(x, N)
+#define w(N)			glue2(w, N)
+#if SIZE < 8
+# define s(N)			w(N)
+#else
+# define s(N)			x(N)
+#endif
+
+#define NAME(BASE)		glue4(__aarch64_, BASE, SIZE, SUFF)
+#define LDXR			glue4(ld, A, xr, S)
+#define STXR			glue4(st, L, xr, S)
+
+/* Temporary registers used.  Other than these, only the return value
+   register (x0) and the flags are modified.  */
+#define tmp0	16
+#define tmp1	17
+#define tmp2	15
+
+/* Start and end a function.  */
+.macro	STARTFN name
+	.text
+	.balign	16
+	.globl	\name
+	.hidden	\name
+	.type	\name, %function
+	.cfi_startproc
+\name:
+.endm
+
+.macro	ENDFN name
+	.cfi_endproc
+	.size	\name, . - \name
+.endm
+
+/* Branch to LABEL if LSE is disabled.  */
+.macro	JUMP_IF_NOT_LSE label
+	adrp	x(tmp0), __aarch64_have_lse_atomics
+	ldrb	w(tmp0), [x(tmp0), :lo12:__aarch64_have_lse_atomics]
+	cbz	w(tmp0), \label
+.endm
+
+#ifdef L_cas
+
+STARTFN	NAME(cas)
+	JUMP_IF_NOT_LSE	8f
+
+#if SIZE < 16
+#define CAS	glue4(cas, A, L, S)
+
+	CAS		s(0), s(1), [x2]
+	ret
+
+8:	UXT		s(tmp0), s(0)
+0:	LDXR		s(0), [x2]
+	cmp		s(0), s(tmp0)
+	bne		1f
+	STXR		w(tmp1), s(1), [x2]
+	cbnz		w(tmp1), 0b
+1:	ret
+
+#else
+#define LDXP	glue3(ld, A, xp)
+#define STXP	glue3(st, L, xp)
+#define CASP	glue3(casp, A, L)
+
+	CASP		x0, x1, x2, x3, [x4]
+	ret
+
+8:	mov		x(tmp0), x0
+	mov		x(tmp1), x1
+0:	LDXP		x0, x1, [x4]
+	cmp		x0, x(tmp0)
+	ccmp		x1, x(tmp1), #0, eq
+	bne		1f
+	STXP		w(tmp2), x(tmp0), x(tmp1), [x4]
+	cbnz		w(tmp2), 0b
+1:	ret
+
+#endif
+
+ENDFN	NAME(cas)
+#endif
+
+#ifdef L_swp
+#define SWP	glue4(swp, A, L, S)
+
+STARTFN	NAME(swp)
+	JUMP_IF_NOT_LSE	8f
+
+	SWP		s(0), s(0), [x1]
+	ret
+
+8:	mov		s(tmp0), s(0)
+0:	LDXR		s(0), [x1]
+	STXR		w(tmp1), s(tmp0), [x1]
+	cbnz		w(tmp1), 0b
+	ret
+
+ENDFN	NAME(swp)
+#endif
+
+#if defined(L_ldadd) || defined(L_ldclr) \
+    || defined(L_ldeor) || defined(L_ldset)
+
+#ifdef L_ldadd
+#define LDNM	ldadd
+#define OP	add
+#elif defined(L_ldclr)
+#define LDNM	ldclr
+#define OP	bic
+#elif defined(L_ldeor)
+#define LDNM	ldeor
+#define OP	eor
+#elif defined(L_ldset)
+#define LDNM	ldset
+#define OP	orr
+#else
+#error
+#endif
+#define LDOP	glue4(LDNM, A, L, S)
+
+STARTFN	NAME(LDNM)
+	JUMP_IF_NOT_LSE	8f
+
+	LDOP		s(0), s(0), [x1]
+	ret
+
+8:	mov		s(tmp0), s(0)
+0:	LDXR		s(0), [x1]
+	OP		s(tmp1), s(0), s(tmp0)
+	STXR		w(tmp1), s(tmp1), [x1]
+	cbnz		w(tmp1), 0b
+	ret
+
+ENDFN	NAME(LDNM)
+#endif
diff --git a/libgcc/config/aarch64/t-lse b/libgcc/config/aarch64/t-lse
new file mode 100644
index 00000000000..fe3868dacbf
--- /dev/null
+++ b/libgcc/config/aarch64/t-lse
@@ -0,0 +1,44 @@
+# Out-of-line LSE atomics for AArch64 architecture.
+# Copyright (C) 2019 Free Software Foundation, Inc.
+# Contributed by Linaro Ltd.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# Compare-and-swap has 5 sizes and 4 memory models.
+S0 := $(foreach s, 1 2 4 8 16, $(addsuffix _$(s), cas))
+O0 := $(foreach m, 1 2 3 4, $(addsuffix _$(m)$(objext), $(S0)))
+
+# Swap, Load-and-operate have 4 sizes and 4 memory models
+S1 := $(foreach s, 1 2 4 8, $(addsuffix _$(s), swp ldadd ldclr ldeor ldset))
+O1 := $(foreach m, 1 2 3 4, $(addsuffix _$(m)$(objext), $(S1)))
+
+LSE_OBJS := $(O0) $(O1)
+
+libgcc-objects += $(LSE_OBJS) lse-init$(objext)
+
+empty      =
+space      = $(empty) $(empty)
+PAT_SPLIT  = $(subst _,$(space),$(*F))
+PAT_BASE   = $(word 1,$(PAT_SPLIT))
+PAT_N      = $(word 2,$(PAT_SPLIT))
+PAT_M      = $(word 3,$(PAT_SPLIT))
+
+lse-init$(objext): $(srcdir)/config/aarch64/lse-init.c
+	$(gcc_compile) -c $<
+
+$(LSE_OBJS): $(srcdir)/config/aarch64/lse.S
+	$(gcc_compile) -DL_$(PAT_BASE) -DSIZE=$(PAT_N) -DMODEL=$(PAT_M) -c $<

commit 36579491fa01039694ad12e673ffe523c69dd156
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:14 2020 +0100

    Add visibility to libfunc constructors
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
    
            * optabs-libfuncs.c (build_libfunc_function_visibility):
            New, split out from...
            (build_libfunc_function): ... here.
            (init_one_libfunc_visibility): New, split out from ...
            (init_one_libfunc): ... here.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 52012bb730d..96d2234c9af 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,6 +1,17 @@
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
+	2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
+
+	* optabs-libfuncs.c (build_libfunc_function_visibility):
+	New, split out from...
+	(build_libfunc_function): ... here.
+	(init_one_libfunc_visibility): New, split out from ...
+	(init_one_libfunc): ... here.
+
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
 	2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
 
 	* config/aarch64/aarch64 (aarch64_split_compare_and_swap): Disable
diff --git a/gcc/optabs-libfuncs.c b/gcc/optabs-libfuncs.c
index bd0df8baa37..73a28e9ca7a 100644
--- a/gcc/optabs-libfuncs.c
+++ b/gcc/optabs-libfuncs.c
@@ -719,10 +719,10 @@ struct libfunc_decl_hasher : ggc_ptr_hash<tree_node>
 /* A table of previously-created libfuncs, hashed by name.  */
 static GTY (()) hash_table<libfunc_decl_hasher> *libfunc_decls;
 
-/* Build a decl for a libfunc named NAME.  */
+/* Build a decl for a libfunc named NAME with visibility VIS.  */
 
 tree
-build_libfunc_function (const char *name)
+build_libfunc_function_visibility (const char *name, symbol_visibility vis)
 {
   /* ??? We don't have any type information; pretend this is "int foo ()".  */
   tree decl = build_decl (UNKNOWN_LOCATION, FUNCTION_DECL,
@@ -731,7 +731,7 @@ build_libfunc_function (const char *name)
   DECL_EXTERNAL (decl) = 1;
   TREE_PUBLIC (decl) = 1;
   DECL_ARTIFICIAL (decl) = 1;
-  DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
+  DECL_VISIBILITY (decl) = vis;
   DECL_VISIBILITY_SPECIFIED (decl) = 1;
   gcc_assert (DECL_ASSEMBLER_NAME (decl));
 
@@ -742,11 +742,19 @@ build_libfunc_function (const char *name)
   return decl;
 }
 
+/* Build a decl for a libfunc named NAME.  */
+
+tree
+build_libfunc_function (const char *name)
+{
+  return build_libfunc_function_visibility (name, VISIBILITY_DEFAULT);
+}
+
 /* Return a libfunc for NAME, creating one if we don't already have one.
-   The returned rtx is a SYMBOL_REF.  */
+   The decl is given visibility VIS.  The returned rtx is a SYMBOL_REF.  */
 
 rtx
-init_one_libfunc (const char *name)
+init_one_libfunc_visibility (const char *name, symbol_visibility vis)
 {
   tree id, decl;
   hashval_t hash;
@@ -763,12 +771,18 @@ init_one_libfunc (const char *name)
     {
       /* Create a new decl, so that it can be passed to
 	 targetm.encode_section_info.  */
-      decl = build_libfunc_function (name);
+      decl = build_libfunc_function_visibility (name, vis);
       *slot = decl;
     }
   return XEXP (DECL_RTL (decl), 0);
 }
 
+rtx
+init_one_libfunc (const char *name)
+{
+  return init_one_libfunc_visibility (name, VISIBILITY_DEFAULT);
+}
+
 /* Adjust the assembler name of libfunc NAME to ASMSPEC.  */
 
 rtx
diff --git a/gcc/optabs-libfuncs.h b/gcc/optabs-libfuncs.h
index 0669ea1fdd7..cf39da36887 100644
--- a/gcc/optabs-libfuncs.h
+++ b/gcc/optabs-libfuncs.h
@@ -63,7 +63,9 @@ void gen_satfract_conv_libfunc (convert_optab, const char *,
 void gen_satfractuns_conv_libfunc (convert_optab, const char *,
 				   machine_mode, machine_mode);
 
+tree build_libfunc_function_visibility (const char *, symbol_visibility);
 tree build_libfunc_function (const char *);
+rtx init_one_libfunc_visibility (const char *, symbol_visibility);
 rtx init_one_libfunc (const char *);
 rtx set_user_assembler_libfunc (const char *, const char *);
 

commit ff54767725cd86e1d937cde50ec499a318b25997
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:15 2020 +0100

    aarch64: Implement -moutline-atomics
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline
            2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/aarch64.opt (-moutline-atomics): New.
            * config/aarch64/aarch64.c (aarch64_atomic_ool_func): New.
            (aarch64_ool_cas_names, aarch64_ool_swp_names): New.
            (aarch64_ool_ldadd_names, aarch64_ool_ldset_names): New.
            (aarch64_ool_ldclr_names, aarch64_ool_ldeor_names): New.
            (aarch64_expand_compare_and_swap): Honor TARGET_OUTLINE_ATOMICS.
            * config/aarch64/atomics.md (atomic_exchange<ALLI>): Likewise.
            (atomic_<atomic_op><ALLI>): Likewise.
            (atomic_fetch_<atomic_op><ALLI>): Likewise.
            (atomic_<atomic_op>_fetch<ALLI>): Likewise.
            * doc/invoke.texi: Document -moutline-atomics.
    
            * gcc.target/aarch64/atomic-op-acq_rel.c: Use -mno-outline-atomics.
            * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Likewise.
            * gcc.target/aarch64/atomic-op-acquire.c: Likewise.
            * gcc.target/aarch64/atomic-op-char.c: Likewise.
            * gcc.target/aarch64/atomic-op-consume.c: Likewise.
            * gcc.target/aarch64/atomic-op-imm.c: Likewise.
            * gcc.target/aarch64/atomic-op-int.c: Likewise.
            * gcc.target/aarch64/atomic-op-long.c: Likewise.
            * gcc.target/aarch64/atomic-op-relaxed.c: Likewise.
            * gcc.target/aarch64/atomic-op-release.c: Likewise.
            * gcc.target/aarch64/atomic-op-seq_cst.c: Likewise.
            * gcc.target/aarch64/atomic-op-short.c: Likewise.
            * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: Likewise.
            * gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c: Likewise.
            * gcc.target/aarch64/sync-comp-swap.c: Likewise.
            * gcc.target/aarch64/sync-op-acquire.c: Likewise.
            * gcc.target/aarch64/sync-op-full.c: Likewise.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 96d2234c9af..a3fc5c2c6c3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/aarch64.opt (-moutline-atomics): New.
+	* config/aarch64/aarch64.c (aarch64_atomic_ool_func): New.
+	(aarch64_ool_cas_names, aarch64_ool_swp_names): New.
+	(aarch64_ool_ldadd_names, aarch64_ool_ldset_names): New.
+	(aarch64_ool_ldclr_names, aarch64_ool_ldeor_names): New.
+	(aarch64_expand_compare_and_swap): Honor TARGET_OUTLINE_ATOMICS.
+	* config/aarch64/atomics.md (atomic_exchange<ALLI>): Likewise.
+	(atomic_<atomic_op><ALLI>): Likewise.
+	(atomic_fetch_<atomic_op><ALLI>): Likewise.
+	(atomic_<atomic_op>_fetch<ALLI>): Likewise.
+	* doc/invoke.texi: Document -moutline-atomics.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index da68ce0e7d0..0f1dc75a27f 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -548,4 +548,17 @@ rtl_opt_pass *make_pass_fma_steering (gcc::context *ctxt);
 
 poly_uint64 aarch64_regmode_natural_size (machine_mode);
 
+struct atomic_ool_names
+{
+    const char *str[5][4];
+};
+
+rtx aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx,
+			    const atomic_ool_names *names);
+extern const atomic_ool_names aarch64_ool_swp_names;
+extern const atomic_ool_names aarch64_ool_ldadd_names;
+extern const atomic_ool_names aarch64_ool_ldset_names;
+extern const atomic_ool_names aarch64_ool_ldclr_names;
+extern const atomic_ool_names aarch64_ool_ldeor_names;
+
 #endif /* GCC_AARCH64_PROTOS_H */
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 2df5bf3db97..ffbf1e38c5f 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -14227,6 +14227,82 @@ aarch64_emit_unlikely_jump (rtx insn)
   add_reg_br_prob_note (jump, profile_probability::very_unlikely ());
 }
 
+/* We store the names of the various atomic helpers in a 5x4 array.
+   Return the libcall function given MODE, MODEL and NAMES.  */
+
+rtx
+aarch64_atomic_ool_func (machine_mode mode, rtx model_rtx,
+			 const atomic_ool_names *names)
+{
+  memmodel model = memmodel_base (INTVAL (model_rtx));
+  int mode_idx, model_idx;
+
+  switch (mode)
+    {
+    case E_QImode:
+      mode_idx = 0;
+      break;
+    case E_HImode:
+      mode_idx = 1;
+      break;
+    case E_SImode:
+      mode_idx = 2;
+      break;
+    case E_DImode:
+      mode_idx = 3;
+      break;
+    case E_TImode:
+      mode_idx = 4;
+      break;
+    default:
+      gcc_unreachable ();
+    }
+
+  switch (model)
+    {
+    case MEMMODEL_RELAXED:
+      model_idx = 0;
+      break;
+    case MEMMODEL_CONSUME:
+    case MEMMODEL_ACQUIRE:
+      model_idx = 1;
+      break;
+    case MEMMODEL_RELEASE:
+      model_idx = 2;
+      break;
+    case MEMMODEL_ACQ_REL:
+    case MEMMODEL_SEQ_CST:
+      model_idx = 3;
+      break;
+    default:
+      gcc_unreachable ();
+    }
+
+  return init_one_libfunc_visibility (names->str[mode_idx][model_idx],
+				      VISIBILITY_HIDDEN);
+}
+
+#define DEF0(B, N) \
+  { "__aarch64_" #B #N "_relax", \
+    "__aarch64_" #B #N "_acq", \
+    "__aarch64_" #B #N "_rel", \
+    "__aarch64_" #B #N "_acq_rel" }
+
+#define DEF4(B)  DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), \
+		 { NULL, NULL, NULL, NULL }
+#define DEF5(B)  DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), DEF0(B, 16)
+
+static const atomic_ool_names aarch64_ool_cas_names = { { DEF5(cas) } };
+const atomic_ool_names aarch64_ool_swp_names = { { DEF4(swp) } };
+const atomic_ool_names aarch64_ool_ldadd_names = { { DEF4(ldadd) } };
+const atomic_ool_names aarch64_ool_ldset_names = { { DEF4(ldset) } };
+const atomic_ool_names aarch64_ool_ldclr_names = { { DEF4(ldclr) } };
+const atomic_ool_names aarch64_ool_ldeor_names = { { DEF4(ldeor) } };
+
+#undef DEF0
+#undef DEF4
+#undef DEF5
+
 /* Expand a compare and swap pattern.  */
 
 void
@@ -14294,6 +14370,17 @@ aarch64_expand_compare_and_swap (rtx operands[])
 
       cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
     }
+  else if (TARGET_OUTLINE_ATOMICS)
+    {
+      /* Oldval must satisfy compare afterward.  */
+      if (!aarch64_plus_operand (oldval, mode))
+	oldval = force_reg (mode, oldval);
+      rtx func = aarch64_atomic_ool_func (mode, mod_s, &aarch64_ool_cas_names);
+      rval = emit_library_call_value (func, NULL_RTX, LCT_NORMAL, r_mode,
+				      oldval, mode, newval, mode,
+				      XEXP (mem, 0), Pmode);
+      cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
+    }
   else
     {
       /* The oldval predicate varies by mode.  Test it and force to reg.  */
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
index 52eaf8c6f40..b4970b73607 100644
--- a/gcc/config/aarch64/aarch64.opt
+++ b/gcc/config/aarch64/aarch64.opt
@@ -214,3 +214,7 @@ Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits)
 mverbose-cost-dump
 Common Undocumented Var(flag_aarch64_verbose_cost)
 Enables verbose cost model dumping in the debug dump files.
+
+moutline-atomics
+Target Report Mask(OUTLINE_ATOMICS) Save
+Generate local calls to out-of-line atomic operations.
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index 4984a08680e..0ee8d2efac0 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -186,16 +186,27 @@
   (match_operand:SI 3 "const_int_operand" "")]
   ""
   {
-    rtx (*gen) (rtx, rtx, rtx, rtx);
-
     /* Use an atomic SWP when available.  */
     if (TARGET_LSE)
-      gen = gen_aarch64_atomic_exchange<mode>_lse;
+      {
+	emit_insn (gen_aarch64_atomic_exchange<mode>_lse
+		   (operands[0], operands[1], operands[2], operands[3]));
+      }
+    else if (TARGET_OUTLINE_ATOMICS)
+      {
+	machine_mode mode = <MODE>mode;
+	rtx func = aarch64_atomic_ool_func (mode, operands[3],
+					    &aarch64_ool_swp_names);
+	rtx rval = emit_library_call_value (func, operands[0], LCT_NORMAL,
+					    mode, operands[2], mode,
+					    XEXP (operands[1], 0), Pmode);
+        emit_move_insn (operands[0], rval);
+      }
     else
-      gen = gen_aarch64_atomic_exchange<mode>;
-
-    emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
-
+      {
+	emit_insn (gen_aarch64_atomic_exchange<mode>
+		   (operands[0], operands[1], operands[2], operands[3]));
+      }
     DONE;
   }
 )
@@ -280,6 +291,39 @@
 	  }
 	operands[1] = force_reg (<MODE>mode, operands[1]);
       }
+    else if (TARGET_OUTLINE_ATOMICS)
+      {
+        const atomic_ool_names *names;
+	switch (<CODE>)
+	  {
+	  case MINUS:
+	    operands[1] = expand_simple_unop (<MODE>mode, NEG, operands[1],
+					      NULL, 1);
+	    /* fallthru */
+	  case PLUS:
+	    names = &aarch64_ool_ldadd_names;
+	    break;
+	  case IOR:
+	    names = &aarch64_ool_ldset_names;
+	    break;
+	  case XOR:
+	    names = &aarch64_ool_ldeor_names;
+	    break;
+	  case AND:
+	    operands[1] = expand_simple_unop (<MODE>mode, NOT, operands[1],
+					      NULL, 1);
+	    names = &aarch64_ool_ldclr_names;
+	    break;
+	  default:
+	    gcc_unreachable ();
+	  }
+        machine_mode mode = <MODE>mode;
+	rtx func = aarch64_atomic_ool_func (mode, operands[2], names);
+	emit_library_call_value (func, NULL_RTX, LCT_NORMAL, mode,
+				 operands[1], mode,
+				 XEXP (operands[0], 0), Pmode);
+        DONE;
+      }
     else
       gen = gen_aarch64_atomic_<atomic_optab><mode>;
 
@@ -405,6 +449,40 @@
 	}
       operands[2] = force_reg (<MODE>mode, operands[2]);
     }
+  else if (TARGET_OUTLINE_ATOMICS)
+    {
+      const atomic_ool_names *names;
+      switch (<CODE>)
+	{
+	case MINUS:
+	  operands[2] = expand_simple_unop (<MODE>mode, NEG, operands[2],
+					    NULL, 1);
+	  /* fallthru */
+	case PLUS:
+	  names = &aarch64_ool_ldadd_names;
+	  break;
+	case IOR:
+	  names = &aarch64_ool_ldset_names;
+	  break;
+	case XOR:
+	  names = &aarch64_ool_ldeor_names;
+	  break;
+	case AND:
+	  operands[2] = expand_simple_unop (<MODE>mode, NOT, operands[2],
+					    NULL, 1);
+	  names = &aarch64_ool_ldclr_names;
+	  break;
+	default:
+	  gcc_unreachable ();
+	}
+      machine_mode mode = <MODE>mode;
+      rtx func = aarch64_atomic_ool_func (mode, operands[3], names);
+      rtx rval = emit_library_call_value (func, operands[0], LCT_NORMAL, mode,
+					  operands[2], mode,
+					  XEXP (operands[1], 0), Pmode);
+      emit_move_insn (operands[0], rval);
+      DONE;
+    }
   else
     gen = gen_aarch64_atomic_fetch_<atomic_optab><mode>;
 
@@ -494,7 +572,7 @@
 {
   /* Use an atomic load-operate instruction when possible.  In this case
      we will re-compute the result from the original mem value. */
-  if (TARGET_LSE)
+  if (TARGET_LSE || TARGET_OUTLINE_ATOMICS)
     {
       rtx tmp = gen_reg_rtx (<MODE>mode);
       operands[2] = force_reg (<MODE>mode, operands[2]);
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c138a0e84ce..bdad016baeb 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -604,7 +604,8 @@ Objective-C and Objective-C++ Dialects}.
 -mpc-relative-literal-loads @gol
 -msign-return-address=@var{scope} @gol
 -march=@var{name}  -mcpu=@var{name}  -mtune=@var{name}  @gol
--moverride=@var{string}  -mverbose-cost-dump}
+-moverride=@var{string}  -mverbose-cost-dump @gol
+-moutline-atomics }
 
 @emph{Adapteva Epiphany Options}
 @gccoptlist{-mhalf-reg-file  -mprefer-short-insn-regs @gol
@@ -14712,6 +14713,19 @@ This option only has an effect if @option{-ffast-math} or
 precision of division results to about 16 bits for
 single precision and to 32 bits for double precision.
 
+@item -moutline-atomics
+@itemx -mno-outline-atomics
+Enable or disable calls to out-of-line helpers to implement atomic operations.
+These helpers will, at runtime, determine if the LSE instructions from
+ARMv8.1-A can be used; if not, they will use the load/store-exclusive
+instructions that are present in the base ARMv8.0 ISA.
+
+This option is only applicable when compiling for the base ARMv8.0
+instruction set.  If using a later revision, e.g. @option{-march=armv8.1-a}
+or @option{-march=armv8-a+lse}, the ARMv8.1-Atomics instructions will be
+used directly.  The same applies when using @option{-mcpu=} when the
+selected cpu supports the @samp{lse} feature.
+
 @item -march=@var{name}
 @opindex march
 Specify the name of the target architecture and, optionally, one or
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 58bbd2ed205..a3cf505b624 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,26 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
+
+	* gcc.target/aarch64/atomic-op-acq_rel.c: Use -mno-outline-atomics.
+	* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Likewise.
+	* gcc.target/aarch64/atomic-op-acquire.c: Likewise.
+	* gcc.target/aarch64/atomic-op-char.c: Likewise.
+	* gcc.target/aarch64/atomic-op-consume.c: Likewise.
+	* gcc.target/aarch64/atomic-op-imm.c: Likewise.
+	* gcc.target/aarch64/atomic-op-int.c: Likewise.
+	* gcc.target/aarch64/atomic-op-long.c: Likewise.
+	* gcc.target/aarch64/atomic-op-relaxed.c: Likewise.
+	* gcc.target/aarch64/atomic-op-release.c: Likewise.
+	* gcc.target/aarch64/atomic-op-seq_cst.c: Likewise.
+	* gcc.target/aarch64/atomic-op-short.c: Likewise.
+	* gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: Likewise.
+	* gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c: Likewise.
+	* gcc.target/aarch64/sync-comp-swap.c: Likewise.
+	* gcc.target/aarch64/sync-op-acquire.c: Likewise.
+	* gcc.target/aarch64/sync-op-full.c: Likewise.
+
 2020-04-21  Martin Jambor  <mjambor@suse.cz>
 
 	Backport from master
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
index 49ca5d0d09c..a828a72aa75 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf -mno-outline-atomics" } */
 
 #include "atomic-comp-swap-release-acquire.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
index 74f26348e42..6823ce381b2 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "atomic-op-acq_rel.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
index 66c1b1efe20..87937de378a 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "atomic-op-acquire.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
index c09d0434ecf..60955e57da3 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "atomic-op-char.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
index 5783ab84f5c..16cb11aeeaf 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "atomic-op-consume.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c
index 18b8f0b04e9..bcab4e481e3 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 int v = 0;
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
index 8520f0839ba..040e4a8d168 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "atomic-op-int.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
index d011f8c5ce2..fc88b92cd3e 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 long v = 0;
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
index ed96bfdb978..503d62b0280 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "atomic-op-relaxed.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
index fc4be17de89..efe14aea7e4 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "atomic-op-release.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
index 613000fe490..09973bf82ba 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "atomic-op-seq_cst.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
index e82c8118ece..e1dcebb0f89 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "atomic-op-short.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c
index f2a21ddf2e1..29246979bfb 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=armv8-a+nolse" } */
+/* { dg-options "-O2 -march=armv8-a+nolse -mno-outline-atomics" } */
 /* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */
 
 int
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c
index 8d2ae67dfbe..6daf9b08f5a 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=armv8-a+nolse" } */
+/* { dg-options "-O2 -march=armv8-a+nolse -mno-outline-atomics" } */
 /* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */
 
 int
diff --git a/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c b/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c
index e571b2f13b3..f56415f3354 100644
--- a/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c
+++ b/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf -mno-outline-atomics" } */
 
 #include "sync-comp-swap.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c b/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c
index 357bf1be3b2..39b3144aa36 100644
--- a/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c
+++ b/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "sync-op-acquire.x"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sync-op-full.c b/gcc/testsuite/gcc.target/aarch64/sync-op-full.c
index c6ba1629965..6b8b2043f40 100644
--- a/gcc/testsuite/gcc.target/aarch64/sync-op-full.c
+++ b/gcc/testsuite/gcc.target/aarch64/sync-op-full.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
 
 #include "sync-op-full.x"
 

commit 4eaef24ba1f83ccfb54c9e473eb203cce3a9f12f
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:16 2020 +0100

    aarch64: Fix store-exclusive in load-operate LSE helpers
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline
            2019-09-25  Richard Henderson  <richard.henderson@linaro.org>
    
            PR target/91834
            * config/aarch64/lse.S (LDNM): Ensure STXR output does not
            overlap the inputs.

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 32e609b1a86..55da8a70c0a 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2019-09-25  Richard Henderson  <richard.henderson@linaro.org>
+
+	PR target/91834
+	* config/aarch64/lse.S (LDNM): Ensure STXR output does not
+	overlap the inputs.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/libgcc/config/aarch64/lse.S b/libgcc/config/aarch64/lse.S
index a5f6673596c..c7979382ad7 100644
--- a/libgcc/config/aarch64/lse.S
+++ b/libgcc/config/aarch64/lse.S
@@ -227,8 +227,8 @@ STARTFN	NAME(LDNM)
 8:	mov		s(tmp0), s(0)
 0:	LDXR		s(0), [x1]
 	OP		s(tmp1), s(0), s(tmp0)
-	STXR		w(tmp1), s(tmp1), [x1]
-	cbnz		w(tmp1), 0b
+	STXR		w(tmp2), s(tmp1), [x1]
+	cbnz		w(tmp2), 0b
 	ret
 
 ENDFN	NAME(LDNM)

commit 5d44ad1e0a66651495ed964058cdd6db0d99d876
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:17 2020 +0100

    aarch64: Configure for sys/auxv.h in libgcc for lse-init.c
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline
            2019-09-25  Richard Henderson  <richard.henderson@linaro.org>
    
            PR target/91833
            * config/aarch64/lse-init.c: Include auto-target.h.  Disable
            initialization if !HAVE_SYS_AUXV_H.
            * configure.ac (AC_CHECK_HEADERS): Add sys/auxv.h.
            * config.in, configure: Rebuild.

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 55da8a70c0a..e641d747332 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2019-09-25  Richard Henderson  <richard.henderson@linaro.org>
+
+	PR target/91833
+	* config/aarch64/lse-init.c: Include auto-target.h.  Disable
+	initialization if !HAVE_SYS_AUXV_H.
+	* configure.ac (AC_CHECK_HEADERS): Add sys/auxv.h.
+	* config.in, configure: Rebuild.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/libgcc/config.in b/libgcc/config.in
index d634af9d949..59a3d8daf52 100644
--- a/libgcc/config.in
+++ b/libgcc/config.in
@@ -43,6 +43,9 @@
 /* Define to 1 if you have the <string.h> header file. */
 #undef HAVE_STRING_H
 
+/* Define to 1 if you have the <sys/auxv.h> header file. */
+#undef HAVE_SYS_AUXV_H
+
 /* Define to 1 if you have the <sys/stat.h> header file. */
 #undef HAVE_SYS_STAT_H
 
@@ -82,6 +85,11 @@
 /* Define to 1 if the target use emutls for thread-local storage. */
 #undef USE_EMUTLS
 
+/* Enable large inode numbers on Mac OS X 10.5.  */
+#ifndef _DARWIN_USE_64_BIT_INODE
+# define _DARWIN_USE_64_BIT_INODE 1
+#endif
+
 /* Number of bits in a file offset, on hosts where this is settable. */
 #undef _FILE_OFFSET_BITS
 
diff --git a/libgcc/config/aarch64/lse-init.c b/libgcc/config/aarch64/lse-init.c
index 33d29147479..1a8f4c55213 100644
--- a/libgcc/config/aarch64/lse-init.c
+++ b/libgcc/config/aarch64/lse-init.c
@@ -23,12 +23,14 @@ a copy of the GCC Runtime Library Exception along with this program;
 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 <http://www.gnu.org/licenses/>.  */
 
+#include "auto-target.h"
+
 /* Define the symbol gating the LSE implementations.  */
 _Bool __aarch64_have_lse_atomics
   __attribute__((visibility("hidden"), nocommon));
 
 /* Disable initialization of __aarch64_have_lse_atomics during bootstrap.  */
-#ifndef inhibit_libc
+#if !defined(inhibit_libc) && defined(HAVE_SYS_AUXV_H)
 # include <sys/auxv.h>
 
 /* Disable initialization if the system headers are too old.  */
diff --git a/libgcc/configure b/libgcc/configure
old mode 100644
new mode 100755
index b2f3f870844..7962cd9b87e
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -641,6 +641,7 @@ infodir
 docdir
 oldincludedir
 includedir
+runstatedir
 localstatedir
 sharedstatedir
 sysconfdir
@@ -729,6 +730,7 @@ datadir='${datarootdir}'
 sysconfdir='${prefix}/etc'
 sharedstatedir='${prefix}/com'
 localstatedir='${prefix}/var'
+runstatedir='${localstatedir}/run'
 includedir='${prefix}/include'
 oldincludedir='/usr/include'
 docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
@@ -980,6 +982,15 @@ do
   | -silent | --silent | --silen | --sile | --sil)
     silent=yes ;;
 
+  -runstatedir | --runstatedir | --runstatedi | --runstated \
+  | --runstate | --runstat | --runsta | --runst | --runs \
+  | --run | --ru | --r)
+    ac_prev=runstatedir ;;
+  -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
+  | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
+  | --run=* | --ru=* | --r=*)
+    runstatedir=$ac_optarg ;;
+
   -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
     ac_prev=sbindir ;;
   -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
@@ -1117,7 +1128,7 @@ fi
 for ac_var in	exec_prefix prefix bindir sbindir libexecdir datarootdir \
 		datadir sysconfdir sharedstatedir localstatedir includedir \
 		oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
-		libdir localedir mandir
+		libdir localedir mandir runstatedir
 do
   eval ac_val=\$$ac_var
   # Remove trailing slashes.
@@ -1272,6 +1283,7 @@ Fine tuning of the installation directories:
   --sysconfdir=DIR        read-only single-machine data [PREFIX/etc]
   --sharedstatedir=DIR    modifiable architecture-independent data [PREFIX/com]
   --localstatedir=DIR     modifiable single-machine data [PREFIX/var]
+  --runstatedir=DIR       modifiable per-process data [LOCALSTATEDIR/run]
   --libdir=DIR            object code libraries [EPREFIX/lib]
   --includedir=DIR        C header files [PREFIX/include]
   --oldincludedir=DIR     C header files for non-gcc [/usr/include]
@@ -4091,7 +4103,7 @@ else
     We can't simply define LARGE_OFF_T to be 9223372036854775807,
     since some C++ compilers masquerading as C compilers
     incorrectly reject 9223372036854775807.  */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
   int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
 		       && LARGE_OFF_T % 2147483647 == 1)
 		      ? 1 : -1];
@@ -4137,7 +4149,7 @@ else
     We can't simply define LARGE_OFF_T to be 9223372036854775807,
     since some C++ compilers masquerading as C compilers
     incorrectly reject 9223372036854775807.  */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
   int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
 		       && LARGE_OFF_T % 2147483647 == 1)
 		      ? 1 : -1];
@@ -4161,7 +4173,7 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
     We can't simply define LARGE_OFF_T to be 9223372036854775807,
     since some C++ compilers masquerading as C compilers
     incorrectly reject 9223372036854775807.  */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
   int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
 		       && LARGE_OFF_T % 2147483647 == 1)
 		      ? 1 : -1];
@@ -4206,7 +4218,7 @@ else
     We can't simply define LARGE_OFF_T to be 9223372036854775807,
     since some C++ compilers masquerading as C compilers
     incorrectly reject 9223372036854775807.  */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
   int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
 		       && LARGE_OFF_T % 2147483647 == 1)
 		      ? 1 : -1];
@@ -4230,7 +4242,7 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
     We can't simply define LARGE_OFF_T to be 9223372036854775807,
     since some C++ compilers masquerading as C compilers
     incorrectly reject 9223372036854775807.  */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
   int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
 		       && LARGE_OFF_T % 2147483647 == 1)
 		      ? 1 : -1];
@@ -4342,7 +4354,7 @@ as_fn_arith $ac_cv_sizeof_long_double \* 8 && long_double_type_size=$as_val
 
 for ac_header in inttypes.h stdint.h stdlib.h ftw.h \
 	unistd.h sys/stat.h sys/types.h \
-	string.h strings.h memory.h
+	string.h strings.h memory.h sys/auxv.h
 do :
   as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
 ac_fn_c_check_header_preproc "$LINENO" "$ac_header" "$as_ac_Header"
diff --git a/libgcc/configure.ac b/libgcc/configure.ac
index b59aa746afc..b18519171c7 100644
--- a/libgcc/configure.ac
+++ b/libgcc/configure.ac
@@ -203,7 +203,7 @@ AC_SUBST(long_double_type_size)
 
 AC_CHECK_HEADERS(inttypes.h stdint.h stdlib.h ftw.h \
 	unistd.h sys/stat.h sys/types.h \
-	string.h strings.h memory.h)
+	string.h strings.h memory.h sys/auxv.h)
 AC_HEADER_STDC
 
 # Check for decimal float support.

commit 163e0d03f2cdc80de4968c4be4694cdaeaf47fcd
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:17 2020 +0100

    aarch64: Fix up aarch64_compare_and_swaphi pattern [PR94368]
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline
            2020-03-31  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94368
            * config/aarch64/constraints.md (Uph): New constraint.
            * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
            (aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
            constraint.
    
            * gcc.dg/pr94368.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a3fc5c2c6c3..cf54f78871d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2020-03-31  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94368
+	* config/aarch64/constraints.md (Uph): New constraint.
+	* config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
+	(aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
+	constraint.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index 0ee8d2efac0..1005462ae23 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -38,6 +38,8 @@
 
 (define_mode_attr cas_short_expected_pred
   [(QI "aarch64_reg_or_imm") (HI "aarch64_plushi_operand")])
+(define_mode_attr cas_short_expected_imm
+  [(QI "n") (HI "Uph")])
 
 (define_insn_and_split "aarch64_compare_and_swap<mode>"
   [(set (reg:CC CC_REGNUM)					;; bool out
@@ -47,7 +49,8 @@
       (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
    (set (match_dup 1)
     (unspec_volatile:SHORT
-      [(match_operand:SHORT 2 "<cas_short_expected_pred>" "rn")	;; expected
+      [(match_operand:SHORT 2 "<cas_short_expected_pred>"
+			      "r<cas_short_expected_imm>")	;; expected
        (match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ")	;; desired
        (match_operand:SI 4 "const_int_operand")			;; is_weak
        (match_operand:SI 5 "const_int_operand")			;; mod_s
diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index 32a0fa60a19..03626d2faf8 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -213,6 +213,13 @@
   (and (match_code "const_int")
        (match_test "(unsigned) exact_log2 (ival) <= 4")))
 
+(define_constraint "Uph"
+  "@internal
+  A constraint that matches HImode integers zero extendable to
+  SImode plus_operand."
+  (and (match_code "const_int")
+       (match_test "aarch64_plushi_immediate (op, VOIDmode)")))
+
 (define_memory_constraint "Q"
  "A memory address which uses a single base register with no offset."
  (and (match_code "mem")
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a3cf505b624..73a32f66ef6 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2020-03-31  Jakub Jelinek  <jakub@redhat.com>
+
+	* gcc.dg/pr94368.c: New test.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/gcc/testsuite/gcc.dg/pr94368.c b/gcc/testsuite/gcc.dg/pr94368.c
new file mode 100644
index 00000000000..1267b822098
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94368.c
@@ -0,0 +1,25 @@
+/* PR target/94368 */
+/* { dg-do compile { target fpic } } */
+/* { dg-options "-fpic -O1 -fcommon" } */
+
+int b, c, d, e, f, h;
+short g;
+int foo (int) __attribute__ ((__const__));
+
+void
+bar (void)
+{
+  while (1)
+    {
+      while (1)
+	{
+	  __atomic_load_n (&e, 0);
+	  if (foo (2))
+	    __sync_val_compare_and_swap (&c, 0, f);
+	  b = 1;
+	  if (h == e)
+	    break;
+	}
+      __sync_val_compare_and_swap (&g, -1, f);
+    }
+}

commit a69a60c4969cea06c1d44b5e3e4970595041e510
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:18 2020 +0100

    aarch64: Fix bootstrap with old binutils [PR93053]
    
    As reported in the PR, GCC 10 (and also 9.3.1 but not 9.3.0) fails to build
    when using older binutils which lack LSE support, because those instructions
    are used in libgcc.
    Thanks to Kyrylo's hint, the following patches (hopefully) allow it to build
    even with older binutils by using .inst directive if LSE support isn't
    available in the assembler.
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline
            2020-04-15  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/93053
            * configure.ac (LIBGCC_CHECK_AS_LSE): Add HAVE_AS_LSE checking.
            * config/aarch64/lse.S: Include auto-target.h, if HAVE_AS_LSE
            is not defined, use just .arch armv8-a.
            (B, M, N, OPN): Define.
            (COMMENT): New .macro.
            (CAS, CASP, SWP, LDOP): Use .inst directive if HAVE_AS_LSE is not
            defined.  Otherwise, move the operands right after the glue? and
            comment out operands where the macros are used.
            * configure: Regenerated.
            * config.in: Regenerated.

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index e641d747332..4942176b80b 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,20 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2020-04-15  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/93053
+	* configure.ac (LIBGCC_CHECK_AS_LSE): Add HAVE_AS_LSE checking.
+	* config/aarch64/lse.S: Include auto-target.h, if HAVE_AS_LSE
+	is not defined, use just .arch armv8-a.
+	(B, M, N, OPN): Define.
+	(COMMENT): New .macro.
+	(CAS, CASP, SWP, LDOP): Use .inst directive if HAVE_AS_LSE is not
+	defined.  Otherwise, move the operands right after the glue? and
+	comment out operands where the macros are used.
+	* configure: Regenerated.
+	* config.in: Regenerated.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/libgcc/config.in b/libgcc/config.in
index 59a3d8daf52..5be5321d258 100644
--- a/libgcc/config.in
+++ b/libgcc/config.in
@@ -10,6 +10,9 @@
    */
 #undef HAVE_AS_CFI_SECTIONS
 
+/* Define to 1 if the assembler supports LSE. */
+#undef HAVE_AS_LSE
+
 /* Define to 1 if the target assembler supports thread-local storage. */
 #undef HAVE_CC_TLS
 
diff --git a/libgcc/config/aarch64/lse.S b/libgcc/config/aarch64/lse.S
index c7979382ad7..f7f1c19587b 100644
--- a/libgcc/config/aarch64/lse.S
+++ b/libgcc/config/aarch64/lse.S
@@ -48,8 +48,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  * separately to minimize code size.
  */
 
+#include "auto-target.h"
+
 /* Tell the assembler to accept LSE instructions.  */
+#ifdef HAVE_AS_LSE
 	.arch armv8-a+lse
+#else
+	.arch armv8-a
+#endif
 
 /* Declare the symbol gating the LSE implementations.  */
 	.hidden	__aarch64_have_lse_atomics
@@ -58,12 +64,19 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #if SIZE == 1
 # define S     b
 # define UXT   uxtb
+# define B     0x00000000
 #elif SIZE == 2
 # define S     h
 # define UXT   uxth
+# define B     0x40000000
 #elif SIZE == 4 || SIZE == 8 || SIZE == 16
 # define S
 # define UXT   mov
+# if SIZE == 4
+#  define B    0x80000000
+# elif SIZE == 8
+#  define B    0xc0000000
+# endif
 #else
 # error
 #endif
@@ -72,18 +85,26 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 # define SUFF  _relax
 # define A
 # define L
+# define M     0x000000
+# define N     0x000000
 #elif MODEL == 2
 # define SUFF  _acq
 # define A     a
 # define L
+# define M     0x400000
+# define N     0x800000
 #elif MODEL == 3
 # define SUFF  _rel
 # define A
 # define L     l
+# define M     0x008000
+# define N     0x400000
 #elif MODEL == 4
 # define SUFF  _acq_rel
 # define A     a
 # define L     l
+# define M     0x408000
+# define N     0xc00000
 #else
 # error
 #endif
@@ -144,9 +165,13 @@ STARTFN	NAME(cas)
 	JUMP_IF_NOT_LSE	8f
 
 #if SIZE < 16
-#define CAS	glue4(cas, A, L, S)
+#ifdef HAVE_AS_LSE
+# define CAS	glue4(cas, A, L, S)	s(0), s(1), [x2]
+#else
+# define CAS	.inst 0x08a07c41 + B + M
+#endif
 
-	CAS		s(0), s(1), [x2]
+	CAS		/* s(0), s(1), [x2] */
 	ret
 
 8:	UXT		s(tmp0), s(0)
@@ -160,9 +185,13 @@ STARTFN	NAME(cas)
 #else
 #define LDXP	glue3(ld, A, xp)
 #define STXP	glue3(st, L, xp)
-#define CASP	glue3(casp, A, L)
+#ifdef HAVE_AS_LSE
+# define CASP	glue3(casp, A, L)	x0, x1, x2, x3, [x4]
+#else
+# define CASP	.inst 0x48207c82 + M
+#endif
 
-	CASP		x0, x1, x2, x3, [x4]
+	CASP		/* x0, x1, x2, x3, [x4] */
 	ret
 
 8:	mov		x(tmp0), x0
@@ -181,12 +210,16 @@ ENDFN	NAME(cas)
 #endif
 
 #ifdef L_swp
-#define SWP	glue4(swp, A, L, S)
+#ifdef HAVE_AS_LSE
+# define SWP	glue4(swp, A, L, S)	s(0), s(0), [x1]
+#else
+# define SWP	.inst 0x38208020 + B + N
+#endif
 
 STARTFN	NAME(swp)
 	JUMP_IF_NOT_LSE	8f
 
-	SWP		s(0), s(0), [x1]
+	SWP		/* s(0), s(0), [x1] */
 	ret
 
 8:	mov		s(tmp0), s(0)
@@ -204,24 +237,32 @@ ENDFN	NAME(swp)
 #ifdef L_ldadd
 #define LDNM	ldadd
 #define OP	add
+#define OPN	0x0000
 #elif defined(L_ldclr)
 #define LDNM	ldclr
 #define OP	bic
+#define OPN	0x1000
 #elif defined(L_ldeor)
 #define LDNM	ldeor
 #define OP	eor
+#define OPN	0x2000
 #elif defined(L_ldset)
 #define LDNM	ldset
 #define OP	orr
+#define OPN	0x3000
 #else
 #error
 #endif
-#define LDOP	glue4(LDNM, A, L, S)
+#ifdef HAVE_AS_LSE
+# define LDOP	glue4(LDNM, A, L, S)	s(0), s(0), [x1]
+#else
+# define LDOP	.inst 0x38200020 + OPN + B + N
+#endif
 
 STARTFN	NAME(LDNM)
 	JUMP_IF_NOT_LSE	8f
 
-	LDOP		s(0), s(0), [x1]
+	LDOP		/* s(0), s(0), [x1] */
 	ret
 
 8:	mov		s(tmp0), s(0)
diff --git a/libgcc/configure b/libgcc/configure
index 7962cd9b87e..aac5e5fb6a7 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5385,6 +5385,46 @@ $as_echo "#define HAVE_AS_AVX 1" >>confdefs.h
   ;;
 esac
 
+
+
+case "${target}" in
+aarch64*-*-*)
+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if the assembler supports LSE" >&5
+$as_echo_n "checking if the assembler supports LSE... " >&6; }
+if ${libgcc_cv_as_lse+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+			asm(".arch armv8-a+lse\n\tcas w0, w1, [x2]");
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  libgcc_cv_as_lse=yes
+else
+  libgcc_cv_as_lse=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_as_lse" >&5
+$as_echo "$libgcc_cv_as_lse" >&6; }
+  if test x$libgcc_cv_as_lse = xyes; then
+
+$as_echo "#define HAVE_AS_LSE 1" >>confdefs.h
+
+  fi
+  ;;
+esac
+
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for init priority support" >&5
 $as_echo_n "checking for init priority support... " >&6; }
 if test "${libgcc_cv_init_priority+set}" = set; then :
diff --git a/libgcc/configure.ac b/libgcc/configure.ac
index b18519171c7..5f0a63ce2f0 100644
--- a/libgcc/configure.ac
+++ b/libgcc/configure.ac
@@ -543,6 +543,25 @@ i[[34567]]86-*-* | x86_64-*-*)
 esac])
 LIBGCC_CHECK_AS_AVX
 
+dnl Check if as supports LSE instructions.
+AC_DEFUN([LIBGCC_CHECK_AS_LSE], [
+case "${target}" in
+aarch64*-*-*)
+  AC_CACHE_CHECK([if the assembler supports LSE], libgcc_cv_as_lse, [
+    AC_TRY_COMPILE([],
+changequote(,)dnl
+			asm(".arch armv8-a+lse\n\tcas w0, w1, [x2]");
+changequote([,])dnl
+		       ,
+		   [libgcc_cv_as_lse=yes], [libgcc_cv_as_lse=no])
+  ])
+  if test x$libgcc_cv_as_lse = xyes; then
+    AC_DEFINE(HAVE_AS_LSE, 1, [Define to 1 if the assembler supports LSE.])
+  fi
+  ;;
+esac])
+LIBGCC_CHECK_AS_LSE
+
 dnl Check if as supports RTM instructions.
 AC_CACHE_CHECK(for init priority support, libgcc_cv_init_priority, [
 AC_COMPILE_IFELSE([AC_LANG_PROGRAM(,

commit 1dbd821ee74e6c234e61e25b0801a0b0949bcc67
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:18 2020 +0100

    aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435]
    
    The following testcase ICEs, because aarch64_gen_compare_reg_maybe_ze emits
    invalid RTL.
    For y_mode [QH]Imode it expects y to be of that mode (or CONST_INT that fits
    into that mode) and x being SImode; for non-CONST_INT y it zero extends y
    into SImode and compares that against x, for CONST_INT y it zero extends y
    into SImode.  The problem is that when the zero extended constant isn't
    usable directly, it forces it into a REG, but with y_mode mode, and then
    compares against y.  That is wrong, because it should force it into a SImode
    REG and compare that way.
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline
            2020-04-02  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94435
            * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
            y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
    
            * gcc.target/aarch64/pr94435.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cf54f78871d..098444f88ee 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2020-04-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94435
+	* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
+	y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index ffbf1e38c5f..a429505fea3 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1556,7 +1556,10 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x, rtx y,
   if (y_mode == E_QImode || y_mode == E_HImode)
     {
       if (CONST_INT_P (y))
-	y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode));
+	{
+	  y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode));
+	  y_mode = SImode;
+	}
       else
 	{
 	  rtx t, cc_reg;
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 73a32f66ef6..f3eca678e3b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2020-04-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94435
+	* gcc.target/aarch64/pr94435.c: New test.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/gcc/testsuite/gcc.target/aarch64/pr94435.c b/gcc/testsuite/gcc.target/aarch64/pr94435.c
new file mode 100644
index 00000000000..5713c14d5f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr94435.c
@@ -0,0 +1,25 @@
+/* PR target/94435 */
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+nolse -moutline-atomics" } */
+
+int b, c, d, e, f, h;
+short g;
+int foo (int) __attribute__ ((__const__));
+
+void
+bar (void)
+{
+  while (1)
+    {
+      while (1)
+	{
+	  __atomic_load_n (&e, 0);
+	  if (foo (2))
+	    __sync_val_compare_and_swap (&c, 0, f);
+	  b = 1;
+	  if (h == e)
+	    break;
+	}
+      __sync_val_compare_and_swap (&g, -1, f);
+    }
+}

commit 69472d76d2456a447f61bc539bd6fe262c167bcf
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:19 2020 +0100

    re PR target/90724 (ICE with __sync_bool_compare_and_swap with -march=armv8.2-a+sve)
    
    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline
            2019-08-21  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
    
            PR target/90724
            * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): Force y
            in reg if it fails aarch64_plus_operand predicate.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 098444f88ee..be6104f289d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline
+	2019-08-21  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+	PR target/90724
+	* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): Force y
+	in reg if it fails aarch64_plus_operand predicate.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index a429505fea3..5eec1aae54a 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1574,6 +1574,9 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x, rtx y,
 	}
     }
 
+  if (!aarch64_plus_operand (y, y_mode))
+    y = force_reg (y_mode, y);
+
   return aarch64_gen_compare_reg (code, x, y);
 }
 

commit a099cb63af86e1725f1966ba82382dd11c016acc
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Apr 23 00:16:55 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index dd5a95e4f6b..0045aa06c5a 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200422
+20200423

commit 51a599bb2de24784c2d38eaedc04fb23587726c1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Apr 24 00:16:54 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0045aa06c5a..f35f88c9b87 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200423
+20200424

commit aadc54867cc200ad7d073222769b9de7f13b5bcd
Author: Thomas König <tkoenig@gcc.gnu.org>
Date:   Fri Apr 24 09:26:48 2020 +0200

    Fix PR 93956, wrong pointer when returned via function.
    
    Backport from trunk.
    
    This one took a bit of detective work.  When array pointers point
    to components of derived types, we currently set the span field
    and then create an array temporary when we pass the array
    pointer to a procedure as a non-pointer or non-target argument.
    (This is inefficient, but that's for another release).
    
    Now, the compiler detected this case when there was a direct assignment
    like p => a%b, but not when p was returned either as a function result
    or via an argument.  This patch fixes that.
    
    2020-04-24  Thomas Koenig  <tkoenig@gcc.gnu.org>
    
            PR fortran/93956
            * expr.c (gfc_check_pointer_assign): Also set subref_array_pointer
            when a function returns a pointer.
            * interface.c (gfc_set_subref_array_pointer_arg): New function.
            (gfc_procedure_use): Call it.
    
    2020-04-24  Thomas Koenig  <tkoenig@gcc.gnu.org>
    
            PR fortran/93956
            * gfortran.dg/pointer_assign_13.f90: New test.

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 9104f16a847..4b4c1d8e886 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-24  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	Backport from trunk.
+	PR fortran/93956
+	* expr.c (gfc_check_pointer_assign): Also set subref_array_pointer
+	when a function returns a pointer.
+	* interface.c (gfc_set_subref_array_pointer_arg): New function.
+	(gfc_procedure_use): Call it.
+
 2020-04-14  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	Backport from trunk.
diff --git a/gcc/fortran/expr.c b/gcc/fortran/expr.c
index f145e9b363b..5348f1bf4ce 100644
--- a/gcc/fortran/expr.c
+++ b/gcc/fortran/expr.c
@@ -3895,8 +3895,11 @@ gfc_check_pointer_assign (gfc_expr *lvalue, gfc_expr *rvalue, bool is_init_expr)
   if (rvalue->expr_type == EXPR_NULL)
     return true;
 
-  if (rvalue->expr_type == EXPR_VARIABLE && is_subref_array (rvalue))
-    lvalue->symtree->n.sym->attr.subref_array_pointer = 1;
+  /* A function may also return subref arrray pointer.  */
+
+  if ((rvalue->expr_type == EXPR_VARIABLE && is_subref_array (rvalue))
+      || rvalue->expr_type == EXPR_FUNCTION)
+      lvalue->symtree->n.sym->attr.subref_array_pointer = 1;
 
   attr = gfc_expr_attr (rvalue);
 
diff --git a/gcc/fortran/interface.c b/gcc/fortran/interface.c
index 04850b0406c..26837d7c1fa 100644
--- a/gcc/fortran/interface.c
+++ b/gcc/fortran/interface.c
@@ -3619,6 +3619,36 @@ check_intents (gfc_formal_arglist *f, gfc_actual_arglist *a)
   return true;
 }
 
+/* Go through the argument list of a procedure and look for
+   pointers which may be set, possibly introducing a span.  */
+
+static void
+gfc_set_subref_array_pointer_arg (gfc_formal_arglist *dummy_args,
+				  gfc_actual_arglist *actual_args)
+{
+  gfc_formal_arglist *f;
+  gfc_actual_arglist *a;
+  gfc_symbol *a_sym;
+  for (f = dummy_args, a = actual_args; f && a ; f = f->next, a = a->next)
+    {
+
+      if (f->sym == NULL)
+	continue;
+
+      if (!f->sym->attr.pointer || f->sym->attr.intent == INTENT_IN)
+	continue;
+
+      if (a->expr == NULL || a->expr->expr_type != EXPR_VARIABLE)
+	continue;
+      a_sym = a->expr->symtree->n.sym;
+
+      if (!a_sym->attr.pointer)
+	continue;
+
+      a_sym->attr.subref_array_pointer = 1;
+    }
+  return;
+}
 
 /* Check how a procedure is used against its interface.  If all goes
    well, the actual argument list will also end up being properly
@@ -3765,6 +3795,10 @@ gfc_procedure_use (gfc_symbol *sym, gfc_actual_arglist **ap, locus *where)
   if (warn_aliasing)
     check_some_aliasing (dummy_args, *ap);
 
+  /* Set the subref_array_pointer_arg if needed.  */
+  if (dummy_args)
+    gfc_set_subref_array_pointer_arg (dummy_args, *ap);
+
   return true;
 }
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f3eca678e3b..2b6aa9e6756 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-24  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	Backport from trunk
+	PR fortran/93956
+	* gfortran.dg/pointer_assign_13.f90: New test.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/gcc/testsuite/gfortran.dg/pointer_assign_13.f90 b/gcc/testsuite/gfortran.dg/pointer_assign_13.f90
new file mode 100644
index 00000000000..b3f2cd9dab7
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pointer_assign_13.f90
@@ -0,0 +1,47 @@
+! { dg-do run }
+! PR 93956 - span was set incorrectly, leading to wrong code.
+! Original test case by "martin".
+program array_temps
+  implicit none
+  
+  type :: tt
+     integer :: u = 1
+     integer :: v = 2
+  end type tt
+
+  type(tt), dimension(:), pointer :: r
+  integer :: n
+  integer, dimension(:), pointer :: p, q, u
+
+  n = 10
+  allocate(r(1:n))
+  call foo(r%v,n)
+  p => get(r(:))
+  call foo(p, n)
+  call get2(r,u)
+  call foo(u,n)
+  q => r%v
+  call foo(q, n)
+
+deallocate(r)
+
+contains
+
+   subroutine foo(a, n)
+      integer, dimension(:), intent(in) :: a
+      integer, intent(in) :: n
+      if (sum(a(1:n)) /= 2*n) stop 1
+   end subroutine foo
+
+   function get(x) result(q)
+      type(tt), dimension(:), target, intent(in) :: x
+      integer, dimension(:), pointer :: q
+      q => x(:)%v
+   end function get
+
+   subroutine get2(x,q)
+      type(tt), dimension(:), target, intent(in) :: x
+      integer, dimension(:), pointer, intent(out) :: q
+      q => x(:)%v
+    end subroutine get2
+end program array_temps

commit 84eaabbb404ba92c37952e64c50d72b4af9ad1dd
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Apr 25 00:16:51 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f35f88c9b87..32e746a043b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200424
+20200425

commit b7832aa71d29aba1679913b0b8fb08bdf00e8d4d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Apr 26 00:16:55 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 32e746a043b..76e67bdca64 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200425
+20200426

commit 661772c7b858ca655b32fa260a571814d503d118
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Apr 27 00:16:54 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 76e67bdca64..42eb287b898 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200426
+20200427

commit 0a6cc68bc0d5525b0da71f59a57286b189781d41
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Apr 28 00:16:55 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 42eb287b898..c8e8b6154e2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200427
+20200428

commit 034dfe065033a846761b0a5c35fc86023bee1874
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Tue Apr 28 13:25:43 2020 +0100

    aarch64: Fix for PR target/94814
    
    Backport of PR target/94518: Fix memmodel index in aarch64_store_exclusive_pair
    
    2020-04-28  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            PR target/94814
            Backport from gcc-9.
            2020-04-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
    
            PR target/94518
            2019-09-23  Richard Sandiford  <richard.sandiford@arm.com>
    
            * config/aarch64/atomics.md (aarch64_store_exclusive_pair): Fix
            memmodel index.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index be6104f289d..96eeb2791d6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2020-04-28  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	PR target/94814
+	Backport from gcc-9.
+	2020-04-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/94518
+	2019-09-23  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/atomics.md (aarch64_store_exclusive_pair): Fix
+	memmodel index.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index 1005462ae23..0e0b0373192 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -752,7 +752,7 @@
 	  UNSPECV_SX))]
   ""
   {
-    enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
+    enum memmodel model = memmodel_from_int (INTVAL (operands[4]));
     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
       return "stxp\t%w0, %x2, %x3, %1";
     else

commit 612c7e2518423ad66c68c4dd240f9fa84c07794e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Apr 29 00:16:54 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c8e8b6154e2..c8ae8f2719b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200428
+20200429

commit 80c605c875fb394212164908151bf0f8665f0391
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Wed Apr 29 15:42:27 2020 +0100

    aarch64: Force TImode values into even registers
    
    The LSE CASP instruction requires values to be placed in even
    register pairs.  A solution involving two additional register
    classes was rejected in favor of the much simpler solution of
    simply requiring all TImode values to be aligned.
    
    gcc/ChangeLog:
    2020-04-29  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    
            Backport from mainline.
            2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
    
            * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
            16-byte modes held in GP registers to use an even regno.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 96eeb2791d6..3fbb6cc36f2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-04-29  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backport from mainline.
+	2018-10-31  Richard Henderson  <richard.henderson@linaro.org>
+
+	* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
+	16-byte modes held in GP registers to use an even regno.
+
 2020-04-28  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	PR target/94814
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5eec1aae54a..525deba56ea 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1369,10 +1369,14 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
   if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
     return mode == Pmode;
 
-  if (GP_REGNUM_P (regno) && known_le (GET_MODE_SIZE (mode), 16))
-    return true;
-
-  if (FP_REGNUM_P (regno))
+  if (GP_REGNUM_P (regno))
+    {
+      if (known_le (GET_MODE_SIZE (mode), 8))
+	return true;
+      else if (known_le (GET_MODE_SIZE (mode), 16))
+	return (regno & 1) == 0;
+    }
+  else if (FP_REGNUM_P (regno))
     {
       if (vec_flags & VEC_STRUCT)
 	return end_hard_regno (mode, regno) - 1 <= V31_REGNUM;

commit 1b3bf1b907a89cdba07c41c47dca9cbe3d7ff453
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Apr 30 00:16:48 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c8ae8f2719b..6be87a3be11 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200429
+20200430

commit 80b9bc568cf5e39a08acbe570671e24814a342e2
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri May 1 00:17:18 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6be87a3be11..577a56c4845 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200430
+20200501

commit b92bb10248a8f99cecf71a54c56bd4d8c75a322f
Author: Thomas Koenig <tkoenig@gcc.gnu.org>
Date:   Fri May 1 14:45:56 2020 +0200

    Revert patch for PR fortran/93956.
    
    2020-04-27  Thomas Koenig  <tkoenig@gcc.gnu.org>
    
                PR fortran/93956
                PR fortran/94788
                * expr.c (gfc_check_pointer_assign): Revert patch for PR 93956.
                * interface.c: Likewise.

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 4b4c1d8e886..b81ffd555ad 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,10 @@
+2020-04-27  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	PR fortran/93956
+	PR fortran/94788
+	* expr.c (gfc_check_pointer_assign): Revert patch for PR 93956.
+	* interface.c: Likewise.
+
 2020-04-24  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	Backport from trunk.
diff --git a/gcc/fortran/expr.c b/gcc/fortran/expr.c
index 5348f1bf4ce..f145e9b363b 100644
--- a/gcc/fortran/expr.c
+++ b/gcc/fortran/expr.c
@@ -3895,11 +3895,8 @@ gfc_check_pointer_assign (gfc_expr *lvalue, gfc_expr *rvalue, bool is_init_expr)
   if (rvalue->expr_type == EXPR_NULL)
     return true;
 
-  /* A function may also return subref arrray pointer.  */
-
-  if ((rvalue->expr_type == EXPR_VARIABLE && is_subref_array (rvalue))
-      || rvalue->expr_type == EXPR_FUNCTION)
-      lvalue->symtree->n.sym->attr.subref_array_pointer = 1;
+  if (rvalue->expr_type == EXPR_VARIABLE && is_subref_array (rvalue))
+    lvalue->symtree->n.sym->attr.subref_array_pointer = 1;
 
   attr = gfc_expr_attr (rvalue);
 
diff --git a/gcc/fortran/interface.c b/gcc/fortran/interface.c
index 26837d7c1fa..04850b0406c 100644
--- a/gcc/fortran/interface.c
+++ b/gcc/fortran/interface.c
@@ -3619,36 +3619,6 @@ check_intents (gfc_formal_arglist *f, gfc_actual_arglist *a)
   return true;
 }
 
-/* Go through the argument list of a procedure and look for
-   pointers which may be set, possibly introducing a span.  */
-
-static void
-gfc_set_subref_array_pointer_arg (gfc_formal_arglist *dummy_args,
-				  gfc_actual_arglist *actual_args)
-{
-  gfc_formal_arglist *f;
-  gfc_actual_arglist *a;
-  gfc_symbol *a_sym;
-  for (f = dummy_args, a = actual_args; f && a ; f = f->next, a = a->next)
-    {
-
-      if (f->sym == NULL)
-	continue;
-
-      if (!f->sym->attr.pointer || f->sym->attr.intent == INTENT_IN)
-	continue;
-
-      if (a->expr == NULL || a->expr->expr_type != EXPR_VARIABLE)
-	continue;
-      a_sym = a->expr->symtree->n.sym;
-
-      if (!a_sym->attr.pointer)
-	continue;
-
-      a_sym->attr.subref_array_pointer = 1;
-    }
-  return;
-}
 
 /* Check how a procedure is used against its interface.  If all goes
    well, the actual argument list will also end up being properly
@@ -3795,10 +3765,6 @@ gfc_procedure_use (gfc_symbol *sym, gfc_actual_arglist **ap, locus *where)
   if (warn_aliasing)
     check_some_aliasing (dummy_args, *ap);
 
-  /* Set the subref_array_pointer_arg if needed.  */
-  if (dummy_args)
-    gfc_set_subref_array_pointer_arg (dummy_args, *ap);
-
   return true;
 }
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2b6aa9e6756..758c191cd7e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2020-05-01  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	PR fortran/93956
+	PR fortran/94788
+	* gfortran.dg/pointer_assign_13.f90: Remove.
+
 2020-04-24  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	Backport from trunk
diff --git a/gcc/testsuite/gfortran.dg/pointer_assign_13.f90 b/gcc/testsuite/gfortran.dg/pointer_assign_13.f90
deleted file mode 100644
index b3f2cd9dab7..00000000000
--- a/gcc/testsuite/gfortran.dg/pointer_assign_13.f90
+++ /dev/null
@@ -1,47 +0,0 @@
-! { dg-do run }
-! PR 93956 - span was set incorrectly, leading to wrong code.
-! Original test case by "martin".
-program array_temps
-  implicit none
-  
-  type :: tt
-     integer :: u = 1
-     integer :: v = 2
-  end type tt
-
-  type(tt), dimension(:), pointer :: r
-  integer :: n
-  integer, dimension(:), pointer :: p, q, u
-
-  n = 10
-  allocate(r(1:n))
-  call foo(r%v,n)
-  p => get(r(:))
-  call foo(p, n)
-  call get2(r,u)
-  call foo(u,n)
-  q => r%v
-  call foo(q, n)
-
-deallocate(r)
-
-contains
-
-   subroutine foo(a, n)
-      integer, dimension(:), intent(in) :: a
-      integer, intent(in) :: n
-      if (sum(a(1:n)) /= 2*n) stop 1
-   end subroutine foo
-
-   function get(x) result(q)
-      type(tt), dimension(:), target, intent(in) :: x
-      integer, dimension(:), pointer :: q
-      q => x(:)%v
-   end function get
-
-   subroutine get2(x,q)
-      type(tt), dimension(:), target, intent(in) :: x
-      integer, dimension(:), pointer, intent(out) :: q
-      q => x(:)%v
-    end subroutine get2
-end program array_temps

commit d07a84a582f85fee86bca506018841382b80db80
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat May 2 00:17:16 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 577a56c4845..fa22dac63c7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200501
+20200502

commit ea74cc16f670890a62821b9207d0441bcf9af8de
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun May 3 00:17:21 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index fa22dac63c7..a9564b61700 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200502
+20200503

commit 4a5244551bf047cbe3981acebc88c8b4d9528f75
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon May 4 00:17:13 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a9564b61700..e9c2b992a49 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200503
+20200504

commit cf16ecdd897a73a1651aba50533c5a6fd73e842c
Author: Andreas Krebbel <krebbel@linux.ibm.com>
Date:   Mon May 4 10:43:02 2020 +0200

    PR94613: Fix vec_sel builtin for IBM Z
    
    The vsel instruction is a bit-wise select instruction.  Using an
    IF_THEN_ELSE to express it in RTL is wrong and leads to wrong code being
    generated in the combine pass.
    
    With the patch the pattern is written using bit operations.  However,
    I've just noticed that the manual still demands a fixed point mode for
    AND/IOR and friends although several targets emit bit ops on floating
    point vectors (including i386, Power, and s390). So I assume this is a
    safe thing to do?!
    
    gcc/ChangeLog:
    
    2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
    
            Backport from mainline
            2020-04-20  Andreas Krebbel  <krebbel@linux.ibm.com>
    
            PR target/94613
            * config/s390/s390-builtin-types.def: Add 3 new function modes.
            * config/s390/s390-builtins.def: Add mode dependent low-level
            builtin and map the overloaded builtins to these.
            * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
            ("vsel<V_HW"): ... this and rewrite the pattern with bitops.
    
    gcc/testsuite/ChangeLog:
    
    2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
    
            Backport from mainline
            2020-04-20  Andreas Krebbel  <krebbel@linux.ibm.com>
    
            PR target/94613
            * gcc.target/s390/zvector/pr94613.c: New test.
            * gcc.target/s390/zvector/vec_sel-1.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3fbb6cc36f2..bcfbba96124 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	Backport from mainline
+	2020-04-20  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	PR target/94613
+	* config/s390/s390-builtin-types.def: Add 3 new function modes.
+	* config/s390/s390-builtins.def: Add mode dependent low-level
+	builtin and map the overloaded builtins to these.
+	* config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
+	("vsel<V_HW"): ... this and rewrite the pattern with bitops.
+
 2020-04-29  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/config/s390/s390-builtin-types.def b/gcc/config/s390/s390-builtin-types.def
index 6f257c6de77..9779666a733 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -293,6 +293,7 @@ DEF_FN_TYPE_3 (BT_FN_UV16QI_UV2DI_UV2DI_UV16QI, BT_UV16QI, BT_UV2DI, BT_UV2DI, B
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV8HI_UV8HI_INTPTR, BT_UV16QI, BT_UV8HI, BT_UV8HI, BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_UV2DI, BT_ULONGLONG, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_INT)
+DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV4SI_UV4SI_UV2DI, BT_UV2DI, BT_UV4SI, BT_UV4SI, BT_UV2DI)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_V2DF_INT_INT, BT_UV2DI, BT_V2DF, BT_INT, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV4SI_UV2DI_UV2DI_INTPTR, BT_UV4SI, BT_UV2DI, BT_UV2DI, BT_INTPTR)
@@ -316,6 +317,7 @@ DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_DBL_INT, BT_V2DF, BT_V2DF, BT_DBL, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_UCHAR_UCHAR, BT_V2DF, BT_V2DF, BT_UCHAR, BT_UCHAR)
 DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_UINT_UINT, BT_V2DF, BT_V2DF, BT_UINT, BT_UINT)
 DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_V2DF_INT, BT_V2DF, BT_V2DF, BT_V2DF, BT_INT)
+DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_V2DF_UV2DI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV2DI)
 DEF_FN_TYPE_3 (BT_FN_V2DF_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF, BT_V2DF)
 DEF_FN_TYPE_3 (BT_FN_V2DF_V2DI_INT_INT, BT_V2DF, BT_V2DI, BT_INT, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_V2DI_UV2DI_UV2DI_INTPTR, BT_V2DI, BT_UV2DI, BT_UV2DI, BT_INTPTR)
@@ -328,6 +330,7 @@ DEF_FN_TYPE_3 (BT_FN_V4SF_V2DF_INT_INT, BT_V4SF, BT_V2DF, BT_INT, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_V4SF_V4SF_FLT_INT, BT_V4SF, BT_V4SF, BT_FLT, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_V4SF_V4SF_UCHAR_UCHAR, BT_V4SF, BT_V4SF, BT_UCHAR, BT_UCHAR)
 DEF_FN_TYPE_3 (BT_FN_V4SF_V4SF_V4SF_INT, BT_V4SF, BT_V4SF, BT_V4SF, BT_INT)
+DEF_FN_TYPE_3 (BT_FN_V4SF_V4SF_V4SF_UV4SI, BT_V4SF, BT_V4SF, BT_V4SF, BT_UV4SI)
 DEF_FN_TYPE_3 (BT_FN_V4SF_V4SF_V4SF_V4SF, BT_V4SF, BT_V4SF, BT_V4SF, BT_V4SF)
 DEF_FN_TYPE_3 (BT_FN_V4SI_UV4SI_UV4SI_INTPTR, BT_V4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_V4SI_V2DI_V2DI_INTPTR, BT_V4SI, BT_V2DI, BT_V2DI, BT_INTPTR)
diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def
index 365e794316a..006669718fa 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -685,36 +685,41 @@ B_DEF      (s390_vsceg,                 vec_scatter_elementv2di,0,
 
 /* First two operands are swapped in s390-c.c */
 OB_DEF     (s390_vec_sel,               s390_vec_sel_b8_a,  s390_vec_sel_dbl_b, B_VX,               BT_FN_OV4SI_OV4SI_OV4SI_OV4SI)
-OB_DEF_VAR (s390_vec_sel_b8_a,          s390_vsel,          0,                  0,                  BT_OV_BV16QI_BV16QI_BV16QI_UV16QI)
-OB_DEF_VAR (s390_vec_sel_b8_b,          s390_vsel,          0,                  0,                  BT_OV_BV16QI_BV16QI_BV16QI_BV16QI)
-OB_DEF_VAR (s390_vec_sel_s8_a,          s390_vsel,          0,                  0,                  BT_OV_V16QI_V16QI_V16QI_UV16QI)
-OB_DEF_VAR (s390_vec_sel_s8_b,          s390_vsel,          0,                  0,                  BT_OV_V16QI_V16QI_V16QI_BV16QI)
-OB_DEF_VAR (s390_vec_sel_u8_a,          s390_vsel,          0,                  0,                  BT_OV_UV16QI_UV16QI_UV16QI_UV16QI)
-OB_DEF_VAR (s390_vec_sel_u8_b,          s390_vsel,          0,                  0,                  BT_OV_UV16QI_UV16QI_UV16QI_BV16QI)
-OB_DEF_VAR (s390_vec_sel_b16_a,         s390_vsel,          0,                  0,                  BT_OV_BV8HI_BV8HI_BV8HI_UV8HI)
-OB_DEF_VAR (s390_vec_sel_b16_b,         s390_vsel,          0,                  0,                  BT_OV_BV8HI_BV8HI_BV8HI_BV8HI)
-OB_DEF_VAR (s390_vec_sel_s16_a,         s390_vsel,          0,                  0,                  BT_OV_V8HI_V8HI_V8HI_UV8HI)
-OB_DEF_VAR (s390_vec_sel_s16_b,         s390_vsel,          0,                  0,                  BT_OV_V8HI_V8HI_V8HI_BV8HI)
-OB_DEF_VAR (s390_vec_sel_u16_a,         s390_vsel,          0,                  0,                  BT_OV_UV8HI_UV8HI_UV8HI_UV8HI)
-OB_DEF_VAR (s390_vec_sel_u16_b,         s390_vsel,          0,                  0,                  BT_OV_UV8HI_UV8HI_UV8HI_BV8HI)
-OB_DEF_VAR (s390_vec_sel_b32_a,         s390_vsel,          0,                  0,                  BT_OV_BV4SI_BV4SI_BV4SI_UV4SI)
-OB_DEF_VAR (s390_vec_sel_b32_b,         s390_vsel,          0,                  0,                  BT_OV_BV4SI_BV4SI_BV4SI_BV4SI)
-OB_DEF_VAR (s390_vec_sel_s32_a,         s390_vsel,          0,                  0,                  BT_OV_V4SI_V4SI_V4SI_UV4SI)
-OB_DEF_VAR (s390_vec_sel_s32_b,         s390_vsel,          0,                  0,                  BT_OV_V4SI_V4SI_V4SI_BV4SI)
-OB_DEF_VAR (s390_vec_sel_u32_a,         s390_vsel,          0,                  0,                  BT_OV_UV4SI_UV4SI_UV4SI_UV4SI)
-OB_DEF_VAR (s390_vec_sel_u32_b,         s390_vsel,          0,                  0,                  BT_OV_UV4SI_UV4SI_UV4SI_BV4SI)
-OB_DEF_VAR (s390_vec_sel_b64_a,         s390_vsel,          0,                  0,                  BT_OV_BV2DI_BV2DI_BV2DI_UV2DI)
-OB_DEF_VAR (s390_vec_sel_b64_b,         s390_vsel,          0,                  0,                  BT_OV_BV2DI_BV2DI_BV2DI_BV2DI)
-OB_DEF_VAR (s390_vec_sel_s64_a,         s390_vsel,          0,                  0,                  BT_OV_V2DI_V2DI_V2DI_UV2DI)
-OB_DEF_VAR (s390_vec_sel_s64_b,         s390_vsel,          0,                  0,                  BT_OV_V2DI_V2DI_V2DI_BV2DI)
-OB_DEF_VAR (s390_vec_sel_u64_a,         s390_vsel,          0,                  0,                  BT_OV_UV2DI_UV2DI_UV2DI_UV2DI)
-OB_DEF_VAR (s390_vec_sel_u64_b,         s390_vsel,          0,                  0,                  BT_OV_UV2DI_UV2DI_UV2DI_BV2DI)
-OB_DEF_VAR (s390_vec_sel_flt_a,         s390_vsel,          B_VXE,              0,                  BT_OV_V4SF_V4SF_V4SF_UV4SI)
-OB_DEF_VAR (s390_vec_sel_flt_b,         s390_vsel,          B_VXE,              0,                  BT_OV_V4SF_V4SF_V4SF_BV4SI)
-OB_DEF_VAR (s390_vec_sel_dbl_a,         s390_vsel,          0,                  0,                  BT_OV_V2DF_V2DF_V2DF_UV2DI)
-OB_DEF_VAR (s390_vec_sel_dbl_b,         s390_vsel,          0,                  0,                  BT_OV_V2DF_V2DF_V2DF_BV2DI)
-
-B_DEF      (s390_vsel,                  vec_selv16qi,       0,                  B_VX,               0,                  BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
+OB_DEF_VAR (s390_vec_sel_b8_a,          s390_vselb,         0,                  0,                  BT_OV_BV16QI_BV16QI_BV16QI_UV16QI)
+OB_DEF_VAR (s390_vec_sel_b8_b,          s390_vselb,         0,                  0,                  BT_OV_BV16QI_BV16QI_BV16QI_BV16QI)
+OB_DEF_VAR (s390_vec_sel_s8_a,          s390_vselb,         0,                  0,                  BT_OV_V16QI_V16QI_V16QI_UV16QI)
+OB_DEF_VAR (s390_vec_sel_s8_b,          s390_vselb,         0,                  0,                  BT_OV_V16QI_V16QI_V16QI_BV16QI)
+OB_DEF_VAR (s390_vec_sel_u8_a,          s390_vselb,         0,                  0,                  BT_OV_UV16QI_UV16QI_UV16QI_UV16QI)
+OB_DEF_VAR (s390_vec_sel_u8_b,          s390_vselb,         0,                  0,                  BT_OV_UV16QI_UV16QI_UV16QI_BV16QI)
+OB_DEF_VAR (s390_vec_sel_b16_a,         s390_vselh,         0,                  0,                  BT_OV_BV8HI_BV8HI_BV8HI_UV8HI)
+OB_DEF_VAR (s390_vec_sel_b16_b,         s390_vselh,         0,                  0,                  BT_OV_BV8HI_BV8HI_BV8HI_BV8HI)
+OB_DEF_VAR (s390_vec_sel_s16_a,         s390_vselh,         0,                  0,                  BT_OV_V8HI_V8HI_V8HI_UV8HI)
+OB_DEF_VAR (s390_vec_sel_s16_b,         s390_vselh,         0,                  0,                  BT_OV_V8HI_V8HI_V8HI_BV8HI)
+OB_DEF_VAR (s390_vec_sel_u16_a,         s390_vselh,         0,                  0,                  BT_OV_UV8HI_UV8HI_UV8HI_UV8HI)
+OB_DEF_VAR (s390_vec_sel_u16_b,         s390_vselh,         0,                  0,                  BT_OV_UV8HI_UV8HI_UV8HI_BV8HI)
+OB_DEF_VAR (s390_vec_sel_b32_a,         s390_vself,         0,                  0,                  BT_OV_BV4SI_BV4SI_BV4SI_UV4SI)
+OB_DEF_VAR (s390_vec_sel_b32_b,         s390_vself,         0,                  0,                  BT_OV_BV4SI_BV4SI_BV4SI_BV4SI)
+OB_DEF_VAR (s390_vec_sel_s32_a,         s390_vself,         0,                  0,                  BT_OV_V4SI_V4SI_V4SI_UV4SI)
+OB_DEF_VAR (s390_vec_sel_s32_b,         s390_vself,         0,                  0,                  BT_OV_V4SI_V4SI_V4SI_BV4SI)
+OB_DEF_VAR (s390_vec_sel_u32_a,         s390_vself,         0,                  0,                  BT_OV_UV4SI_UV4SI_UV4SI_UV4SI)
+OB_DEF_VAR (s390_vec_sel_u32_b,         s390_vself,         0,                  0,                  BT_OV_UV4SI_UV4SI_UV4SI_BV4SI)
+OB_DEF_VAR (s390_vec_sel_b64_a,         s390_vselg,         0,                  0,                  BT_OV_BV2DI_BV2DI_BV2DI_UV2DI)
+OB_DEF_VAR (s390_vec_sel_b64_b,         s390_vselg,         0,                  0,                  BT_OV_BV2DI_BV2DI_BV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_sel_s64_a,         s390_vselg,         0,                  0,                  BT_OV_V2DI_V2DI_V2DI_UV2DI)
+OB_DEF_VAR (s390_vec_sel_s64_b,         s390_vselg,         0,                  0,                  BT_OV_V2DI_V2DI_V2DI_BV2DI)
+OB_DEF_VAR (s390_vec_sel_u64_a,         s390_vselg,         0,                  0,                  BT_OV_UV2DI_UV2DI_UV2DI_UV2DI)
+OB_DEF_VAR (s390_vec_sel_u64_b,         s390_vselg,         0,                  0,                  BT_OV_UV2DI_UV2DI_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_sel_flt_a,         s390_vself_flt,     B_VXE,              0,                  BT_OV_V4SF_V4SF_V4SF_UV4SI)
+OB_DEF_VAR (s390_vec_sel_flt_b,         s390_vself_flt,     B_VXE,              0,                  BT_OV_V4SF_V4SF_V4SF_BV4SI)
+OB_DEF_VAR (s390_vec_sel_dbl_a,         s390_vselg_dbl,     0,                  0,                  BT_OV_V2DF_V2DF_V2DF_UV2DI)
+OB_DEF_VAR (s390_vec_sel_dbl_b,         s390_vselg_dbl,     0,                  0,                  BT_OV_V2DF_V2DF_V2DF_BV2DI)
+
+B_DEF      (s390_vselb,                 vselv16qi,          0,                  B_VX,               0,                  BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
+B_DEF      (s390_vselh,                 vselv8hi,           0,                  B_VX,               0,                  BT_FN_UV8HI_UV8HI_UV8HI_UV8HI)
+B_DEF      (s390_vself,                 vselv4si,           0,                  B_VX,               0,                  BT_FN_UV4SI_UV4SI_UV4SI_UV4SI)
+B_DEF      (s390_vselg,                 vselv2di,           0,                  B_VX,               0,                  BT_FN_UV2DI_UV2DI_UV2DI_UV2DI)
+B_DEF      (s390_vself_flt,             vselv4sf,           0,                  B_VXE,              0,                  BT_FN_V4SF_V4SF_V4SF_UV4SI)
+B_DEF      (s390_vselg_dbl,             vselv2df,           0,                  B_VX,               0,                  BT_FN_V2DF_V2DF_V2DF_UV2DI)
 
 OB_DEF     (s390_vec_extend_s64,        s390_vec_extend_s64_s8,s390_vec_extend_s64_s32,B_VX,        BT_FN_OV4SI_OV4SI)
 OB_DEF_VAR (s390_vec_extend_s64_s8,     s390_vsegb,         0,                  0,                  BT_OV_V2DI_V16QI)
diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index 37a64ab58f9..210cfdbaba2 100644
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -487,23 +487,22 @@
 
 ; Vector select
 
-; Operand 3 selects bits from either OP1 (0) or OP2 (1)
+; for all b in bits op0[b] = op3[b] == 0 ? op2[b] : op1[b]
+; implemented as: op0 = (op1 & op3) | (op2 & ~op3)
 
-; Comparison operator should not matter as long as we always use the same ?!
+; Used to expand the vec_sel builtin. Operands op1 and op2 already got
+; swapped in s390-c.c when we get here.
 
-; Operands 1 and 2 are swapped in order to match the altivec builtin.
-; If operand 3 is a const_int bitmask this would be vec_merge
-(define_expand "vec_sel<mode>"
-  [(set (match_operand:V_HW 0 "register_operand" "")
-	(if_then_else:V_HW
-	 (eq (match_operand:<tointvec> 3 "register_operand"  "")
-	     (match_dup 4))
-	 (match_operand:V_HW 2 "register_operand"  "")
-	 (match_operand:V_HW 1 "register_operand"  "")))]
+(define_insn "vsel<mode>"
+  [(set (match_operand:V_HW                      0 "register_operand" "=v")
+	(ior:V_HW
+	 (and:V_HW (match_operand:V_HW           1 "register_operand"  "v")
+		   (match_operand:V_HW           3 "register_operand"  "v"))
+	 (and:V_HW (not:V_HW (match_dup 3))
+		   (match_operand:V_HW           2 "register_operand"  "v"))))]
   "TARGET_VX"
-{
-  operands[4] = CONST0_RTX (<tointvec>mode);
-})
+  "vsel\t%v0,%1,%2,%3"
+  [(set_attr "op_type" "VRR")])
 
 
 ; Vector sign extend to doubleword
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 758c191cd7e..63131c29a50 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	Backport from mainline
+	2020-04-20  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	PR target/94613
+	* gcc.target/s390/zvector/pr94613.c: New test.
+	* gcc.target/s390/zvector/vec_sel-1.c: New test.
+
 2020-05-01  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	PR fortran/93956
diff --git a/gcc/testsuite/gcc.target/s390/zvector/pr94613.c b/gcc/testsuite/gcc.target/s390/zvector/pr94613.c
new file mode 100644
index 00000000000..c3581d82ede
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/zvector/pr94613.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target s390_vx } */
+/* { dg-options "-O3 -mzarch -march=z13 -mzvector -std=gnu99 --save-temps" } */
+
+#include <vecintrin.h>
+
+/* The initial implementation of vec_sel used an IF_THEN_ELSE rtx.
+   This did NOT match what the vsel instruction does.  vsel is a
+   bit-wise operation.  Using IF_THEN_ELSE made the + operation to be
+   simplified away in combine.  A plus operation affects other bits in
+   the same element. Hence per-element simplifications are wrong for
+   vsel.  */
+vector unsigned char __attribute__((noinline))
+foo (vector unsigned char a, vector unsigned char b, vector unsigned char c)
+{
+  return vec_sel (a + b, c, a);
+}
+
+/* FIXME: The OR operation still should be optimized away in that case.  */
+vector unsigned char __attribute__((noinline))
+bar (vector unsigned char a, vector unsigned char b, vector unsigned char c)
+{
+  return vec_sel (a | b, c, a);
+}
+
+int
+main ()
+{
+  vector unsigned char v = (vector unsigned char){ 1 };
+
+  if (foo (v, v, v)[0] != 3)
+      __builtin_abort ();
+
+  if (bar (v, v, v)[0] != 1)
+    __builtin_abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec_sel-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec_sel-1.c
new file mode 100644
index 00000000000..d310f70d3a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/zvector/vec_sel-1.c
@@ -0,0 +1,211 @@
+/* { dg-do run } */
+/* { dg-require-effective-target s390_vxe } */
+/* { dg-options "-O3 -mzarch -march=z14 -mzvector --save-temps -Wno-attributes" } */
+
+#include <string.h>
+#include <vecintrin.h>
+
+typedef vector signed char v16qi;
+typedef vector unsigned char uv16qi;
+typedef vector bool char bv16qi;
+
+typedef vector signed short int v8hi;
+typedef vector unsigned short int uv8hi;
+typedef vector bool short int bv8hi;
+
+typedef vector signed int v4si;
+typedef vector unsigned int uv4si;
+typedef vector bool int bv4si;
+
+typedef vector signed long long v2di;
+typedef vector unsigned long long uv2di;
+typedef vector bool long long bv2di;
+
+typedef vector float v4sf;
+typedef vector double v2df;
+
+#define NUM_CONSTS 8
+
+const v16qi v16qi_vals[NUM_CONSTS] =
+  { (v16qi){ 1 },
+    (v16qi){ 2 },
+    (v16qi){ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 },
+    (v16qi){ 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2 },
+    (v16qi){ -1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 },
+    (v16qi){ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },
+    (v16qi){ 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 },
+    (v16qi){ 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1 }
+  };
+
+const v8hi v8hi_vals[NUM_CONSTS] =
+  { (v8hi){ 1 },
+    (v8hi){ 2 },
+    (v8hi){ 1,1,1,1,1,1,1,1 },
+    (v8hi){ 2,2,2,2,2,2,2,2 },
+    (v8hi){ -1,-1,-1,-1,-1,-1,-1,-1 },
+    (v8hi){ 0,0,0,0,0,0,0,0 },
+    (v8hi){ 1,2,3,4,5,6,7,8 },
+    (v8hi){ 8,7,6,5,4,3,2,1 }
+  };
+
+const v4si v4si_vals[NUM_CONSTS] =
+  { (v4si){ 1 },
+    (v4si){ 2 },
+    (v4si){ 1,1,1,1 },
+    (v4si){ 2,2,2,2 },
+    (v4si){ -1,-1,-1,-1 },
+    (v4si){ 0,0,0,0 },
+    (v4si){ 1,2,3,4 },
+    (v4si){ 4,3,2,1 }
+  };
+
+const v2di v2di_vals[NUM_CONSTS] =
+  { (v2di){ 1 },
+    (v2di){ 2 },
+    (v2di){ 1,1 },
+    (v2di){ 2,2 },
+    (v2di){ -1,-1 },
+    (v2di){ 0,0 },
+    (v2di){ 1,2 },
+    (v2di){ 2,1 }
+  };
+
+const v4sf v4sf_vals[NUM_CONSTS] =
+  { (v4sf){ 1.0f },
+    (v4sf){ 2.0f },
+    (v4sf){ 1.0f,1.0f,1.0f,1.0f },
+    (v4sf){ 2.0f,2.0f,2.0f,2.0f },
+    (v4sf){ -1.0f,-1.0f,-1.0f,-1.0f },
+    (v4sf){ 0.0f,0.0f,0.0f,0.0f },
+    (v4sf){ 1.1f,2.1f,3.1f,4.1f },
+    (v4sf){ 4.1f,3.1f,2.1f,1.1f }
+  };
+
+const v2df v2df_vals[NUM_CONSTS] =
+  { (v2df){ 1.0 },
+    (v2df){ 2.0 },
+    (v2df){ 1.0,1.0 },
+    (v2df){ 2.0,2.0 },
+    (v2df){ -1.0,-1.0 },
+    (v2df){ 0.0,0.0 },
+    (v2df){ 1.1,2.1 },
+    (v2df){ 2.1,1.1 }
+  };
+
+/* Each bit of the result vector has the value of the corresponding
+   bit of A if the corresponding bit of C is 0, or the value of the
+   corresponding bit of B otherwise.  */
+void __attribute__((noinline, noclone, target ("arch=zEC12")))
+emul (unsigned char *result, unsigned char *a,
+      unsigned char *b, unsigned char *c)
+{
+  for (int i = 0; i < 16; i++)
+    result[i] = (a[i] & ~c[i]) | (b[i] & c[i]);
+}
+
+#define GENFUNC(NAME, T1, T2)						\
+  T1 __attribute__((noinline, noclone))					\
+  NAME##_reg (T1 a, T1 b, T2 c) { return vec_sel (a, b, c); }		\
+  void __attribute__((noinline, noclone))				\
+  NAME##_mem (T1 *a, T1 *b, T2 *c, T1 *out) { *out = vec_sel (*a, *b, *c); } \
+  T1 __attribute__((always_inline))					\
+  NAME##_const (T1 a, T1 b, T2 c) { return vec_sel (a, b, c); }
+
+GENFUNC (vec_sel_b8_a, bv16qi, uv16qi)
+GENFUNC (vec_sel_b8_b, bv16qi, bv16qi)
+GENFUNC (vec_sel_s8_a,  v16qi, uv16qi)
+GENFUNC (vec_sel_s8_b,  v16qi, bv16qi)
+GENFUNC (vec_sel_u8_a, uv16qi, uv16qi)
+GENFUNC (vec_sel_u8_b, uv16qi, bv16qi)
+
+GENFUNC (vec_sel_b16_a, bv8hi, uv8hi)
+GENFUNC (vec_sel_b16_b, bv8hi, bv8hi)
+GENFUNC (vec_sel_s16_a,  v8hi, uv8hi)
+GENFUNC (vec_sel_s16_b,  v8hi, bv8hi)
+GENFUNC (vec_sel_u16_a, uv8hi, uv8hi)
+GENFUNC (vec_sel_u16_b, uv8hi, bv8hi)
+
+GENFUNC (vec_sel_b32_a, bv4si, uv4si)
+GENFUNC (vec_sel_b32_b, bv4si, bv4si)
+GENFUNC (vec_sel_s32_a,  v4si, uv4si)
+GENFUNC (vec_sel_s32_b,  v4si, bv4si)
+GENFUNC (vec_sel_u32_a, uv4si, uv4si)
+GENFUNC (vec_sel_u32_b, uv4si, bv4si)
+
+GENFUNC (vec_sel_b64_a, bv2di, uv2di)
+GENFUNC (vec_sel_b64_b, bv2di, bv2di)
+GENFUNC (vec_sel_s64_a,  v2di, uv2di)
+GENFUNC (vec_sel_s64_b,  v2di, bv2di)
+GENFUNC (vec_sel_u64_a, uv2di, uv2di)
+GENFUNC (vec_sel_u64_b, uv2di, bv2di)
+
+GENFUNC (vec_sel_flt_a,  v4sf, uv4si)
+GENFUNC (vec_sel_flt_b,  v4sf, bv4si)
+
+GENFUNC (vec_sel_dbl_a,  v2df, uv2di)
+GENFUNC (vec_sel_dbl_b,  v2df, bv2di)
+
+#define TESTFUNC(NAME, T1, T2, VAL_TYPE)				\
+  for (int i = 0; i < NUM_CONSTS; i++)					\
+    for (int j = 0; j < NUM_CONSTS; j++)				\
+      for (int k = 0; k < NUM_CONSTS; k++)				\
+	{								\
+	  unsigned char result[16];					\
+	  T1 in1 = (T1)VAL_TYPE##_vals[i];				\
+	  T1 in2 = (T1)VAL_TYPE##_vals[j];				\
+	  T2 in3 = (T2)VAL_TYPE##_vals[k];				\
+	  emul (result, (char*)&in1, (char*)&in2, (char*)&in3);		\
+									\
+	  T1 reg = NAME##_reg (in1, in2, in3);				\
+	  if (memcmp ((char*)&reg, result, 16) != 0)			\
+	    __builtin_abort ();						\
+									\
+	  T1 mem;							\
+	  NAME##_mem (&in1, &in2, &in3, &mem);				\
+	  if (memcmp ((char*)&mem, result, 16) != 0)			\
+	    __builtin_abort ();						\
+									\
+	  T1 cons = NAME##_const (in1, in2, in3);			\
+	  if (memcmp ((char*)&cons, result, 16) != 0)			\
+	    __builtin_abort ();						\
+	}
+
+int
+main ()
+{
+  TESTFUNC (vec_sel_b8_a, bv16qi, uv16qi, v16qi);
+  TESTFUNC (vec_sel_b8_b, bv16qi, bv16qi, v16qi);
+  TESTFUNC (vec_sel_s8_a,  v16qi, uv16qi, v16qi);
+  TESTFUNC (vec_sel_s8_b,  v16qi, bv16qi, v16qi);
+  TESTFUNC (vec_sel_u8_a, uv16qi, uv16qi, v16qi);
+  TESTFUNC (vec_sel_u8_b, uv16qi, bv16qi, v16qi);
+
+  TESTFUNC (vec_sel_b16_a, bv8hi, uv8hi, v8hi);
+  TESTFUNC (vec_sel_b16_b, bv8hi, bv8hi, v8hi);
+  TESTFUNC (vec_sel_s16_a,  v8hi, uv8hi, v8hi);
+  TESTFUNC (vec_sel_s16_b,  v8hi, bv8hi, v8hi);
+  TESTFUNC (vec_sel_u16_a, uv8hi, uv8hi, v8hi);
+  TESTFUNC (vec_sel_u16_b, uv8hi, bv8hi, v8hi);
+
+  TESTFUNC (vec_sel_b32_a, bv4si, uv4si, v4si);
+  TESTFUNC (vec_sel_b32_b, bv4si, bv4si, v4si);
+  TESTFUNC (vec_sel_s32_a,  v4si, uv4si, v4si);
+  TESTFUNC (vec_sel_s32_b,  v4si, bv4si, v4si);
+  TESTFUNC (vec_sel_u32_a, uv4si, uv4si, v4si);
+  TESTFUNC (vec_sel_u32_b, uv4si, bv4si, v4si);
+
+  TESTFUNC (vec_sel_b64_a, bv2di, uv2di, v2di);
+  TESTFUNC (vec_sel_b64_b, bv2di, bv2di, v2di);
+  TESTFUNC (vec_sel_s64_a,  v2di, uv2di, v2di);
+  TESTFUNC (vec_sel_s64_b,  v2di, bv2di, v2di);
+  TESTFUNC (vec_sel_u64_a, uv2di, uv2di, v2di);
+  TESTFUNC (vec_sel_u64_b, uv2di, bv2di, v2di);
+
+  TESTFUNC (vec_sel_flt_a,  v4sf, uv4si, v4sf);
+  TESTFUNC (vec_sel_flt_b,  v4sf, bv4si, v4sf);
+
+  TESTFUNC (vec_sel_dbl_a,  v2df, uv2di, v2df);
+  TESTFUNC (vec_sel_dbl_b,  v2df, bv2di, v2df);
+}
+
+/* { dg-final { scan-assembler {\n\tvsel\t} } } */

commit 2c7bab44f1e080a58bb09c5dd72e9f18e7b50cd7
Author: Andreas Krebbel <krebbel@linux.ibm.com>
Date:   Mon May 4 10:43:02 2020 +0200

    S/390: Fix PR94666
    
    The vector popcount expanders use a hardcoded subreg.  This might lead
    to double subregs being generated which then fail to match.  With this
    patch simplify_gen_subreg is used instead to fold the subregs.
    
    gcc/ChangeLog:
    
    2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
    
            Backport from mainline
            2020-04-20  Andreas Krebbel  <krebbel@linux.ibm.com>
    
            * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
            ("popcountv2di2_vx"): Use simplify_gen_subreg.
    
    gcc/testsuite/ChangeLog:
    
    2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
    
            Backport from mainline
            2020-04-20  Andreas Krebbel  <krebbel@linux.ibm.com>
    
            * g++.dg/pr94666.C: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bcfbba96124..36bda7eeb00 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	Backport from mainline
+	2020-04-20  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	* config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
+	("popcountv2di2_vx"): Use simplify_gen_subreg.
+
 2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
 
 	Backport from mainline
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index f11ca85ad97..24b200e0c57 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -818,7 +818,7 @@
 
 (define_expand "popcountv8hi2_vx"
   [(set (match_dup 2)
-	(unspec:V16QI [(subreg:V16QI (match_operand:V8HI 1 "register_operand" "v") 0)]
+	(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")]
 		      UNSPEC_POPCNT))
    ; Make a copy of the result
    (set (match_dup 3) (match_dup 2))
@@ -850,6 +850,8 @@
 ]
   "TARGET_VX && !TARGET_VXE"
 {
+  operands[1] = simplify_gen_subreg (V16QImode, operands[1],
+				     V8HImode, 0);
   operands[2] = gen_reg_rtx (V16QImode);
   operands[3] = gen_reg_rtx (V16QImode);
   operands[4] = gen_reg_rtx (V16QImode);
@@ -858,20 +860,21 @@
 
 (define_expand "popcountv4si2_vx"
   [(set (match_dup 2)
-	(unspec:V16QI [(subreg:V16QI (match_operand:V4SI 1 "register_operand" "v") 0)]
+	(unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")]
 		      UNSPEC_POPCNT))
    (set (match_operand:V4SI 0 "register_operand" "=v")
 	(unspec:V4SI [(match_dup 2) (match_dup 3)]
 		     UNSPEC_VEC_VSUM))]
   "TARGET_VX && !TARGET_VXE"
 {
+  operands[1] = simplify_gen_subreg (V16QImode, operands[1], V4SImode, 0);
   operands[2] = gen_reg_rtx (V16QImode);
   operands[3] = force_reg (V16QImode, CONST0_RTX (V16QImode));
 })
 
 (define_expand "popcountv2di2_vx"
   [(set (match_dup 2)
-	(unspec:V16QI [(subreg:V16QI (match_operand:V2DI 1 "register_operand" "v") 0)]
+	(unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v")]
 		      UNSPEC_POPCNT))
    (set (match_dup 3)
 	(unspec:V4SI [(match_dup 2) (match_dup 4)]
@@ -881,6 +884,7 @@
 		     UNSPEC_VEC_VSUMG))]
   "TARGET_VX && !TARGET_VXE"
 {
+  operands[1] = simplify_gen_subreg (V16QImode, operands[1], V2DImode, 0);
   operands[2] = gen_reg_rtx (V16QImode);
   operands[3] = gen_reg_rtx (V4SImode);
   operands[4] = force_reg (V16QImode, CONST0_RTX (V16QImode));
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 63131c29a50..8060e2e8fc8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	Backport from mainline
+	2020-04-20  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	* g++.dg/pr94666.C: New test.
+
 2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
 
 	Backport from mainline
diff --git a/gcc/testsuite/g++.dg/pr94666.C b/gcc/testsuite/g++.dg/pr94666.C
new file mode 100644
index 00000000000..a9bfb24f795
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr94666.C
@@ -0,0 +1,20 @@
+// { dg-do compile }
+// { dg-options "-O3" }
+// { dg-additional-options "-march=z13" { target s390*-*-* } }
+
+int a, c;
+struct A {
+  int e() {
+    int f;
+    for (int b = 0; b < 4; b++) {
+      a = __builtin_popcountl(d[b]);
+      f += a;
+    }
+    return f;
+  }
+  long d[4];
+} * g;
+void h() {
+  for (int b; b; b++)
+    c += g[b].e();
+}

commit 386f23b84aafbdb43701b5a50ebe2dc1f4e6201f
Author: Bin Cheng <bin.cheng@linux.alibaba.com>
Date:   Mon May 4 16:56:34 2020 +0800

    Add unsigned type iv_cand for iv_use with non mode-precision type
    
    Precisely,  for iv_use if it's not integer/pointer type, or non-mode
    precision type, add candidate for the corresponding scev in unsigned
    type with the same precision, rather than its original type.
    
    Backport from master.
    2020-04-09  Bin Cheng  <bin.cheng@linux.alibaba.com>
        PR tree-optimization/93674
    
    gcc/
        * tree-ssa-loop-ivopts.c (langhooks.h): New include.
        (add_iv_candidate_for_use): For iv_use of non integer or pointer type,
        or non-mode precision type, add candidate in unsigned type with the
        same precision.
    
    gcc/testsuite/
        * g++.dg/pr93674.C: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 36bda7eeb00..50fd225dea6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-05-04  Bin Cheng  <bin.cheng@linux.alibaba.com>
+
+	PR tree-optimization/93674
+	Backport from master
+	2020-04-09  Bin Cheng  <bin.cheng@linux.alibaba.com>
+
+	* tree-ssa-loop-ivopts.c (langhooks.h): New include.
+	(add_iv_candidate_for_use): For iv_use of non integer or pointer type,
+	or non-mode precision type, add candidate in unsigned type with the
+	same precision.
+
 2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
 
 	Backport from mainline
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8060e2e8fc8..88c74e6fc15 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-05-04  Bin Cheng  <bin.cheng@linux.alibaba.com>
+
+	PR tree-optimization/93674
+	Backport from master
+	2020-04-09  Bin Cheng  <bin.cheng@linux.alibaba.com>
+
+	* g++.dg/pr93674.C: New test.
+
 2020-05-04  Andreas Krebbel  <krebbel@linux.ibm.com>
 
 	Backport from mainline
diff --git a/gcc/testsuite/g++.dg/pr93674.C b/gcc/testsuite/g++.dg/pr93674.C
new file mode 100644
index 00000000000..8c59f1b0079
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr93674.C
@@ -0,0 +1,16 @@
+// { dg-do compile }
+// { dg-options "-O3 -std=c++14 -fstrict-enums -pedantic -fdump-tree-optimized" }
+enum some_enum { x = 1000 };
+void sink(some_enum);
+
+int __attribute__((noinline)) func() {
+  int sum = 0;
+  for (int i = 0; i < 3; ++i) {
+      for (int j = 3; j >= 0; --j) {
+          sink((some_enum)(i + j));
+      }
+  }
+  return sum;
+}
+
+// { dg-final { scan-tree-dump-not "some_enum ivtmp" "optimized" } }
diff --git a/gcc/tree-ssa-loop-ivopts.c b/gcc/tree-ssa-loop-ivopts.c
index a61e5f3b43e..a976a12205f 100644
--- a/gcc/tree-ssa-loop-ivopts.c
+++ b/gcc/tree-ssa-loop-ivopts.c
@@ -109,6 +109,9 @@ along with GCC; see the file COPYING3.  If not see
 #include "builtins.h"
 #include "tree-vectorizer.h"
 
+/* For lang_hooks.types.type_for_mode.  */
+#include "langhooks.h"
+
 /* FIXME: Expressions are expanded to RTL in this pass to determine the
    cost of different addressing modes.  This should be moved to a TBD
    interface between the GIMPLE and RTL worlds.  */
@@ -3476,8 +3479,21 @@ add_iv_candidate_for_use (struct ivopts_data *data, struct iv_use *use)
 {
   poly_uint64 offset;
   tree base;
-  tree basetype;
   struct iv *iv = use->iv;
+  tree basetype = TREE_TYPE (iv->base);
+
+  /* Don't add candidate for iv_use with non integer, pointer or non-mode
+     precision types, instead, add candidate for the corresponding scev in
+     unsigned type with the same precision.  See PR93674 for more info.  */
+  if ((TREE_CODE (basetype) != INTEGER_TYPE && !POINTER_TYPE_P (basetype))
+      || !type_has_mode_precision_p (basetype))
+    {
+      basetype = lang_hooks.types.type_for_mode (TYPE_MODE (basetype),
+						 TYPE_UNSIGNED (basetype));
+      add_candidate (data, fold_convert (basetype, iv->base),
+		     fold_convert (basetype, iv->step), false, NULL);
+      return;
+    }
 
   add_candidate (data, iv->base, iv->step, false, use);
 

commit f6965321b1c00bfb2b9c8407df56bcf38f096088
Author: Marek Polacek <polacek@redhat.com>
Date:   Mon May 4 13:25:42 2020 -0400

    c++: Bogus error with alignof [PR90736]
    
            PR c++/90736 - bogus error with alignof.
            * constexpr.c (adjust_temp_type): Use cv_unqualified type.

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index d1d829a8bca..ebebbe29e38 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,11 @@
+2020-05-04  Marek Polacek  <polacek@redhat.com>
+
+	Backported from mainline
+	2019-06-12  Marek Polacek  <polacek@redhat.com>
+
+	PR c++/90736 - bogus error with alignof.
+	* constexpr.c (adjust_temp_type): Use cv_unqualified type.
+
 2020-04-04  Jason Merrill  <jason@redhat.com>
 
 	PR c++/91377
diff --git a/gcc/cp/constexpr.c b/gcc/cp/constexpr.c
index bebe72e4db9..f68ad758a14 100644
--- a/gcc/cp/constexpr.c
+++ b/gcc/cp/constexpr.c
@@ -1255,7 +1255,9 @@ adjust_temp_type (tree type, tree temp)
   if (TREE_CODE (temp) == EMPTY_CLASS_EXPR)
     return build0 (EMPTY_CLASS_EXPR, type);
   gcc_assert (scalarish_type_p (type));
-  return cp_fold_convert (type, temp);
+  /* Now we know we're dealing with a scalar, and a prvalue of non-class
+     type is cv-unqualified.  */
+  return cp_fold_convert (cv_unqualified (type), temp);
 }
 
 /* Callback for walk_tree used by unshare_constructor.  */
diff --git a/gcc/testsuite/g++.dg/cpp0x/alignof5.C b/gcc/testsuite/g++.dg/cpp0x/alignof5.C
new file mode 100644
index 00000000000..09354d3e1d0
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/alignof5.C
@@ -0,0 +1,6 @@
+// PR c++/90736 - bogus error with alignof.
+// { dg-do compile { target c++11 } }
+
+constexpr int fn(const int b) { return b; }
+constexpr int c = fn(alignof(int));
+alignas(c) char d;

commit 4b0a1274faa64cbbe3c3b5db1129b3d2b3b530bb
Author: Eric Botcazou <ebotcazou@gcc.gnu.org>
Date:   Mon May 4 23:32:39 2020 +0200

    Fix Ada bootstrap on Cygwin64
    
    This fixes a compilation error preventing bootstrap with Ada
    on x86_64-pc-cygwin.
    
    2020-05-04  Mikael Pettersson  <mikpelinux@gmail.com>
    
            PR bootstrap/94918
            * mingw32.h: Prevent windows.h from including emmintrin.h on Cygw64.

diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index cb4bdaf32cb..2718106f024 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,8 @@
+2020-05-04  Mikael Pettersson  <mikpelinux@gmail.com>
+
+	PR bootstrap/94918
+	* mingw32.h: Prevent windows.h from including emmintrin.h on Cygwin64.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/gcc/ada/mingw32.h b/gcc/ada/mingw32.h
index 7fad146a9e3..438fb31602d 100644
--- a/gcc/ada/mingw32.h
+++ b/gcc/ada/mingw32.h
@@ -56,6 +56,7 @@
 /* Note: windows.h on cygwin-64 includes x86intrin.h which uses malloc.
    That fails to compile, if malloc is poisoned, i.e. if !IN_RTS.  */
 #define _X86INTRIN_H_INCLUDED
+#define _EMMINTRIN_H_INCLUDED
 #endif
 #include <windows.h>
 

commit afd6cb78ec214fd6eeaf3ea33c1b937609cafe0a
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Mon May 4 22:54:25 2020 +0100

    libstdc++: Fix broken link to SGI STL FAQ
    
    The previous URL to an entry in the wayback machine now redirects to a
    page saying "SGI.com Tech Archive Resources now retired" so use an older
    entry from the archive.
    
            * doc/xml/faq.xml: Use working link for SGI STL FAQ.
            * doc/html/*: Regenerate.

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 8d3f7f9b185..30b1561b954 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,8 @@
+2020-05-04  Jonathan Wakely  <jwakely@redhat.com>
+
+	* doc/xml/faq.xml: Use working link for SGI STL FAQ.
+	* doc/html/*: Regenerate.
+
 2020-04-21  Jonathan Wakely  <jwakely@redhat.com>
 
 	* doc/xml/manual/status_cxx2017.xml: Fix name of feature test macro.
diff --git a/libstdc++-v3/doc/html/faq.html b/libstdc++-v3/doc/html/faq.html
index ac99835acf2..18407225d7a 100644
--- a/libstdc++-v3/doc/html/faq.html
+++ b/libstdc++-v3/doc/html/faq.html
@@ -194,7 +194,7 @@
     information is available on the homepage (including how to browse
     the list archives); to send a message to the list,
     use <code class="email">&lt;<a class="email" href="mailto:libstdc++@gcc.gnu.org">libstdc++@gcc.gnu.org</a>&gt;</code>.
-    </p><p> 
+    </p><p>
     If you have a question that you think should be included
     here, or if you have a question <span class="emphasis"><em>about</em></span> a question/answer
     here, please send email to the libstdc++ mailing list, as above.
@@ -246,8 +246,8 @@
     development tools. It may be necessary to install extra
     development packages to get the headers, or the documentation, or
     the source: please consult your vendor for details.
-    </p><p> 
-    To build and install from the GNU GCC sources, please consult the 
+    </p><p>
+    To build and install from the GNU GCC sources, please consult the
     <a class="link" href="manual/setup.html" title="Chapter 2. Setup">setup
     documentation</a> for detailed
     instructions. You may wish to browse those files ahead
@@ -268,7 +268,7 @@
     </p></td></tr><tr class="answer"><td align="left" valign="top"><a id="a-how_to_test"></a></td><td align="left" valign="top"><p>
     Libstdc++ comes with its own validation testsuite, which includes
     conformance testing, regression testing, ABI testing, and
-    performance testing. Please consult the 
+    performance testing. Please consult the
     <a class="link" href="http://gcc.gnu.org/install/test.html" target="_top">testing
     documentation</a> for GCC and
     <a class="link" href="manual/test.html" title="Testing">Testing</a> in the libstdc++
@@ -424,12 +424,12 @@
     </p></td></tr><tr class="answer"><td align="left" valign="top"><a id="a-solaris_long_long"></a></td><td align="left" valign="top"><div class="note" style="margin-left: 0.5in; margin-right: 0.5in;"><h3 class="title">Note</h3><p>This answer is old and probably no longer be relevant.</p></div><p>
     By default we try to support the C99 <span class="type">long long</span> type.
     This requires that certain functions from your C library be present.
-    </p><p> 
+    </p><p>
     Up through release 3.0.2 the platform-specific tests performed by
     libstdc++ were too general, resulting in a conservative approach
     to enabling the <span class="type">long long</span> code paths. The most
     commonly reported platform affected was Solaris.
-    </p><p> 
+    </p><p>
     This has been fixed for libstdc++ releases greater than 3.0.3.
     </p></td></tr><tr class="question"><td align="left" valign="top"><a id="faq.predefined"></a><a id="q-predefined"></a><p><strong>4.3.</strong></p></td><td align="left" valign="top"><p>
       <code class="constant">_XOPEN_SOURCE</code> and <code class="constant">_GNU_SOURCE</code> are always defined?
@@ -484,7 +484,7 @@
     and later.  A patch went in just after the 3.3 release to
     make mips* use the generic implementation instead.  You can also
     configure for mipsel-elf as a workaround.
-    </p><p>    
+    </p><p>
     The mips*-*-linux* port continues to use the MIPS II routines, and more
     work in this area is expected.
     </p></td></tr><tr class="question"><td align="left" valign="top"><a id="faq.linux_glibc"></a><a id="q-linux_glibc"></a><p><strong>4.7.</strong></p></td><td align="left" valign="top"><p>
@@ -510,7 +510,7 @@
     enable <span class="type">wchar_t</span> and C++ library structures
     like <code class="classname">wstring</code> were present. This impacted Solaris,
     Darwin, and BSD variants, and is fixed in libstdc++ versions post 4.1.0.
-    </p><p> 
+    </p><p>
     </p></td></tr><tr class="toc"><td align="left" valign="top" colspan="2"><dl><dt>5.1. <a href="faq.html#faq.what_works">
       What works already?
     </a></dt><dt>5.2. <a href="faq.html#faq.standard_bugs">
@@ -526,8 +526,8 @@
     platforms. Also dependent on the underlying platform is support
     for <span class="type">wchar_t</span> and <span class="type">long long</span> specializations,
     and details of thread support.
-    </p><p>    
-    Long answer: See the implementation status pages for 
+    </p><p>
+    Long answer: See the implementation status pages for
     <a class="link" href="manual/status.html#status.iso.1998" title="C++ 1998/2003">C++98</a>,
     <a class="link" href="manual/status.html#status.iso.tr1" title="C++ TR1">TR1</a>,
     <a class="link" href="manual/status.html#status.iso.2011" title="C++ 2011">C++11</a>,
@@ -536,7 +536,7 @@
     </p></td></tr><tr class="question"><td align="left" valign="top"><a id="faq.standard_bugs"></a><a id="q-standard_bugs"></a><p><strong>5.2.</strong></p></td><td align="left" valign="top"><p>
       Bugs in the ISO C++ language or library specification
     </p></td></tr><tr class="answer"><td align="left" valign="top"><a id="a-standard_bugs"></a></td><td align="left" valign="top"><p>
-    Unfortunately, there are some. 
+    Unfortunately, there are some.
     </p><p>
     For those people who are not part of the ISO Library Group
     (i.e., nearly all of us needing to read this page in the first
@@ -560,7 +560,7 @@
     or an older version of the GNU compilers. Third, you can find more
     information on the libstdc++ and the GCC mailing lists: search
     these lists with terms describing your issue.
-    </p><p> 
+    </p><p>
     Before reporting a bug, please examine the
     <a class="link" href="https://gcc.gnu.org/bugs/" target="_top">bugs database</a>, with the
     component set to <span class="quote">“<span class="quote">c++</span>”</span>.
@@ -813,7 +813,7 @@
     and <a class="link" href="manual/backwards.html" title="Backwards Compatibility">backwards
     compatibility</a> documentation.
     </p><p>
-    The <a class="link" href="https://web.archive.org/web/20171225062613/http://www.sgi.com/tech/stl/FAQ.html" target="_top">FAQ</a>
+    The <a class="link" href="https://web.archive.org/web/20171104092813/http://www.sgi.com/tech/stl/FAQ.html" target="_top">FAQ</a>
     for SGI's STL is still recommended reading.
     </p></td></tr><tr class="question"><td align="left" valign="top"><a id="faq.extensions_and_backwards_compat"></a><a id="q-extensions_and_backwards_compat"></a><p><strong>7.4.</strong></p></td><td align="left" valign="top"><p>
       Extensions and Backward Compatibility
diff --git a/libstdc++-v3/doc/xml/faq.xml b/libstdc++-v3/doc/xml/faq.xml
index aff6c8d6004..cf8684e1cea 100644
--- a/libstdc++-v3/doc/xml/faq.xml
+++ b/libstdc++-v3/doc/xml/faq.xml
@@ -2,9 +2,9 @@
 
 <article xml:id="faq" xreflabel="Frequently Asked Questions">
 <?dbhtml filename="faq.html"?>
- 
+
 <info><title>Frequently Asked Questions</title>
-  
+
   <copyright>
     <year>
       2008-2018
@@ -36,7 +36,7 @@
      exactly how far the project has come, or just want the latest
      bleeding-edge code, the up-to-date source can be cloned via
      <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="https://gcc.gnu.org/git.html">Git</link>.
-    </para> 
+    </para>
 
     <para>
     N.B. The library is called libstdc++ <emphasis>not</emphasis> stdlibc++.
@@ -58,7 +58,7 @@
     (as the Draft Standard used to say) <quote>incomplet and
     incorrekt</quote>, and many suffered from limitations of the compilers
     that used them.
-    </para> 
+    </para>
     <para>
     The GNU compiler collection
     (<command>gcc</command>, <command>g++</command>, etc) is widely
@@ -68,7 +68,7 @@
     the rapid development and near-legendary
     <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="https://gcc.gnu.org/buildstat.html">portability</link>
     that are the hallmarks of an open-source project are applied to libstdc++.
-    </para> 
+    </para>
     <para>
     All of the standard classes and functions from C++98/C++03, C++11 and C++14
     (such as <classname>string</classname>,
@@ -100,7 +100,7 @@
     archives, is open to everyone.  You can read instructions for
     doing so on the <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="https://gcc.gnu.org/lists.html">GCC mailing lists</link> page.
     If you have questions, ideas, code, or are just curious, sign up!
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -115,7 +115,7 @@
     Nathan Myers gave the best of all possible answers, responding to
     a Usenet article asking this question: <emphasis>Sooner, if you
     help.</emphasis>
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -135,7 +135,7 @@
     anybody who is willing to help write documentation, for example,
     or has found a bug in code that we all thought was working and is
     willing to provide details, is more than welcome!
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -152,7 +152,7 @@
     being developed.</quote>
     It should not be used for new projects, and won't even compile with
     recent releases of GCC (or most other C++ compilers).
-    </para> 
+    </para>
     <para>
     More information can be found in the
     <link linkend="manual.appendix.porting.backwards">Backwards
@@ -175,13 +175,13 @@
     information is available on the homepage (including how to browse
     the list archives); to send a message to the list,
     use <email>libstdc++@gcc.gnu.org</email>.
-    </para> 
+    </para>
 
-    <para> 
+    <para>
     If you have a question that you think should be included
     here, or if you have a question <emphasis>about</emphasis> a question/answer
     here, please send email to the libstdc++ mailing list, as above.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -201,7 +201,7 @@
     <para>
     See <link linkend="manual.intro.status.license">our license description</link>
     for these and related questions.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -215,7 +215,7 @@
     <para>
      No. The special exception permits use of the library in
      proprietary applications.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -235,7 +235,7 @@
      are expanded inside the code that uses the library.  So to allow people
      to replace the library code, someone using the library would have to
      distribute their own source, rendering the LGPL equivalent to the GPL.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -249,7 +249,7 @@
     <para>
       None.  We encourage such programs to be released as free software,
      but we won't punish you or sue you if you choose otherwise.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -271,14 +271,14 @@
     development tools. It may be necessary to install extra
     development packages to get the headers, or the documentation, or
     the source: please consult your vendor for details.
-    </para> 
-    <para> 
-    To build and install from the GNU GCC sources, please consult the 
+    </para>
+    <para>
+    To build and install from the GNU GCC sources, please consult the
     <link linkend="manual.intro.setup">setup
     documentation</link> for detailed
     instructions. You may wish to browse those files ahead
     of time to get a feel for what's required.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -313,12 +313,12 @@
     <para>
     Libstdc++ comes with its own validation testsuite, which includes
     conformance testing, regression testing, ABI testing, and
-    performance testing. Please consult the 
+    performance testing. Please consult the
     <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/install/test.html">testing
     documentation</link> for GCC and
     <link linkend="manual.intro.setup.test">Testing</link> in the libstdc++
     manual for more details.
-    </para> 
+    </para>
     <para>
     If you find bugs in the testsuite programs themselves, or if you
     think of a new test program that should be added to the suite,
@@ -432,7 +432,7 @@
       using anything from the rest of the library, such as IOStreams
       or vectors, then you'll still need pieces from
       <filename class="libraryfile">libstdc++.a</filename>.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -465,7 +465,7 @@
     is only possible to a certain extent; the object files in question contain
     template classes and template functions, pre-instantiated, and
     splitting those up causes severe maintenance headaches.
-    </para> 
+    </para>
     <para>
     On supported platforms, libstdc++ takes advantage of garbage
     collection in the GNU linker to get a result similar to separating
@@ -495,12 +495,12 @@
   <answer xml:id="a-other_compilers">
     <para>
     Perhaps.
-    </para> 
+    </para>
     <para>
     Since the goal of ISO Standardization is for all C++
     implementations to be able to share code, libstdc++ should be
     usable under any ISO-compliant compiler, at least in theory.
-    </para> 
+    </para>
     <para>
     However, the reality is that libstdc++ is targeted and optimized
     for GCC/G++. This means that often libstdc++ uses specific,
@@ -515,7 +515,7 @@
     been known to work with versions of the EDG C++ compiler, and
     vendor-specific proprietary C++ compilers such as the Intel ICC
     C++ compiler.
-    </para> 
+    </para>
 
   </answer>
 </qandaentry>
@@ -533,16 +533,16 @@
     <para>
     By default we try to support the C99 <type>long long</type> type.
     This requires that certain functions from your C library be present.
-    </para> 
-    <para> 
+    </para>
+    <para>
     Up through release 3.0.2 the platform-specific tests performed by
     libstdc++ were too general, resulting in a conservative approach
     to enabling the <type>long long</type> code paths. The most
     commonly reported platform affected was Solaris.
-    </para> 
-    <para> 
+    </para>
+    <para>
     This has been fixed for libstdc++ releases greater than 3.0.3.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -651,10 +651,10 @@
     make mips* use the generic implementation instead.  You can also
     configure for mipsel-elf as a workaround.
     </para>
-    <para>    
+    <para>
     The mips*-*-linux* port continues to use the MIPS II routines, and more
     work in this area is expected.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -700,9 +700,9 @@
     enable <type>wchar_t</type> and C++ library structures
     like <classname>wstring</classname> were present. This impacted Solaris,
     Darwin, and BSD variants, and is fixed in libstdc++ versions post 4.1.0.
-    </para> 
-    <para> 
-    </para> 
+    </para>
+    <para>
+    </para>
   </answer>
 </qandaentry>
 
@@ -728,14 +728,14 @@
     for <type>wchar_t</type> and <type>long long</type> specializations,
     and details of thread support.
     </para>
-    <para>    
-    Long answer: See the implementation status pages for 
+    <para>
+    Long answer: See the implementation status pages for
     <link linkend="status.iso.1998">C++98</link>,
     <link linkend="status.iso.tr1">TR1</link>,
     <link linkend="status.iso.2011">C++11</link>,
     <link linkend="status.iso.2014">C++14</link>, and
     <link linkend="status.iso.2017">C++17</link>.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -747,7 +747,7 @@
   </question>
   <answer xml:id="a-standard_bugs">
     <para>
-    Unfortunately, there are some. 
+    Unfortunately, there are some.
     </para>
     <para>
     For those people who are not part of the ISO Library Group
@@ -758,7 +758,7 @@
     website</link>.
     Many of these issues have resulted in
     <link linkend="manual.intro.status.bugs.iso">code changes in libstdc++</link>.
-    </para> 
+    </para>
     <para>
     If you think you've discovered a new bug that is not listed,
     please post a message describing your problem to the author of
@@ -784,12 +784,12 @@
     or an older version of the GNU compilers. Third, you can find more
     information on the libstdc++ and the GCC mailing lists: search
     these lists with terms describing your issue.
-    </para> 
-    <para> 
+    </para>
+    <para>
     Before reporting a bug, please examine the
     <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="https://gcc.gnu.org/bugs/">bugs database</link>, with the
     component set to <quote>c++</quote>.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -824,7 +824,7 @@
     fs.close();
     fs.open("a_new_file");
     </programlisting>
-    
+
     <para>
     All operations on the re-opened <varname>fs</varname> would fail, or at
     least act very strangely, especially if <varname>fs</varname> reached the
@@ -840,7 +840,7 @@
     of <link linkend="manual.bugs.dr409">DR #409</link> and
     <function>open()</function>
     now calls <function>clear()</function> on success.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -859,7 +859,7 @@
     necessarily trying to be OO. The option also enforces outdated guidelines
     from old editions of the books, and the advice isn't all relevant to
     modern C++ (especially C++11 and later).
-    </para> 
+    </para>
     <para>
     We do, however, try to have libstdc++ sources as clean as possible. If
     you see some simple changes that pacify <option>-Weffc++</option>
@@ -889,7 +889,7 @@
     <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/ml/libstdc++/2001-01/msg00247.html">sums
       things up here</link>.  The collisions with vector/string iterator
     types have been fixed for 3.1.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -947,7 +947,7 @@
     checks, is available in the
     <link linkend="std.diagnostics.concept_checking">Diagnostics</link>.
     chapter of the manual.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -1013,7 +1013,7 @@
     want to test the library for memory leaks please read
     <link linkend="debug.memory">Tips for memory leak hunting</link>
     first.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -1028,7 +1028,7 @@
     See
     the <link linkend="std.containers">Containers</link>
     chapter.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -1056,7 +1056,7 @@
     fixes.  Bugs have a way of being reintroduced; if an old bug
     creeps back in, it will be caught immediately by the testsuite -
     but only if such a test exists.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -1150,9 +1150,9 @@
     compatibility</link> documentation.
     </para>
     <para>
-    The <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="https://web.archive.org/web/20171225062613/http://www.sgi.com/tech/stl/FAQ.html">FAQ</link>
+    The <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="https://web.archive.org/web/20171104092813/http://www.sgi.com/tech/stl/FAQ.html">FAQ</link>
     for SGI's STL is still recommended reading.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -1165,7 +1165,7 @@
   <answer xml:id="a-extensions_and_backwards_compat">
     <para>
       See the <link linkend="manual.appendix.porting.backwards">link</link> on backwards compatibility and <link linkend="appendix.porting.api">link</link> on evolution.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -1206,7 +1206,7 @@
     <para>
     Please refer to the <link linkend="appendix.contrib">Contributing</link>
     section in our manual.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -1272,7 +1272,7 @@
     so they may later be changed.  Deciding which, and implementing
     the decisions, must happen before you can reasonably document a
     candidate C++ ABI that encompasses the standard library.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 
@@ -1302,7 +1302,7 @@
     <para>
     See <link linkend="strings.string.shrink">Shrink-to-fit
     strings</link> for a similar solution for strings.
-    </para> 
+    </para>
   </answer>
 </qandaentry>
 

commit 152e4526687b9913b7e4df656f00a05b5b4d9ecb
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue May 5 00:17:24 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e9c2b992a49..7eba2873492 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200504
+20200505

commit 6734f3c79656e16cea671f393434b90e3dabe9e0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed May 6 00:17:16 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7eba2873492..e48c8ef49f7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200505
+20200506

commit ce7eda645d20cde0eca901fc770446451b2ce7f8
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Wed May 6 11:16:16 2020 +0100

    libstdc++: Replace pre-release version number in docs
    
            * doc/xml/manual/abi.xml (abi.versioning.history): Update 8.0.0 to
            8.1.0 in list of versions.
            * doc/html/*: Regenerate.

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 30b1561b954..675ac448998 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,9 @@
+2020-05-06  Jonathan Wakely  <jwakely@redhat.com>
+
+	* doc/xml/manual/abi.xml (abi.versioning.history): Update 8.0.0 to
+	8.1.0 in list of versions.
+	* doc/html/*: Regenerate.
+
 2020-05-04  Jonathan Wakely  <jwakely@redhat.com>
 
 	* doc/xml/faq.xml: Use working link for SGI STL FAQ.
diff --git a/libstdc++-v3/doc/html/manual/abi.html b/libstdc++-v3/doc/html/manual/abi.html
index 16723dee1bb..7516618a31b 100644
--- a/libstdc++-v3/doc/html/manual/abi.html
+++ b/libstdc++-v3/doc/html/manual/abi.html
@@ -110,7 +110,7 @@ compatible.
 	has the same filename and <code class="constant">DT_SONAME</code> as the
 	preceding release.
       </p><p>It is versioned as follows:
-    </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: libstdc++.so.3.0.0</p></li><li class="listitem"><p>GCC 3.0.1: libstdc++.so.3.0.1</p></li><li class="listitem"><p>GCC 3.0.2: libstdc++.so.3.0.2</p></li><li class="listitem"><p>GCC 3.0.3: libstdc++.so.3.0.2 (See Note 1)</p></li><li class="listitem"><p>GCC 3.0.4: libstdc++.so.3.0.4</p></li><li class="listitem"><p>GCC 3.1.0: libstdc++.so.4.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.1.1: libstdc++.so.4.0.1</p></li><li class="listitem"><p>GCC 3.2.0: libstdc++.so.5.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.2.1: libstdc++.so.5.0.1</p></li><li class="listitem"><p>GCC 3.2.2: libstdc++.so.5.0.2</p></li><li class="listitem"><p>GCC 3.2.3: libstdc++.so.5.0.3 (See Note 2)</p></li><li class="listitem"><p>GCC 3.3.0: libstdc++.so.5.0.4</p></li><li class="listitem"><p>GCC 3.3.1: libstdc++.so.5.0.5</p></li><li class="listitem"><p>GCC 3.4.0: libstdc++.so.6.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.4.1: libstdc++.so.6.0.1</p></li><li class="listitem"><p>GCC 3.4.2: libstdc++.so.6.0.2</p></li><li class="listitem"><p>GCC 3.4.3: libstdc++.so.6.0.3</p></li><li class="listitem"><p>GCC 4.0.0: libstdc++.so.6.0.4</p></li><li class="listitem"><p>GCC 4.0.1: libstdc++.so.6.0.5</p></li><li class="listitem"><p>GCC 4.0.2: libstdc++.so.6.0.6</p></li><li class="listitem"><p>GCC 4.0.3: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.0: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.1: libstdc++.so.6.0.8</p></li><li class="listitem"><p>GCC 4.2.0: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.2.1: libstdc++.so.6.0.9 (See Note 3)</p></li><li class="listitem"><p>GCC 4.2.2: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.3.0: libstdc++.so.6.0.10</p></li><li class="listitem"><p>GCC 4.4.0: libstdc++.so.6.0.11</p></li><li class="listitem"><p>GCC 4.4.1: libstdc++.so.6.0.12</p></li><li class="listitem"><p>GCC 4.4.2: libstdc++.so.6.0.13</p></li><li class="listitem"><p>GCC 4.5.0: libstdc++.so.6.0.14</p></li><li class="listitem"><p>GCC 4.6.0: libstdc++.so.6.0.15</p></li><li class="listitem"><p>GCC 4.6.1: libstdc++.so.6.0.16</p></li><li class="listitem"><p>GCC 4.7.0: libstdc++.so.6.0.17</p></li><li class="listitem"><p>GCC 4.8.0: libstdc++.so.6.0.18</p></li><li class="listitem"><p>GCC 4.8.3: libstdc++.so.6.0.19</p></li><li class="listitem"><p>GCC 4.9.0: libstdc++.so.6.0.20</p></li><li class="listitem"><p>GCC 5.1.0: libstdc++.so.6.0.21</p></li><li class="listitem"><p>GCC 6.1.0: libstdc++.so.6.0.22</p></li><li class="listitem"><p>GCC 7.1.0: libstdc++.so.6.0.23</p></li><li class="listitem"><p>GCC 7.2.0: libstdc++.so.6.0.24</p></li><li class="listitem"><p>GCC 8.0.0: libstdc++.so.6.0.25</p></li></ul></div><p>
+    </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: libstdc++.so.3.0.0</p></li><li class="listitem"><p>GCC 3.0.1: libstdc++.so.3.0.1</p></li><li class="listitem"><p>GCC 3.0.2: libstdc++.so.3.0.2</p></li><li class="listitem"><p>GCC 3.0.3: libstdc++.so.3.0.2 (See Note 1)</p></li><li class="listitem"><p>GCC 3.0.4: libstdc++.so.3.0.4</p></li><li class="listitem"><p>GCC 3.1.0: libstdc++.so.4.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.1.1: libstdc++.so.4.0.1</p></li><li class="listitem"><p>GCC 3.2.0: libstdc++.so.5.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.2.1: libstdc++.so.5.0.1</p></li><li class="listitem"><p>GCC 3.2.2: libstdc++.so.5.0.2</p></li><li class="listitem"><p>GCC 3.2.3: libstdc++.so.5.0.3 (See Note 2)</p></li><li class="listitem"><p>GCC 3.3.0: libstdc++.so.5.0.4</p></li><li class="listitem"><p>GCC 3.3.1: libstdc++.so.5.0.5</p></li><li class="listitem"><p>GCC 3.4.0: libstdc++.so.6.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.4.1: libstdc++.so.6.0.1</p></li><li class="listitem"><p>GCC 3.4.2: libstdc++.so.6.0.2</p></li><li class="listitem"><p>GCC 3.4.3: libstdc++.so.6.0.3</p></li><li class="listitem"><p>GCC 4.0.0: libstdc++.so.6.0.4</p></li><li class="listitem"><p>GCC 4.0.1: libstdc++.so.6.0.5</p></li><li class="listitem"><p>GCC 4.0.2: libstdc++.so.6.0.6</p></li><li class="listitem"><p>GCC 4.0.3: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.0: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.1: libstdc++.so.6.0.8</p></li><li class="listitem"><p>GCC 4.2.0: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.2.1: libstdc++.so.6.0.9 (See Note 3)</p></li><li class="listitem"><p>GCC 4.2.2: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.3.0: libstdc++.so.6.0.10</p></li><li class="listitem"><p>GCC 4.4.0: libstdc++.so.6.0.11</p></li><li class="listitem"><p>GCC 4.4.1: libstdc++.so.6.0.12</p></li><li class="listitem"><p>GCC 4.4.2: libstdc++.so.6.0.13</p></li><li class="listitem"><p>GCC 4.5.0: libstdc++.so.6.0.14</p></li><li class="listitem"><p>GCC 4.6.0: libstdc++.so.6.0.15</p></li><li class="listitem"><p>GCC 4.6.1: libstdc++.so.6.0.16</p></li><li class="listitem"><p>GCC 4.7.0: libstdc++.so.6.0.17</p></li><li class="listitem"><p>GCC 4.8.0: libstdc++.so.6.0.18</p></li><li class="listitem"><p>GCC 4.8.3: libstdc++.so.6.0.19</p></li><li class="listitem"><p>GCC 4.9.0: libstdc++.so.6.0.20</p></li><li class="listitem"><p>GCC 5.1.0: libstdc++.so.6.0.21</p></li><li class="listitem"><p>GCC 6.1.0: libstdc++.so.6.0.22</p></li><li class="listitem"><p>GCC 7.1.0: libstdc++.so.6.0.23</p></li><li class="listitem"><p>GCC 7.2.0: libstdc++.so.6.0.24</p></li><li class="listitem"><p>GCC 8.1.0: libstdc++.so.6.0.25</p></li></ul></div><p>
       Note 1: Error should be libstdc++.so.3.0.3.
     </p><p>
       Note 2: Not strictly required.
@@ -128,7 +128,7 @@ compatible.
    GLIBCPP_3.2 for symbols that were introduced in the GCC 3.2.0
    release.) If a particular release is not listed, it has the same
    version labels as the preceding release.
-   </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.1: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.2: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.3: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.4: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.1.0: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.1.1: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.2.0: GLIBCPP_3.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.1: GLIBCPP_3.2.1, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.2: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.3: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.3.0: GLIBCPP_3.2.2, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.1: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.2: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.3: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.4.0: GLIBCXX_3.4, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.1: GLIBCXX_3.4.1, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.2: GLIBCXX_3.4.2</p></li><li class="listitem"><p>GCC 3.4.3: GLIBCXX_3.4.3</p></li><li class="listitem"><p>GCC 4.0.0: GLIBCXX_3.4.4, CXXABI_1.3.1</p></li><li class="listitem"><p>GCC 4.0.1: GLIBCXX_3.4.5</p></li><li class="listitem"><p>GCC 4.0.2: GLIBCXX_3.4.6</p></li><li class="listitem"><p>GCC 4.0.3: GLIBCXX_3.4.7</p></li><li class="listitem"><p>GCC 4.1.1: GLIBCXX_3.4.8</p></li><li class="listitem"><p>GCC 4.2.0: GLIBCXX_3.4.9</p></li><li class="listitem"><p>GCC 4.3.0: GLIBCXX_3.4.10, CXXABI_1.3.2</p></li><li class="listitem"><p>GCC 4.4.0: GLIBCXX_3.4.11, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.1: GLIBCXX_3.4.12, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.2: GLIBCXX_3.4.13, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.5.0: GLIBCXX_3.4.14, CXXABI_1.3.4</p></li><li class="listitem"><p>GCC 4.6.0: GLIBCXX_3.4.15, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.6.1: GLIBCXX_3.4.16, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.7.0: GLIBCXX_3.4.17, CXXABI_1.3.6</p></li><li class="listitem"><p>GCC 4.8.0: GLIBCXX_3.4.18, CXXABI_1.3.7</p></li><li class="listitem"><p>GCC 4.8.3: GLIBCXX_3.4.19, CXXABI_1.3.7</p></li><li class="listitem"><p>GCC 4.9.0: GLIBCXX_3.4.20, CXXABI_1.3.8</p></li><li class="listitem"><p>GCC 5.1.0: GLIBCXX_3.4.21, CXXABI_1.3.9</p></li><li class="listitem"><p>GCC 6.1.0: GLIBCXX_3.4.22, CXXABI_1.3.10</p></li><li class="listitem"><p>GCC 7.1.0: GLIBCXX_3.4.23, CXXABI_1.3.11</p></li><li class="listitem"><p>GCC 7.2.0: GLIBCXX_3.4.24, CXXABI_1.3.11</p></li><li class="listitem"><p>GCC 8.0.0: GLIBCXX_3.4.25, CXXABI_1.3.11</p></li></ul></div></li><li class="listitem"><p>Incremental bumping of a compiler pre-defined macro,
+   </p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.1: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.2: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.3: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.4: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.1.0: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.1.1: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.2.0: GLIBCPP_3.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.1: GLIBCPP_3.2.1, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.2: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.3: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.3.0: GLIBCPP_3.2.2, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.1: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.2: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.3: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.4.0: GLIBCXX_3.4, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.1: GLIBCXX_3.4.1, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.2: GLIBCXX_3.4.2</p></li><li class="listitem"><p>GCC 3.4.3: GLIBCXX_3.4.3</p></li><li class="listitem"><p>GCC 4.0.0: GLIBCXX_3.4.4, CXXABI_1.3.1</p></li><li class="listitem"><p>GCC 4.0.1: GLIBCXX_3.4.5</p></li><li class="listitem"><p>GCC 4.0.2: GLIBCXX_3.4.6</p></li><li class="listitem"><p>GCC 4.0.3: GLIBCXX_3.4.7</p></li><li class="listitem"><p>GCC 4.1.1: GLIBCXX_3.4.8</p></li><li class="listitem"><p>GCC 4.2.0: GLIBCXX_3.4.9</p></li><li class="listitem"><p>GCC 4.3.0: GLIBCXX_3.4.10, CXXABI_1.3.2</p></li><li class="listitem"><p>GCC 4.4.0: GLIBCXX_3.4.11, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.1: GLIBCXX_3.4.12, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.2: GLIBCXX_3.4.13, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.5.0: GLIBCXX_3.4.14, CXXABI_1.3.4</p></li><li class="listitem"><p>GCC 4.6.0: GLIBCXX_3.4.15, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.6.1: GLIBCXX_3.4.16, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.7.0: GLIBCXX_3.4.17, CXXABI_1.3.6</p></li><li class="listitem"><p>GCC 4.8.0: GLIBCXX_3.4.18, CXXABI_1.3.7</p></li><li class="listitem"><p>GCC 4.8.3: GLIBCXX_3.4.19, CXXABI_1.3.7</p></li><li class="listitem"><p>GCC 4.9.0: GLIBCXX_3.4.20, CXXABI_1.3.8</p></li><li class="listitem"><p>GCC 5.1.0: GLIBCXX_3.4.21, CXXABI_1.3.9</p></li><li class="listitem"><p>GCC 6.1.0: GLIBCXX_3.4.22, CXXABI_1.3.10</p></li><li class="listitem"><p>GCC 7.1.0: GLIBCXX_3.4.23, CXXABI_1.3.11</p></li><li class="listitem"><p>GCC 7.2.0: GLIBCXX_3.4.24, CXXABI_1.3.11</p></li><li class="listitem"><p>GCC 8.1.0: GLIBCXX_3.4.25, CXXABI_1.3.11</p></li></ul></div></li><li class="listitem"><p>Incremental bumping of a compiler pre-defined macro,
     __GXX_ABI_VERSION. This macro is defined as the version of the
     compiler v3 ABI, with g++ 3.0 being version 100. This macro will
     be automatically defined whenever g++ is used (the curious can
diff --git a/libstdc++-v3/doc/xml/manual/abi.xml b/libstdc++-v3/doc/xml/manual/abi.xml
index 733c803ffac..50570a3115a 100644
--- a/libstdc++-v3/doc/xml/manual/abi.xml
+++ b/libstdc++-v3/doc/xml/manual/abi.xml
@@ -267,7 +267,7 @@ compatible.
     <listitem><para>GCC 6.1.0: libstdc++.so.6.0.22</para></listitem>
     <listitem><para>GCC 7.1.0: libstdc++.so.6.0.23</para></listitem>
     <listitem><para>GCC 7.2.0: libstdc++.so.6.0.24</para></listitem>
-    <listitem><para>GCC 8.0.0: libstdc++.so.6.0.25</para></listitem>
+    <listitem><para>GCC 8.1.0: libstdc++.so.6.0.25</para></listitem>
     </itemizedlist>
     <para>
       Note 1: Error should be libstdc++.so.3.0.3.
@@ -337,7 +337,7 @@ compatible.
     <listitem><para>GCC 6.1.0: GLIBCXX_3.4.22, CXXABI_1.3.10</para></listitem>
     <listitem><para>GCC 7.1.0: GLIBCXX_3.4.23, CXXABI_1.3.11</para></listitem>
     <listitem><para>GCC 7.2.0: GLIBCXX_3.4.24, CXXABI_1.3.11</para></listitem>
-    <listitem><para>GCC 8.0.0: GLIBCXX_3.4.25, CXXABI_1.3.11</para></listitem>
+    <listitem><para>GCC 8.1.0: GLIBCXX_3.4.25, CXXABI_1.3.11</para></listitem>
     </itemizedlist>
     </listitem>
 

commit f088749058e0fdffa8f8bbaf6e9630ad09f7a9a8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu May 7 00:17:31 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e48c8ef49f7..e0dd7b4aaaf 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200506
+20200507

commit 49ad77be9c797562c47b74c98a2b9cbd17f6b285
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Thu May 7 17:26:37 2020 +0200

    alpha: Implement the PR94780 fix for alpha.
    
    Essentially the same fix as for x86.
    
    2020-05-07  Uroš Bizjak  <ubizjak@gmail.com>
    
    gcc/
            * config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use
            TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
            fenv_var and new_fenv_var.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 50fd225dea6..9fadbea59e2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-05-07  Uroš Bizjak  <ubizjak@gmail.com>
+
+	* config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use
+	TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
+	fenv_var and new_fenv_var.
+
 2020-05-04  Bin Cheng  <bin.cheng@linux.alibaba.com>
 
 	PR tree-optimization/93674
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index ee95b4428ec..8f68be199e1 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -9903,8 +9903,8 @@ alpha_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
     = build_fn_decl ("__ieee_set_fp_control",
 		     build_function_type_list (void_type_node, NULL));
   mask = build_int_cst (long_unsigned_type_node, ~SWCR_STATUS_MASK);
-  ld_fenv = build2 (MODIFY_EXPR, long_unsigned_type_node,
-		    fenv_var, build_call_expr (get_fpscr, 0));
+  ld_fenv = build4 (TARGET_EXPR, long_unsigned_type_node, fenv_var,
+		    build_call_expr (get_fpscr, 0), NULL_TREE, NULL_TREE);
   masked_fenv = build2 (BIT_AND_EXPR, long_unsigned_type_node, fenv_var, mask);
   hold_fnclex = build_call_expr (set_fpscr, 1, masked_fenv);
   *hold = build2 (COMPOUND_EXPR, void_type_node,
@@ -9925,8 +9925,8 @@ alpha_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
        __atomic_feraiseexcept (new_fenv_var);  */
 
   new_fenv_var = create_tmp_var_raw (long_unsigned_type_node);
-  reload_fenv = build2 (MODIFY_EXPR, long_unsigned_type_node, new_fenv_var,
-			build_call_expr (get_fpscr, 0));
+  reload_fenv = build4 (TARGET_EXPR, long_unsigned_type_node, new_fenv_var,
+			build_call_expr (get_fpscr, 0), NULL_TREE, NULL_TREE);
   restore_fnenv = build_call_expr (set_fpscr, 1, fenv_var);
   atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
   update_call

commit 53b71b7b9d497d6da82892c2a54ed28f4a6caec7
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri May 8 00:17:20 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e0dd7b4aaaf..a4ec51424d2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200507
+20200508

commit dc7687581143f5d546b3023139b4433b6f91bd10
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat May 9 00:17:14 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a4ec51424d2..edea0329ce1 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200508
+20200509

commit 1684d7cd879febbd06292c6f1f543069f1be8caf
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun May 10 00:17:19 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index edea0329ce1..4ae7902f547 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200509
+20200510

commit fae191ba5c100db4f181f995dbcd06db38126f44
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon May 11 00:17:26 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4ae7902f547..7cc5ad9fe46 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200510
+20200511

commit 3d32b5c89438dbec423e48954ebffe51ee2b8dda
Author: Mark Eggleston <markeggleston@gcc.gnu.org>
Date:   Mon May 11 12:38:14 2020 +0100

    Fortran : Spurious warning message with -Wsurprising PR59107
    
    This change is from a patch developed for gcc-5.  The code
    has moved on since then requiring a change to interface.c
    
    2020-05-11  Mark Eggleston  <markeggleston@gcc.gnu.org>
    
    Backported from mainline
    2020-05-11  Janus Weil  <janus@gcc.gnu.org>
                Dominique d'Humieres  <dominiq@lps.ens.fr>
    
    gcc/fortran/
    
            PR fortran/59107
            * gfortran.h: Rename field resolved as resolve_symbol_called
            and assign two 2 bits instead of 1.
            * interface.c (gfc_find_typebound_dtio_proc): Use new field name.
            * resolve.c (gfc_resolve_intrinsic): Replace check of the formal
            field with resolve_symbol_called is at least 2, if it is not
            set the field to 2.  (resolve_symbol): Use new field name and
            check whether it is at least 1, if it is not set the field to 1.
    
    Backported from mainline
    2020-05-11  Mark Eggleston  <markeggleston@gcc.gnu.org>
    
    gcc/testsuite/
    
            PR fortran/59107
            * gfortran.dg/pr59107.f90: New test.

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index b81ffd555ad..dc79913f47b 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,18 @@
+2020-05-11  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	Backported from mainline
+	2020-05-11  Janus Weil  <janus@gcc.gnu.org>
+		    Dominique d'Humieres  <dominiq@lps.ens.fr>
+
+	PR fortran/59107
+	* gfortran.h: Rename field resolved as resolve_symbol_called
+	and assign two 2 bits instead of 1.
+	* interface.c (gfc_find_typebound_dtio_proc): Use new field name.
+	* resolve.c (gfc_resolve_intrinsic): Replace check of the formal
+	field with resolve_symbol_called is at least 2, if it is not
+	set the field to 2.  (resolve_symbol): Use new field name and
+	check whether it is at least 1, if it is not set the field to 1.
+
 2020-04-27  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	PR fortran/93956
diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h
index b2e80a6b0a9..3d6e25a3ff4 100644
--- a/gcc/fortran/gfortran.h
+++ b/gcc/fortran/gfortran.h
@@ -1587,7 +1587,10 @@ typedef struct gfc_symbol
   /* Set if the symbol is used in a function result specification .  */
   unsigned fn_result_spec:1;
   /* Used to avoid multiple resolutions of a single symbol.  */
-  unsigned resolved:1;
+  /* = 2 if this has already been resolved as an intrinsic,
+       in gfc_resolve_intrinsic,
+     = 1 if it has been resolved in resolve_symbol.  */
+  unsigned resolve_symbol_called:2;
   /* Set if this is a module function or subroutine with the
      abreviated declaration in a submodule.  */
   unsigned abr_modproc_decl:1;
diff --git a/gcc/fortran/interface.c b/gcc/fortran/interface.c
index 04850b0406c..689c30210d7 100644
--- a/gcc/fortran/interface.c
+++ b/gcc/fortran/interface.c
@@ -4940,7 +4940,8 @@ gfc_find_typebound_dtio_proc (gfc_symbol *derived, bool write, bool formatted)
   gfc_symtree *tb_io_st = NULL;
   bool t = false;
 
-  if (!derived || !derived->resolved || derived->attr.flavor != FL_DERIVED)
+  if (!derived || !derived->resolve_symbol_called
+      || derived->attr.flavor != FL_DERIVED)
     return NULL;
 
   /* Try to find a typebound DTIO binding.  */
diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
index 69d877ed55b..d34d3dc66fd 100644
--- a/gcc/fortran/resolve.c
+++ b/gcc/fortran/resolve.c
@@ -1746,9 +1746,11 @@ gfc_resolve_intrinsic (gfc_symbol *sym, locus *loc)
   gfc_intrinsic_sym* isym = NULL;
   const char* symstd;
 
-  if (sym->formal)
+  if (sym->resolve_symbol_called >= 2)
     return true;
 
+  sym->resolve_symbol_called = 2;
+
   /* Already resolved.  */
   if (sym->from_intmod && sym->ts.type != BT_UNKNOWN)
     return true;
@@ -14601,9 +14603,9 @@ resolve_symbol (gfc_symbol *sym)
   gfc_array_spec *as;
   bool saved_specification_expr;
 
-  if (sym->resolved)
+  if (sym->resolve_symbol_called >= 1)
     return;
-  sym->resolved = 1;
+  sym->resolve_symbol_called = 1;
 
   /* No symbol will ever have union type; only components can be unions.
      Union type declaration symbols have type BT_UNKNOWN but flavor FL_UNION
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 88c74e6fc15..436ee423db1 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-05-11  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	Backported from mainline
+	2020-05-11  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	PR fortran/59107
+	* gfortran.dg/pr59107.f90: New test.
+
 2020-05-04  Bin Cheng  <bin.cheng@linux.alibaba.com>
 
 	PR tree-optimization/93674
diff --git a/gcc/testsuite/gfortran.dg/pr59107.f90 b/gcc/testsuite/gfortran.dg/pr59107.f90
new file mode 100644
index 00000000000..a84328f0851
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr59107.f90
@@ -0,0 +1,11 @@
+! { dg-compile }
+! { dg-options "-Wsurprising" }
+
+! There should be no surprising warnings
+
+program p
+  Integer :: nargs
+  intrinsic :: command_argument_count
+  nargs = command_argument_count()
+end
+

commit 83263a280460fd99e35149f386787435b8e7627e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue May 12 00:17:16 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7cc5ad9fe46..10771293e10 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200511
+20200512

commit 24c54df7f3643fd911fef2eb2953577664bf43eb
Author: David Edelsohn <dje.gcc@gmail.com>
Date:   Tue May 12 17:09:36 2020 -0400

        rs6000: AIX long double builtins for 64 bit long double.
    
        When long doubles are 64 bit, the AIX C library overrides the definitions
        but GCC builtins point to 128 bit names.  This patch overrides the
        builtins for fmodl, frexpl, ldexpl and modfl to refer to the 64 bit symbols.
    
        Backport from mainline
        2020-05-04  Clement Chigot  <clement.chigot@atos.net>
                    David Edelsohn  <dje.gcc@gmail.com>
    
                * config/rs6000/rs6000-call.c (rs6000_init_builtins): Override expli
    cit
                for fmodl, frexpl, ldexpl and modfl builtins.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9fadbea59e2..eda5a7fbabe 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-05-12  David Edelsohn  <dje.gcc@gmail.com>
+
+	Backport from mainline
+	2020-05-04  Clement Chigot  <clement.chigot@atos.net>
+		    David Edelsohn  <dje.gcc@gmail.com>
+
+	* config/rs6000/rs6000.c (rs6000_init_builtins): Override explicit
+	for fmodl, frexpl, ldexpl and modfl builtins.
+
 2020-05-07  Uroš Bizjak  <ubizjak@gmail.com>
 
 	* config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 95643c01b5a..75d40367a98 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -17513,10 +17513,28 @@ rs6000_init_builtins (void)
   def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
   def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
 
-  /* AIX libm provides clog as __clog.  */
-  if (TARGET_XCOFF &&
-      (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
-    set_user_assembler_name (tdecl, "__clog");
+  if (TARGET_XCOFF)
+    {
+      /* AIX libm provides clog as __clog.  */
+      if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
+	set_user_assembler_name (tdecl, "__clog");
+
+      /* When long double is 64 bit, some long double builtins of libc
+	 functions (like __builtin_frexpl) must call the double version
+	 (frexp) not the long double version (frexpl) that expects a 128 bit
+	 argument.  */
+      if (! TARGET_LONG_DOUBLE_128)
+	{
+	  if ((tdecl = builtin_decl_explicit (BUILT_IN_FMODL)) != NULL_TREE)
+	    set_user_assembler_name (tdecl, "fmod");
+	  if ((tdecl = builtin_decl_explicit (BUILT_IN_FREXPL)) != NULL_TREE)
+	    set_user_assembler_name (tdecl, "frexp");
+	  if ((tdecl = builtin_decl_explicit (BUILT_IN_LDEXPL)) != NULL_TREE)
+	    set_user_assembler_name (tdecl, "ldexp");
+	  if ((tdecl = builtin_decl_explicit (BUILT_IN_MODFL)) != NULL_TREE)
+	    set_user_assembler_name (tdecl, "modf");
+	}
+    }
 
 #ifdef SUBTARGET_INIT_BUILTINS
   SUBTARGET_INIT_BUILTINS;

commit 18aabb0cb3fbf44e04152fd2e1fbe522e5d99095
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed May 13 00:17:29 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 10771293e10..aa5d21b148b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200512
+20200513

commit 9ced3bd38b020aa29d2fbf1cb6e75906f68e7376
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu May 14 00:17:20 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index aa5d21b148b..307f2b18da7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200513
+20200514

commit d523cd5109bc5ab42edf85385f6a1085e0d6028c
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Fri Apr 3 09:35:41 2020 +0000

    aarch64, libgcc: Fix unwinding from pac-ret to normal frames [PR94514]
    
    With -mbranch-protection=pac-ret the debug info toggles the
    signedness state of the return address so the unwinder knows when
    the return address needs pointer authentication.
    
    The unwind context flags were not updated according to the dwarf
    frame info.
    
    This causes unwinding across frames that were built without pac-ret
    to incorrectly authenticate the return address wich corrupts the
    return address on a system where PAuth is enabled.
    
    Note: This even affects systems where all code use pac-ret because
    unwinding across a signal frame the return address is not signed.
    
    Changed branch-protection=pac-ret to sign-return-address=all etc
    in the tests for the backport.
    
    gcc/testsuite/ChangeLog:
    
            Backport from mainline.
            2020-04-23  Szabolcs Nagy  <szabolcs.nagy@arm.com>
    
            PR target/94514
            * g++.target/aarch64/pr94514.C: Require lp64.
            * gcc.target/aarch64/pr94514.c: Likewise.
    
            Backport from mainline.
            2020-04-21  Szabolcs Nagy  <szabolcs.nagy@arm.com>
    
            PR target/94514
            * g++.target/aarch64/pr94514.C: New test.
            * gcc.target/aarch64/pr94514.c: New test.
    
    libgcc/ChangeLog:
    
            Backport from mainline.
            2020-04-21  Szabolcs Nagy  <szabolcs.nagy@arm.com>
    
            PR target/94514
            * config/aarch64/aarch64-unwind.h (aarch64_frob_update_context):
            Update context->flags accroding to the frame state.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 436ee423db1..3b1b58d87b0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,19 @@
+2020-05-14  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	Backport from mainline.
+	2020-04-23  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	PR target/94514
+	* g++.target/aarch64/pr94514.C: Require lp64.
+	* gcc.target/aarch64/pr94514.c: Likewise.
+
+	Backport from mainline.
+	2020-04-21  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	PR target/94514
+	* g++.target/aarch64/pr94514.C: New test.
+	* gcc.target/aarch64/pr94514.c: New test.
+
 2020-05-11  Mark Eggleston  <markeggleston@gcc.gnu.org>
 
 	Backported from mainline
diff --git a/gcc/testsuite/g++.target/aarch64/pr94514.C b/gcc/testsuite/g++.target/aarch64/pr94514.C
new file mode 100644
index 00000000000..f73e64c9fc5
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/pr94514.C
@@ -0,0 +1,27 @@
+/* PR target/94514. Unwind across mixed pac-ret and non-pac-ret frames.  */
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+
+__attribute__((noinline, target("sign-return-address=all")))
+static void do_throw (void)
+{
+  throw 42;
+  __builtin_abort ();
+}
+
+__attribute__((noinline, target("sign-return-address=none")))
+static void no_pac_ret (void)
+{
+  do_throw ();
+  __builtin_abort ();
+}
+
+int main ()
+{
+  try {
+    no_pac_ret ();
+  } catch (...) {
+    return 0;
+  }
+  __builtin_abort ();
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/pr94514.c b/gcc/testsuite/gcc.target/aarch64/pr94514.c
new file mode 100644
index 00000000000..a6a0fb1adc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr94514.c
@@ -0,0 +1,77 @@
+/* PR target/94514. Unwind across mixed pac-ret and non-pac-ret frames.  */
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-fexceptions -O2" } */
+
+#include <unwind.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+#define die() \
+  do { \
+    printf ("%s:%d: reached unexpectedly.\n", __FILE__, __LINE__); \
+    fflush (stdout); \
+    abort (); \
+  } while (0)
+
+static struct _Unwind_Exception exc;
+
+static _Unwind_Reason_Code
+force_unwind_stop (int version, _Unwind_Action actions,
+                   _Unwind_Exception_Class exc_class,
+                   struct _Unwind_Exception *exc_obj,
+                   struct _Unwind_Context *context,
+                   void *stop_parameter)
+{
+  printf ("%s: CFA: %p PC: %p actions: %d\n",
+	  __func__,
+	  (void *)_Unwind_GetCFA (context),
+	  (void *)_Unwind_GetIP (context),
+	  (int)actions);
+  if (actions & _UA_END_OF_STACK)
+    die ();
+  return _URC_NO_REASON;
+}
+
+static void force_unwind (void)
+{
+#ifndef __USING_SJLJ_EXCEPTIONS__
+  _Unwind_ForcedUnwind (&exc, force_unwind_stop, 0);
+#else
+  _Unwind_SjLj_ForcedUnwind (&exc, force_unwind_stop, 0);
+#endif
+}
+
+__attribute__((noinline, target("sign-return-address=all")))
+static void f2_pac_ret (void)
+{
+  force_unwind ();
+  die ();
+}
+
+__attribute__((noinline, target("sign-return-address=none")))
+static void f1_no_pac_ret (void)
+{
+  f2_pac_ret ();
+  die ();
+}
+
+__attribute__((noinline, target("sign-return-address=all")))
+static void f0_pac_ret (void)
+{
+  f1_no_pac_ret ();
+  die ();
+}
+
+static void cleanup_handler (void *p)
+{
+  printf ("%s: Success.\n", __func__);
+  exit (0);
+}
+
+int main ()
+{
+  char dummy __attribute__((cleanup (cleanup_handler)));
+  f0_pac_ret ();
+  die ();
+}
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 4942176b80b..fff1a58e3db 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-05-14  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	Backport from mainline.
+	2020-04-21  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	PR target/94514
+	* config/aarch64/aarch64-unwind.h (aarch64_frob_update_context):
+	Update context->flags accroding to the frame state.
+
 2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	Backport from mainline
diff --git a/libgcc/config/aarch64/aarch64-unwind.h b/libgcc/config/aarch64/aarch64-unwind.h
index ff05226f49c..f3b4cfa3b8c 100644
--- a/libgcc/config/aarch64/aarch64-unwind.h
+++ b/libgcc/config/aarch64/aarch64-unwind.h
@@ -80,6 +80,8 @@ aarch64_frob_update_context (struct _Unwind_Context *context,
   if (fs->regs.reg[DWARF_REGNUM_AARCH64_RA_STATE].loc.offset & 0x1)
     /* The flag is used for re-authenticating EH handler's address.  */
     context->flags |= RA_A_SIGNED_BIT;
+  else
+    context->flags &= ~RA_A_SIGNED_BIT;
 
   return;
 }

commit 62ab8b9114b0bdae508ed76fa9028e0040d35e6b
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Mon Apr 27 09:07:15 2020 +0100

    aarch64: Fix .cfi_window_save with pac-ret [PR94515]
    
    On aarch64 -mbranch-protection=pac-ret reuses the dwarf
    opcode for window_save to mean "toggle the return address
    mangle state", but in the dwarf2cfi internal logic the
    state was not updated when an opcode was emitted, the
    currently present update logic is only valid for the
    original sparc use of window_save so a separate bool is
    used on aarch64 to track the state.
    
    This bug can cause the unwinder not to authenticate return
    addresses that were signed (or vice versa) which means a
    runtime crash on a pauth enabled system.
    
    Currently only aarch64 pac-ret uses REG_CFA_TOGGLE_RA_MANGLE.
    
    This should be backported to gcc-9 and gcc-8 branches.
    
    Changed branch-protection=pac-ret to sign-return-address=all etc
    in the tests for the backport and adjusted the dwarf2cfi.c
    changes because the sparc change was missing.
    
    gcc/ChangeLog:
    
            Backport from mainline.
            2020-04-27  Szabolcs Nagy  <szabolcs.nagy@arm.com>
    
            PR target/94515
            * dwarf2cfi.c (struct GTY): Add ra_mangled.
            (cfi_row_equal_p): Check ra_mangled.
            (dwarf2out_frame_debug_cfa_window_save): Remove the argument,
            this only handles the sparc logic now.
            (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for
            the aarch64 specific logic.
            (dwarf2out_frame_debug): Update to use the new subroutines.
            (change_cfi_row): Check ra_mangled.
    
    gcc/testsuite/ChangeLog:
    
            Backport from mainline.
            2020-04-27  Szabolcs Nagy  <szabolcs.nagy@arm.com>
    
            PR target/94515
            * g++.target/aarch64/pr94515-1.C: New test.
            * g++.target/aarch64/pr94515-2.C: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eda5a7fbabe..99aea924392 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2020-05-14  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	Backport from mainline.
+	2020-04-27  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	PR target/94515
+	* dwarf2cfi.c (struct GTY): Add ra_mangled.
+	(cfi_row_equal_p): Check ra_mangled.
+	(dwarf2out_frame_debug_cfa_window_save): Remove the argument,
+	this only handles the sparc logic now.
+	(dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for
+	the aarch64 specific logic.
+	(dwarf2out_frame_debug): Update to use the new subroutines.
+	(change_cfi_row): Check ra_mangled.
+
 2020-05-12  David Edelsohn  <dje.gcc@gmail.com>
 
 	Backport from mainline
diff --git a/gcc/dwarf2cfi.c b/gcc/dwarf2cfi.c
index bed6c981852..d496f57547a 100644
--- a/gcc/dwarf2cfi.c
+++ b/gcc/dwarf2cfi.c
@@ -68,6 +68,9 @@ struct GTY(()) dw_cfi_row
 
   /* The expressions for any register column that is saved.  */
   cfi_vec reg_save;
+
+  /* True if the return address is in a mangled state.  */
+  bool ra_mangled;
 };
 
 /* The caller's ORIG_REG is saved in SAVED_IN_REG.  */
@@ -763,6 +766,9 @@ cfi_row_equal_p (dw_cfi_row *a, dw_cfi_row *b)
         return false;
     }
 
+  if (a->ra_mangled != b->ra_mangled)
+    return false;
+
   return true;
 }
 
@@ -1370,6 +1376,21 @@ dwarf2out_frame_debug_cfa_window_save (void)
   add_cfi (cfi);
 }
 
+/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_TOGGLE_RA_MANGLE.
+   Note: DW_CFA_GNU_window_save dwarf opcode is reused for toggling RA mangle
+   state, this is a target specific operation on AArch64 and can only be used
+   on other targets if they don't use the window save operation otherwise.  */
+
+static void
+dwarf2out_frame_debug_cfa_toggle_ra_mangle (void)
+{
+  dw_cfi_ref cfi = new_cfi ();
+
+  cfi->dw_cfi_opc = DW_CFA_GNU_window_save;
+  add_cfi (cfi);
+  cur_row->ra_mangled = !cur_row->ra_mangled;
+}
+
 /* Record call frame debugging information for an expression EXPR,
    which either sets SP or FP (adjusting how we calculate the frame
    address) or saves a register to the stack or another register.
@@ -2127,8 +2148,11 @@ dwarf2out_frame_debug (rtx_insn *insn)
 	break;
 
       case REG_CFA_TOGGLE_RA_MANGLE:
+	dwarf2out_frame_debug_cfa_toggle_ra_mangle ();
+	handled_one = true;
+	break;
+
       case REG_CFA_WINDOW_SAVE:
-	/* We overload both of these operations onto the same DWARF opcode.  */
 	dwarf2out_frame_debug_cfa_window_save ();
 	handled_one = true;
 	break;
@@ -2193,6 +2217,15 @@ change_cfi_row (dw_cfi_row *old_row, dw_cfi_row *new_row)
       else if (!cfi_equal_p (r_old, r_new))
         add_cfi (r_new);
     }
+
+  if (old_row->ra_mangled != new_row->ra_mangled)
+    {
+      dw_cfi_ref cfi = new_cfi ();
+
+      /* DW_CFA_GNU_window_save is reused for toggling RA mangle state.  */
+      cfi->dw_cfi_opc = DW_CFA_GNU_window_save;
+      add_cfi (cfi);
+    }
 }
 
 /* Examine CFI and return true if a cfi label and set_loc is needed
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3b1b58d87b0..457e9ab93e4 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2020-05-14  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	Backport from mainline.
+	2020-04-27  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	PR target/94515
+	* g++.target/aarch64/pr94515-1.C: New test.
+	* g++.target/aarch64/pr94515-2.C: New test.
+
 2020-05-14  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/testsuite/g++.target/aarch64/pr94515-1.C b/gcc/testsuite/g++.target/aarch64/pr94515-1.C
new file mode 100644
index 00000000000..3640347945a
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/pr94515-1.C
@@ -0,0 +1,44 @@
+/* PR target/94515. Check .cfi_window_save with multiple return paths.  */
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-additional-options "-O2 --save-temps" } */
+
+volatile int zero = 0;
+
+__attribute__((noinline, target("sign-return-address=none")))
+void unwind (void)
+{
+  if (zero == 0)
+    throw 42;
+}
+
+__attribute__((noinline, noipa, target("sign-return-address=all")))
+int test (int z)
+{
+  if (z) {
+    asm volatile ("":::"x20","x21");
+    unwind ();
+    return 1;
+  } else {
+    unwind ();
+    return 2;
+  }
+}
+
+__attribute__((target("sign-return-address=none")))
+int main ()
+{
+  try {
+    test (zero);
+    __builtin_abort ();
+  } catch (...) {
+    return 0;
+  }
+  __builtin_abort ();
+}
+
+/* This check only works if there are two return paths in test and
+   cfi_window_save is used for both instead of cfi_remember_state
+   plus cfi_restore_state.  This is currently the case with -O2.  */
+
+/* { dg-final { scan-assembler-times {\t\.cfi_window_save\n} 4 } } */
diff --git a/gcc/testsuite/g++.target/aarch64/pr94515-2.C b/gcc/testsuite/g++.target/aarch64/pr94515-2.C
new file mode 100644
index 00000000000..92e79831ff9
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/pr94515-2.C
@@ -0,0 +1,41 @@
+/* PR target/94515. Check .cfi_window_save with multiple return paths.  */
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-additional-options "-O2 -msign-return-address=all" } */
+
+volatile int zero = 0;
+int global = 0;
+
+__attribute__((noinline))
+int bar(void)
+{
+  if (zero == 0) return 3;
+  return 0;
+}
+
+__attribute__((noinline, noreturn))
+void unwind (void)
+{
+  throw 42;
+}
+
+__attribute__((noinline, noipa))
+int test(int x)
+{
+  if (x==1) return 2; /* This return path may not use the stack.  */
+  int y = bar();
+  if (y > global) global=y;
+  if (y==3) unwind(); /* This return path must have RA mangle state set.  */
+  return 0;
+}
+
+int main ()
+{
+  try {
+    test (zero);
+    __builtin_abort ();
+  } catch (...) {
+    return 0;
+  }
+  __builtin_abort ();
+}

commit 95cf5933a319365fd62276f867a923ebe7ef35c0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri May 15 00:17:17 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 307f2b18da7..996d73f1867 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200514
+20200515

commit 12188df11006211e04bcb7398778dc3d51256eaa
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat May 16 00:17:19 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 996d73f1867..c4c2f91fd71 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200515
+20200516

commit de5ec5993aefb8f3ca4266d46646c8f571a8c0a5
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun May 17 00:17:24 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c4c2f91fd71..a4634f14410 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200516
+20200517

commit 445028d31f51ee37c32df8052bfd459b4e9f36bc
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon May 18 00:17:15 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a4634f14410..5b6c5c3863b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200517
+20200518

commit 81c539d7d78dd80e356eadf7af090ecba901d4c6
Author: Douglas Rupp <rupp@adacore.com>
Date:   Mon May 18 11:43:48 2020 -0700

    Require powerpc_vsx_ok in gcc.target/powerpc/pr71763.c
    
    We're getting an error when running this test on PowerPC VxWorks 7,
    due to an unexpected warning:
    
        | Excess errors:
        | cc1: warning: '-mvsx' and '-mno-altivec' are incompatible
    
    The warning comes from a combination of factors:
      - The test itself uses -mvsx explicitly via the following directive:
           // { dg-options "-O1 -mvsx" }
      - Our toolchain was configured so as to make -mno-altivec
        the default;
      - These two options are mutually exclusive.
    
    This commit adds a powerpc_vsx_ok dg-require-effective-target directive
    to that test, and thus making it UNSUPPORTED instead.
    
    Tested on PowerPC VxWorks 7. Also tested on PowerPC ELF as well,
    a platform where we do not make -mno-altivec the default, to verify
    that the test continues to run as usual in that case.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/pr71763.c: Require powerpc_vsx_ok.
    
    (cherry picked from commit c917584aa9ec32934acf0082ed383b04f49fd174)

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 457e9ab93e4..8c3bd994b1c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2020-05-18  Doug Rupp  <rupp@adacore.com>
+
+	* gcc.target/powerpc/pr71763.c: Require powerpc_vsx_ok.
+
 2020-05-14  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/testsuite/gcc.target/powerpc/pr71763.c b/gcc/testsuite/gcc.target/powerpc/pr71763.c
index b36ddfa26b0..b8888394393 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr71763.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr71763.c
@@ -1,5 +1,6 @@
 // PR target/71763
 // { dg-do compile }
+// { dg-require-effective-target powerpc_vsx_ok }
 // { dg-options "-O1 -mvsx" }
 
 int a, b;

commit 13df06ec2c307c4ac016470a45ea208213dbcb95
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue May 19 00:17:33 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 5b6c5c3863b..d5c3321b50c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200518
+20200519

commit 0dce839465e65f65bb61a0550c4baf30f1d4a4c5
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed May 20 00:17:29 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d5c3321b50c..7e4dd6dda15 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200519
+20200520

commit 15e518600a9ef82b55d2ec75d8d41d767132f475
Author: Mark Eggleston <markeggleston@gcc.gnu.org>
Date:   Thu May 7 08:02:02 2020 +0100

    Fortran  : ProcPtr function results: 'ppr@' in error message PR39695
    
    The value 'ppr@' is set in the name of result symbol, the actual
    name of the symbol is in the procedure name symbol pointed
    to by the result symbol's namespace (ns). When reporting errors for
    symbols that have the proc_pointer attribute check whether the
    result attribute is set and set the name accordingly.
    
    Backport from master.
    
    2020-05-20  Mark Eggleston  <markeggleston@gcc.gnu.org>
    
    gcc/fortran/
    
            PR fortran/39695
            * resolve.c (resolve_fl_procedure): Set name depending on
            whether the result attribute is set.  For PROCEDURE/RESULT
            conflict use the name in sym->ns->proc_name->name.
            * symbol.c (gfc_add_type): Add check for function and result
            attributes use sym->ns->proc_name->name if both are set.
            Where the symbol cannot have a type use the name in
            sym->ns->proc_name->name.
    
    2020-05-20  Mark Eggleston  <markeggleston@gcc.gnu.org>
    
    gcc/testsuite/
    
            PR fortran/39695
            * gfortran.dg/pr39695_1.f90: New test.
            * gfortran.dg/pr39695_2.f90: New test.
            * gfortran.dg/pr39695_3.f90: New test.
            * gfortran.dg/pr39695_4.f90: New test.
    
            (cherry picked from commit eb069ae8819c3a84d7f78becc5501e21ee3a9554)

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index dc79913f47b..b1490c06f41 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,17 @@
+2020-05-20  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	Backport from master
+	2020-05-20  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	PR fortran/39695
+	* resolve.c (resolve_fl_procedure): Set name depending on
+	whether the result attribute is set.  For PROCEDURE/RESULT
+	conflict use the name in sym->ns->proc_name->name.
+	* symbol.c (gfc_add_type): Add check for function and result
+	attributes use sym->ns->proc_name->name if both are set.
+	Where the symbol cannot have a type use the name in
+	sym->ns->proc_name->name.
+
 2020-05-11  Mark Eggleston  <markeggleston@gcc.gnu.org>
 
 	Backported from mainline
diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
index d34d3dc66fd..e3212ff55d2 100644
--- a/gcc/fortran/resolve.c
+++ b/gcc/fortran/resolve.c
@@ -12592,8 +12592,10 @@ resolve_fl_procedure (gfc_symbol *sym, int mp_flag)
     {
       if (sym->attr.proc_pointer)
 	{
+	  const char* name = (sym->attr.result ? sym->ns->proc_name->name
+					       : sym->name);
 	  gfc_error ("Procedure pointer %qs at %L shall not be elemental",
-		     sym->name, &sym->declared_at);
+		     name, &sym->declared_at);
 	  return false;
 	}
       if (sym->attr.dummy)
@@ -12680,7 +12682,7 @@ resolve_fl_procedure (gfc_symbol *sym, int mp_flag)
       if (sym->attr.subroutine && sym->attr.result)
 	{
 	  gfc_error ("PROCEDURE attribute conflicts with RESULT attribute "
-		     "in %qs at %L", sym->name, &sym->declared_at);
+		     "in %qs at %L", sym->ns->proc_name->name, &sym->declared_at);
 	  return false;
 	}
       if (sym->attr.external && sym->attr.function && !sym->attr.module_procedure
diff --git a/gcc/fortran/symbol.c b/gcc/fortran/symbol.c
index e783319298c..e07b48ab082 100644
--- a/gcc/fortran/symbol.c
+++ b/gcc/fortran/symbol.c
@@ -2000,9 +2000,12 @@ gfc_add_type (gfc_symbol *sym, gfc_typespec *ts, locus *where)
 	gfc_error ("Symbol %qs at %L conflicts with symbol from module %qs, "
 		   "use-associated at %L", sym->name, where, sym->module,
 		   &sym->declared_at);
+      else if (sym->attr.function && sym->attr.result)
+	gfc_error ("Symbol %qs at %L already has basic type of %s",
+		   sym->ns->proc_name->name, where, gfc_basic_typename (type));
       else
 	gfc_error ("Symbol %qs at %L already has basic type of %s", sym->name,
-		 where, gfc_basic_typename (type));
+		   where, gfc_basic_typename (type));
       return false;
     }
 
@@ -2020,7 +2023,7 @@ gfc_add_type (gfc_symbol *sym, gfc_typespec *ts, locus *where)
       || (flavor == FL_PROCEDURE && sym->attr.subroutine)
       || flavor == FL_DERIVED || flavor == FL_NAMELIST)
     {
-      gfc_error ("Symbol %qs at %L cannot have a type", sym->name, where);
+      gfc_error ("Symbol %qs at %L cannot have a type", sym->ns->proc_name->name, where);
       return false;
     }
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8c3bd994b1c..090eb019106 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2020-05-20  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	Backport from master
+	2020-05-20  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	PR fortran/39695
+	* gfortran.dg/pr39695_1.f90: New test.
+	* gfortran.dg/pr39695_2.f90: New test.
+	* gfortran.dg/pr39695_3.f90: New test.
+	* gfortran.dg/pr39695_4.f90: New test.
+
 2020-05-18  Doug Rupp  <rupp@adacore.com>
 
 	* gcc.target/powerpc/pr71763.c: Require powerpc_vsx_ok.
diff --git a/gcc/testsuite/gfortran.dg/pr39695_1.f90 b/gcc/testsuite/gfortran.dg/pr39695_1.f90
new file mode 100644
index 00000000000..4c4b3045f69
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr39695_1.f90
@@ -0,0 +1,8 @@
+! { dg-do compile }
+!
+
+function f()
+  intrinsic :: sin
+  procedure(sin), pointer :: f ! { dg-error "Procedure pointer 'f'" }
+  f => sin
+end function f
diff --git a/gcc/testsuite/gfortran.dg/pr39695_2.f90 b/gcc/testsuite/gfortran.dg/pr39695_2.f90
new file mode 100644
index 00000000000..8534724959a
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr39695_2.f90
@@ -0,0 +1,12 @@
+! { dg-do compile }
+!
+
+function g()
+ interface
+    subroutine g()
+    end subroutine g
+  end interface
+  pointer g
+  real g   ! { dg-error "Symbol 'g' at .1. cannot have a type" }
+end function
+
diff --git a/gcc/testsuite/gfortran.dg/pr39695_3.f90 b/gcc/testsuite/gfortran.dg/pr39695_3.f90
new file mode 100644
index 00000000000..661e2540bb3
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr39695_3.f90
@@ -0,0 +1,11 @@
+! { dg-do compile }
+!
+
+function g()
+ interface
+    subroutine g()   ! { dg-error "RESULT attribute in 'g'" }
+    end subroutine g
+  end interface
+  real g             ! { dg-error "Symbol 'g' at .1. cannot have a type" }
+end function
+
diff --git a/gcc/testsuite/gfortran.dg/pr39695_4.f90 b/gcc/testsuite/gfortran.dg/pr39695_4.f90
new file mode 100644
index 00000000000..ecb0a43929f
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr39695_4.f90
@@ -0,0 +1,14 @@
+! { dg-do compile }
+!
+
+function g()
+  implicit none
+  interface
+    function g()
+      integer g
+    end function g
+  end interface
+  pointer g
+  real g   ! { dg-error "Symbol 'g' at .1. already has basic type of INTEGER" }
+end function
+

commit 527a1978797339062dfd240f9be7b8f727e36a73
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu May 21 00:17:29 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7e4dd6dda15..bf0113a0c6e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200520
+20200521

commit aad7ffb62247fce56e03b03dd696b49bbc8913e7
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue May 19 14:42:12 2020 -0700

    x86: Update GFNI check
    
    Update GFNI check to support processors with SSE and AVX versions of GFNI.
    
            Backport from master
            PR target/95220
            * config/i386/cpuinfo.c (get_available_features): Fix
            FEATURE_GFNI check.
    
    (cherry picked from commit 1e46a443f25d26816536c0c480211714b123a1d5)

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index fff1a58e3db..c559361ade5 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-05-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backport from master
+	2020-05-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/95220
+	* config/i386/cpuinfo.c (get_available_features): Fix
+	FEATURE_GFNI check.
+
 2020-05-14  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 
 	Backport from mainline.
diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
index d1853d5515b..46f530c24cb 100644
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -330,6 +330,8 @@ get_available_features (unsigned int ecx, unsigned int edx,
 	}
       if (ebx & bit_BMI2)
 	set_feature (FEATURE_BMI2);
+      if (ecx & bit_GFNI)
+	set_feature (FEATURE_GFNI);
       if (avx512_usable)
 	{
 	  if (ebx & bit_AVX512F)
@@ -352,8 +354,6 @@ get_available_features (unsigned int ecx, unsigned int edx,
 	    set_feature (FEATURE_AVX512VBMI);
 	  if (ecx & bit_AVX512VBMI2)
 	    set_feature (FEATURE_AVX512VBMI2);
-	  if (ecx & bit_GFNI)
-	    set_feature (FEATURE_GFNI);
 	  if (ecx & bit_VPCLMULQDQ)
 	    set_feature (FEATURE_VPCLMULQDQ);
 	  if (ecx & bit_AVX512VNNI)

commit 69b35b7c91ebbc1a6df57e957303e904210ad265
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue May 19 18:55:08 2020 -0700

    x86: Update VPCLMULQDQ check
    
    Update VPCLMULQDQ check to support processors with AVX version of
    VPCLMULQDQ.
    
            Backport from master
            PR target/91695
            * config/i386/cpuinfo.c (get_available_features): Fix VPCLMULQDQ
            check.
    
    (cherry picked from commit 1e46a443f25d26816536c0c480211714b123a1d5)

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index c559361ade5..030e4d7ee24 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-05-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backport from master
+	2020-05-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/91695
+	* config/i386/cpuinfo.c (get_available_features): Fix VPCLMULQDQ
+	check.
+
 2020-05-19  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from master
diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
index 46f530c24cb..14bc574f5de 100644
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -327,6 +327,8 @@ get_available_features (unsigned int ecx, unsigned int edx,
 	{
 	  if (ebx & bit_AVX2)
 	    set_feature (FEATURE_AVX2);
+	  if (ecx & bit_VPCLMULQDQ)
+	    set_feature (FEATURE_VPCLMULQDQ);
 	}
       if (ebx & bit_BMI2)
 	set_feature (FEATURE_BMI2);
@@ -354,8 +356,6 @@ get_available_features (unsigned int ecx, unsigned int edx,
 	    set_feature (FEATURE_AVX512VBMI);
 	  if (ecx & bit_AVX512VBMI2)
 	    set_feature (FEATURE_AVX512VBMI2);
-	  if (ecx & bit_VPCLMULQDQ)
-	    set_feature (FEATURE_VPCLMULQDQ);
 	  if (ecx & bit_AVX512VNNI)
 	    set_feature (FEATURE_AVX512VNNI);
 	  if (ecx & bit_AVX512BITALG)

commit 9f561d35223b7cd11e5486ba087d8e7890cf9b1d
Author: Martin Liska <mliska@suse.cz>
Date:   Thu May 21 12:45:47 2020 +0200

    Add outline-atomics to target attribute.
    
            * common/config/aarch64/aarch64-common.c (aarch64_handle_option):
            Handle OPT_moutline_atomics.
            * config/aarch64/aarch64.c: Add outline-atomics to
            aarch64_attributes.
    
            * doc/extend.texi: Document the newly added target attribute.
    
            * gcc.target/aarch64/target_attr_20.c: New test.
            * gcc.target/aarch64/target_attr_21.c: New test.
    
    (cherry picked from commit 9e02b45ffc60e0078bde3c56a14f00c54b7f8039)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 99aea924392..eded702d1ff 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-05-21  Martin Liska  <mliska@suse.cz>
+
+	* common/config/aarch64/aarch64-common.c (aarch64_handle_option):
+	Handle OPT_moutline_atomics.
+	* config/aarch64/aarch64.c: Add outline-atomics to
+	aarch64_attributes.
+	* doc/extend.texi: Document the newly added target attribute.
+
 2020-05-14  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 
 	Backport from mainline.
diff --git a/gcc/common/config/aarch64/aarch64-common.c b/gcc/common/config/aarch64/aarch64-common.c
index d500ae53cc0..eaa90406c60 100644
--- a/gcc/common/config/aarch64/aarch64-common.c
+++ b/gcc/common/config/aarch64/aarch64-common.c
@@ -110,6 +110,10 @@ aarch64_handle_option (struct gcc_options *opts,
       opts->x_flag_omit_leaf_frame_pointer = val;
       return true;
 
+    case OPT_moutline_atomics:
+      opts->x_aarch64_flag_outline_atomics = val;
+      return true;
+
     default:
       return true;
     }
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 525deba56ea..ad339ab1d54 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -11391,6 +11391,8 @@ static const struct aarch64_attribute_info aarch64_attributes[] =
      OPT_mtune_ },
   { "sign-return-address", aarch64_attr_enum, false, NULL,
      OPT_msign_return_address_ },
+  { "outline-atomics", aarch64_attr_bool, true, NULL,
+     OPT_moutline_atomics},
   { NULL, aarch64_attr_custom, false, NULL, OPT____ }
 };
 
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 2ab45763a6b..bef02fc0b29 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -3655,6 +3655,12 @@ Select the function scope on which return address signing will be applied.  The
 behavior and permissible arguments are the same as for the command-line option
 @option{-msign-return-address=}.  The default value is @code{none}.
 
+@item outline-atomics
+@cindex @code{outline-atomics} function attribute, AArch64
+Enable or disable calls to out-of-line helpers to implement atomic operations.
+This corresponds to the behavior of the command line options
+@option{-moutline-atomics} and @option{-mno-outline-atomics}.
+
 @end table
 
 The above target attributes can be specified as follows:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 090eb019106..8898202f114 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-05-21  Martin Liska  <mliska@suse.cz>
+
+	* gcc.target/aarch64/target_attr_20.c: New test.
+	* gcc.target/aarch64/target_attr_21.c: New test.
+
 2020-05-20  Mark Eggleston  <markeggleston@gcc.gnu.org>
 
 	Backport from master
diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_20.c b/gcc/testsuite/gcc.target/aarch64/target_attr_20.c
new file mode 100644
index 00000000000..509fb039e84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_20.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+nolse -moutline-atomics" } */
+
+int b, c, d, e, f, h;
+short g;
+int foo (int) __attribute__ ((__const__));
+
+__attribute__ ((target ("no-outline-atomics")))
+void
+bar (void)
+{
+  while (1)
+    {
+      while (1)
+	{
+	  __atomic_load_n (&e, 0);
+	  if (foo (2))
+	    __sync_val_compare_and_swap (&c, 0, f);
+	  b = 1;
+	  if (h == e)
+	    break;
+	}
+      __sync_val_compare_and_swap (&g, -1, f);
+    }
+}
+
+/* { dg-final { scan-assembler-not "bl.*__aarch64_cas2_acq_rel" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_21.c b/gcc/testsuite/gcc.target/aarch64/target_attr_21.c
new file mode 100644
index 00000000000..acace4c8f2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_21.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+nolse -mno-outline-atomics" } */
+
+int b, c, d, e, f, h;
+short g;
+int foo (int) __attribute__ ((__const__));
+
+__attribute__ ((target ("outline-atomics")))
+void
+bar (void)
+{
+  while (1)
+    {
+      while (1)
+	{
+	  __atomic_load_n (&e, 0);
+	  if (foo (2))
+	    __sync_val_compare_and_swap (&c, 0, f);
+	  b = 1;
+	  if (h == e)
+	    break;
+	}
+      __sync_val_compare_and_swap (&g, -1, f);
+    }
+}
+
+/* { dg-final { scan-assembler-times "bl.*__aarch64_cas2_acq_rel" 1 } } */

commit f26cfe27e19eeb538675ffb2de0503b760662261
Author: Martin Liska <mliska@suse.cz>
Date:   Thu May 21 16:53:35 2020 +0200

    Fix backport due to usage for x_target_flags.
    
    gcc/ChangeLog:
    
            * common/config/aarch64/aarch64-common.c (aarch64_handle_option):
            Use MASK_OUTLINE_ATOMICS for x_target_flags.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eded702d1ff..7a6c2ea8908 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-05-21  Martin Liska  <mliska@suse.cz>
+
+	* common/config/aarch64/aarch64-common.c (aarch64_handle_option):
+	Use MASK_OUTLINE_ATOMICS for x_target_flags.
+
 2020-05-21  Martin Liska  <mliska@suse.cz>
 
 	* common/config/aarch64/aarch64-common.c (aarch64_handle_option):
diff --git a/gcc/common/config/aarch64/aarch64-common.c b/gcc/common/config/aarch64/aarch64-common.c
index eaa90406c60..21e7820cdb4 100644
--- a/gcc/common/config/aarch64/aarch64-common.c
+++ b/gcc/common/config/aarch64/aarch64-common.c
@@ -111,7 +111,10 @@ aarch64_handle_option (struct gcc_options *opts,
       return true;
 
     case OPT_moutline_atomics:
-      opts->x_aarch64_flag_outline_atomics = val;
+      if (val)
+	opts->x_target_flags |= MASK_OUTLINE_ATOMICS;
+      else
+	opts->x_target_flags &= ~MASK_OUTLINE_ATOMICS;
       return true;
 
     default:

commit 5d1d79fd3f89c902207992e7843ae37505e79d29
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri May 22 00:17:09 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index bf0113a0c6e..c444971dd5d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200521
+20200522

commit b732ebc9ce61151fc7eca52d1b84c3b7227422e7
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat May 23 00:17:12 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c444971dd5d..41b7769d36e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200522
+20200523

commit 18ff359bc9bb4cf4ae49004bd214e36e11de41df
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun May 24 00:17:19 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 41b7769d36e..a352902ec65 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200523
+20200524

commit 0055fa9a7b7239c50e6067724f28e64eceadd0fe
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Fri May 22 04:18:34 2020 -0700

    x86: Handle -mavx512vpopcntdq for -march=native
    
    Add -mavx512vpopcntdq for -march=native if AVX512VPOPCNTDQ is available.
    
            PR target/95258
            * config/i386/driver-i386.c (host_detect_local_cpu): Detect
            AVX512VPOPCNTDQ.
    
    (cherry picked from commit 808b611bfb4b05703ea174e50874c711dca44c98)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7a6c2ea8908..956ad8b39fe 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-05-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/95258
+	* config/i386/driver-i386.c (host_detect_local_cpu): Detect
+	AVX512VPOPCNTDQ.
+
 2020-05-21  Martin Liska  <mliska@suse.cz>
 
 	* common/config/aarch64/aarch64-common.c (aarch64_handle_option):
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 704cadd8fcf..97eaf68442d 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -420,6 +420,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
   unsigned int has_avx5124fmaps = 0, has_avx5124vnniw = 0;
   unsigned int has_gfni = 0, has_avx512vbmi2 = 0;
   unsigned int has_avx512bitalg = 0;
+  unsigned int has_avx512vpopcntdq = 0;
   unsigned int has_shstk = 0;
   unsigned int has_avx512vnni = 0, has_vaes = 0;
   unsigned int has_vpclmulqdq = 0;
@@ -519,6 +520,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       has_vaes = ecx & bit_VAES;
       has_vpclmulqdq = ecx & bit_VPCLMULQDQ;
       has_avx512bitalg = ecx & bit_AVX512BITALG;
+      has_avx512vpopcntdq = ecx & bit_AVX512VPOPCNTDQ;
       has_movdiri = ecx & bit_MOVDIRI;
       has_movdir64b = ecx & bit_MOVDIR64B;
 
@@ -1098,6 +1100,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       const char *vaes = has_vaes ? " -mvaes" : " -mno-vaes";
       const char *vpclmulqdq = has_vpclmulqdq ? " -mvpclmulqdq" : " -mno-vpclmulqdq";
       const char *avx512bitalg = has_avx512bitalg ? " -mavx512bitalg" : " -mno-avx512bitalg";
+      const char *avx512vpopcntdq = has_avx512vpopcntdq ? " -mavx512vpopcntdq" : " -mno-avx512vpopcntdq";
       const char *movdiri = has_movdiri ? " -mmovdiri" : " -mno-movdiri";
       const char *movdir64b = has_movdir64b ? " -mmovdir64b" : " -mno-movdir64b";
       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
@@ -1112,7 +1115,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 			avx512ifma, avx512vbmi, avx5124fmaps, avx5124vnniw,
 			clwb, mwaitx, clzero, pku, rdpid, gfni, shstk,
 			avx512vbmi2, avx512vnni, vaes, vpclmulqdq,
-			avx512bitalg, movdiri, movdir64b, NULL);
+			avx512bitalg, avx512vpopcntdq, movdiri, movdir64b,
+			NULL);
     }
 
 done:

commit 341e59fef8d4b9c86f1c95abfe3ed60482293f23
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon May 25 00:17:20 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a352902ec65..3d6d20ac122 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200524
+20200525

commit 487f16a7f2a6f849497a0d2f8fff61225e2270f6
Author: Jason Merrill <jason@redhat.com>
Date:   Mon May 25 18:38:09 2020 -0400

    c++: generic lambda and -fsanitize=vla-bound [PR93822]
    
    Within the generic lambda the VLA capture proxy VAR_DECL has DECL_VALUE_EXPR
    which is a NOP_EXPR to the VLA type of the proxy.  The problem here was that
    when instantiating we were tsubsting that type twice, once for the type of
    the DECL and once for the type of the NOP_EXPR, and getting two
    different (though equivalent) types.  Then gimplify_type_sizes fixed up the
    type of the DECL, but that didn't affect the type of the NOP_EXPR, leading
    to sadness.
    
    Fixed by directly reusing the type from the DECL.
    
    gcc/cp/ChangeLog
    2020-05-01  Jason Merrill  <jason@redhat.com>
    
            PR c++/93822
            * pt.c (tsubst_decl): Make sure DECL_VALUE_EXPR continues to have
            the same type as the variable.

diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index 4673c27468e..2d38310f1fb 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -13817,6 +13817,11 @@ tsubst_decl (tree t, tree args, tsubst_flags_t complain)
 	    if (DECL_HAS_VALUE_EXPR_P (t))
 	      {
 		tree ve = DECL_VALUE_EXPR (t);
+		/* If the DECL_VALUE_EXPR is converted to the declared type,
+		   preserve the identity so that gimplify_type_sizes works.  */
+		bool nop = (TREE_CODE (ve) == NOP_EXPR);
+		if (nop)
+		  ve = TREE_OPERAND (ve, 0);
 		ve = tsubst_expr (ve, args, complain, in_decl,
 				  /*constant_expression_p=*/false);
 		if (REFERENCE_REF_P (ve))
@@ -13824,6 +13829,10 @@ tsubst_decl (tree t, tree args, tsubst_flags_t complain)
 		    gcc_assert (TREE_CODE (type) == REFERENCE_TYPE);
 		    ve = TREE_OPERAND (ve, 0);
 		  }
+		if (nop)
+		  ve = build_nop (type, ve);
+		else
+		  gcc_checking_assert (TREE_TYPE (ve) == type);
 		SET_DECL_VALUE_EXPR (r, ve);
 	      }
 	    if (CP_DECL_THREAD_LOCAL_P (r)

commit 09831707ce65606f951c97632d882f083ad3ed02
Author: Jason Merrill <jason@redhat.com>
Date:   Mon May 25 18:38:09 2020 -0400

    c++: -fmerge-all-constants vs. destructors [PR91529]
    
    cp_finish_decl avoids setting TREE_READONLY on TREE_STATIC variables that
    have non-constant construction or destruction, but -fmerge-all-constants was
    converting an automatic variable to static while leaving TREE_READONLY set.
    
    Fixed by clearing the flag in cp_finish_decl in the presence of
    -fmerge-all-constants.
    
    gcc/cp/ChangeLog
    2020-05-01  Jason Merrill  <jason@redhat.com>
    
            PR c++/91529
            * decl.c (cp_finish_decl): Also clear TREE_READONLY if
            -fmerge-all-constants.

diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c
index 5642791446f..f2b52fb674e 100644
--- a/gcc/cp/decl.c
+++ b/gcc/cp/decl.c
@@ -7250,7 +7250,10 @@ cp_finish_decl (tree decl, tree init, bool init_const_expr_p,
       /* This needs to happen after the linkage is set. */
       determine_visibility (decl);
 
-      if (var_definition_p && TREE_STATIC (decl))
+      if (var_definition_p
+	  /* With -fmerge-all-constants, gimplify_init_constructor
+	     might add TREE_STATIC to the variable.  */
+	  && (TREE_STATIC (decl) || flag_merge_constants >= 2))
 	{
 	  /* If a TREE_READONLY variable needs initialization
 	     at runtime, it is no longer readonly and we need to
diff --git a/gcc/testsuite/g++.dg/init/const14.C b/gcc/testsuite/g++.dg/init/const14.C
new file mode 100644
index 00000000000..f29c7e58cfc
--- /dev/null
+++ b/gcc/testsuite/g++.dg/init/const14.C
@@ -0,0 +1,14 @@
+// PR c++/91529
+// { dg-do run }
+// { dg-additional-options -fmerge-all-constants }
+
+struct A
+{
+  int i[2];
+  ~A() { i[0] = 0; }
+};
+
+int main()
+{
+  const A a = { 1,2 };
+}

commit bc721725161c6ee3813870a734c0b0c18429a922
Author: Jason Merrill <jason@redhat.com>
Date:   Mon May 25 18:38:09 2020 -0400

    c++: Local class DMI using local static [PR90749]
    
    For default member initializers in templates it's important to push into the
    right context during get_nsdmi.  But for a local class that's not possible,
    and trying leaves the function context we need to be in, so don't try.
    
    gcc/cp/ChangeLog
    2020-05-01  Jason Merrill  <jason@redhat.com>
    
            PR c++/90749
            * init.c (get_nsdmi): Don't push_to_top_level for a local class.

diff --git a/gcc/cp/init.c b/gcc/cp/init.c
index 1a2a1f58819..7bd3f0e548b 100644
--- a/gcc/cp/init.c
+++ b/gcc/cp/init.c
@@ -587,16 +587,18 @@ get_nsdmi (tree member, bool in_ctor, tsubst_flags_t complain)
 	  DECL_INSTANTIATING_NSDMI_P (member) = 1;
 
 	  bool pushed = false;
-	  if (!currently_open_class (DECL_CONTEXT (member)))
+	  tree ctx = DECL_CONTEXT (member);
+	  if (!currently_open_class (ctx)
+	      && !LOCAL_CLASS_P (ctx))
 	    {
 	      push_to_top_level ();
-	      push_nested_class (DECL_CONTEXT (member));
+	      push_nested_class (ctx);
 	      pushed = true;
 	    }
 
 	  gcc_checking_assert (!processing_template_decl);
 
-	  inject_this_parameter (DECL_CONTEXT (member), TYPE_UNQUALIFIED);
+	  inject_this_parameter (ctx, TYPE_UNQUALIFIED);
 
 	  start_lambda_scope (member);
 
diff --git a/gcc/testsuite/g++.dg/cpp0x/nsdmi-template20.C b/gcc/testsuite/g++.dg/cpp0x/nsdmi-template20.C
new file mode 100644
index 00000000000..06448d92f12
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/nsdmi-template20.C
@@ -0,0 +1,13 @@
+// PR c++/90479
+// { dg-do compile { target c++11 } }
+
+template <int n>
+void foo ()
+{
+  static int i {100};
+  struct { int a {i++}; } b {};
+}
+int main ()
+{
+  foo<0> ();
+}

commit 4b33a9faae8dd2e6cacb1e3d39734ea3b0c51e3e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue May 26 00:17:22 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3d6d20ac122..997e5b57791 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200525
+20200526

commit dd9f457caeb2693a3172380b5211982bba98124c
Author: Martin Liska <mliska@suse.cz>
Date:   Tue May 26 09:40:09 2020 +0200

    Add missing ChangeLog entries.

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index ebebbe29e38..311cc43936d 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,20 @@
+2020-05-25  Jason Merrill  <jason@redhat.com>
+
+	PR c++/90749
+	* init.c (get_nsdmi): Don't push_to_top_level for a local class.
+
+2020-05-25  Jason Merrill  <jason@redhat.com>
+
+	PR c++/91529
+	* decl.c (cp_finish_decl): Also clear TREE_READONLY if
+	-fmerge-all-constants.
+
+2020-05-25  Jason Merrill  <jason@redhat.com>
+
+	PR c++/93822
+	* pt.c (tsubst_decl): Make sure DECL_VALUE_EXPR continues to have
+	the same type as the variable.
+
 2020-05-04  Marek Polacek  <polacek@redhat.com>
 
 	Backported from mainline
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8898202f114..66d288eaddd 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2020-05-25  Jason Merrill  <jason@redhat.com>
+
+	PR c++/90749
+	* g++.dg/cpp0x/nsdmi-template20.C: New file.
+
+2020-05-25  Jason Merrill  <jason@redhat.com>
+
+	PR c++/91529
+	* g++.dg/init/const14.C: New file.
+
 2020-05-21  Martin Liska  <mliska@suse.cz>
 
 	* gcc.target/aarch64/target_attr_20.c: New test.

commit d8465ff121d9c01cfef6ae0068274eea0c53ca02
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed May 27 07:47:00 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 997e5b57791..b7b667a34d1 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200526
+20200527

commit b22157432d5ce4f80ab832aab6c8a071a1e76623
Author: Martin Liska <mliska@suse.cz>
Date:   Tue May 26 15:32:32 2020 +0200

    Add new git-backport.py script.
    
    contrib/ChangeLog:
    
            * git-backport.py: New file.

diff --git a/contrib/git-backport.py b/contrib/git-backport.py
new file mode 100755
index 00000000000..6a115c34d40
--- /dev/null
+++ b/contrib/git-backport.py
@@ -0,0 +1,60 @@
+#!/usr/bin/env python3
+
+# Copyright (C) 2020 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING.  If not, write to
+# the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+# Boston, MA 02110-1301, USA.
+
+import argparse
+import subprocess
+
+if __name__ == '__main__':
+    parser = argparse.ArgumentParser(description='Backport a git revision and '
+                                     'stash all ChangeLog files.')
+    parser.add_argument('revision', help='Revision')
+    args = parser.parse_args()
+
+    r = subprocess.run('git cherry-pick -x %s' % args.revision, shell=True)
+    if r.returncode == 0:
+        cmd = 'git show --name-only --pretty="" -- "*ChangeLog" |' \
+              'xargs git checkout HEAD~'
+        subprocess.check_output(cmd, shell=True)
+        subprocess.check_output('git commit --amend --no-edit', shell=True)
+    else:
+        # 1) remove all ChangeLog files from conflicts
+        out = subprocess.check_output('git diff --name-only --diff-filter=U',
+                                      shell=True,
+                                      encoding='utf8')
+        conflicts = out.strip().split('\n')
+        changelogs = [c for c in conflicts if c.endswith('ChangeLog')]
+        if changelogs:
+            cmd = 'git checkout --theirs %s' % '\n'.join(changelogs)
+            subprocess.check_output(cmd, shell=True)
+        # 2) remove all ChangeLog files from index
+        cmd = 'git diff --name-only --diff-filter=M HEAD'
+        out = subprocess.check_output(cmd, shell=True, encoding='utf8')
+        out = out.strip().split('\n')
+        modified = [c for c in out if c.endswith('ChangeLog')]
+        for m in modified:
+            subprocess.check_output('git reset %s' % m, shell=True)
+            subprocess.check_output('git checkout %s' % m, shell=True)
+
+        # try to continue
+        if len(conflicts) == len(changelogs):
+            subprocess.check_output('git cherry-pick --continue', shell=True)
+        else:
+            print('Please resolve all remaining file conflicts.')

commit 77690650eddf4cd789c3d94de0d3c80d71f21a0c
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu May 28 04:25:02 2020 +0000

    Daily bump.

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index e6dc6514fbe..2315d51a89e 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,7 @@
+2020-05-27  Martin Liska  <mliska@suse.cz>
+
+	* git-backport.py: New file.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b7b667a34d1..5118880926f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200527
+20200528

commit 83b84b6ef84ffc0ca25aef5c91720d8f82212a5c
Author: Mark Eggleston <markeggleston@gcc.gnu.org>
Date:   Thu May 7 08:15:26 2020 +0100

    Fortran  : ICE in gfc_trans_label_assign PR50392
    
    A function may contain an assigned goto.  If the the return variable
    is an integer a statement can be assigned to it.  Prior to this fix
    this resulted in an ICE.
    
    2020-05-28  Tobias Burnus  <tobias@codesourcery.com>
    
    gcc/fortran/
    
            PR fortran/50392
            * trans-decl.c (gfc_get_symbol_decl): Remove unnecessary block
            delimiters.  Add auxiliary variables if a label is assigned to
            a return variable. (gfc_gat_fake_result): If the symbol has an
            assign attribute set declaration from the symbol's backend
            declaration.
    
    2020-05-28  Mark Eggleston  <markeggleston@gnu.gcc.org>
    
    gcc/testsuite/
    
            PR fortran/50392
            * gfortran.dg/pr50392.f: New test.
    
    (cherry picked from commit a7fd43c38f7469a3ef5ee30e889d60e1376d4dfc)

diff --git a/gcc/fortran/trans-decl.c b/gcc/fortran/trans-decl.c
index 30ed449e12f..3780d27a9f6 100644
--- a/gcc/fortran/trans-decl.c
+++ b/gcc/fortran/trans-decl.c
@@ -1673,9 +1673,7 @@ gfc_get_symbol_decl (gfc_symbol * sym)
 
       TREE_USED (sym->backend_decl) = 1;
       if (sym->attr.assign && GFC_DECL_ASSIGN (sym->backend_decl) == 0)
-	{
-	  gfc_add_assign_aux_vars (sym);
-	}
+	gfc_add_assign_aux_vars (sym);
 
       if ((sym->attr.dimension || IS_CLASS_ARRAY (sym))
 	  && DECL_LANG_SPECIFIC (sym->backend_decl)
@@ -1689,6 +1687,10 @@ gfc_get_symbol_decl (gfc_symbol * sym)
      return sym->backend_decl;
     }
 
+  if (sym->result == sym && sym->attr.assign
+      && GFC_DECL_ASSIGN (sym->backend_decl) == 0)
+    gfc_add_assign_aux_vars (sym);
+
   if (sym->backend_decl)
     return sym->backend_decl;
 
@@ -3142,6 +3144,9 @@ gfc_get_fake_result_decl (gfc_symbol * sym, int parent_flag)
   else
     current_fake_result_decl = build_tree_list (NULL, decl);
 
+  if (sym->attr.assign)
+    DECL_LANG_SPECIFIC (decl) = DECL_LANG_SPECIFIC (sym->backend_decl);
+
   return decl;
 }
 
diff --git a/gcc/testsuite/gfortran.dg/pr50392.f b/gcc/testsuite/gfortran.dg/pr50392.f
new file mode 100644
index 00000000000..2cb883e41a3
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr50392.f
@@ -0,0 +1,12 @@
+! { dg-do compile }
+! 
+      function kf()
+      integer kf
+      assign 1 to kf ! { dg-warning "Deleted feature: ASSIGN statement at" }
+      kf = 2
+      goto kf ! { dg-warning "Deleted feature: Assigned GOTO statement at" }
+      kf = 1
+ 1    continue
+      kf = 0
+      end
+

commit 73e995ebef836e2f9ea34517511296e4c71624ea
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri May 29 00:17:30 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 5118880926f..065a3b85610 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200528
+20200529
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index b1490c06f41..240c28bfbd8 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,13 @@
+2020-05-28  Tobias Burnus  <tobias@codesourcery.com>
+	    Mark Eggleston  <markeggleston@gnu.gcc.org>
+
+	PR fortran/50392
+	* trans-decl.c (gfc_get_symbol_decl): Remove unnecessary block
+	delimiters.  Add auxiliary variables if a label is assigned to
+	a return variable. (gfc_gat_fake_result): If the symbol has an
+	assign attribute set declaration from the symbol's backend
+	declaration.
+
 2020-05-20  Mark Eggleston  <markeggleston@gcc.gnu.org>
 
 	Backport from master
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 66d288eaddd..aadf5071c29 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-05-28  Tobias Burnus  <tobias@codesourcery.com>
+
+	PR fortran/50392
+	* gfortran.dg/pr50392.f: New test.
+
 2020-05-25  Jason Merrill  <jason@redhat.com>
 
 	PR c++/90749

commit b721e2855d92372ab1efbc7e35cf0a71ceb35b80
Author: Martin Liska <mliska@suse.cz>
Date:   Fri May 29 11:29:25 2020 +0200

    Fix various limitations of git-backport.py.
    
    I've just tested the script and I'm going to install the patch
    to all active branches.
    
    contrib/ChangeLog:
    
            * git-backport.py: The script did 'git co HEAD~' when
            there was no modified ChangeLog file in a successful
            git cherry pick.
            Run cherry-pick --continue without editor.
    
    (cherry picked from commit 24663f1f6d709daf8913484914ed01af9f7a480a)

diff --git a/contrib/git-backport.py b/contrib/git-backport.py
index 6a115c34d40..3a9413dcd27 100755
--- a/contrib/git-backport.py
+++ b/contrib/git-backport.py
@@ -30,9 +30,13 @@ if __name__ == '__main__':
 
     r = subprocess.run('git cherry-pick -x %s' % args.revision, shell=True)
     if r.returncode == 0:
-        cmd = 'git show --name-only --pretty="" -- "*ChangeLog" |' \
-              'xargs git checkout HEAD~'
-        subprocess.check_output(cmd, shell=True)
+        cmd = 'git show --name-only --pretty="" -- "*ChangeLog"'
+        changelogs = subprocess.check_output(cmd, shell=True, encoding='utf8')
+        changelogs = changelogs.strip()
+        if changelogs:
+            for changelog in changelogs.split('\n'):
+                subprocess.check_output('git checkout HEAD~ %s' % changelog,
+                                        shell=True)
         subprocess.check_output('git commit --amend --no-edit', shell=True)
     else:
         # 1) remove all ChangeLog files from conflicts
@@ -55,6 +59,7 @@ if __name__ == '__main__':
 
         # try to continue
         if len(conflicts) == len(changelogs):
-            subprocess.check_output('git cherry-pick --continue', shell=True)
+            cmd = 'git -c core.editor=true cherry-pick --continue'
+            subprocess.check_output(cmd, shell=True)
         else:
             print('Please resolve all remaining file conflicts.')

commit 406f6d0ad7325f872c4a084d360196302029fbeb
Author: Martin Liska <mliska@suse.cz>
Date:   Thu May 28 08:16:58 2020 +0200

    gcov-tool: Flexible endian adjustment for merging coverage data
    
    gcc/ChangeLog:
    2020-05-27  Dong JianQiang  <dongjianqiang2@huawei.com>
    
            PR gcov-profile/95332
            * gcov-io.c (gcov_var::endian): Move field.
            (from_file): Add IN_GCOV_TOOL check.
            * gcov-io.h (gcov_magic): Ditto.
    
    libgcc/ChangeLog:
    2020-05-27  Dong JianQiang  <dongjianqiang2@huawei.com>
    
            PR gcov-profile/95332
            * libgcov-util.c (read_gcda_file): Call gcov_magic.
            * libgcov.h (gcov_magic): Disable GCC poison.
    
    (cherry picked from commit 17d1594bfe08f3c768e024b180816cbe37ac08ac)

diff --git a/gcc/gcov-io.c b/gcc/gcov-io.c
index 3fe1e613ebc..56d8e41fbca 100644
--- a/gcc/gcov-io.c
+++ b/gcc/gcov-io.c
@@ -48,6 +48,7 @@ struct gcov_var
   unsigned overread;		/* Number of words overread.  */
   int error;			/* < 0 overflow, > 0 disk error.  */
   int mode;	                /* < 0 writing, > 0 reading */
+  int endian;			/* Swap endianness.  */
 #if IN_LIBGCOV
   /* Holds one block plus 4 bytes, thus all coverage reads & writes
      fit within this buffer and we always can transfer GCOV_BLOCK_SIZE
@@ -55,7 +56,6 @@ struct gcov_var
      or 8 byte objects.  */
   gcov_unsigned_t buffer[GCOV_BLOCK_SIZE + 1];
 #else
-  int endian;			/* Swap endianness.  */
   /* Holds a variable length block, as the compiler can write
      strings and needs to backtrack.  */
   size_t alloc;
@@ -100,7 +100,7 @@ gcov_rewrite (void)
 
 static inline gcov_unsigned_t from_file (gcov_unsigned_t value)
 {
-#if !IN_LIBGCOV
+#if !IN_LIBGCOV || defined (IN_GCOV_TOOL)
   if (gcov_var.endian)
     {
       value = (value >> 16) | (value << 16);
@@ -222,7 +222,7 @@ gcov_close (void)
   return gcov_var.error;
 }
 
-#if !IN_LIBGCOV
+#if !IN_LIBGCOV || defined (IN_GCOV_TOOL)
 /* Check if MAGIC is EXPECTED. Use it to determine endianness of the
    file. Returns +1 for same endian, -1 for other endian and zero for
    not EXPECTED.  */
diff --git a/gcc/gcov-io.h b/gcc/gcov-io.h
index d6389c48908..b239651f1fe 100644
--- a/gcc/gcov-io.h
+++ b/gcc/gcov-io.h
@@ -370,6 +370,9 @@ struct gcov_summary
 
 #if !IN_LIBGCOV
 GCOV_LINKAGE int gcov_open (const char */*name*/, int /*direction*/);
+#endif
+
+#if !IN_LIBGCOV || defined (IN_GCOV_TOOL)
 GCOV_LINKAGE int gcov_magic (gcov_unsigned_t, gcov_unsigned_t);
 #endif
 
diff --git a/libgcc/libgcov-util.c b/libgcc/libgcov-util.c
index 9cf56a82859..9ff973cd488 100644
--- a/libgcc/libgcov-util.c
+++ b/libgcc/libgcov-util.c
@@ -259,7 +259,7 @@ read_gcda_file (const char *filename)
 {
   unsigned tags[4];
   unsigned depth = 0;
-  unsigned magic, version;
+  unsigned version;
   struct gcov_info *obj_info;
   int i;
 
@@ -274,8 +274,7 @@ read_gcda_file (const char *filename)
     }
 
   /* Read magic.  */
-  magic = gcov_read_unsigned ();
-  if (magic != GCOV_DATA_MAGIC)
+  if (!gcov_magic (gcov_read_unsigned (), GCOV_DATA_MAGIC))
     {
       fnotice (stderr, "%s:not a gcov data file\n", filename);
       gcov_close ();
diff --git a/libgcc/libgcov.h b/libgcc/libgcov.h
index 21422873cf2..ded98862797 100644
--- a/libgcc/libgcov.h
+++ b/libgcc/libgcov.h
@@ -149,7 +149,7 @@ extern struct gcov_info *gcov_list;
 
 /* Poison these, so they don't accidentally slip in.  */
 #pragma GCC poison gcov_write_string gcov_write_tag gcov_write_length
-#pragma GCC poison gcov_time gcov_magic
+#pragma GCC poison gcov_time
 
 #ifdef HAVE_GAS_HIDDEN
 #define ATTRIBUTE_HIDDEN  __attribute__ ((__visibility__ ("hidden")))

commit d0d2a937abf6ea0e03bfd7cb56c0f976ba03cbf1
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed May 6 16:20:38 2020 +0100

    [AArch64] Use __getauxval instead of getauxval in LSE detection code in libgcc
    
    This version of the fix uses __getauxval instead of getauxval.
    The whole thing is guarded simply on __gnu_linux__.
    __getauxval was introduced in 2.16 but the aarch64 port was added in 2.17 so in practice I expect all aarch64 glibcs to support __getauxval.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    Also tested on aarch64-none-elf.
    
    2020-05-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
    
            * config/aarch64/lse-init.c (init_have_lse_atomics): Use __getauxval
            instead of getauxval.
            (AT_HWCAP): Define.
            (HWCAP_ATOMICS): Define.
            Guard detection on __gnu_linux__.
    
    (cherry picked from commit 1266778548e20de82983b6446f3cb685068cfb1e)

diff --git a/libgcc/config/aarch64/lse-init.c b/libgcc/config/aarch64/lse-init.c
index 1a8f4c55213..2f2921349e7 100644
--- a/libgcc/config/aarch64/lse-init.c
+++ b/libgcc/config/aarch64/lse-init.c
@@ -29,19 +29,20 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 _Bool __aarch64_have_lse_atomics
   __attribute__((visibility("hidden"), nocommon));
 
-/* Disable initialization of __aarch64_have_lse_atomics during bootstrap.  */
-#if !defined(inhibit_libc) && defined(HAVE_SYS_AUXV_H)
-# include <sys/auxv.h>
+/* Gate availability of __getauxval on glibc.  All AArch64-supporting glibc
+   versions support it.  */
+#ifdef __gnu_linux__
 
-/* Disable initialization if the system headers are too old.  */
-# if defined(AT_HWCAP) && defined(HWCAP_ATOMICS)
+# define AT_HWCAP	16
+# define HWCAP_ATOMICS	(1 << 8)
+
+unsigned long int __getauxval (unsigned long int);
 
 static void __attribute__((constructor))
 init_have_lse_atomics (void)
 {
-  unsigned long hwcap = getauxval (AT_HWCAP);
+  unsigned long hwcap = __getauxval (AT_HWCAP);
   __aarch64_have_lse_atomics = (hwcap & HWCAP_ATOMICS) != 0;
 }
 
-# endif /* HWCAP */
-#endif /* inhibit_libc */
+#endif /* __gnu_linux__  */

commit b64ec9c3eea5204b90936e332704e6f57470f6e5
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Fri May 29 14:23:02 2020 +0100

    aarch64: PR target/94591: Don't generate invalid REV64 insns
    
    This fixes PR94591. The problem was the function
    aarch64_evpc_rev_local() matching vector permutations that were not
    reversals. In particular, prior to this patch, this function matched the
    identity permutation which led to generating bogus REV64 insns which
    were rejected by the assembler.
    
    gcc/
            PR target/94591
            * config/aarch64/aarch64.c (aarch64_evpc_rev_local): Don't match
            identity permutation.
    
    gcc/testsuite/
            PR target/94591
            * gcc.c-torture/execute/pr94591.c: New test.
    
    (cherry picked from commit 98452668d362bb9e6358f7eb5cff69f4f5ab1d45)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index ad339ab1d54..14ed69f460d 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -15294,7 +15294,8 @@ aarch64_evpc_rev_local (struct expand_vec_perm_d *d)
 
   if (d->vec_flags == VEC_SVE_PRED
       || !d->one_vector_p
-      || !d->perm[0].is_constant (&diff))
+      || !d->perm[0].is_constant (&diff)
+      || !diff)
     return false;
 
   size = (diff + 1) * GET_MODE_UNIT_SIZE (d->vmode);
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr94591.c b/gcc/testsuite/gcc.c-torture/execute/pr94591.c
new file mode 100644
index 00000000000..42271ad8bce
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr94591.c
@@ -0,0 +1,32 @@
+typedef unsigned __attribute__((__vector_size__(8))) V2SI_u;
+typedef int __attribute__((__vector_size__(8))) V2SI_d;
+
+typedef unsigned long __attribute__((__vector_size__(16))) V2DI_u;
+typedef long __attribute__((__vector_size__(16))) V2DI_d;
+
+void id_V2SI(V2SI_d *v)
+{
+  *v = __builtin_shuffle(*v, (V2SI_d)(V2SI_u) { 0, 1 });
+}
+
+void id_V2DI(V2DI_d *v)
+{
+  *v = __builtin_shuffle(*v, (V2DI_d)(V2DI_u) { 0, 1 });
+}
+
+extern void abort(void);
+
+int main(void)
+{
+  V2SI_d si = { 35, 42 };
+  id_V2SI(&si);
+
+  if (si[0] != 35 || si[1] != 42)
+    abort();
+
+  V2DI_d di = { 63, 38 };
+  id_V2DI(&di);
+
+  if (di[0] != 63 || di[1] != 38)
+    abort();
+}

commit e120b454c310311a659b87bcfe5cd2bb39c75f13
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat May 30 00:17:38 2020 +0000

    Daily bump.

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index 2315d51a89e..3e0a7a4a147 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,10 @@
+2020-05-29  Martin Liska  <mliska@suse.cz>
+
+	* git-backport.py: The script did 'git co HEAD~' when
+	there was no modified ChangeLog file in a successful
+	git cherry pick.
+	Run cherry-pick --continue without editor.
+
 2020-05-27  Martin Liska  <mliska@suse.cz>
 
 	* git-backport.py: New file.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 956ad8b39fe..fe3fd974880 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2020-05-29  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/94591
+	* config/aarch64/aarch64.c (aarch64_evpc_rev_local): Don't match
+	identity permutation.
+
+2020-05-29  Dong JianQiang  <dongjianqiang2@huawei.com>
+
+	PR gcov-profile/95332
+	* gcov-io.c (gcov_var::endian): Move field.
+	(from_file): Add IN_GCOV_TOOL check.
+	* gcov-io.h (gcov_magic): Ditto.
+
 2020-05-24  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/95258
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 065a3b85610..cadcec3f8ad 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200529
+20200530
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index aadf5071c29..8038e5798d5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-05-29  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/94591
+	* gcc.c-torture/execute/pr94591.c: New test.
+
 2020-05-28  Tobias Burnus  <tobias@codesourcery.com>
 
 	PR fortran/50392
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 030e4d7ee24..2d7e900a653 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,17 @@
+2020-05-29  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/lse-init.c (init_have_lse_atomics): Use __getauxval
+	instead of getauxval.
+	(AT_HWCAP): Define.
+	(HWCAP_ATOMICS): Define.
+	Guard detection on __gnu_linux__.
+
+2020-05-29  Dong JianQiang  <dongjianqiang2@huawei.com>
+
+	PR gcov-profile/95332
+	* libgcov-util.c (read_gcda_file): Call gcov_magic.
+	* libgcov.h (gcov_magic): Disable GCC poison.
+
 2020-05-20  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from master

commit c3169253d97b1ab0b09e8d42bee2dc027e97429d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun May 31 00:17:31 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index cadcec3f8ad..6ac640bbe01 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200530
+20200531

commit b801fb54a13532e37e2e2102f7e3f3398038db2d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jun 1 00:17:35 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6ac640bbe01..babac42a65f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200531
+20200601

commit 75f5824b77632ef583a7a65302b326e8bf1b851c
Author: Thomas Koenig <tkoenig@gcc.gnu.org>
Date:   Sun May 31 10:26:40 2020 +0200

    Finalization depends on the expression, not on the component.
    
    This patch fixes a 8/9/10/11 regression, where finalized types
    were not finalized (and deallocated), which led to memory
    leaks.
    
    gcc/fortran/ChangeLog:
    
    2020-05-24  Thomas Koenig  <tkoenig@gcc.gnu.org>
    
            PR fortran/94361
            * class.c (finalize_component): Use expr->finalized instead of
            comp->finalized.
            * gfortran.h (gfc_component): Remove finalized member.
            (gfc_expr): Add it here instead.
    
    gcc/testsuite/ChangeLog:
    
    2020-05-24  Thomas Koenig  <tkoenig@gcc.gnu.org>
    
            PR fortran/94361
            * gfortran.dg/finalize_28.f90: Adjusted free counts.
            * gfortran.dg/finalize_34.f90: Likewise.
            * gfortran.dg/finalize_35.f90: New test.
    
    (cherry picked from commit 2a0de88ccf2ecc6659b0f1e4580c1ce5cff976b3)

diff --git a/- b/-
new file mode 100644
index 00000000000..61f10ee21d6
--- /dev/null
+++ b/-
@@ -0,0 +1 @@
+ChangeLog*	merge=merge-changelog
diff --git a/gcc/fortran/class.c b/gcc/fortran/class.c
index 23a0468dedd..90563cac7b0 100644
--- a/gcc/fortran/class.c
+++ b/gcc/fortran/class.c
@@ -907,7 +907,7 @@ finalize_component (gfc_expr *expr, gfc_symbol *derived, gfc_component *comp,
   if (!comp_is_finalizable (comp))
     return;
 
-  if (comp->finalized)
+  if (expr->finalized)
     return;
 
   e = gfc_copy_expr (expr);
@@ -998,6 +998,7 @@ finalize_component (gfc_expr *expr, gfc_symbol *derived, gfc_component *comp,
 	}
       else
 	(*code) = cond;
+
     }
   else if (comp->ts.type == BT_DERIVED
 	    && comp->ts.u.derived->f2k_derived
@@ -1037,7 +1038,7 @@ finalize_component (gfc_expr *expr, gfc_symbol *derived, gfc_component *comp,
 			    sub_ns);
       gfc_free_expr (e);
     }
-  comp->finalized = true;
+  expr->finalized = 1;
 }
 
 
diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h
index 3d6e25a3ff4..d9ba843b096 100644
--- a/gcc/fortran/gfortran.h
+++ b/gcc/fortran/gfortran.h
@@ -1080,7 +1080,6 @@ typedef struct gfc_component
   struct gfc_typebound_proc *tb;
   /* When allocatable/pointer and in a coarray the associated token.  */
   tree caf_token;
-  bool finalized;
 }
 gfc_component;
 
@@ -2155,6 +2154,10 @@ typedef struct gfc_expr
   /* Set this if no warning should be given somewhere in a lower level.  */
 
   unsigned int do_not_warn : 1;
+
+  /* Set this if the expression has already been finalized.  */
+  unsigned int finalized : 1;
+
   /* If an expression comes from a Hollerith constant or compile-time
      evaluation of a transfer statement, it may have a prescribed target-
      memory representation, and these cannot always be backformed from
diff --git a/gcc/testsuite/gfortran.dg/finalize_28.f90 b/gcc/testsuite/gfortran.dg/finalize_28.f90
index 597413b2dd3..f0c9665252f 100644
--- a/gcc/testsuite/gfortran.dg/finalize_28.f90
+++ b/gcc/testsuite/gfortran.dg/finalize_28.f90
@@ -21,4 +21,4 @@ contains
     integer, intent(out) :: edges(:,:)
   end subroutine coo_dump_edges
 end module coo_graphs
-! { dg-final { scan-tree-dump-times "__builtin_free" 5 "original" } }
+! { dg-final { scan-tree-dump-times "__builtin_free" 6 "original" } }
diff --git a/gcc/testsuite/gfortran.dg/finalize_34.f90 b/gcc/testsuite/gfortran.dg/finalize_34.f90
index e2f02a5c51c..fef7dac6d89 100644
--- a/gcc/testsuite/gfortran.dg/finalize_34.f90
+++ b/gcc/testsuite/gfortran.dg/finalize_34.f90
@@ -22,4 +22,4 @@ program main
   use testmodule
   type(evtlist_type), dimension(10) :: a
 end program main
-! { dg-final  { scan-tree-dump-times "__builtin_free" 8 "original" } }
+! { dg-final  { scan-tree-dump-times "__builtin_free" 12 "original" } }
diff --git a/gcc/testsuite/gfortran.dg/finalize_35.f90 b/gcc/testsuite/gfortran.dg/finalize_35.f90
new file mode 100644
index 00000000000..66435c43ecc
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/finalize_35.f90
@@ -0,0 +1,48 @@
+! { dg-do compile }
+! { dg-additional-options "-fdump-tree-original" }
+! PR 94361 - this left open some memory leaks.  Original test case by
+! Antony Lewis.
+
+module debug
+  private
+
+  Type TypeWithFinal
+   contains
+     FINAL :: finalizer  !No leak if this line is commented
+  end type TypeWithFinal
+
+  Type Tester
+     real, dimension(:), allocatable :: Dat
+     Type(TypeWithFinal) :: X
+  end Type Tester
+
+  Type :: TestType2
+     Type(Tester) :: T
+  end type TestType2
+  public Leaker
+contains
+
+  subroutine Leaker
+    type(TestType2) :: Test
+
+    allocate(Test%T%Dat(1000))
+  end subroutine Leaker
+
+  subroutine finalizer(this)
+    Type(TypeWithFinal) :: this
+  end subroutine finalizer
+
+end module debug
+
+
+program run
+  use debug
+  implicit none
+  integer i
+
+  do i=1, 1000
+     call Leaker()
+  end do
+
+end program run
+! { dg-final  { scan-tree-dump-times "__builtin_free\\ \\(ptr2" 2 "original" } }

commit ac2b67cb07f19817261bb235d8cda332ce8e02ed
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jun 2 00:17:36 2020 +0000

    Daily bump.

diff --git a/ChangeLog b/ChangeLog
index 659e82a2a51..252cc911947 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2020-06-01  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	PR fortran/94361
+	* -: New file.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index babac42a65f..2bd6d2b45fc 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200601
+20200602
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 240c28bfbd8..1039aa5252e 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,11 @@
+2020-06-01  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	PR fortran/94361
+	* class.c (finalize_component): Use expr->finalized instead of
+	comp->finalized.
+	* gfortran.h (gfc_component): Remove finalized member.
+	(gfc_expr): Add it here instead.
+
 2020-05-28  Tobias Burnus  <tobias@codesourcery.com>
 	    Mark Eggleston  <markeggleston@gnu.gcc.org>
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8038e5798d5..d5e5890e4ae 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-06-01  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	PR fortran/94361
+	* gfortran.dg/finalize_28.f90: Adjusted free counts.
+	* gfortran.dg/finalize_34.f90: Likewise.
+	* gfortran.dg/finalize_35.f90: New test.
+
 2020-05-29  Alex Coplan  <alex.coplan@arm.com>
 
 	PR target/94591

commit 195e4bd2a7eeb94b53e22c48ad0cbf168158f9ad
Author: Martin Liska <mliska@suse.cz>
Date:   Tue Jun 2 08:54:54 2020 +0200

    Remove accidentally installed file.
    
    ChangeLog:
    
            * -: Remove.

diff --git a/- b/-
deleted file mode 100644
index 61f10ee21d6..00000000000
--- a/-
+++ /dev/null
@@ -1 +0,0 @@
-ChangeLog*	merge=merge-changelog

commit aafd10254f9c2025bfb23a680f52ef1c2bb297da
Author: Martin Liska <mliska@suse.cz>
Date:   Tue Jun 2 08:58:33 2020 +0200

    Remove bad ChangeLog entry.

diff --git a/ChangeLog b/ChangeLog
index 252cc911947..659e82a2a51 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,8 +1,3 @@
-2020-06-01  Thomas Koenig  <tkoenig@gcc.gnu.org>
-
-	PR fortran/94361
-	* -: New file.
-
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.

commit 60286b92fb8fbf7edaaa0d7e234c5223ac87980f
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Jun 2 17:52:16 2020 +0100

    aarch64: Add initial support for -mcpu=zeus
    
    This patch adds support for the Arm Zeus CPU.
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
    
    2020-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
    
            * config/aarch64/aarch64-cores.def (zeus): Define.
            * config/aarch64/aarch64-tune.md: Regenerate.
            * doc/invoke.texi (AArch64 Options): Document zeus -mcpu option.

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index f48b7c22b2d..eb01390c262 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -94,6 +94,11 @@ AARCH64_CORE("neoverse-n1", neoversen1,cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2
 /* Qualcomm ('Q') cores. */
 AARCH64_CORE("saphira",     saphira,    falkor,    8_3A,  AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,   0x51, 0xC01, -1)
 
+/* ARMv8.4-A Architecture Processors.  */
+
+/* ARM ('A') cores. */
+AARCH64_CORE("zeus", zeus, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE, cortexa72, 0x41, 0xd40, -1)
+
 /* ARMv8-A big.LITTLE implementations.  */
 
 AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1)
diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index f08b7e44b27..c2de5e873a7 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr "tune"
-	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55"
+	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,saphira,zeus,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55"
 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index bdad016baeb..e48ccce1c6e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14771,7 +14771,7 @@ Specify the name of the target processor for which GCC should tune the
 performance of the code.  Permissible values for this option are:
 @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
 @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
-@samp{cortex-a76}, @samp{ares}, @samp{neoverse-n1}
+@samp{cortex-a76}, @samp{ares}, @samp{neoverse-n1}, @samp{zeus},
 @samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{saphira},
 @samp{xgene1}, @samp{vulcan}, @samp{thunderx},
 @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},

commit 6f8917d0a065173de628463d11c277e5ec5066c6
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jun 3 00:17:42 2020 +0000

    Daily bump.

diff --git a/ChangeLog b/ChangeLog
index 659e82a2a51..4062e4cbf57 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,7 @@
+2020-06-02  Martin Liska  <mliska@suse.cz>
+
+	* -: Remove.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fe3fd974880..1eed9dbb77e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-cores.def (zeus): Define.
+	* config/aarch64/aarch64-tune.md: Regenerate.
+	* doc/invoke.texi (AArch64 Options): Document zeus -mcpu option.
+
 2020-05-29  Alex Coplan  <alex.coplan@arm.com>
 
 	PR target/94591
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2bd6d2b45fc..2850e546047 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200602
+20200603

commit 53c76137ab03432194fd6322429577c7f838b484
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jun 4 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2850e546047..6c883c98853 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200603
+20200604

commit f4a45e0d85e51bd6550a82f31f70484c03332a4e
Author: Thomas Schwinge <thomas@codesourcery.com>
Date:   Wed May 6 10:05:49 2020 +0200

    'libgomp.oacc-fortran/{error_,}stop-{1,2,3}.f': initialize before the checkpoint
    
    If, for example, GCC is configured such that 'libgomp-plugin-nvptx.so.1'
    dynamically links against 'libcuda.so.1', but testing is run on a system where
    there is no 'libcuda.so.1', this produces output such as:
    
        PASS: libgomp.oacc-fortran/error_stop-1.f -DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O0  (test for excess errors)
        PASS: libgomp.oacc-fortran/error_stop-1.f -DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O0  execution test
        FAIL: libgomp.oacc-fortran/error_stop-1.f -DACC_DEVICE_TYPE_host=1 -DACC_MEM_SHARED=1 -foffload=disable  -O0  output pattern test, is  CheCKpOInT
    
        libgomp: while loading libgomp-plugin-nvptx.so.1: libcuda.so.1: cannot open shared object file: No such file or directory
        ERROR STOP
    
        Error termination. Backtrace: [...]
        , should match CheCKpOInT(
        |
        |^M)+ERROR STOP (
        |
        |^M)+Error termination.*
    
    ..., where after 'CheCKpOInT' we got 'libgomp: while loading [...]' injected
    before the expected 'ERROR STOP'.
    
            libgomp/
            * testsuite/libgomp.oacc-fortran/error_stop-1.f: Initialize before
            the checkpoint.
            * testsuite/libgomp.oacc-fortran/error_stop-2.f: Likewise.
            * testsuite/libgomp.oacc-fortran/error_stop-3.f: Likewise.
            * testsuite/libgomp.oacc-fortran/stop-1.f: Likewise.
            * testsuite/libgomp.oacc-fortran/stop-2.f: Likewise.
            * testsuite/libgomp.oacc-fortran/stop-3.f: Likewise.
    
    (cherry picked from commit 1e378edd8f038c52914bc6cac8f6dd5a5c4f8a98)

diff --git a/libgomp/testsuite/libgomp.oacc-fortran/error_stop-1.f b/libgomp/testsuite/libgomp.oacc-fortran/error_stop-1.f
index 4965e674c27..a995d955fc2 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/error_stop-1.f
+++ b/libgomp/testsuite/libgomp.oacc-fortran/error_stop-1.f
@@ -3,6 +3,10 @@
       PROGRAM MAIN
       IMPLICIT NONE
 
+! Initialize before the checkpoint, in case this produces any output.
+!$ACC PARALLEL
+!$ACC END PARALLEL
+
       PRINT *, "CheCKpOInT"
 !$ACC PARALLEL
       ERROR STOP
diff --git a/libgomp/testsuite/libgomp.oacc-fortran/error_stop-2.f b/libgomp/testsuite/libgomp.oacc-fortran/error_stop-2.f
index 7103fdb5d8e..426c15abcdf 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/error_stop-2.f
+++ b/libgomp/testsuite/libgomp.oacc-fortran/error_stop-2.f
@@ -3,6 +3,10 @@
       PROGRAM MAIN
       IMPLICIT NONE
 
+! Initialize before the checkpoint, in case this produces any output.
+!$ACC PARALLEL
+!$ACC END PARALLEL
+
       PRINT *, "CheCKpOInT"
 !$ACC PARALLEL
       ERROR STOP 35
diff --git a/libgomp/testsuite/libgomp.oacc-fortran/error_stop-3.f b/libgomp/testsuite/libgomp.oacc-fortran/error_stop-3.f
index 9c217f14ea1..bef01e6d505 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/error_stop-3.f
+++ b/libgomp/testsuite/libgomp.oacc-fortran/error_stop-3.f
@@ -3,6 +3,10 @@
       PROGRAM MAIN
       IMPLICIT NONE
 
+! Initialize before the checkpoint, in case this produces any output.
+!$ACC PARALLEL
+!$ACC END PARALLEL
+
       PRINT *, "CheCKpOInT"
 !$ACC PARALLEL
       ERROR STOP "SiGN"
diff --git a/libgomp/testsuite/libgomp.oacc-fortran/stop-1.f b/libgomp/testsuite/libgomp.oacc-fortran/stop-1.f
index af267fc08d1..2c00d2e5bf8 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/stop-1.f
+++ b/libgomp/testsuite/libgomp.oacc-fortran/stop-1.f
@@ -3,6 +3,10 @@
       PROGRAM MAIN
       IMPLICIT NONE
 
+! Initialize before the checkpoint, in case this produces any output.
+!$ACC PARALLEL
+!$ACC END PARALLEL
+
       PRINT *, "CheCKpOInT"
 !$ACC PARALLEL
       STOP
diff --git a/libgomp/testsuite/libgomp.oacc-fortran/stop-2.f b/libgomp/testsuite/libgomp.oacc-fortran/stop-2.f
index 13c06845c08..adade54557c 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/stop-2.f
+++ b/libgomp/testsuite/libgomp.oacc-fortran/stop-2.f
@@ -3,6 +3,10 @@
       PROGRAM MAIN
       IMPLICIT NONE
 
+! Initialize before the checkpoint, in case this produces any output.
+!$ACC PARALLEL
+!$ACC END PARALLEL
+
       PRINT *, "CheCKpOInT"
 !$ACC PARALLEL
       STOP 35
diff --git a/libgomp/testsuite/libgomp.oacc-fortran/stop-3.f b/libgomp/testsuite/libgomp.oacc-fortran/stop-3.f
index 3bd7446571d..157e369d4e7 100644
--- a/libgomp/testsuite/libgomp.oacc-fortran/stop-3.f
+++ b/libgomp/testsuite/libgomp.oacc-fortran/stop-3.f
@@ -3,6 +3,10 @@
       PROGRAM MAIN
       IMPLICIT NONE
 
+! Initialize before the checkpoint, in case this produces any output.
+!$ACC PARALLEL
+!$ACC END PARALLEL
+
       PRINT *, "CheCKpOInT"
 !$ACC PARALLEL
       STOP "SiGN"

commit 2af0ef6477f20198574db98be32fc5d4b0a94ccb
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jun 5 00:17:39 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6c883c98853..de253bc14b7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200604
+20200605
diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 58323c23735..1490061187f 100644
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,13 @@
+2020-06-04  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* testsuite/libgomp.oacc-fortran/error_stop-1.f: Initialize before
+	the checkpoint.
+	* testsuite/libgomp.oacc-fortran/error_stop-2.f: Likewise.
+	* testsuite/libgomp.oacc-fortran/error_stop-3.f: Likewise.
+	* testsuite/libgomp.oacc-fortran/stop-1.f: Likewise.
+	* testsuite/libgomp.oacc-fortran/stop-2.f: Likewise.
+	* testsuite/libgomp.oacc-fortran/stop-3.f: Likewise.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.

commit 2b595aed9f0335ecf2e2652e4e875816a888c014
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Mon May 18 05:35:27 2020 -0700

    x86: Update Intel processor detection
    
    Add cpu model numbers for Intel Airmont, Comet Lake and Ice Lake
    processor families.
    
            * config/i386/driver-i386.c (host_detect_local_cpu): Support
            Intel Airmont, Comet Lake and Ice Lake processor families.

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 97eaf68442d..f9bd27bf0d7 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -752,9 +752,12 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	case 0x37:
 	case 0x4a:
 	case 0x4d:
-	case 0x5a:
 	case 0x5d:
 	  /* Silvermont.  */
+	case 0x4c:
+	case 0x5a:
+	case 0x75:
+	  /* Airmont.  */
 	  cpu = "silvermont";
 	  break;
 	case 0x0f:
@@ -807,12 +810,26 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	case 0x8e:
 	case 0x9e:
 	  /* Kaby Lake.  */
+	case 0xa5:
+	case 0xa6:
+	  /* Comet Lake.  */
 	  cpu = "skylake";
 	  break;
 	case 0x55:
 	  /* Skylake with AVX-512.  */
 	  cpu = "skylake-avx512";
 	  break;
+	case 0x6a:
+	case 0x6c:
+	  /* Ice Lake server.  */
+	  cpu = "icelake-server";
+	  break;
+	case 0x7e:
+	case 0x7d:
+	case 0x9d:
+	  /* Ice Lake client.  */
+	  cpu = "icelake-client";
+	  break;
 	case 0x57:
 	  /* Knights Landing.  */
 	  cpu = "knl";

commit d64b74ce3dfe4f2f7342921cdd9fae54e257b248
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jun 6 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1eed9dbb77e..448d3deed7d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-06-05  H.J. Lu  <hjl.tools@gmail.com>
+
+	* config/i386/driver-i386.c (host_detect_local_cpu): Support
+	Intel Airmont, Comet Lake and Ice Lake processor families.
+
 2020-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* config/aarch64/aarch64-cores.def (zeus): Define.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index de253bc14b7..4d03d79ce42 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200605
+20200606

commit 8da53517387ceb8d0e5ce87750b31d619d7b3b3b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jun 7 00:17:27 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4d03d79ce42..7329e39884d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200606
+20200607

commit 22d2ef94289e4d6ea5e2ed011c069021d3b0b7a1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jun 8 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7329e39884d..3b45689b2c3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200607
+20200608

commit 33ebf40daa79a73e66c379728b4c0ef7297297fe
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jun 9 00:17:58 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3b45689b2c3..ec1b34716f2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200608
+20200609

commit 26eabd4bf492907087371b9db2131adc8b7c58d0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jun 10 00:17:50 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ec1b34716f2..51c41f0bb81 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200609
+20200610

commit c6dce1d8083a2fdc94be167a2465db7fd837ccae
Author: Carl Love <cel@us.ibm.com>
Date:   Wed Jun 10 16:12:08 2020 -0500

    pr94833, fix vec_first_match_index for nulls
    
    Backported patch from mainline.  Updated ChangeLog format
            commit 24f68831d25bad739a6fe167a58b5b4c0c3cbf9a
            Author: Carl Love <cel@us.ibm.com>
            Date:   Wed Apr 29 10:23:11 2020 -0500
    
            Note the mainlin patch adds tests to the test case in mainline.  The test
            case does not exist in GCC 8.  Only the functional change in
            gcc/config/rs6000/vsx.md was backported.
    
    2020-06-10  Carl Love  <cel@us.ibm.com>
    
    gcc/
            PR target/94833
            * config/rs6000/vsx.md (define_expand): Fix instruction generation for
            first_match_index_<mode>.

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 17c24551306..ea2f2226a31 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4809,8 +4809,8 @@
   rtx cmp_result = gen_reg_rtx (<MODE>mode);
   rtx not_result = gen_reg_rtx (<MODE>mode);
 
-  emit_insn (gen_vcmpnez<VSX_EXTRACT_WIDTH> (cmp_result, operands[1],
-					     operands[2]));
+  emit_insn (gen_vcmpne<VSX_EXTRACT_WIDTH> (cmp_result, operands[1],
+					    operands[2]));
   emit_insn (gen_one_cmpl<mode>2 (not_result, cmp_result));
 
   sh = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) / 2;

commit 6194bfb2647ce7a18556c10a091a139cd9477710
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jun 11 00:17:54 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 448d3deed7d..682b7ac0ec5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-06-10  Carl Love  <cel@us.ibm.com>
+
+	PR target/94833
+	* config/rs6000/vsx.md (define_expand): Fix instruction generation for
+	first_match_index_<mode>.
+
 2020-06-05  H.J. Lu  <hjl.tools@gmail.com>
 
 	* config/i386/driver-i386.c (host_detect_local_cpu): Support
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 51c41f0bb81..1094e86b516 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200610
+20200611

commit 2e710aa664fc9e00cc083d8a0bc1a44ca9b5d758
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jun 12 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1094e86b516..98278266c63 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200611
+20200612

commit 5d746191e271949e530d9e5f46cde7e7bf08272f
Author: Martin Liska <mliska@suse.cz>
Date:   Tue May 19 16:57:56 2020 +0200

    Add missing store in emission of asan_stack_free.
    
    gcc/ChangeLog:
    
    2020-05-19  Martin Liska  <mliska@suse.cz>
    
            PR sanitizer/94910
            * asan.c (asan_emit_stack_protection): Emit
            also **SavedFlagPtr(FakeStack, class_id) = 0 in order to release
            a stack frame.
    
    (cherry picked from commit 8b6731e674c76cb48a417f2eef74ced92a17f469)

diff --git a/gcc/asan.c b/gcc/asan.c
index 235e219479d..4c99e3d9912 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1465,8 +1465,24 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
       if (use_after_return_class < 5
 	  && can_store_by_pieces (sz, builtin_memset_read_str, &c,
 				  BITS_PER_UNIT, true))
-	store_by_pieces (shadow_mem, sz, builtin_memset_read_str, &c,
-			 BITS_PER_UNIT, true, 0);
+	{
+	  /* Emit:
+	       memset(ShadowBase, kAsanStackAfterReturnMagic, ShadowSize);
+	       **SavedFlagPtr(FakeStack, class_id) = 0
+	  */
+	  store_by_pieces (shadow_mem, sz, builtin_memset_read_str, &c,
+			   BITS_PER_UNIT, true, 0);
+
+	  unsigned HOST_WIDE_INT offset
+	    = (1 << (use_after_return_class + 6));
+	  offset -= GET_MODE_SIZE (ptr_mode);
+	  mem = gen_rtx_MEM (ptr_mode, base);
+	  mem = adjust_address (mem, ptr_mode, offset);
+	  rtx addr = gen_reg_rtx (ptr_mode);
+	  emit_move_insn (addr, mem);
+	  mem = gen_rtx_MEM (QImode, addr);
+	  emit_move_insn (mem, const0_rtx);
+	}
       else if (use_after_return_class >= 5
 	       || !set_storage_via_setmem (shadow_mem,
 					   GEN_INT (sz),

commit 5222017313f5abf39e2374dc11bcac9b444f1b4c
Author: Martin Liska <mliska@suse.cz>
Date:   Thu Jun 11 09:34:41 2020 +0200

    asan: fix RTX emission for ilp32
    
    gcc/ChangeLog:
    
            PR sanitizer/95634
            * asan.c (asan_emit_stack_protection): Fix emission for ilp32
            by using Pmode instead of ptr_mode.
    
    Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
    (cherry picked from commit 8cff672cb9a132d3d3158c2edfc9a64b55292b80)

diff --git a/gcc/asan.c b/gcc/asan.c
index 4c99e3d9912..9014df19939 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1480,6 +1480,7 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb,
 	  mem = adjust_address (mem, ptr_mode, offset);
 	  rtx addr = gen_reg_rtx (ptr_mode);
 	  emit_move_insn (addr, mem);
+	  addr = convert_memory_address (Pmode, addr);
 	  mem = gen_rtx_MEM (QImode, addr);
 	  emit_move_insn (mem, const0_rtx);
 	}

commit cb4a12ade7e024f7d592214f7f8317d9b9dc1206
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jun 13 00:17:35 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 682b7ac0ec5..761ad57f860 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2020-06-12  Martin Liska  <mliska@suse.cz>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	PR sanitizer/95634
+	* asan.c (asan_emit_stack_protection): Fix emission for ilp32
+	by using Pmode instead of ptr_mode.
+
+2020-06-12  Martin Liska  <mliska@suse.cz>
+
+	PR sanitizer/94910
+	* asan.c (asan_emit_stack_protection): Emit
+	also **SavedFlagPtr(FakeStack, class_id) = 0 in order to release
+	a stack frame.
+
 2020-06-10  Carl Love  <cel@us.ibm.com>
 
 	PR target/94833
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 98278266c63..d540cbfb2c4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200612
+20200613

commit eb99c92ee882b112f99f09921e55b988061bfbe8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jun 14 00:17:25 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d540cbfb2c4..90b1180b434 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200613
+20200614

commit a5cda02410222030c0af6679998a997bbcddb021
Author: Thomas Koenig <tkoenig@gcc.gnu.org>
Date:   Sun Jun 14 13:54:19 2020 +0200

    When avoiding double deallocation, look at namespace, expression and component.
    
    Our finalization handling is a mess.  Really, we should get to try and get
    this fixed for gcc 11.
    
    In the meantime, here is a patch which fixes a regression I introduced
    when fixing a regression with a memory leak.  The important thing
    here is to realize that we do not need to finalize (and deallocate)
    multiple times for the same expression and the same component
    in the same namespace.  It might cause code size regressions, but
    better big code than wrong code...
    
    Backported from r11-1296-g1af22e455584ef5fcad2b4474c1efc3fd26f6cb3 .
    
    gcc/fortran/ChangeLog:
    
            PR fortran/94109
            * class.c (finalize_component): Return early if finalization has
            already happened for expression and component within namespace.
            * gfortran.h (gfc_was_finalized): New type.
            (gfc_namespace): Add member was_finalzed.
            (gfc_expr): Remove finalized.
            * symbol.c (gfc_free_namespace): Free was_finalized.
    
    gcc/testsuite/ChangeLog:
    
            PR fortran/94109
            * gfortran.dg/finalize_34.f90: Adjust free counts.
            * gfortran.dg/finalize_36.f90: New test.

diff --git a/gcc/fortran/class.c b/gcc/fortran/class.c
index 90563cac7b0..8d7ea836800 100644
--- a/gcc/fortran/class.c
+++ b/gcc/fortran/class.c
@@ -903,12 +903,18 @@ finalize_component (gfc_expr *expr, gfc_symbol *derived, gfc_component *comp,
 {
   gfc_expr *e;
   gfc_ref *ref;
+  gfc_was_finalized *f;
 
   if (!comp_is_finalizable (comp))
     return;
 
-  if (expr->finalized)
-    return;
+  /* If this expression with this component has been finalized
+     already in this namespace, there is nothing to do.  */
+  for (f = sub_ns->was_finalized; f; f = f->next)
+    {
+      if (f->e == expr && f->c == comp)
+	return;
+    }
 
   e = gfc_copy_expr (expr);
   if (!e->ref)
@@ -1038,7 +1044,13 @@ finalize_component (gfc_expr *expr, gfc_symbol *derived, gfc_component *comp,
 			    sub_ns);
       gfc_free_expr (e);
     }
-  expr->finalized = 1;
+
+  /* Record that this was finalized already in this namespace.  */
+  f = sub_ns->was_finalized;
+  sub_ns->was_finalized = XCNEW (gfc_was_finalized);
+  sub_ns->was_finalized->e = expr;
+  sub_ns->was_finalized->c = comp;
+  sub_ns->was_finalized->next = f;
 }
 
 
diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h
index d9ba843b096..8256bdc61a3 100644
--- a/gcc/fortran/gfortran.h
+++ b/gcc/fortran/gfortran.h
@@ -1739,6 +1739,16 @@ gfc_oacc_routine_name;
 
 #define gfc_get_oacc_routine_name() XCNEW (gfc_oacc_routine_name)
 
+/* Node in linked list to see what has already been finalized
+   earlier.  */
+
+typedef struct gfc_was_finalized {
+  gfc_expr *e;
+  gfc_component *c;
+  struct gfc_was_finalized *next;
+}
+gfc_was_finalized;
+
 /* A namespace describes the contents of procedure, module, interface block
    or BLOCK construct.  */
 /* ??? Anything else use these?  */
@@ -1831,6 +1841,11 @@ typedef struct gfc_namespace
   /* Linked list of !$omp declare simd constructs.  */
   struct gfc_omp_declare_simd *omp_declare_simd;
 
+  /* A hash set for the the gfc expressions that have already
+     been finalized in this namespace.  */
+
+  gfc_was_finalized *was_finalized;
+
   /* Set to 1 if namespace is a BLOCK DATA program unit.  */
   unsigned is_block_data:1;
 
@@ -2155,9 +2170,6 @@ typedef struct gfc_expr
 
   unsigned int do_not_warn : 1;
 
-  /* Set this if the expression has already been finalized.  */
-  unsigned int finalized : 1;
-
   /* If an expression comes from a Hollerith constant or compile-time
      evaluation of a transfer statement, it may have a prescribed target-
      memory representation, and these cannot always be backformed from
diff --git a/gcc/fortran/symbol.c b/gcc/fortran/symbol.c
index e07b48ab082..b63b625eb70 100644
--- a/gcc/fortran/symbol.c
+++ b/gcc/fortran/symbol.c
@@ -4059,6 +4059,7 @@ gfc_free_namespace (gfc_namespace *ns)
 {
   gfc_namespace *p, *q;
   int i;
+  gfc_was_finalized *f;
 
   if (ns == NULL)
     return;
@@ -4091,6 +4092,17 @@ gfc_free_namespace (gfc_namespace *ns)
     gfc_free_interface (ns->op[i]);
 
   gfc_free_data (ns->data);
+
+  /* Free all the expr + component combinations that have been
+     finalized.  */
+  f = ns->was_finalized;
+  while (f)
+    {
+      gfc_was_finalized* current = f;
+      f = f->next;
+      free (current);
+    }
+
   p = ns->contained;
   free (ns);
 
diff --git a/gcc/testsuite/gfortran.dg/finalize_34.f90 b/gcc/testsuite/gfortran.dg/finalize_34.f90
index fef7dac6d89..8fb801d4235 100644
--- a/gcc/testsuite/gfortran.dg/finalize_34.f90
+++ b/gcc/testsuite/gfortran.dg/finalize_34.f90
@@ -22,4 +22,4 @@ program main
   use testmodule
   type(evtlist_type), dimension(10) :: a
 end program main
-! { dg-final  { scan-tree-dump-times "__builtin_free" 12 "original" } }
+! { dg-final  { scan-tree-dump-times "__builtin_free" 24 "original" } }
diff --git a/gcc/testsuite/gfortran.dg/finalize_36.f90 b/gcc/testsuite/gfortran.dg/finalize_36.f90
new file mode 100644
index 00000000000..432f5472aeb
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/finalize_36.f90
@@ -0,0 +1,39 @@
+! { dg-do run }
+! { dg-additional-options "-fdump-tree-original" }
+! PR 94109
+! This used to leak memory.  Test case by Antony Lewis.
+    module debug
+    implicit none
+
+    Type Tester
+        real, dimension(:), allocatable :: Dat, Dat2
+    end Type
+
+    Type TestType2
+        Type(Tester) :: T
+    end type TestType2
+
+    contains
+
+    subroutine Leaker
+    class(TestType2), pointer :: ActiveState
+    Type(Tester) :: Temp
+
+    allocate(Temp%Dat2(10000))
+
+    allocate(TestType2::ActiveState)
+    ActiveState%T = Temp
+    deallocate(ActiveState)
+
+    end subroutine
+
+    end module
+
+
+    program run
+    use debug
+
+    call Leaker()
+
+    end program
+! { dg-final { scan-tree-dump-times "__builtin_free\\ \\(ptr2" 4 "original" } }

commit f1a8a7dc133e18afe28cae0b7533d1694cf6095b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jun 15 00:17:27 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 90b1180b434..0dab8e8132f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200614
+20200615
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 1039aa5252e..f0a3a30dad0 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,13 @@
+2020-06-14  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	PR fortran/94109
+	* class.c (finalize_component): Return early if finalization has
+	already happened for expression and component within namespace.
+	* gfortran.h (gfc_was_finalized): New type.
+	(gfc_namespace): Add member was_finalzed.
+	(gfc_expr): Remove finalized.
+	* symbol.c (gfc_free_namespace): Free was_finalized.
+
 2020-06-01  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	PR fortran/94361
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d5e5890e4ae..0af007f252e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2020-06-14  Thomas Koenig  <tkoenig@gcc.gnu.org>
+
+	PR fortran/94109
+	* gfortran.dg/finalize_34.f90: Adjust free counts.
+	* gfortran.dg/finalize_36.f90: New test.
+
 2020-06-01  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	PR fortran/94361

commit 76e147e6e32bc5fd3d597d49423558c061325f83
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jun 16 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0dab8e8132f..3ca7808b314 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200615
+20200616

commit 572c0aff9a5fcc19adad0b0c392e7c10db189244
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jun 17 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3ca7808b314..d2b0822d197 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200616
+20200617

commit e7fad65109690ae41be04a23093cd7504d022d4c
Author: Thomas Schwinge <thomas@codesourcery.com>
Date:   Sat Jun 6 18:44:34 2020 +0200

    [HSA] Avoid ICE when "HSA does not implement indirect calls"
    
    Made apparent by recent commit dc703151d4f4560e647649506d5b4ceb0ee11e90
    "openmp: Implement discovery of implicit declare target to clauses":
    
        +FAIL: libgomp.c/target-39.c (internal compiler error)
        +FAIL: libgomp.c/target-39.c (test for excess errors)
        +UNRESOLVED: libgomp.c/target-39.c compilation failed to produce executable
    
    This is in a '--enable-offload-targets=[...],hsa' build, with '-foffload=hsa'
    enabled (by default).
    
        during GIMPLE pass: hsagen
        source-gcc/libgomp/testsuite/libgomp.c/target-39.c: In function ‘main._omp_fn.0.hsa.0’:
        source-gcc/libgomp/testsuite/libgomp.c/target-39.c:23:11: internal compiler error: Segmentation fault
           23 |   #pragma omp target map(from:err)
              |           ^~~
        [...]
    
    GDB:
    
        Program received signal SIGSEGV, Segmentation fault.
        fndecl_built_in_p (node=0x0, name=BUILT_IN_PREFETCH) at [...]/source-gcc/gcc/tree.h:6267
        6267      return (fndecl_built_in_p (node, BUILT_IN_NORMAL)
        (gdb) bt
        #0  fndecl_built_in_p (node=0x0, name=BUILT_IN_PREFETCH) at [...]/source-gcc/gcc/tree.h:6267
        #1  0x0000000000b19739 in gen_hsa_insns_for_call (stmt=stmt@entry=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at [...]/source-gcc/gcc/hsa-gen.c:5304
        #2  0x0000000000b1aca7 in gen_hsa_insns_for_gimple_stmt (stmt=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at [...]/source-gcc/gcc/hsa-gen.c:5770
        #3  0x0000000000b1bd21 in gen_body_from_gimple () at [...]/source-gcc/gcc/hsa-gen.c:5999
        #4  0x0000000000b1dbd2 in generate_hsa (kernel=<optimized out>) at [...]/source-gcc/gcc/hsa-gen.c:6596
        #5  0x0000000000b1de66 in (anonymous namespace)::pass_gen_hsail::execute (this=0x2a2aac0) at [...]/source-gcc/gcc/hsa-gen.c:6680
        #6  0x0000000000d06f90 in execute_one_pass (pass=pass@entry=0x2a2aac0) at [...]/source-gcc/gcc/passes.c:2502
        [...]
        (gdb) up
        #1  0x0000000000b19739 in gen_hsa_insns_for_call (stmt=stmt@entry=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at /home/thomas/tmp/source/gcc/build/track-slim-omp/source-gcc/gcc/hsa-gen.c:5304
        5304          if (fndecl_built_in_p (function_decl, BUILT_IN_PREFETCH))
        (gdb) print function_decl
        $1 = (tree) 0x0
        (gdb) list
        5299      if (!gimple_call_builtin_p (stmt, BUILT_IN_NORMAL))
        5300        {
        5301          tree function_decl = gimple_call_fndecl (stmt);
        5302          /* Prefetch pass can create type-mismatching prefetch builtin calls which
        5303             fail the gimple_call_builtin_p test above.  Handle them here.  */
        5304          if (fndecl_built_in_p (function_decl, BUILT_IN_PREFETCH))
        5305            return;
        5306
        5307          if (function_decl == NULL_TREE)
        5308            {
    
    The problem is present already since 2016-11-23 commit
    56b1c60e412fcf1245b4780871553cbdebb956a3 (r242761) "Merge from HSA branch to
    trunk", and the fix obvious enough.
    
            gcc/
            * hsa-gen.c (gen_hsa_insns_for_call): Move 'function_decl ==
            NULL_TREE' check earlier.
            gcc/testsuite/
            * c-c++-common/gomp/hsa-indirect-call-1.c: New file.
    
    (cherry picked from commit 973bce0fb50bbfd91f47238b82b99935525716ad)

diff --git a/gcc/hsa-gen.c b/gcc/hsa-gen.c
index 7974fffe360..5a4b38d717b 100644
--- a/gcc/hsa-gen.c
+++ b/gcc/hsa-gen.c
@@ -5251,11 +5251,6 @@ gen_hsa_insns_for_call (gimple *stmt, hsa_bb *hbb)
   if (!gimple_call_builtin_p (stmt, BUILT_IN_NORMAL))
     {
       tree function_decl = gimple_call_fndecl (stmt);
-      /* Prefetch pass can create type-mismatching prefetch builtin calls which
-	 fail the gimple_call_builtin_p test above.  Handle them here.  */
-      if (DECL_BUILT_IN_CLASS (function_decl)
-	  && DECL_FUNCTION_CODE (function_decl) == BUILT_IN_PREFETCH)
-	return;
 
       if (function_decl == NULL_TREE)
 	{
@@ -5264,6 +5259,12 @@ gen_hsa_insns_for_call (gimple *stmt, hsa_bb *hbb)
 	  return;
 	}
 
+      /* Prefetch pass can create type-mismatching prefetch builtin calls which
+	 fail the gimple_call_builtin_p test above.  Handle them here.  */
+      if (DECL_BUILT_IN_CLASS (function_decl)
+	  && DECL_FUNCTION_CODE (function_decl) == BUILT_IN_PREFETCH)
+	return;
+
       if (hsa_callable_function_p (function_decl))
 	gen_hsa_insns_for_direct_call (stmt, hbb);
       else if (!gen_hsa_insns_for_known_library_call (stmt, hbb))
diff --git a/gcc/testsuite/c-c++-common/gomp/hsa-indirect-call-1.c b/gcc/testsuite/c-c++-common/gomp/hsa-indirect-call-1.c
new file mode 100644
index 00000000000..67ee6af309a
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/gomp/hsa-indirect-call-1.c
@@ -0,0 +1,24 @@
+/* Instead of ICE, we'd like "HSA does not implement indirect calls".  */
+
+/* Reduced from 'libgomp.c/target-39.c'.  */
+
+/* { dg-require-effective-target offload_hsa } */
+/* { dg-additional-options "-Whsa" } to override '{gcc,g++}.dg/gomp/gomp.exp'.  */
+
+typedef void (*fnp) (void);
+void f1 (void) { }
+fnp f2 (void) { return f1; }
+#pragma omp declare target to (f1, f2)
+
+int
+main ()
+{
+  #pragma omp target
+  {
+    fnp fnp = f2 ();
+    fnp (); /* { dg-message "note: support for HSA does not implement indirect calls" } */
+  }
+  return 0;
+}
+
+/* { dg-warning "could not emit HSAIL for the function" "" { target *-*-* } 0 } */

commit 9c5787ea072e16f26c9950139c00ae28fddadd72
Author: Samuel Thibault <samuel.thibault@gnu.org>
Date:   Fri May 29 13:46:50 2020 +0200

    hurd: libgcc unwinding support over signal trampolines
    
            libgcc/
            * config.host (md_unwind_header) <i[34567]86-*-gnu*>: Set to
            'i386/gnu-unwind.h'
            * config/i386/gnu-unwind.h: New file.
    
    Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
    (cherry picked from commit 5e2eebc80d6eeca24745c27a925afdb64292ed22)

diff --git a/libgcc/config.host b/libgcc/config.host
index e436ade1a68..677173eee43 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -651,11 +651,17 @@ i[34567]86-*-linux*)
 	tm_file="${tm_file} i386/elf-lib.h"
 	md_unwind_header=i386/linux-unwind.h
 	;;
-i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-gnu* | i[34567]86-*-kopensolaris*-gnu)
+i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-kopensolaris*-gnu)
 	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
 	tmake_file="${tmake_file} i386/t-crtpc t-crtfm i386/t-crtstuff t-dfprules"
 	tm_file="${tm_file} i386/elf-lib.h"
 	;;
+i[34567]86-*-gnu*)
+	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
+	tmake_file="${tmake_file} i386/t-crtpc t-crtfm i386/t-crtstuff t-dfprules"
+	tm_file="${tm_file} i386/elf-lib.h"
+	md_unwind_header=i386/gnu-unwind.h
+	;;
 x86_64-*-linux*)
 	extra_parts="$extra_parts crtprec32.o crtprec64.o crtprec80.o crtfastmath.o"
 	tmake_file="${tmake_file} i386/t-crtpc t-crtfm i386/t-crtstuff t-dfprules"
diff --git a/libgcc/config/i386/gnu-unwind.h b/libgcc/config/i386/gnu-unwind.h
new file mode 100644
index 00000000000..db47f0ac1d4
--- /dev/null
+++ b/libgcc/config/i386/gnu-unwind.h
@@ -0,0 +1,107 @@
+/* DWARF2 EH unwinding support for GNU Hurd: x86.
+   Copyright (C) 2020 Free Software Foundation, Inc.
+   Contributed by Samuel Thibault <samuel.thibault@gnu.org>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+/* Do code reading to identify a signal frame, and set the frame
+   state data appropriately.  See unwind-dw2.c for the structs. */
+
+#ifndef inhibit_libc
+
+#include <signal.h>
+
+#define MD_FALLBACK_FRAME_STATE_FOR x86_gnu_fallback_frame_state
+
+static _Unwind_Reason_Code
+x86_gnu_fallback_frame_state
+(struct _Unwind_Context *context, _Unwind_FrameState *fs)
+{
+  struct handler_args {
+    int signo;
+    int sigcode;
+    struct sigcontext *scp;
+  } *handler_args;
+  struct sigcontext *scp;
+  unsigned long usp;
+
+/*
+ * i386 sigtramp frame we are looking for follows.
+ * (see glibc/sysdeps/mach/hurd/i386/trampoline.c assembly)
+ *
+ * rpc_wait_trampoline:
+ *   0:	b8 e7 ff ff ff       	mov    $-25,%eax       mach_msg_trap
+ *   5:	9a 00 00 00 00 07 00 	lcall  $7,$0
+ *  12:	89 01                	movl   %eax, (%ecx)
+ *  14:	89 dc                	movl   %ebx, %esp      switch to signal stack
+ *
+ * trampoline:
+ *  16:	ff d2                	call   *%edx           call the handler function
+ * RA HERE
+ *  18:	83 c4 0c             	addl   $12, %esp       pop its args
+ *  21:	c3                   	ret                    return to sigreturn
+ *
+ * firewall:
+ *  22:	f4                   	hlt
+ */
+
+  if (!(   *(unsigned int   *)(context->ra     ) == 0xc30cc483
+        && *(unsigned char  *)(context->ra +  4) ==       0xf4
+
+        && *(unsigned int   *)(context->ra -  4) == 0xd2ffdc89
+        && *(unsigned int   *)(context->ra -  8) == 0x01890007
+        && *(unsigned int   *)(context->ra - 12) == 0x00000000
+        && *(unsigned int   *)(context->ra - 16) == 0x9affffff
+        && *(unsigned short *)(context->ra - 18) ==     0xe7b8))
+    return _URC_END_OF_STACK;
+
+  handler_args = context->cfa;
+  scp = handler_args->scp;
+  usp = scp->sc_uesp;
+
+  fs->regs.cfa_how = CFA_REG_OFFSET;
+  fs->regs.cfa_reg = 4;
+  fs->regs.cfa_offset = usp - (unsigned long) context->cfa;
+
+  fs->regs.reg[0].how = REG_SAVED_OFFSET;
+  fs->regs.reg[0].loc.offset = (unsigned long)&scp->sc_eax - usp;
+  fs->regs.reg[1].how = REG_SAVED_OFFSET;
+  fs->regs.reg[1].loc.offset = (unsigned long)&scp->sc_ecx - usp;
+  fs->regs.reg[2].how = REG_SAVED_OFFSET;
+  fs->regs.reg[2].loc.offset = (unsigned long)&scp->sc_edx - usp;
+  fs->regs.reg[3].how = REG_SAVED_OFFSET;
+  fs->regs.reg[3].loc.offset = (unsigned long)&scp->sc_ebx - usp;
+  fs->regs.reg[5].how = REG_SAVED_OFFSET;
+  fs->regs.reg[5].loc.offset = (unsigned long)&scp->sc_ebp - usp;
+  fs->regs.reg[6].how = REG_SAVED_OFFSET;
+  fs->regs.reg[6].loc.offset = (unsigned long)&scp->sc_esi - usp;
+  fs->regs.reg[7].how = REG_SAVED_OFFSET;
+  fs->regs.reg[7].loc.offset = (unsigned long)&scp->sc_edi - usp;
+  fs->regs.reg[8].how = REG_SAVED_OFFSET;
+  fs->regs.reg[8].loc.offset = (unsigned long)&scp->sc_eip - usp;
+  fs->retaddr_column = 8;
+  fs->signal_frame = 1;
+
+  return _URC_NO_REASON;
+}
+
+#endif /* ifndef inhibit_libc */

commit 496966ffb81a32b38781cf5542cbb6f8e128a57a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jun 18 00:17:52 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 761ad57f860..89fb41a029b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-06-17  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2020-06-17  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* hsa-gen.c (gen_hsa_insns_for_call): Move 'function_decl ==
+	NULL_TREE' check earlier.
+
 2020-06-12  Martin Liska  <mliska@suse.cz>
 	    Jakub Jelinek  <jakub@redhat.com>
 
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d2b0822d197..e94346fce10 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200617
+20200618
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0af007f252e..e1d826c3e13 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-06-17  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2020-06-17  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* c-c++-common/gomp/hsa-indirect-call-1.c: New file.
+
 2020-06-14  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	PR fortran/94109
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 2d7e900a653..bca0c1c212e 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-06-17  Samuel Thibault  <samuel.thibault@gnu.org>
+
+	Backported from master:
+	2020-06-17  Samuel Thibault  <samuel.thibault@gnu.org>
+
+	* config.host (md_unwind_header) <i[34567]86-*-gnu*>: Set to
+	'i386/gnu-unwind.h'
+	* config/i386/gnu-unwind.h: New file.
+
 2020-05-29  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* config/aarch64/lse-init.c (init_have_lse_atomics): Use __getauxval

commit 7d86dedb6a36b7ce472b71726584d7f2542cf583
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jun 19 00:17:41 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e94346fce10..bfd6abf660d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200618
+20200619

commit 913b045b87cc59ca24f121d1e25f80fcc71b248a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jun 20 00:17:30 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index bfd6abf660d..34d423ff9ba 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200619
+20200620

commit 0a7a2b7c64a77218e504e8390af29cfa5f79a242
Author: Bin Cheng <bin.cheng@linux.alibaba.com>
Date:   Sat Jun 20 16:56:21 2020 +0800

    Add missing unit dependence vector in data dependence analysis
    
    Current data dependence analysis misses unit distant vector if DRs in
    DDR have the same invariant access functions.  This adds the vector as
    the constant access function case.
    
    Also fix typo in testcase.
    
    Backport from master commit: 287552950d56be47adb6b6bf2eae2d612233eaec
    and f6e1a4cd83190746b6544917f7526fa480ca5f18
    
    2020-06-20  Bin Cheng  <bin.cheng@linux.alibaba.com>
    
    gcc/
            PR tree-optimization/94969
            * tree-data-ref.c (constant_access_functions): Rename to...
            (invariant_access_functions): ...this.  Add parameter.  Check for
            invariant access function, rather than constant.
            (build_classic_dist_vector): Call above function.
            * tree-loop-distribution.c (pg_add_dependence_edges): Add comment.
    
    gcc/testsuite/
            PR tree-optimization/94969
            * gcc.dg/tree-ssa/pr94969.c: New test.
    
    2020-06-20  Jakub Jelinek  <jakub@redhat.com>
    
    gcc/testsuite/
            PR tree-optimization/95110
            * gcc.dg/tree-ssa/pr94969.c: Swap scan-tree-dump-not arguments.

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr94969.c b/gcc/testsuite/gcc.dg/tree-ssa/pr94969.c
new file mode 100644
index 00000000000..f15046122ff
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr94969.c
@@ -0,0 +1,28 @@
+/* PR tree-optimization/52267 */
+/* { dg-do run } */
+/* { dg-options "-O3 -fdump-tree-ldist-details" } */
+
+int a = 0, b = 0, c = 0;
+struct S {
+  signed m : 7;
+  signed e : 2;
+};
+struct S f[2] = {{0, 0}, {0, 0}};
+struct S g = {0, 0};
+
+void __attribute__((noinline))
+k()
+{
+  for (; c <= 1; c++) {
+    f[b] = g;
+    f[b].e ^= 1;
+  }
+}
+int main()
+{
+  k();
+  if (f[b].e != 1)
+    __builtin_abort ();
+}
+
+/* { dg-final { scan-tree-dump-not "Loop 1 distributed: split to 3 loops" "ldist" } } */
diff --git a/gcc/tree-data-ref.c b/gcc/tree-data-ref.c
index fc86bc25951..c90e862fb16 100644
--- a/gcc/tree-data-ref.c
+++ b/gcc/tree-data-ref.c
@@ -4342,17 +4342,19 @@ build_classic_dist_vector_1 (struct data_dependence_relation *ddr,
   return true;
 }
 
-/* Return true when the DDR contains only constant access functions.  */
+/* Return true when the DDR contains only invariant access functions wrto. loop
+   number LNUM.  */
 
 static bool
-constant_access_functions (const struct data_dependence_relation *ddr)
+invariant_access_functions (const struct data_dependence_relation *ddr,
+			    int lnum)
 {
   unsigned i;
   subscript *sub;
 
   FOR_EACH_VEC_ELT (DDR_SUBSCRIPTS (ddr), i, sub)
-    if (!evolution_function_is_constant_p (SUB_ACCESS_FN (sub, 0))
-	|| !evolution_function_is_constant_p (SUB_ACCESS_FN (sub, 1)))
+    if (!evolution_function_is_invariant_p (SUB_ACCESS_FN (sub, 0), lnum)
+	|| !evolution_function_is_invariant_p (SUB_ACCESS_FN (sub, 1), lnum))
       return false;
 
   return true;
@@ -4551,7 +4553,7 @@ build_classic_dist_vector (struct data_dependence_relation *ddr,
       dist_v = lambda_vector_new (DDR_NB_LOOPS (ddr));
       save_dist_v (ddr, dist_v);
 
-      if (constant_access_functions (ddr))
+      if (invariant_access_functions (ddr, loop_nest->num))
 	add_distance_for_zero_overlaps (ddr);
 
       if (DDR_NB_LOOPS (ddr) > 1)
diff --git a/gcc/tree-loop-distribution.c b/gcc/tree-loop-distribution.c
index 769523ba214..05766c7300d 100644
--- a/gcc/tree-loop-distribution.c
+++ b/gcc/tree-loop-distribution.c
@@ -1919,7 +1919,8 @@ pg_add_dependence_edges (struct graph *rdg, int dir,
 		this_dir = -this_dir;
 
 	      /* Known dependences can still be unordered througout the
-		 iteration space, see gcc.dg/tree-ssa/ldist-16.c.  */
+		 iteration space, see gcc.dg/tree-ssa/ldist-16.c and
+		 gcc.dg/tree-ssa/pr94969.c.  */
 	      if (DDR_NUM_DIST_VECTS (ddr) != 1)
 		this_dir = 2;
 	      /* If the overlap is exact preserve stmt order.  */

commit 79ce007d4369114ae5e680ae0a8df8098f676f3e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jun 21 00:17:30 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 89fb41a029b..c8483a6f56a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-06-20  Bin Cheng  <bin.cheng@linux.alibaba.com>
+
+	PR tree-optimization/94969
+	* tree-data-ref.c (constant_access_functions): Rename to...
+	(invariant_access_functions): ...this.  Add parameter.  Check for
+	invariant access function, rather than constant.
+	(build_classic_dist_vector): Call above function.
+	* tree-loop-distribution.c (pg_add_dependence_edges): Add comment.
+
 2020-06-17  Thomas Schwinge  <thomas@codesourcery.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 34d423ff9ba..61722185183 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200620
+20200621
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e1d826c3e13..b15d18a5bb0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2020-06-20  Bin Cheng  <bin.cheng@linux.alibaba.com>
+
+	PR tree-optimization/95110
+	* gcc.dg/tree-ssa/pr94969.c: Swap scan-tree-dump-not arguments.
+
+2020-06-20  Bin Cheng  <bin.cheng@linux.alibaba.com>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94969
+	* gcc.dg/tree-ssa/pr94969.c: New test.
+
 2020-06-17  Thomas Schwinge  <thomas@codesourcery.com>
 
 	Backported from master:

commit 31b4a3509a5eb119821888394c3606d52459f4bd
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jun 22 00:17:35 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 61722185183..5316c6c6e85 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200621
+20200622

commit 837329193e40efcbd040b687420b1bcd4dac1c40
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jun 23 00:17:29 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 5316c6c6e85..01621c4e820 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200622
+20200623

commit 8cd9870d1b29ba7f6d6550611892036ed49f5bcf
Author: Eric Botcazou <ebotcazou@gcc.gnu.org>
Date:   Tue Jun 23 18:33:28 2020 +0200

    Fix memory corruption with vector and variant record
    
    The problem is that Has_Constrained_Partial_View must be tested on the
    base type of the designated type of an allocator.
    
    gcc/ada/ChangeLog:
            * gcc-interface/trans.c (gnat_to_gnu) <N_Allocator>: Minor tweaks.
            Call Has_Constrained_Partial_View on base type of designated type.

diff --git a/gcc/ada/gcc-interface/trans.c b/gcc/ada/gcc-interface/trans.c
index 5925a4860da..80575d46e37 100644
--- a/gcc/ada/gcc-interface/trans.c
+++ b/gcc/ada/gcc-interface/trans.c
@@ -6840,9 +6840,8 @@ gnat_to_gnu (Node_Id gnat_node)
 
     case N_Allocator:
       {
-	tree gnu_init = NULL_TREE;
-	tree gnu_type;
-	bool ignore_init_type = false;
+	tree gnu_type, gnu_init;
+	bool ignore_init_type;
 
 	gnat_temp = Expression (gnat_node);
 
@@ -6852,15 +6851,22 @@ gnat_to_gnu (Node_Id gnat_node)
 	   initial value for the object.  */
 	if (Nkind (gnat_temp) == N_Identifier
 	    || Nkind (gnat_temp) == N_Expanded_Name)
-	  gnu_type = gnat_to_gnu_type (Entity (gnat_temp));
+	  {
+	    ignore_init_type = false;
+	    gnu_init = NULL_TREE;
+	    gnu_type = gnat_to_gnu_type (Entity (gnat_temp));
+	  }
+
 	else if (Nkind (gnat_temp) == N_Qualified_Expression)
 	  {
 	    Entity_Id gnat_desig_type
 	      = Designated_Type (Underlying_Type (Etype (gnat_node)));
 
-	    ignore_init_type = Has_Constrained_Partial_View (gnat_desig_type);
-	    gnu_init = gnat_to_gnu (Expression (gnat_temp));
+	    /* The flag is effectively only set on the base types.  */
+	    ignore_init_type
+	      = Has_Constrained_Partial_View (Base_Type (gnat_desig_type));
 
+	    gnu_init = gnat_to_gnu (Expression (gnat_temp));
 	    gnu_init = maybe_unconstrained_array (gnu_init);
 	    if (Do_Range_Check (Expression (gnat_temp)))
 	      gnu_init

commit 4cfdae8e4a96912871865d289a5a817cec68eaa0
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Sat Jun 20 16:09:45 2020 +0200

    PR fortran/95689 - ICE in check_sym_interfaces, at fortran/interface.c:2015
    
    With submodules, name mangling of interfaces may result in long internal
    symbols overflowing an internal buffer.  We now check that we do not
    exceed the enlarged buffer size.
    
    gcc/fortran/
            PR fortran/95689
            * interface.c (check_sym_interfaces): Enlarge temporary buffer,
            and add check on length on mangled name to prevent overflow.
    
    (cherry picked from commit 62c0c0ea7bfb6f8f6b8d767b05120cafb6823da6)

diff --git a/gcc/fortran/interface.c b/gcc/fortran/interface.c
index 689c30210d7..ec8fd3a8f68 100644
--- a/gcc/fortran/interface.c
+++ b/gcc/fortran/interface.c
@@ -1944,7 +1944,8 @@ check_interface1 (gfc_interface *p, gfc_interface *q0,
 static void
 check_sym_interfaces (gfc_symbol *sym)
 {
-  char interface_name[GFC_MAX_SYMBOL_LEN + sizeof("generic interface ''")];
+  /* Provide sufficient space to hold "generic interface 'symbol.symbol'".  */
+  char interface_name[2*GFC_MAX_SYMBOL_LEN+2 + sizeof("generic interface ''")];
   gfc_interface *p;
 
   if (sym->ns != gfc_current_ns)
@@ -1952,6 +1953,8 @@ check_sym_interfaces (gfc_symbol *sym)
 
   if (sym->generic != NULL)
     {
+      size_t len = strlen (sym->name) + sizeof("generic interface ''");
+      gcc_assert (len < sizeof (interface_name));
       sprintf (interface_name, "generic interface '%s'", sym->name);
       if (check_interface0 (sym->generic, interface_name))
 	return;
diff --git a/gcc/testsuite/gfortran.dg/pr95689.f90 b/gcc/testsuite/gfortran.dg/pr95689.f90
new file mode 100644
index 00000000000..287ae50b0cb
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr95689.f90
@@ -0,0 +1,16 @@
+! { dg-do compile }
+! { dg-options "-fsecond-underscore" }
+! PR fortran/95689 - ICE in check_sym_interfaces, at fortran/interface.c:2015
+
+module m2345678901234567890123456789012345678901234567890123456789_123
+  type t2345678901234567890123456789012345678901234567890123456789_123
+   end type
+   interface
+      module subroutine s2345678901234567890123456789012345678901234567890123456789_123 &
+                       (x2345678901234567890123456789012345678901234567890123456789_123)
+      end
+   end interface
+end
+submodule(m2345678901234567890123456789012345678901234567890123456789_123) &
+          t2345678901234567890123456789012345678901234567890123456789_123
+end

commit 55b27ca8e60c96d28a3a635a7dd0842f6aee57be
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jun 24 00:17:41 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 01621c4e820..1e6790229fe 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200623
+20200624
diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index 2718106f024..966bfbd9233 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,8 @@
+2020-06-23  Eric Botcazou  <ebotcazou@gcc.gnu.org>
+
+	* gcc-interface/trans.c (gnat_to_gnu) <N_Allocator>: Minor tweaks.
+	Call Has_Constrained_Partial_View on base type of designated type.
+
 2020-05-04  Mikael Pettersson  <mikpelinux@gmail.com>
 
 	PR bootstrap/94918
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index f0a3a30dad0..6b6fb37a1be 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,12 @@
+2020-06-23  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-06-20  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/95689
+	* interface.c (check_sym_interfaces): Enlarge temporary buffer,
+	and add check on length on mangled name to prevent overflow.
+
 2020-06-14  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	PR fortran/94109
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b15d18a5bb0..ed70818d4fc 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-06-23  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-06-20  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/95689
+	* gfortran.dg/pr95689.f90: New file.
+
 2020-06-20  Bin Cheng  <bin.cheng@linux.alibaba.com>
 
 	PR tree-optimization/95110

commit e1edfe597d9157b8b9b61c4677b38730a9a59936
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Wed Jun 24 22:33:11 2020 +0200

    Revert "PR fortran/95689 - ICE in check_sym_interfaces, at fortran/interface.c:2015"
    
    With submodules, name mangling of interfaces may result in long internal
    symbols overflowing an internal buffer.  We now check that we do not
    exceed the enlarged buffer size.
    
    gcc/fortran/
            PR fortran/95689
            * interface.c (check_sym_interfaces): Enlarge temporary buffer,
            and add check on length on mangled name to prevent overflow.
    
    gcc/testsuite/
            PR fortran/95689
            * gfortran.dg/pr95689.f90: New test.
    
            (reverts the cherry-pick from commit 62c0c0ea7bfb6f8f6b8d767b05120cafb6823da6)

diff --git a/gcc/fortran/interface.c b/gcc/fortran/interface.c
index ec8fd3a8f68..689c30210d7 100644
--- a/gcc/fortran/interface.c
+++ b/gcc/fortran/interface.c
@@ -1944,8 +1944,7 @@ check_interface1 (gfc_interface *p, gfc_interface *q0,
 static void
 check_sym_interfaces (gfc_symbol *sym)
 {
-  /* Provide sufficient space to hold "generic interface 'symbol.symbol'".  */
-  char interface_name[2*GFC_MAX_SYMBOL_LEN+2 + sizeof("generic interface ''")];
+  char interface_name[GFC_MAX_SYMBOL_LEN + sizeof("generic interface ''")];
   gfc_interface *p;
 
   if (sym->ns != gfc_current_ns)
@@ -1953,8 +1952,6 @@ check_sym_interfaces (gfc_symbol *sym)
 
   if (sym->generic != NULL)
     {
-      size_t len = strlen (sym->name) + sizeof("generic interface ''");
-      gcc_assert (len < sizeof (interface_name));
       sprintf (interface_name, "generic interface '%s'", sym->name);
       if (check_interface0 (sym->generic, interface_name))
 	return;
diff --git a/gcc/testsuite/gfortran.dg/pr95689.f90 b/gcc/testsuite/gfortran.dg/pr95689.f90
deleted file mode 100644
index 287ae50b0cb..00000000000
--- a/gcc/testsuite/gfortran.dg/pr95689.f90
+++ /dev/null
@@ -1,16 +0,0 @@
-! { dg-do compile }
-! { dg-options "-fsecond-underscore" }
-! PR fortran/95689 - ICE in check_sym_interfaces, at fortran/interface.c:2015
-
-module m2345678901234567890123456789012345678901234567890123456789_123
-  type t2345678901234567890123456789012345678901234567890123456789_123
-   end type
-   interface
-      module subroutine s2345678901234567890123456789012345678901234567890123456789_123 &
-                       (x2345678901234567890123456789012345678901234567890123456789_123)
-      end
-   end interface
-end
-submodule(m2345678901234567890123456789012345678901234567890123456789_123) &
-          t2345678901234567890123456789012345678901234567890123456789_123
-end

commit 58b191815896857d540937704f85e7574ae4b792
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jun 25 00:17:35 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1e6790229fe..ab7687c5b0d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200624
+20200625
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 6b6fb37a1be..c30feaa5d76 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,9 @@
+2020-06-24  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/95689
+	* interface.c (check_sym_interfaces): Enlarge temporary buffer,
+	and add check on length on mangled name to prevent overflow.
+
 2020-06-23  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ed70818d4fc..ac3300985fb 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2020-06-24  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/95689
+	* gfortran.dg/pr95689.f90: New test.
+	(reverts the cherry-pick from commit 62c0c0ea7bfb6f8f6b8d767b05120cafb6823da6)
+
 2020-06-23  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:

commit e39a8763c4dead0f448981d9488d7b264db9da55
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Jun 24 09:12:47 2020 -0700

    x96: Remove PTA_CLWB from PTA_ICELAKE_CLIENT
    
    CLWB isn't supported on Ice Lake client.  But Ice Lake server support it.
    Move PTA_CLWB to PTA_ICELAKE_SERVER.
    
            PR target/95874
            * config/i386/i386.c (PTA_ICELAKE_CLIENT): Remove PTA_CLWB.
            (PTA_ICELAKE_SERVER): Add PTA_CLWB.
    
    (cherry picked from commit c422e5f81f42a0fc197f0715f4fcd81f1be90bff)

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index f1baecda28e..7ea67fe64de 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3385,9 +3385,9 @@ ix86_option_override_internal (bool main_args_p,
     | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
   const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
     | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
-    | PTA_RDPID | PTA_CLWB | PTA_AVX512VPOPCNTDQ;
+    | PTA_RDPID | PTA_AVX512VPOPCNTDQ;
   const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
-    | PTA_WBNOINVD;
+    | PTA_WBNOINVD | PTA_CLWB;
   const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
     | PTA_AVX512F | PTA_AVX512CD;
   const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;

commit 985e3cda5669c10d1ef713bfad1b8aad64ee54d0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jun 26 00:17:32 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c8483a6f56a..f45758eb967 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-06-25  H.J. Lu  <hjl.tools@gmail.com>
+
+	Backported from master:
+	2020-06-25  H.J. Lu  <hjl.tools@gmail.com>
+
+	PR target/95874
+	* config/i386/i386.c (PTA_ICELAKE_CLIENT): Remove PTA_CLWB.
+	(PTA_ICELAKE_SERVER): Add PTA_CLWB.
+
 2020-06-20  Bin Cheng  <bin.cheng@linux.alibaba.com>
 
 	PR tree-optimization/94969
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ab7687c5b0d..17bd6d56b3d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200625
+20200626

commit 7bba78283adcc9f3153d90358b57a27e270b0572
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jun 27 00:17:31 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 17bd6d56b3d..a93dbc29b11 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200626
+20200627

commit 160a8aed47609576da2bb9958f03406625bd7fe8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jun 28 00:17:32 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a93dbc29b11..47ccf01cbbe 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200627
+20200628

commit b0b770c42f266d87c022aa5ae3f2c92dd7245a66
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jun 29 00:17:42 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 47ccf01cbbe..39082fd9fab 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200628
+20200629

commit e2cc377f4231467ab61876aee00746dbd9cd6573
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jun 30 09:03:38 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 39082fd9fab..88cb34f9be6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200629
+20200630

commit 4ff0022df0f013a9bea23e3f6d4025633b9dc528
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Mon May 18 16:29:04 2020 +0100

    arm: Don't generate invalid LDRD insns
    
    This fixes a bug in the arm backend where GCC generates invalid LDRD
    instructions. The LDRD instruction requires the first transfer register to be
    even, but GCC attempts to use odd registers here. For example, with the
    following C code:
    
        struct c {
          double a;
        } __attribute((aligned)) __attribute((packed));
        struct c d;
        struct c f(struct c);
        void e() { f(d); }
    
    The struct d is passed in registers r1 and r2 to the function f, and GCC
    attempted to do this with a LDRD instruction when compiling with -march=armv7-a
    on a soft float toolchain.
    
    The fix is analogous to the corresponding one for STRD in the same function:
    https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=52057dc4ac5295caebf83147f688d769c93cbc8d
    
    gcc/:
            * config/arm/arm.c (output_move_double): Fix codegen when loading into
            a register pair with an odd base register.
    
    gcc/testsuite/:
            * gcc.c-torture/compile/packed-aligned-1.c: New test.
            * gcc.c-torture/execute/packed-aligned.c: New test.
    
    (cherry picked from commit 8b8f3117263ca79b3febadadb07732588d99d5f6)

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index b7e734e897d..f990ca11bcb 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -18211,6 +18211,7 @@ output_move_double (rtx *operands, bool emit, int *count)
   if (code0 == REG)
     {
       unsigned int reg0 = REGNO (operands[0]);
+      const bool can_ldrd = TARGET_LDRD && (TARGET_THUMB2 || (reg0 % 2 == 0));
 
       otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
 
@@ -18222,7 +18223,7 @@ output_move_double (rtx *operands, bool emit, int *count)
 
 	  if (emit)
 	    {
-	      if (TARGET_LDRD
+	      if (can_ldrd
 		  && !(fix_cm3_ldrd && reg0 == REGNO(XEXP (operands[1], 0))))
 		output_asm_insn ("ldrd%?\t%0, [%m1]", operands);
 	      else
@@ -18231,7 +18232,7 @@ output_move_double (rtx *operands, bool emit, int *count)
 	  break;
 
 	case PRE_INC:
-	  gcc_assert (TARGET_LDRD);
+	  gcc_assert (can_ldrd);
 	  if (emit)
 	    output_asm_insn ("ldrd%?\t%0, [%m1, #8]!", operands);
 	  break;
@@ -18239,7 +18240,7 @@ output_move_double (rtx *operands, bool emit, int *count)
 	case PRE_DEC:
 	  if (emit)
 	    {
-	      if (TARGET_LDRD)
+	      if (can_ldrd)
 		output_asm_insn ("ldrd%?\t%0, [%m1, #-8]!", operands);
 	      else
 		output_asm_insn ("ldmdb%?\t%m1!, %M0", operands);
@@ -18249,7 +18250,7 @@ output_move_double (rtx *operands, bool emit, int *count)
 	case POST_INC:
 	  if (emit)
 	    {
-	      if (TARGET_LDRD)
+	      if (can_ldrd)
 		output_asm_insn ("ldrd%?\t%0, [%m1], #8", operands);
 	      else
 		output_asm_insn ("ldmia%?\t%m1!, %M0", operands);
@@ -18257,7 +18258,7 @@ output_move_double (rtx *operands, bool emit, int *count)
 	  break;
 
 	case POST_DEC:
-	  gcc_assert (TARGET_LDRD);
+	  gcc_assert (can_ldrd);
 	  if (emit)
 	    output_asm_insn ("ldrd%?\t%0, [%m1], #-8", operands);
 	  break;
@@ -18279,6 +18280,7 @@ output_move_double (rtx *operands, bool emit, int *count)
 		  /* Registers overlap so split out the increment.  */
 		  if (emit)
 		    {
+		      gcc_assert (can_ldrd);
 		      output_asm_insn ("add%?\t%1, %1, %2", otherops);
 		      output_asm_insn ("ldrd%?\t%0, [%1] @split", otherops);
 		    }
@@ -18290,10 +18292,11 @@ output_move_double (rtx *operands, bool emit, int *count)
 		  /* Use a single insn if we can.
 		     FIXME: IWMMXT allows offsets larger than ldrd can
 		     handle, fix these up with a pair of ldr.  */
-		  if (TARGET_THUMB2
+		  if (can_ldrd
+		      && (TARGET_THUMB2
 		      || !CONST_INT_P (otherops[2])
 		      || (INTVAL (otherops[2]) > -256
-			  && INTVAL (otherops[2]) < 256))
+			  && INTVAL (otherops[2]) < 256)))
 		    {
 		      if (emit)
 			output_asm_insn ("ldrd%?\t%0, [%1, %2]!", otherops);
@@ -18316,10 +18319,11 @@ output_move_double (rtx *operands, bool emit, int *count)
 	      /* Use a single insn if we can.
 		 FIXME: IWMMXT allows offsets larger than ldrd can handle,
 		 fix these up with a pair of ldr.  */
-	      if (TARGET_THUMB2
+	      if (can_ldrd
+		  && (TARGET_THUMB2
 		  || !CONST_INT_P (otherops[2])
 		  || (INTVAL (otherops[2]) > -256
-		      && INTVAL (otherops[2]) < 256))
+		      && INTVAL (otherops[2]) < 256)))
 		{
 		  if (emit)
 		    output_asm_insn ("ldrd%?\t%0, [%1], %2", otherops);
@@ -18350,7 +18354,7 @@ output_move_double (rtx *operands, bool emit, int *count)
 	  operands[1] = otherops[0];
 	  if (emit)
 	    {
-	      if (TARGET_LDRD)
+	      if (can_ldrd)
 		output_asm_insn ("ldrd%?\t%0, [%1]", operands);
 	      else
 		output_asm_insn ("ldmia%?\t%1, %M0", operands);
@@ -18395,7 +18399,7 @@ output_move_double (rtx *operands, bool emit, int *count)
 		    }
 		  otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1);
 		  operands[1] = otherops[0];
-		  if (TARGET_LDRD
+		  if (can_ldrd
 		      && (REG_P (otherops[2])
 			  || TARGET_THUMB2
 			  || (CONST_INT_P (otherops[2])
@@ -18456,7 +18460,7 @@ output_move_double (rtx *operands, bool emit, int *count)
 	      if (count)
 		*count = 2;
 
-	      if (TARGET_LDRD)
+	      if (can_ldrd)
 		return "ldrd%?\t%0, [%1]";
 
 	      return "ldmia%?\t%1, %M0";
diff --git a/gcc/testsuite/gcc.c-torture/compile/packed-aligned-1.c b/gcc/testsuite/gcc.c-torture/compile/packed-aligned-1.c
new file mode 100644
index 00000000000..9f0923e29ee
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/packed-aligned-1.c
@@ -0,0 +1,11 @@
+struct c {
+  double a;
+} __attribute((packed)) __attribute((aligned));
+
+void f(struct c *, struct c);
+
+void g(struct c *ptr)
+{
+  ptr++;
+  f(ptr, *ptr);
+}
diff --git a/gcc/testsuite/gcc.c-torture/execute/packed-aligned.c b/gcc/testsuite/gcc.c-torture/execute/packed-aligned.c
new file mode 100644
index 00000000000..f768af0ab02
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/packed-aligned.c
@@ -0,0 +1,28 @@
+struct c {
+  double a;
+} __attribute((packed)) __attribute((aligned));
+
+extern void abort(void);
+
+double g_expect = 32.25;
+
+void f(unsigned x, struct c y)
+{
+  if (x != 0)
+    abort();
+
+  if (y.a != g_expect)
+    abort();
+}
+
+struct c e = { 64.25 };
+
+int main(void)
+{
+  struct c d = { 32.25 };
+  f(0, d);
+
+  g_expect = 64.25;
+  f(0, e);
+  return 0;
+}

commit 6bd944f066b2a2c630959b1b460894cd512c6080
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jul 1 00:17:37 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f45758eb967..5c5a1a9ac63 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-06-30  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2020-05-18  Alex Coplan  <alex.coplan@arm.com>
+
+	* config/arm/arm.c (output_move_double): Fix codegen when loading into
+	a register pair with an odd base register.
+
 2020-06-25  H.J. Lu  <hjl.tools@gmail.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 88cb34f9be6..1fb34e73e11 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200630
+20200701
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ac3300985fb..3d0f1fff63e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-06-30  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2020-05-18  Alex Coplan  <alex.coplan@arm.com>
+
+	* gcc.c-torture/compile/packed-aligned-1.c: New test.
+	* gcc.c-torture/execute/packed-aligned.c: New test.
+
 2020-06-24  Harald Anlauf  <anlauf@gmx.de>
 
 	PR fortran/95689

commit 88b44ed719378a52e001a474bcf963ea4c4841b1
Author: Mark Eggleston <markeggleston@gcc.gnu.org>
Date:   Tue Jun 23 11:01:28 2020 +0100

    Fortran  : Bogus error with additional blanks in type(*) PR95829
    
    Checking for "* ) " instead of "*)" clears the bogus error.
    
    2020-07-01  Steven G. Kargl  <kargl@gcc.gnu.org>
    
    gcc/fortran/
    
            PR fortran/95829
            * decl.c (gfc_match_decl_type_spec): Compare with "* ) " instead
            of "*)".
    
    2020-07-01  Mark Eggleston  <markeggleston@gcc.gnu.org>
    
    gcc/testsuite/
    
            PR fortran/95829
            * gfortran.dg/pr95829.f90: New test.
    
    (cherry picked from commit 624e60f080989fa57756575a0bb47a97748b52b8)

diff --git a/gcc/fortran/decl.c b/gcc/fortran/decl.c
index 8e7327dc568..3d04e65015d 100644
--- a/gcc/fortran/decl.c
+++ b/gcc/fortran/decl.c
@@ -3928,7 +3928,7 @@ gfc_match_decl_type_spec (gfc_typespec *ts, int implicit_flag)
       gfc_gobble_whitespace ();
       if (gfc_peek_ascii_char () == '*')
 	{
-	  if ((m = gfc_match ("*)")) != MATCH_YES)
+	  if ((m = gfc_match ("* ) ")) != MATCH_YES)
 	    return m;
 	  if (gfc_comp_struct (gfc_current_state ()))
 	    {
diff --git a/gcc/testsuite/gfortran.dg/pr95829.f90 b/gcc/testsuite/gfortran.dg/pr95829.f90
new file mode 100644
index 00000000000..081d647c7c0
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr95829.f90
@@ -0,0 +1,14 @@
+! { dg-do compile }
+!
+! Declaration of b used to be a bogus failure.
+
+subroutine s (a, b, c, d, e, f, g)
+  type(*) :: a
+  type(* ) :: b
+  type( *) :: c
+  type( * ) :: d
+  type(*  ) :: e
+  type(  *) :: f
+  type(  *  ) :: g
+end
+

commit 43cd501a48e869fa44617c78c100de956d0c78c0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jul 2 00:17:35 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1fb34e73e11..d5b9f0ff5db 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200701
+20200702
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index c30feaa5d76..ec4b0704aad 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,13 @@
+2020-07-01  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	Backported from master:
+	2020-07-01  Steven G. Kargl  <kargl@gcc.gnu.org>
+		    Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	PR fortran/95829
+	* decl.c (gfc_match_decl_type_spec): Compare with "* ) " instead
+	of "*)".
+
 2020-06-24  Harald Anlauf  <anlauf@gmx.de>
 
 	PR fortran/95689
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3d0f1fff63e..4ca1e01ea61 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-07-01  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	Backported from master:
+	2020-07-01  Steven G. Kargl  <kargl@gcc.gnu.org>
+
+	PR fortran/95829
+	* gfortran.dg/pr95829.f90: New test.
+
 2020-06-30  Alex Coplan  <alex.coplan@arm.com>
 
 	Backported from master:

commit ee7491826111f55ff6aed4f04f1812ce19f68196
Author: Martin Liska <mliska@suse.cz>
Date:   Thu Jul 2 10:51:06 2020 +0200

    gcc-changelog: sync from master.
    
    contrib/ChangeLog:
    
            * gcc-changelog/git_check_commit.py: New file.
            * gcc-changelog/git_commit.py: New file.
            * gcc-changelog/git_email.py: New file.
            * gcc-changelog/git_repository.py: New file.
            * gcc-changelog/git_update_version.py: New file.
            * gcc-changelog/test_email.py: New file.
            * gcc-changelog/test_patches.txt: New file.

diff --git a/contrib/gcc-changelog/git_check_commit.py b/contrib/gcc-changelog/git_check_commit.py
new file mode 100755
index 00000000000..935425ef813
--- /dev/null
+++ b/contrib/gcc-changelog/git_check_commit.py
@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3, or (at your option) any later
+# version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.  */
+
+import argparse
+
+from git_repository import parse_git_revisions
+
+parser = argparse.ArgumentParser(description='Check git ChangeLog format '
+                                 'of a commit')
+parser.add_argument('revisions', default='HEAD', nargs='?',
+                    help='Git revisions (e.g. hash~5..hash or just hash)')
+parser.add_argument('-g', '--git-path', default='.',
+                    help='Path to git repository')
+parser.add_argument('-p', '--print-changelog', action='store_true',
+                    help='Print final changelog entires')
+parser.add_argument('-n', '--non-strict-mode', action='store_true',
+                    help='Use non-strict mode (allow changes in ChangeLog and '
+                    'other automatically updated files).')
+args = parser.parse_args()
+
+retval = 0
+for git_commit in parse_git_revisions(args.git_path, args.revisions,
+                                      not args.non_strict_mode):
+    res = 'OK' if git_commit.success else 'FAILED'
+    print('Checking %s: %s' % (git_commit.original_info.hexsha, res))
+    if git_commit.success:
+        if args.print_changelog:
+            git_commit.print_output()
+    else:
+        for error in git_commit.errors:
+            print('ERR: %s' % error)
+        retval = 1
+
+exit(retval)
diff --git a/contrib/gcc-changelog/git_commit.py b/contrib/gcc-changelog/git_commit.py
new file mode 100755
index 00000000000..4d003ccf496
--- /dev/null
+++ b/contrib/gcc-changelog/git_commit.py
@@ -0,0 +1,676 @@
+#!/usr/bin/env python3
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3, or (at your option) any later
+# version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.  */
+
+import os
+import re
+
+changelog_locations = set([
+    'config',
+    'contrib',
+    'contrib/header-tools',
+    'contrib/reghunt',
+    'contrib/regression',
+    'fixincludes',
+    'gcc/ada',
+    'gcc/analyzer',
+    'gcc/brig',
+    'gcc/c',
+    'gcc/c-family',
+    'gcc',
+    'gcc/cp',
+    'gcc/d',
+    'gcc/fortran',
+    'gcc/go',
+    'gcc/jit',
+    'gcc/lto',
+    'gcc/objc',
+    'gcc/objcp',
+    'gcc/po',
+    'gcc/testsuite',
+    'gnattools',
+    'gotools',
+    'include',
+    'intl',
+    'libada',
+    'libatomic',
+    'libbacktrace',
+    'libcc1',
+    'libcpp',
+    'libcpp/po',
+    'libdecnumber',
+    'libffi',
+    'libgcc',
+    'libgcc/config/avr/libf7',
+    'libgcc/config/libbid',
+    'libgfortran',
+    'libgomp',
+    'libhsail-rt',
+    'libiberty',
+    'libitm',
+    'libobjc',
+    'liboffloadmic',
+    'libphobos',
+    'libquadmath',
+    'libsanitizer',
+    'libssp',
+    'libstdc++-v3',
+    'libvtv',
+    'lto-plugin',
+    'maintainer-scripts',
+    'zlib'])
+
+bug_components = set([
+    'ada',
+    'analyzer',
+    'boehm-gc',
+    'bootstrap',
+    'c',
+    'c++',
+    'd',
+    'debug',
+    'demangler',
+    'driver',
+    'fastjar',
+    'fortran',
+    'gcov-profile',
+    'go',
+    'hsa',
+    'inline-asm',
+    'ipa',
+    'java',
+    'jit',
+    'libbacktrace',
+    'libf2c',
+    'libffi',
+    'libfortran',
+    'libgcc',
+    'libgcj',
+    'libgomp',
+    'libitm',
+    'libobjc',
+    'libquadmath',
+    'libstdc++',
+    'lto',
+    'middle-end',
+    'modula2',
+    'objc',
+    'objc++',
+    'other',
+    'pch',
+    'pending',
+    'plugins',
+    'preprocessor',
+    'regression',
+    'rtl-optimization',
+    'sanitizer',
+    'spam',
+    'target',
+    'testsuite',
+    'translation',
+    'tree-optimization',
+    'web'])
+
+ignored_prefixes = [
+    'gcc/d/dmd/',
+    'gcc/go/gofrontend/',
+    'gcc/testsuite/gdc.test/',
+    'gcc/testsuite/go.test/test/',
+    'libgo/',
+    'libphobos/libdruntime/',
+    'libphobos/src/',
+    'libsanitizer/',
+    ]
+
+wildcard_prefixes = [
+    'gcc/testsuite/',
+    'libstdc++-v3/doc/html/'
+    ]
+
+misc_files = [
+    'gcc/DATESTAMP',
+    'gcc/BASE-VER',
+    'gcc/DEV-PHASE'
+    ]
+
+author_line_regex = \
+        re.compile(r'^(?P<datetime>\d{4}-\d{2}-\d{2})\ {2}(?P<name>.*  <.*>)')
+additional_author_regex = re.compile(r'^\t(?P<spaces>\ *)?(?P<name>.*  <.*>)')
+changelog_regex = re.compile(r'^(?:[fF]or +)?([a-z0-9+-/]*)ChangeLog:?')
+pr_regex = re.compile(r'\tPR (?P<component>[a-z+-]+\/)?([0-9]+)$')
+dr_regex = re.compile(r'\tDR ([0-9]+)$')
+star_prefix_regex = re.compile(r'\t\*(?P<spaces>\ *)(?P<content>.*)')
+
+LINE_LIMIT = 100
+TAB_WIDTH = 8
+CO_AUTHORED_BY_PREFIX = 'co-authored-by: '
+CHERRY_PICK_PREFIX = '(cherry picked from commit '
+REVERT_PREFIX = 'This reverts commit '
+
+REVIEW_PREFIXES = ('reviewed-by: ', 'reviewed-on: ', 'signed-off-by: ',
+                   'acked-by: ', 'tested-by: ', 'reported-by: ',
+                   'suggested-by: ')
+DATE_FORMAT = '%Y-%m-%d'
+
+
+class Error:
+    def __init__(self, message, line=None):
+        self.message = message
+        self.line = line
+
+    def __repr__(self):
+        s = self.message
+        if self.line:
+            s += ':"%s"' % self.line
+        return s
+
+
+class ChangeLogEntry:
+    def __init__(self, folder, authors, prs):
+        self.folder = folder
+        # The 'list.copy()' function is not available before Python 3.3
+        self.author_lines = list(authors)
+        self.initial_prs = list(prs)
+        self.prs = list(prs)
+        self.lines = []
+        self.files = []
+        self.file_patterns = []
+
+    def parse_file_names(self):
+        # Whether the content currently processed is between a star prefix the
+        # end of the file list: a colon or an open paren.
+        in_location = False
+
+        for line in self.lines:
+            # If this line matches the star prefix, start the location
+            # processing on the information that follows the star.
+            m = star_prefix_regex.match(line)
+            if m:
+                in_location = True
+                line = m.group('content')
+
+            if in_location:
+                # Strip everything that is not a filename in "line": entities
+                # "(NAME)", entry text (the colon, if present, and anything
+                # that follows it).
+                if '(' in line:
+                    line = line[:line.index('(')]
+                    in_location = False
+                if ':' in line:
+                    line = line[:line.index(':')]
+                    in_location = False
+
+                # At this point, all that's left is a list of filenames
+                # separated by commas and whitespaces.
+                for file in line.split(','):
+                    file = file.strip()
+                    if file:
+                        if file.endswith('*'):
+                            self.file_patterns.append(file[:-1])
+                        else:
+                            self.files.append(file)
+
+    @property
+    def datetime(self):
+        for author in self.author_lines:
+            if author[1]:
+                return author[1]
+        return None
+
+    @property
+    def authors(self):
+        return [author_line[0] for author_line in self.author_lines]
+
+    @property
+    def is_empty(self):
+        return not self.lines and self.prs == self.initial_prs
+
+    def contains_author(self, author):
+        for author_lines in self.author_lines:
+            if author_lines[0] == author:
+                return True
+        return False
+
+
+class GitInfo:
+    def __init__(self, hexsha, date, author, lines, modified_files):
+        self.hexsha = hexsha
+        self.date = date
+        self.author = author
+        self.lines = lines
+        self.modified_files = modified_files
+
+
+class GitCommit:
+    def __init__(self, info, strict=True, commit_to_info_hook=None):
+        self.original_info = info
+        self.info = info
+        self.message = None
+        self.changes = None
+        self.changelog_entries = []
+        self.errors = []
+        self.top_level_authors = []
+        self.co_authors = []
+        self.top_level_prs = []
+        self.cherry_pick_commit = None
+        self.revert_commit = None
+        self.commit_to_info_hook = commit_to_info_hook
+
+        # Identify first if the commit is a Revert commit
+        for line in self.info.lines:
+            if line.startswith(REVERT_PREFIX):
+                self.revert_commit = line[len(REVERT_PREFIX):].rstrip('.')
+                break
+        if self.revert_commit:
+            self.info = self.commit_to_info_hook(self.revert_commit)
+
+        project_files = [f for f in self.info.modified_files
+                         if self.is_changelog_filename(f[0])
+                         or f[0] in misc_files]
+        ignored_files = [f for f in self.info.modified_files
+                         if self.in_ignored_location(f[0])]
+        if len(project_files) == len(self.info.modified_files):
+            # All modified files are only MISC files
+            return
+        elif project_files and strict:
+            self.errors.append(Error('ChangeLog, DATESTAMP, BASE-VER and '
+                                     'DEV-PHASE updates should be done '
+                                     'separately from normal commits'))
+            return
+
+        all_are_ignored = (len(project_files) + len(ignored_files)
+                           == len(self.info.modified_files))
+        self.parse_lines(all_are_ignored)
+        if self.changes:
+            self.parse_changelog()
+            self.parse_file_names()
+            self.check_for_empty_description()
+            self.deduce_changelog_locations()
+            self.check_file_patterns()
+            if not self.errors:
+                self.check_mentioned_files()
+                self.check_for_correct_changelog()
+
+    @property
+    def success(self):
+        return not self.errors
+
+    @property
+    def new_files(self):
+        return [x[0] for x in self.info.modified_files if x[1] == 'A']
+
+    @classmethod
+    def is_changelog_filename(cls, path):
+        return path.endswith('/ChangeLog') or path == 'ChangeLog'
+
+    @classmethod
+    def find_changelog_location(cls, name):
+        if name.startswith('\t'):
+            name = name[1:]
+        if name.endswith(':'):
+            name = name[:-1]
+        if name.endswith('/'):
+            name = name[:-1]
+        return name if name in changelog_locations else None
+
+    @classmethod
+    def format_git_author(cls, author):
+        assert '<' in author
+        return author.replace('<', ' <')
+
+    @classmethod
+    def parse_git_name_status(cls, string):
+        modified_files = []
+        for entry in string.split('\n'):
+            parts = entry.split('\t')
+            t = parts[0]
+            if t == 'A' or t == 'D' or t == 'M':
+                modified_files.append((parts[1], t))
+            elif t.startswith('R'):
+                modified_files.append((parts[1], 'D'))
+                modified_files.append((parts[2], 'A'))
+        return modified_files
+
+    def parse_lines(self, all_are_ignored):
+        body = self.info.lines
+
+        for i, b in enumerate(body):
+            if not b:
+                continue
+            if (changelog_regex.match(b) or self.find_changelog_location(b)
+                    or star_prefix_regex.match(b) or pr_regex.match(b)
+                    or dr_regex.match(b) or author_line_regex.match(b)):
+                self.changes = body[i:]
+                return
+        if not all_are_ignored:
+            self.errors.append(Error('cannot find a ChangeLog location in '
+                                     'message'))
+
+    def parse_changelog(self):
+        last_entry = None
+        will_deduce = False
+        for line in self.changes:
+            if not line:
+                if last_entry and will_deduce:
+                    last_entry = None
+                continue
+            if line != line.rstrip():
+                self.errors.append(Error('trailing whitespace', line))
+            if len(line.replace('\t', ' ' * TAB_WIDTH)) > LINE_LIMIT:
+                self.errors.append(Error('line exceeds %d character limit'
+                                         % LINE_LIMIT, line))
+            m = changelog_regex.match(line)
+            if m:
+                last_entry = ChangeLogEntry(m.group(1).rstrip('/'),
+                                            self.top_level_authors,
+                                            self.top_level_prs)
+                self.changelog_entries.append(last_entry)
+            elif self.find_changelog_location(line):
+                last_entry = ChangeLogEntry(self.find_changelog_location(line),
+                                            self.top_level_authors,
+                                            self.top_level_prs)
+                self.changelog_entries.append(last_entry)
+            else:
+                author_tuple = None
+                pr_line = None
+                if author_line_regex.match(line):
+                    m = author_line_regex.match(line)
+                    author_tuple = (m.group('name'), m.group('datetime'))
+                elif additional_author_regex.match(line):
+                    m = additional_author_regex.match(line)
+                    if len(m.group('spaces')) != 4:
+                        msg = 'additional author must be indented with '\
+                              'one tab and four spaces'
+                        self.errors.append(Error(msg, line))
+                    else:
+                        author_tuple = (m.group('name'), None)
+                elif pr_regex.match(line):
+                    component = pr_regex.match(line).group('component')
+                    if not component:
+                        self.errors.append(Error('missing PR component', line))
+                        continue
+                    elif not component[:-1] in bug_components:
+                        self.errors.append(Error('invalid PR component', line))
+                        continue
+                    else:
+                        pr_line = line.lstrip()
+                elif dr_regex.match(line):
+                    pr_line = line.lstrip()
+
+                lowered_line = line.lower()
+                if lowered_line.startswith(CO_AUTHORED_BY_PREFIX):
+                    name = line[len(CO_AUTHORED_BY_PREFIX):]
+                    author = self.format_git_author(name)
+                    self.co_authors.append(author)
+                    continue
+                elif lowered_line.startswith(REVIEW_PREFIXES):
+                    continue
+                elif line.startswith(CHERRY_PICK_PREFIX):
+                    commit = line[len(CHERRY_PICK_PREFIX):].rstrip(')')
+                    self.cherry_pick_commit = commit
+                    continue
+
+                # ChangeLog name will be deduced later
+                if not last_entry:
+                    if author_tuple:
+                        self.top_level_authors.append(author_tuple)
+                        continue
+                    elif pr_line:
+                        # append to top_level_prs only when we haven't met
+                        # a ChangeLog entry
+                        if (pr_line not in self.top_level_prs
+                                and not self.changelog_entries):
+                            self.top_level_prs.append(pr_line)
+                        continue
+                    else:
+                        last_entry = ChangeLogEntry(None,
+                                                    self.top_level_authors,
+                                                    self.top_level_prs)
+                        self.changelog_entries.append(last_entry)
+                        will_deduce = True
+                elif author_tuple:
+                    if not last_entry.contains_author(author_tuple[0]):
+                        last_entry.author_lines.append(author_tuple)
+                    continue
+
+                if not line.startswith('\t'):
+                    err = Error('line should start with a tab', line)
+                    self.errors.append(err)
+                elif pr_line:
+                    last_entry.prs.append(pr_line)
+                else:
+                    m = star_prefix_regex.match(line)
+                    if m:
+                        if len(m.group('spaces')) != 1:
+                            msg = 'one space should follow asterisk'
+                            self.errors.append(Error(msg, line))
+                        else:
+                            last_entry.lines.append(line)
+                    else:
+                        if last_entry.is_empty:
+                            msg = 'first line should start with a tab, ' \
+                                  'an asterisk and a space'
+                            self.errors.append(Error(msg, line))
+                        else:
+                            last_entry.lines.append(line)
+
+    def parse_file_names(self):
+        for entry in self.changelog_entries:
+            entry.parse_file_names()
+
+    def check_file_patterns(self):
+        for entry in self.changelog_entries:
+            for pattern in entry.file_patterns:
+                name = os.path.join(entry.folder, pattern)
+                if name not in wildcard_prefixes:
+                    msg = 'unsupported wildcard prefix'
+                    self.errors.append(Error(msg, name))
+
+    def check_for_empty_description(self):
+        for entry in self.changelog_entries:
+            for i, line in enumerate(entry.lines):
+                if (star_prefix_regex.match(line) and line.endswith(':') and
+                    (i == len(entry.lines) - 1
+                     or star_prefix_regex.match(entry.lines[i + 1]))):
+                    msg = 'missing description of a change'
+                    self.errors.append(Error(msg, line))
+
+    def get_file_changelog_location(self, changelog_file):
+        for file in self.info.modified_files:
+            if file[0] == changelog_file:
+                # root ChangeLog file
+                return ''
+            index = file[0].find('/' + changelog_file)
+            if index != -1:
+                return file[0][:index]
+        return None
+
+    def deduce_changelog_locations(self):
+        for entry in self.changelog_entries:
+            if not entry.folder:
+                changelog = None
+                for file in entry.files:
+                    location = self.get_file_changelog_location(file)
+                    if (location == ''
+                       or (location and location in changelog_locations)):
+                        if changelog and changelog != location:
+                            msg = 'could not deduce ChangeLog file, ' \
+                                  'not unique location'
+                            self.errors.append(Error(msg))
+                            return
+                        changelog = location
+                if changelog is not None:
+                    entry.folder = changelog
+                else:
+                    msg = 'could not deduce ChangeLog file'
+                    self.errors.append(Error(msg))
+
+    @classmethod
+    def in_ignored_location(cls, path):
+        for ignored in ignored_prefixes:
+            if path.startswith(ignored):
+                return True
+        return False
+
+    @classmethod
+    def get_changelog_by_path(cls, path):
+        components = path.split('/')
+        while components:
+            if '/'.join(components) in changelog_locations:
+                break
+            components = components[:-1]
+        return '/'.join(components)
+
+    def check_mentioned_files(self):
+        folder_count = len([x.folder for x in self.changelog_entries])
+        assert folder_count == len(self.changelog_entries)
+
+        mentioned_files = set()
+        mentioned_patterns = []
+        used_patterns = set()
+        for entry in self.changelog_entries:
+            if not entry.files:
+                msg = 'no files mentioned for ChangeLog in directory'
+                self.errors.append(Error(msg, entry.folder))
+            assert not entry.folder.endswith('/')
+            for file in entry.files:
+                if not self.is_changelog_filename(file):
+                    mentioned_files.add(os.path.join(entry.folder, file))
+            for pattern in entry.file_patterns:
+                mentioned_patterns.append(os.path.join(entry.folder, pattern))
+
+        cand = [x[0] for x in self.info.modified_files
+                if not self.is_changelog_filename(x[0])]
+        changed_files = set(cand)
+        for file in sorted(mentioned_files - changed_files):
+            msg = 'unchanged file mentioned in a ChangeLog'
+            self.errors.append(Error(msg, file))
+        for file in sorted(changed_files - mentioned_files):
+            if not self.in_ignored_location(file):
+                if file in self.new_files:
+                    changelog_location = self.get_changelog_by_path(file)
+                    # Python2: we cannot use next(filter(...))
+                    entries = filter(lambda x: x.folder == changelog_location,
+                                     self.changelog_entries)
+                    entries = list(entries)
+                    entry = entries[0] if entries else None
+                    if not entry:
+                        prs = self.top_level_prs
+                        if not prs:
+                            # if all ChangeLog entries have identical PRs
+                            # then use them
+                            prs = self.changelog_entries[0].prs
+                            for entry in self.changelog_entries:
+                                if entry.prs != prs:
+                                    prs = []
+                                    break
+                        entry = ChangeLogEntry(changelog_location,
+                                               self.top_level_authors,
+                                               prs)
+                        self.changelog_entries.append(entry)
+                    # strip prefix of the file
+                    assert file.startswith(entry.folder)
+                    file = file[len(entry.folder):].lstrip('/')
+                    entry.lines.append('\t* %s: New file.' % file)
+                    entry.files.append(file)
+                else:
+                    used_pattern = [p for p in mentioned_patterns
+                                    if file.startswith(p)]
+                    used_pattern = used_pattern[0] if used_pattern else None
+                    if used_pattern:
+                        used_patterns.add(used_pattern)
+                    else:
+                        msg = 'changed file not mentioned in a ChangeLog'
+                        self.errors.append(Error(msg, file))
+
+        for pattern in mentioned_patterns:
+            if pattern not in used_patterns:
+                error = 'pattern doesn''t match any changed files'
+                self.errors.append(Error(error, pattern))
+
+    def check_for_correct_changelog(self):
+        for entry in self.changelog_entries:
+            for file in entry.files:
+                full_path = os.path.join(entry.folder, file)
+                changelog_location = self.get_changelog_by_path(full_path)
+                if changelog_location != entry.folder:
+                    msg = 'wrong ChangeLog location "%s", should be "%s"'
+                    err = Error(msg % (entry.folder, changelog_location), file)
+                    self.errors.append(err)
+
+    @classmethod
+    def format_authors_in_changelog(cls, authors, timestamp, prefix=''):
+        output = ''
+        for i, author in enumerate(authors):
+            if i == 0:
+                output += '%s%s  %s\n' % (prefix, timestamp, author)
+            else:
+                output += '%s\t    %s\n' % (prefix, author)
+        output += '\n'
+        return output
+
+    def to_changelog_entries(self, use_commit_ts=False):
+        current_timestamp = self.info.date.strftime(DATE_FORMAT)
+        for entry in self.changelog_entries:
+            output = ''
+            timestamp = entry.datetime
+            if self.cherry_pick_commit:
+                info = self.commit_to_info_hook(self.cherry_pick_commit)
+                # it can happen that it is a cherry-pick for a different
+                # repository
+                if info:
+                    timestamp = info.date.strftime(DATE_FORMAT)
+                else:
+                    timestamp = current_timestamp
+            elif self.revert_commit:
+                timestamp = current_timestamp
+                orig_date = self.original_info.date
+                current_timestamp = orig_date.strftime(DATE_FORMAT)
+            elif not timestamp or use_commit_ts:
+                timestamp = current_timestamp
+            authors = entry.authors if entry.authors else [self.info.author]
+            # add Co-Authored-By authors to all ChangeLog entries
+            for author in self.co_authors:
+                if author not in authors:
+                    authors.append(author)
+
+            if self.cherry_pick_commit or self.revert_commit:
+                output += self.format_authors_in_changelog([self.info.author],
+                                                           current_timestamp)
+                if self.cherry_pick_commit:
+                    output += '\tBackported from master:\n'
+                else:
+                    output += '\tRevert:\n'
+                output += self.format_authors_in_changelog(authors,
+                                                           timestamp, '\t')
+            else:
+                output += self.format_authors_in_changelog(authors, timestamp)
+            for pr in entry.prs:
+                output += '\t%s\n' % pr
+            for line in entry.lines:
+                output += line + '\n'
+            yield (entry.folder, output.rstrip())
+
+    def print_output(self):
+        for entry, output in self.to_changelog_entries():
+            print('------ %s/ChangeLog ------ ' % entry)
+            print(output)
+
+    def print_errors(self):
+        print('Errors:')
+        for error in self.errors:
+            print(error)
diff --git a/contrib/gcc-changelog/git_email.py b/contrib/gcc-changelog/git_email.py
new file mode 100755
index 00000000000..014fdd1004b
--- /dev/null
+++ b/contrib/gcc-changelog/git_email.py
@@ -0,0 +1,107 @@
+#!/usr/bin/env python3
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3, or (at your option) any later
+# version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.  */
+
+import os
+import sys
+from itertools import takewhile
+
+from dateutil.parser import parse
+
+from git_commit import GitCommit, GitInfo
+
+from unidiff import PatchSet
+
+DATE_PREFIX = 'Date: '
+FROM_PREFIX = 'From: '
+
+
+class GitEmail(GitCommit):
+    def __init__(self, filename, strict=False):
+        self.filename = filename
+        diff = PatchSet.from_filename(filename)
+        date = None
+        author = None
+
+        with open(self.filename, 'r') as f:
+            lines = f.read().splitlines()
+        lines = list(takewhile(lambda line: line != '---', lines))
+        for line in lines:
+            if line.startswith(DATE_PREFIX):
+                date = parse(line[len(DATE_PREFIX):])
+            elif line.startswith(FROM_PREFIX):
+                author = GitCommit.format_git_author(line[len(FROM_PREFIX):])
+        header = list(takewhile(lambda line: line != '', lines))
+        body = lines[len(header) + 1:]
+
+        modified_files = []
+        for f in diff:
+            # Strip "a/" and "b/" prefixes
+            source = f.source_file[2:]
+            target = f.target_file[2:]
+
+            if f.is_added_file:
+                t = 'A'
+            elif f.is_removed_file:
+                t = 'D'
+            elif f.is_rename:
+                # Consider that renamed files are two operations: the deletion
+                # of the original name and the addition of the new one.
+                modified_files.append((source, 'D'))
+                t = 'A'
+            else:
+                t = 'M'
+            modified_files.append((target, t))
+        git_info = GitInfo(None, date, author, body, modified_files)
+        super().__init__(git_info, strict=strict,
+                         commit_to_info_hook=lambda x: None)
+
+
+# With zero arguments, process every patch file in the ./patches directory.
+# With one argument, process the named patch file.
+# Patch files must be in 'git format-patch' format.
+if __name__ == '__main__':
+    if len(sys.argv) == 1:
+        allfiles = []
+        for root, _dirs, files in os.walk('patches'):
+            for f in files:
+                full = os.path.join(root, f)
+                allfiles.append(full)
+
+        success = 0
+        for full in sorted(allfiles):
+            email = GitEmail(full, False)
+            print(email.filename)
+            if email.success:
+                success += 1
+                print('  OK')
+            else:
+                for error in email.errors:
+                    print('  ERR: %s' % error)
+
+        print()
+        print('Successfully parsed: %d/%d' % (success, len(allfiles)))
+    else:
+        email = GitEmail(sys.argv[1], False)
+        if email.success:
+            print('OK')
+            email.print_output()
+        else:
+            if not email.info.lines:
+                print('Error: patch contains no parsed lines', file=sys.stderr)
+            email.print_errors()
+            sys.exit(1)
diff --git a/contrib/gcc-changelog/git_repository.py b/contrib/gcc-changelog/git_repository.py
new file mode 100755
index 00000000000..90edc3ce3d8
--- /dev/null
+++ b/contrib/gcc-changelog/git_repository.py
@@ -0,0 +1,78 @@
+#!/usr/bin/env python3
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3, or (at your option) any later
+# version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.  */
+
+from datetime import datetime
+
+try:
+    from git import Repo
+except ImportError:
+    print('Cannot import GitPython package, please install the package:')
+    print('  Fedora, openSUSE: python3-GitPython')
+    print('  Debian, Ubuntu: python3-git')
+    exit(1)
+
+from git_commit import GitCommit, GitInfo
+
+
+def parse_git_revisions(repo_path, revisions, strict=False):
+    repo = Repo(repo_path)
+
+    def commit_to_info(commit):
+        try:
+            c = repo.commit(commit)
+            diff = repo.commit(commit + '~').diff(commit)
+
+            modified_files = []
+            for file in diff:
+                if hasattr(file, 'renamed_file'):
+                    is_renamed = file.renamed_file
+                else:
+                    is_renamed = file.renamed
+                if file.new_file:
+                    t = 'A'
+                elif file.deleted_file:
+                    t = 'D'
+                elif is_renamed:
+                    # Consider that renamed files are two operations:
+                    # the deletion of the original name
+                    # and the addition of the new one.
+                    modified_files.append((file.a_path, 'D'))
+                    t = 'A'
+                else:
+                    t = 'M'
+                modified_files.append((file.b_path, t))
+
+            date = datetime.utcfromtimestamp(c.committed_date)
+            author = '%s  <%s>' % (c.author.name, c.author.email)
+            git_info = GitInfo(c.hexsha, date, author,
+                               c.message.split('\n'), modified_files)
+            return git_info
+        except ValueError:
+            return None
+
+    parsed_commits = []
+    if '..' in revisions:
+        commits = list(repo.iter_commits(revisions))
+    else:
+        commits = [repo.commit(revisions)]
+
+    for commit in commits:
+        git_commit = GitCommit(commit_to_info(commit.hexsha), strict=strict,
+                               commit_to_info_hook=commit_to_info)
+        parsed_commits.append(git_commit)
+    return parsed_commits
diff --git a/contrib/gcc-changelog/git_update_version.py b/contrib/gcc-changelog/git_update_version.py
new file mode 100755
index 00000000000..ac1b206d238
--- /dev/null
+++ b/contrib/gcc-changelog/git_update_version.py
@@ -0,0 +1,145 @@
+#!/usr/bin/env python3
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3, or (at your option) any later
+# version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.  */
+
+import argparse
+import datetime
+import os
+
+from git import Repo
+
+from git_repository import parse_git_revisions
+
+current_timestamp = datetime.datetime.now().strftime('%Y%m%d\n')
+
+
+def read_timestamp(path):
+    with open(path) as f:
+        return f.read()
+
+
+def prepend_to_changelog_files(repo, folder, git_commit, add_to_git):
+    if not git_commit.success:
+        for error in git_commit.errors:
+            print(error)
+        raise AssertionError()
+    for entry, output in git_commit.to_changelog_entries(use_commit_ts=True):
+        full_path = os.path.join(folder, entry, 'ChangeLog')
+        print('writting to %s' % full_path)
+        if os.path.exists(full_path):
+            with open(full_path) as f:
+                content = f.read()
+        else:
+            content = ''
+        with open(full_path, 'w+') as f:
+            f.write(output)
+            if content:
+                f.write('\n\n')
+                f.write(content)
+        if add_to_git:
+            repo.git.add(full_path)
+
+
+active_refs = ['master', 'releases/gcc-8', 'releases/gcc-9', 'releases/gcc-10']
+
+parser = argparse.ArgumentParser(description='Update DATESTAMP and generate '
+                                 'ChangeLog entries')
+parser.add_argument('-g', '--git-path', default='.',
+                    help='Path to git repository')
+parser.add_argument('-p', '--push', action='store_true',
+                    help='Push updated active branches')
+parser.add_argument('-d', '--dry-mode',
+                    help='Generate patch for ChangeLog entries and do it'
+                         ' even if DATESTAMP is unchanged; folder argument'
+                         ' is expected')
+parser.add_argument('-c', '--current', action='store_true',
+                    help='Modify current branch (--push argument is ignored)')
+args = parser.parse_args()
+
+repo = Repo(args.git_path)
+origin = repo.remotes['origin']
+
+
+def update_current_branch():
+    commit = repo.head.commit
+    commit_count = 1
+    while commit:
+        if (commit.author.email == 'gccadmin@gcc.gnu.org'
+                and commit.message.strip() == 'Daily bump.'):
+            break
+        # We support merge commits but only with 2 parensts
+        assert len(commit.parents) <= 2
+        commit = commit.parents[-1]
+        commit_count += 1
+
+    print('%d revisions since last Daily bump' % commit_count)
+    datestamp_path = os.path.join(args.git_path, 'gcc/DATESTAMP')
+    if (read_timestamp(datestamp_path) != current_timestamp
+            or args.dry_mode or args.current):
+        head = repo.head.commit
+        # if HEAD is a merge commit, start with second parent
+        # (branched that is being merged into the current one)
+        assert len(head.parents) <= 2
+        if len(head.parents) == 2:
+            head = head.parents[1]
+        commits = parse_git_revisions(args.git_path, '%s..%s'
+                                      % (commit.hexsha, head.hexsha))
+        for git_commit in reversed(commits):
+            prepend_to_changelog_files(repo, args.git_path, git_commit,
+                                       not args.dry_mode)
+        if args.dry_mode:
+            diff = repo.git.diff('HEAD')
+            patch = os.path.join(args.dry_mode,
+                                 branch.name.split('/')[-1] + '.patch')
+            with open(patch, 'w+') as f:
+                f.write(diff)
+            print('branch diff written to %s' % patch)
+            repo.git.checkout(force=True)
+        else:
+            # update timestamp
+            print('DATESTAMP will be changed:')
+            with open(datestamp_path, 'w+') as f:
+                f.write(current_timestamp)
+            repo.git.add(datestamp_path)
+            if not args.current:
+                repo.index.commit('Daily bump.')
+                if args.push:
+                    repo.git.push('origin', branch)
+                    print('branch is pushed')
+    else:
+        print('DATESTAMP unchanged')
+
+
+if args.current:
+    print('=== Working on the current branch ===', flush=True)
+    update_current_branch()
+else:
+    for ref in origin.refs:
+        assert ref.name.startswith('origin/')
+        name = ref.name[len('origin/'):]
+        if name in active_refs:
+            if name in repo.branches:
+                branch = repo.branches[name]
+            else:
+                branch = repo.create_head(name, ref).set_tracking_branch(ref)
+            print('=== Working on: %s ===' % branch, flush=True)
+            branch.checkout()
+            origin.pull(rebase=True)
+            print('branch pulled and checked out')
+            update_current_branch()
+            assert not repo.index.diff(None)
+            print('branch is done\n', flush=True)
diff --git a/contrib/gcc-changelog/test_email.py b/contrib/gcc-changelog/test_email.py
new file mode 100755
index 00000000000..1c9f8847fe7
--- /dev/null
+++ b/contrib/gcc-changelog/test_email.py
@@ -0,0 +1,363 @@
+#!/usr/bin/env python3
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3, or (at your option) any later
+# version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.  */
+
+import os
+import tempfile
+import unittest
+
+from git_commit import GitCommit
+
+from git_email import GitEmail
+
+import unidiff
+
+script_path = os.path.dirname(os.path.realpath(__file__))
+
+unidiff_supports_renaming = hasattr(unidiff.PatchedFile(), 'is_rename')
+
+
+NAME_STATUS1 = """
+M	gcc/ada/impunit.adb'
+R097	gcc/ada/libgnat/s-atopar.adb	gcc/ada/libgnat/s-aoinar.adb
+"""
+
+
+class TestGccChangelog(unittest.TestCase):
+    def setUp(self):
+        self.patches = {}
+        self.temps = []
+
+        filename = None
+        patch_lines = []
+        with open(os.path.join(script_path, 'test_patches.txt')) as f:
+            lines = f.read()
+        for line in lines.split('\n'):
+            if line.startswith('==='):
+                if patch_lines:
+                    self.patches[filename] = patch_lines
+                filename = line.split(' ')[1]
+                patch_lines = []
+            else:
+                patch_lines.append(line)
+        if patch_lines:
+            self.patches[filename] = patch_lines
+
+    def tearDown(self):
+        for t in self.temps:
+            assert t.endswith('.patch')
+            os.remove(t)
+
+    def get_git_email(self, filename, strict=False):
+        with tempfile.NamedTemporaryFile(mode='w+', suffix='.patch',
+                                         delete=False) as f:
+            f.write('\n'.join(self.patches[filename]))
+            self.temps.append(f.name)
+        return GitEmail(f.name, strict)
+
+    def from_patch_glob(self, name, strict=False):
+        files = [f for f in self.patches.keys() if f.startswith(name)]
+        assert len(files) == 1
+        return self.get_git_email(files[0], strict)
+
+    def test_simple_patch_format(self):
+        email = self.get_git_email('0577-aarch64-Add-an-and.patch')
+        assert not email.errors
+        assert len(email.changelog_entries) == 2
+        entry = email.changelog_entries[0]
+        assert (entry.author_lines ==
+                [('Richard Sandiford  <richard.sandiford@arm.com>',
+                  '2020-02-06')])
+        assert len(entry.authors) == 1
+        assert (entry.authors[0]
+                == 'Richard Sandiford  <richard.sandiford@arm.com>')
+        assert entry.folder == 'gcc'
+        assert entry.prs == ['PR target/87763']
+        assert len(entry.files) == 3
+        assert entry.files[0] == 'config/aarch64/aarch64-protos.h'
+
+    def test_daily_bump(self):
+        email = self.get_git_email('0085-Daily-bump.patch')
+        assert not email.errors
+        assert not email.changelog_entries
+
+    def test_deduce_changelog_entries(self):
+        email = self.from_patch_glob('0040')
+        assert len(email.changelog_entries) == 2
+        assert email.changelog_entries[0].folder == 'gcc/cp'
+        assert email.changelog_entries[0].prs == ['PR c++/90916']
+        assert email.changelog_entries[0].files == ['pt.c']
+        # this one is added automatically
+        assert email.changelog_entries[1].folder == 'gcc/testsuite'
+
+    def test_only_changelog_updated(self):
+        email = self.from_patch_glob('0129')
+        assert not email.errors
+        assert not email.changelog_entries
+
+    def test_wrong_mentioned_filename(self):
+        email = self.from_patch_glob('0096')
+        assert email.errors
+        err = email.errors[0]
+        assert err.message == 'unchanged file mentioned in a ChangeLog'
+        assert err.line == 'gcc/testsuite/gcc.target/aarch64/' \
+                           'advsimd-intrinsics/vdot-compile-3-1.c'
+
+    def test_missing_tab(self):
+        email = self.from_patch_glob('0031')
+        assert len(email.errors) == 2
+        err = email.errors[0]
+        assert err.message == 'line should start with a tab'
+        assert err.line == '    * cfgloopanal.c (average_num_loop_insns): ' \
+                           'Free bbs when early'
+
+    def test_leading_changelog_format(self):
+        email = self.from_patch_glob('0184')
+        assert len(email.errors) == 4
+        assert email.errors[0].line == 'gcc/c-family/c-cppbuiltins.c'
+        assert email.errors[2].line == 'gcc/c-family/c-cppbuiltin.c'
+
+    def test_cannot_deduce_no_blank_line(self):
+        email = self.from_patch_glob('0334')
+        assert len(email.errors) == 1
+        assert len(email.changelog_entries) == 1
+        assert email.changelog_entries[0].folder is None
+
+    def test_author_lines(self):
+        email = self.from_patch_glob('0814')
+        assert not email.errors
+        assert (email.changelog_entries[0].author_lines ==
+                [('Martin Jambor  <mjambor@suse.cz>', '2020-02-19')])
+
+    def test_multiple_authors_and_prs(self):
+        email = self.from_patch_glob('0735')
+        assert len(email.changelog_entries) == 1
+        entry = email.changelog_entries[0]
+        assert len(entry.author_lines) == 2
+        assert len(entry.authors) == 2
+        assert (entry.author_lines[1] ==
+                ('Bernd Edlinger  <bernd.edlinger@hotmail.de>', None))
+
+    def test_multiple_prs(self):
+        email = self.from_patch_glob('1699')
+        assert len(email.changelog_entries) == 2
+        assert len(email.changelog_entries[0].prs) == 2
+
+    def test_missing_PR_component(self):
+        email = self.from_patch_glob('0735')
+        assert len(email.errors) == 1
+        assert email.errors[0].message == 'missing PR component'
+
+    def test_invalid_PR_component(self):
+        email = self.from_patch_glob('0198')
+        assert len(email.errors) == 1
+        assert email.errors[0].message == 'invalid PR component'
+
+    def test_additional_author_list(self):
+        email = self.from_patch_glob('0342')
+        msg = 'additional author must be indented ' \
+              'with one tab and four spaces'
+        assert email.errors[1].message == msg
+
+    def test_trailing_whitespaces(self):
+        email = self.get_git_email('trailing-whitespaces.patch')
+        assert len(email.errors) == 3
+
+    def test_space_after_asterisk(self):
+        email = self.from_patch_glob('1999')
+        assert len(email.errors) == 1
+        assert email.errors[0].message == 'one space should follow asterisk'
+
+    def test_long_lines(self):
+        email = self.get_git_email('long-lines.patch')
+        assert len(email.errors) == 1
+        assert email.errors[0].message == 'line exceeds 100 character limit'
+
+    def test_new_files(self):
+        email = self.from_patch_glob('0030')
+        assert not email.errors
+
+    def test_wrong_changelog_location(self):
+        email = self.from_patch_glob('0043')
+        assert len(email.errors) == 2
+        assert (email.errors[0].message ==
+                'wrong ChangeLog location "gcc", should be "gcc/testsuite"')
+
+    def test_single_author_name(self):
+        email = self.from_patch_glob('1975')
+        assert len(email.changelog_entries) == 2
+        assert len(email.changelog_entries[0].author_lines) == 1
+        assert len(email.changelog_entries[1].author_lines) == 1
+
+    def test_bad_first_line(self):
+        email = self.from_patch_glob('0413')
+        assert len(email.errors) == 1
+
+    def test_co_authored_by(self):
+        email = self.from_patch_glob('1850')
+        assert email.co_authors == ['Jakub Jelinek  <jakub@redhat.com>']
+        output_entries = list(email.to_changelog_entries())
+        assert len(output_entries) == 2
+        ent0 = output_entries[0]
+        assert ent0[1].startswith('2020-04-16  Martin Liska  '
+                                  '<mliska@suse.cz>\n\t'
+                                  '    Jakub Jelinek  <jakub@redhat.com>')
+
+    def test_multiple_co_author_formats(self):
+        email = self.get_git_email('co-authored-by.patch')
+        assert len(email.co_authors) == 3
+        assert email.co_authors[0] == 'Jakub Jelinek  <jakub@redhat.com>'
+        assert email.co_authors[1] == 'John Miller  <jm@example.com>'
+        assert email.co_authors[2] == 'John Miller2  <jm2@example.com>'
+
+    def test_new_file_added_entry(self):
+        email = self.from_patch_glob('1957')
+        output_entries = list(email.to_changelog_entries())
+        assert len(output_entries) == 2
+        needle = ('\t* g++.dg/cpp2a/lambda-generic-variadic20.C'
+                  ': New file.')
+        assert output_entries[1][1].endswith(needle)
+        assert email.changelog_entries[1].prs == ['PR c++/94546']
+
+    def test_global_pr_entry(self):
+        email = self.from_patch_glob('2004')
+        assert not email.errors
+        assert email.changelog_entries[0].prs == ['PR other/94629']
+
+    def test_unique_prs(self):
+        email = self.get_git_email('pr-check1.patch')
+        assert not email.errors
+        assert email.changelog_entries[0].prs == ['PR ipa/12345']
+        assert email.changelog_entries[1].prs == []
+
+    def test_multiple_prs_not_added(self):
+        email = self.from_patch_glob('0001-Add-patch_are')
+        assert not email.errors
+        assert email.changelog_entries[0].prs == ['PR target/93492']
+        assert email.changelog_entries[1].prs == ['PR target/12345']
+        assert email.changelog_entries[2].prs == []
+        assert email.changelog_entries[2].folder == 'gcc/testsuite'
+
+    def test_strict_mode(self):
+        email = self.from_patch_glob('0001-Add-patch_are',
+                                     True)
+        msg = 'ChangeLog, DATESTAMP, BASE-VER and DEV-PHASE updates should ' \
+              'be done separately from normal commits'
+        assert email.errors[0].message == msg
+
+    def test_strict_mode_normal_patch(self):
+        email = self.get_git_email('0001-Just-test-it.patch', True)
+        assert not email.errors
+
+    def test_strict_mode_datestamp_only(self):
+        email = self.get_git_email('0002-Bump-date.patch', True)
+        assert not email.errors
+
+    def test_wrong_changelog_entry(self):
+        email = self.from_patch_glob('0020-IPA-Avoid')
+        msg = 'first line should start with a tab, an asterisk and a space'
+        assert (email.errors[0].message == msg)
+
+    def test_cherry_pick_format(self):
+        email = self.from_patch_glob('0001-c-Alias.patch')
+        assert not email.errors
+
+    def test_signatures(self):
+        email = self.from_patch_glob('0001-RISC-V-Make-unique.patch')
+        assert not email.errors
+        assert len(email.changelog_entries) == 1
+
+    def test_duplicate_top_level_author(self):
+        email = self.from_patch_glob('0001-Fortran-ProcPtr-function.patch')
+        assert not email.errors
+        assert len(email.changelog_entries[0].author_lines) == 1
+
+    def test_dr_entry(self):
+        email = self.from_patch_glob('0001-c-C-20-DR-2237.patch')
+        assert email.changelog_entries[0].prs == ['DR 2237']
+
+    def test_changes_only_in_ignored_location(self):
+        email = self.from_patch_glob('0001-go-in-ignored-location.patch')
+        assert not email.errors
+
+    def test_changelog_for_ignored_location(self):
+        email = self.from_patch_glob('0001-Update-merge.sh-to-reflect.patch')
+        assert (email.changelog_entries[0].lines[0]
+                == '\t* LOCAL_PATCHES: Use git hash instead of SVN id.')
+
+    def test_multiline_file_list(self):
+        email = self.from_patch_glob(
+            '0001-Ada-Reuse-Is_Package_Or_Generic_Package-where-possib.patch')
+        assert (email.changelog_entries[0].files
+                == ['contracts.adb', 'einfo.adb', 'exp_ch9.adb',
+                    'sem_ch12.adb', 'sem_ch4.adb', 'sem_ch7.adb',
+                    'sem_ch8.adb', 'sem_elab.adb', 'sem_type.adb',
+                    'sem_util.adb'])
+
+    @unittest.skipIf(not unidiff_supports_renaming,
+                     'Newer version of unidiff is needed (0.6.0+)')
+    def test_renamed_file(self):
+        email = self.from_patch_glob(
+            '0001-Ada-Add-support-for-XDR-streaming-in-the-default-run.patch')
+        assert not email.errors
+
+    def test_duplicite_author_lines(self):
+        email = self.from_patch_glob('0001-Fortran-type-is-real-kind-1.patch')
+        assert (email.changelog_entries[0].author_lines[0][0]
+                == 'Steven G. Kargl  <kargl@gcc.gnu.org>')
+        assert (email.changelog_entries[0].author_lines[1][0]
+                == 'Mark Eggleston  <markeggleston@gcc.gnu.org>')
+
+    def test_missing_change_description(self):
+        email = self.from_patch_glob('0001-Missing-change-description.patch')
+        assert len(email.errors) == 2
+        assert email.errors[0].message == 'missing description of a change'
+        assert email.errors[1].message == 'missing description of a change'
+
+    def test_libstdcxx_html_regenerated(self):
+        email = self.from_patch_glob('0001-Fix-text-of-hyperlink')
+        assert not email.errors
+        email = self.from_patch_glob('0002-libstdc-Fake-test-change-1.patch')
+        assert len(email.errors) == 1
+        msg = 'pattern doesn''t match any changed files'
+        assert email.errors[0].message == msg
+        assert email.errors[0].line == 'libstdc++-v3/doc/html/'
+        email = self.from_patch_glob('0003-libstdc-Fake-test-change-2.patch')
+        assert len(email.errors) == 1
+        msg = 'changed file not mentioned in a ChangeLog'
+        assert email.errors[0].message == msg
+
+    def test_not_deduce(self):
+        email = self.from_patch_glob('0001-configure.patch')
+        assert not email.errors
+        assert len(email.changelog_entries) == 2
+
+    def test_parse_git_name_status(self):
+        modified_files = GitCommit.parse_git_name_status(NAME_STATUS1)
+        assert len(modified_files) == 3
+        assert modified_files[1] == ('gcc/ada/libgnat/s-atopar.adb', 'D')
+        assert modified_files[2] == ('gcc/ada/libgnat/s-aoinar.adb', 'A')
+
+    def test_backport(self):
+        email = self.from_patch_glob('0001-asan-fix-RTX-emission.patch')
+        assert not email.errors
+        assert len(email.changelog_entries) == 1
+        entry = list(email.to_changelog_entries())[0][1]
+        assert entry.startswith('2020-06-11  Martin Liska  <mliska@suse.cz>')
+        assert '\tBackported from master:' in entry
+        assert '\t2020-06-11  Martin Liska  <mliska@suse.cz>' in entry
+        assert '\t\t    Jakub Jelinek  <jakub@redhat.com>' in entry
diff --git a/contrib/gcc-changelog/test_patches.txt b/contrib/gcc-changelog/test_patches.txt
new file mode 100644
index 00000000000..1463fb94936
--- /dev/null
+++ b/contrib/gcc-changelog/test_patches.txt
@@ -0,0 +1,3162 @@
+=== 0342-ARC-Propagate-uncached-type-attribute-to-each-member.patch ===
+From 62a715c706d8482560dadfa9ead0766f3c20e434 Mon Sep 17 00:00:00 2001
+From: Claudiu Zissulescu <claziss@gmail.com>
+Date: Mon, 27 Jan 2020 14:51:03 +0200
+Subject: [PATCH 0342/2034] [ARC] Propagate uncached type attribute to each
+ member of a struct.
+
+Like `packed` type attribute, the ARC's `uncached` type attribute
+needs to be propagated to each member of the struct where it is used,
+triggering the .di flag for any access of the struct members. However,
+any complex CFG manipulation may drop memory pointer type attributes,
+leading to the impossibility to discriminate the direct accesses from
+normal ones. To solve this issue, we will treat the direct memory
+accessed specially via unspecs.
+
+gcc/
+xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
+	Petro Karashchenko  <petro.karashchenko@ring.com>
+
+	* config/arc/arc.c (arc_is_uncached_mem_p): Check struct
+	attributes if needed.
+	(prepare_move_operands): Generate special
+	unspec instruction for direct access.
+	(arc_isuncached_mem_p): Propagate uncached attribute to each
+	structure member.
+	* config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
+	(VUNSPEC_ARC_STDI): Likewise.
+	(ALLI): New mode iterator.
+	(mALLI): New mode attribute.
+	(lddi): New instruction pattern.
+	(stdi): Likewise.
+	(stdidi_split): Split instruction for architectures which are not
+	supporting ll64 option.
+	(lddidi_split): Likewise.
+
+testsuite/
+xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
+	Petro Karashchenko  <petro.karashchenko@ring.com>
+
+	* gcc.target/arc/uncached-1.c: Update test.
+	* gcc.target/arc/uncached-2.c: Likewise.
+	* gcc.target/arc/uncached-3.c: New test.
+	* gcc.target/arc/uncached-4.c: Likewise.
+	* gcc.target/arc/uncached-5.c: Likewise.
+	* gcc.target/arc/uncached-6.c: Likewise.
+	* gcc.target/arc/uncached-7.c: Likewise.
+	* gcc.target/arc/uncached-8.c: Likewise.
+	* gcc.target/arc/arc.exp (ll64): New predicate.
+---
+ gcc/ChangeLog                             |  19 ++++
+ gcc/config/arc/arc.c                      | 118 ++++++++++++++--------
+ gcc/config/arc/arc.md                     |  60 +++++++++++
+ gcc/testsuite/ChangeLog                   |  11 ++
+ gcc/testsuite/gcc.target/arc/arc.exp      |   9 ++
+ gcc/testsuite/gcc.target/arc/uncached-1.c |   2 +-
+ gcc/testsuite/gcc.target/arc/uncached-2.c |   2 +-
+ gcc/testsuite/gcc.target/arc/uncached-3.c |  22 ++++
+ gcc/testsuite/gcc.target/arc/uncached-4.c |  42 ++++++++
+ gcc/testsuite/gcc.target/arc/uncached-5.c |  29 ++++++
+ gcc/testsuite/gcc.target/arc/uncached-6.c |  35 +++++++
+ gcc/testsuite/gcc.target/arc/uncached-7.c |  11 ++
+ gcc/testsuite/gcc.target/arc/uncached-8.c |  33 ++++++
+ 13 files changed, 351 insertions(+), 42 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/arc/uncached-3.c
+ create mode 100644 gcc/testsuite/gcc.target/arc/uncached-4.c
+ create mode 100644 gcc/testsuite/gcc.target/arc/uncached-5.c
+ create mode 100644 gcc/testsuite/gcc.target/arc/uncached-6.c
+ create mode 100644 gcc/testsuite/gcc.target/arc/uncached-7.c
+ create mode 100644 gcc/testsuite/gcc.target/arc/uncached-8.c
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 91dfcd71a4b..2cc61d68cf3 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
+index 22475f2732e..e1a865f02e6 100644
+--- a/gcc/config/arc/arc.c
++++ b/gcc/config/arc/arc.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
+index cf7aa8d83c9..46cb254ed28 100644
+--- a/gcc/config/arc/arc.md
++++ b/gcc/config/arc/arc.md
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 16ddef07516..991934272e0 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/arc/arc.exp b/gcc/testsuite/gcc.target/arc/arc.exp
+index 8d1844edd22..501d4589c53 100644
+--- a/gcc/testsuite/gcc.target/arc/arc.exp
++++ b/gcc/testsuite/gcc.target/arc/arc.exp
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/arc/uncached-1.c b/gcc/testsuite/gcc.target/arc/uncached-1.c
+index 7a6bade81c4..fa5ecb7b7d3 100644
+--- a/gcc/testsuite/gcc.target/arc/uncached-1.c
++++ b/gcc/testsuite/gcc.target/arc/uncached-1.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/arc/uncached-2.c b/gcc/testsuite/gcc.target/arc/uncached-2.c
+index 89eed326e01..9d6bfbbb50e 100644
+--- a/gcc/testsuite/gcc.target/arc/uncached-2.c
++++ b/gcc/testsuite/gcc.target/arc/uncached-2.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/arc/uncached-3.c b/gcc/testsuite/gcc.target/arc/uncached-3.c
+new file mode 100644
+index 00000000000..f2a317b2816
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/arc/uncached-3.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gcc.target/arc/uncached-4.c b/gcc/testsuite/gcc.target/arc/uncached-4.c
+new file mode 100644
+index 00000000000..fecb16648b8
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/arc/uncached-4.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gcc.target/arc/uncached-5.c b/gcc/testsuite/gcc.target/arc/uncached-5.c
+new file mode 100644
+index 00000000000..4fe0464fdde
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/arc/uncached-5.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gcc.target/arc/uncached-6.c b/gcc/testsuite/gcc.target/arc/uncached-6.c
+new file mode 100644
+index 00000000000..581a9eccb3b
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/arc/uncached-6.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gcc.target/arc/uncached-7.c b/gcc/testsuite/gcc.target/arc/uncached-7.c
+new file mode 100644
+index 00000000000..4001b8bd821
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/arc/uncached-7.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gcc.target/arc/uncached-8.c b/gcc/testsuite/gcc.target/arc/uncached-8.c
+new file mode 100644
+index 00000000000..060229b11df
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/arc/uncached-8.c
+@@ -0,0 +1 @@
++
+-- 
+2.26.1
+
+=== 0814-sra-Avoid-totally-scalarizing-overallping-field_decl.patch ===
+From 665c5bad168ab63629b29ed2ce08ed042c088dc2 Mon Sep 17 00:00:00 2001
+From: Martin Jambor <mjambor@suse.cz>
+Date: Wed, 19 Feb 2020 11:08:40 +0100
+Subject: [PATCH 0814/2034] sra: Avoid totally scalarizing overallping
+ field_decls (PR 93667)
+
+[[no_unique_address]] C++ attribute can cause two fields of a
+RECORD_TYPE overlap, which currently confuses the totally scalarizing
+code into creating invalid access tree.  For GCC 10, I'd like to
+simply disable total scalarization of types where this happens.
+
+For GCC 11 I'll write down a TODO item to enable total scalarization
+of cases like this where the problematic fields are basically empty -
+despite having a non-zero size - i.e. when they are just RECORD_TYPEs
+without any data fields.
+
+2020-02-19  Martin Jambor  <mjambor@suse.cz>
+
+	gcc/
+
+	PR tree-optimization/93667
+	* tree-sra.c (scalarizable_type_p): Return false if record fields
+	do not follow wach other.
+
+	gcc/testsuite/
+
+	PR tree-optimization/93667
+	* g++.dg/tree-ssa/pr93667.C: New test.
+---
+ gcc/ChangeLog                           |  6 ++++++
+ gcc/testsuite/ChangeLog                 |  5 +++++
+ gcc/testsuite/g++.dg/tree-ssa/pr93667.C | 11 +++++++++++
+ gcc/tree-sra.c                          | 14 ++++++++++++++
+ 4 files changed, 36 insertions(+)
+ create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr93667.C
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 77c2a9ad810..6b53f9a2f07 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 9b4fe11a6f6..8033fa0a3bb 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr93667.C b/gcc/testsuite/g++.dg/tree-ssa/pr93667.C
+new file mode 100644
+index 00000000000..d875f53d9ec
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/tree-ssa/pr93667.C
+@@ -0,0 +1 @@
++
+diff --git a/gcc/tree-sra.c b/gcc/tree-sra.c
+index 0cfac0a8192..4c7d651e6b9 100644
+--- a/gcc/tree-sra.c
++++ b/gcc/tree-sra.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0413-SRA-Total-scalarization-after-access-propagation-PR9.patch ===
+From 636e80eea24b780f1d5f4c14c58fc00001df8508 Mon Sep 17 00:00:00 2001
+From: Martin Jambor <mjambor@suse.cz>
+Date: Wed, 29 Jan 2020 13:13:13 +0100
+Subject: [PATCH 0413/2034] SRA: Total scalarization after access propagation
+ [PR92706]
+
+2020-01-29  Martin Jambor  <mjambor@suse.cz>
+
+	PR tree-optimization/92706
+	* tree-sra.c (struct access): Adjust comment of
+	grp_total_scalarization.
+	(find_access_in_subtree): Look for single children spanning an entire
+	access.
+	(scalarizable_type_p): Allow register accesses, adjust callers.
+	(completely_scalarize): Remove function.
+	(scalarize_elem): Likewise.
+	(create_total_scalarization_access): Likewise.
+	(sort_and_splice_var_accesses): Do not track total scalarization
+	flags.
+	(analyze_access_subtree): New parameter totally, adjust to new meaning
+	of grp_total_scalarization.
+	(analyze_access_trees): Pass new parameter to analyze_access_subtree.
+	(can_totally_scalarize_forest_p): New function.
+	(create_total_scalarization_access): Likewise.
+	(create_total_access_and_reshape): Likewise.
+	(total_should_skip_creating_access): Likewise.
+	(totally_scalarize_subtree): Likewise.
+	(analyze_all_variable_accesses): Perform total scalarization after
+	subaccess propagation using the new functions above.
+	(initialize_constant_pool_replacements): Output initializers by
+	traversing the access tree.
+
+	testsuite/
+	* gcc.dg/tree-ssa/pr92706-2.c: New test.
+	* gcc.dg/guality/pr59776.c: Xfail tests for s2.g.
+---
+ gcc/ChangeLog                             |  26 +
+ gcc/testsuite/ChangeLog                   |   6 +
+ gcc/testsuite/gcc.dg/guality/pr59776.c    |   4 +-
+ gcc/testsuite/gcc.dg/tree-ssa/pr92706-2.c |  19 +
+ gcc/tree-sra.c                            | 666 ++++++++++++++++------
+ 5 files changed, 537 insertions(+), 184 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr92706-2.c
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 16247a59304..61da54df346 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 05518848829..38758207989 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.dg/guality/pr59776.c b/gcc/testsuite/gcc.dg/guality/pr59776.c
+index 382abb622bb..6c1c8165b70 100644
+--- a/gcc/testsuite/gcc.dg/guality/pr59776.c
++++ b/gcc/testsuite/gcc.dg/guality/pr59776.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr92706-2.c b/gcc/testsuite/gcc.dg/tree-ssa/pr92706-2.c
+new file mode 100644
+index 00000000000..37ab9765db0
+--- /dev/null
++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr92706-2.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/tree-sra.c b/gcc/tree-sra.c
+index 36106fecaf1..2b0849858de 100644
+--- a/gcc/tree-sra.c
++++ b/gcc/tree-sra.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0334-Do-not-generate-a-unique-fnname-for-resolver.patch ===
+From c2bd2b4664be8b73f8fd58a64dec1e93871797cc Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Mon, 27 Jan 2020 10:48:18 +0100
+Subject: [PATCH 0334/2034] Do not generate a unique fnname for resolver.
+
+	PR target/93274
+	* config/i386/i386-features.c (make_resolver_func):
+	Align the code with ppc64 target implementation.
+	Do not generate a unique name for resolver function.
+	PR target/93274
+	* gcc.target/i386/pr81213.c: Adjust to not expect
+	a globally unique name.
+---
+ gcc/ChangeLog                           |  7 +++++++
+ gcc/config/i386/i386-features.c         | 19 ++++---------------
+ gcc/testsuite/ChangeLog                 |  6 ++++++
+ gcc/testsuite/gcc.target/i386/pr81213.c |  4 ++--
+ 4 files changed, 19 insertions(+), 17 deletions(-)
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 45075840824..59806baa757 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/i386/i386-features.c b/gcc/config/i386/i386-features.c
+index e580b26b995..b49e6f8d408 100644
+--- a/gcc/config/i386/i386-features.c
++++ b/gcc/config/i386/i386-features.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 2de060843d9..22a37dd1ab2 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/i386/pr81213.c b/gcc/testsuite/gcc.target/i386/pr81213.c
+index 13e15d5fef0..89c47529861 100644
+--- a/gcc/testsuite/gcc.target/i386/pr81213.c
++++ b/gcc/testsuite/gcc.target/i386/pr81213.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 1850-List-valid-pairs-for-new-and-delete-operators.patch ===
+From d7a65edb629a010f7ef907d457343abcb569fab7 Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Thu, 16 Apr 2020 15:39:22 +0200
+Subject: [PATCH 1850/2034] List valid pairs for new and delete operators.
+
+	PR c++/94314
+	* cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
+	DECL_IS_REPLACEABLE_OPERATOR during cloning.
+	* tree-ssa-dce.c (valid_new_delete_pair_p): New function.
+	(propagate_necessity): Check operator names.
+
+	PR c++/94314
+	* g++.dg/pr94314.C: Do not use dg-additional-options
+	and remove not needed stdio.h include.
+	* g++.dg/pr94314-2.C: Likewise.
+	* g++.dg/pr94314-3.C: Likewise.
+	* g++.dg/pr94314-4.C: New test.
+
+Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
+---
+ gcc/ChangeLog                    |  9 +++
+ gcc/cgraphclones.c               |  2 +
+ gcc/testsuite/ChangeLog          | 10 ++++
+ gcc/testsuite/g++.dg/pr94314-2.C |  5 +-
+ gcc/testsuite/g++.dg/pr94314-3.C |  5 +-
+ gcc/testsuite/g++.dg/pr94314-4.C | 30 ++++++++++
+ gcc/testsuite/g++.dg/pr94314.C   |  5 +-
+ gcc/tree-ssa-dce.c               | 98 ++++++++++++++++++++++++++++----
+ 8 files changed, 142 insertions(+), 22 deletions(-)
+ create mode 100644 gcc/testsuite/g++.dg/pr94314-4.C
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 74dbeeb44c6..9e499ec9c86 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/cgraphclones.c b/gcc/cgraphclones.c
+index c73b8f810f0..8f541a28b6e 100644
+--- a/gcc/cgraphclones.c
++++ b/gcc/cgraphclones.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 756f1d759e6..94d2312022d 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/pr94314-2.C b/gcc/testsuite/g++.dg/pr94314-2.C
+index 36b93ed6d4d..998ce601767 100644
+--- a/gcc/testsuite/g++.dg/pr94314-2.C
++++ b/gcc/testsuite/g++.dg/pr94314-2.C
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/pr94314-3.C b/gcc/testsuite/g++.dg/pr94314-3.C
+index 575ba9d8ad8..846a5d6a3d8 100644
+--- a/gcc/testsuite/g++.dg/pr94314-3.C
++++ b/gcc/testsuite/g++.dg/pr94314-3.C
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/pr94314-4.C b/gcc/testsuite/g++.dg/pr94314-4.C
+new file mode 100644
+index 00000000000..d097f29d4ad
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/pr94314-4.C
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/g++.dg/pr94314.C b/gcc/testsuite/g++.dg/pr94314.C
+index 86e651d10ba..4e5ae122e9f 100644
+--- a/gcc/testsuite/g++.dg/pr94314.C
++++ b/gcc/testsuite/g++.dg/pr94314.C
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/tree-ssa-dce.c b/gcc/tree-ssa-dce.c
+index fd5f24c746c..757cfad5b5e 100644
+--- a/gcc/tree-ssa-dce.c
++++ b/gcc/tree-ssa-dce.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0085-Daily-bump.patch ===
+From 03647d2e26176bb874460b67deab0c30aa715d59 Mon Sep 17 00:00:00 2001
+From: GCC Administrator <gccadmin@gcc.gnu.org>
+Date: Thu, 16 Jan 2020 00:16:32 +0000
+Subject: [PATCH 0085/2034] Daily bump.
+
+---
+ gcc/DATESTAMP | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
+index ba948c594d4..62611957f86 100644
+--- a/gcc/DATESTAMP
++++ b/gcc/DATESTAMP
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0040-PR90916-ICE-in-retrieve-specialization.patch ===
+From a5a3c2dcf73aa245b0eb6f6cf56c4d03ab6056da Mon Sep 17 00:00:00 2001
+From: Nathan Sidwell <nathans@fb.com>
+Date: Tue, 14 Jan 2020 11:12:40 -0800
+Subject: [PATCH 0040/2034] [PR90916] ICE in retrieve specialization
+
+https://gcc.gnu.org/ml/gcc-patches/2020-01/msg00809.html
+	PR c++/90916
+	* pt.c (retrieve_specialization): Get the TI from the decl or the
+	classtype as appropriate.
+---
+ gcc/cp/ChangeLog                        |  6 ++++++
+ gcc/cp/pt.c                             | 15 ++++++++++-----
+ gcc/testsuite/g++.dg/template/pr90916.C |  8 ++++++++
+ 3 files changed, 24 insertions(+), 5 deletions(-)
+ create mode 100644 gcc/testsuite/g++.dg/template/pr90916.C
+
+diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
+index 004ce0fdcdf..3cc7c48b490 100644
+--- a/gcc/cp/ChangeLog
++++ b/gcc/cp/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
+index fa82ecad233..4fdc74f9ca8 100644
+--- a/gcc/cp/pt.c
++++ b/gcc/cp/pt.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/template/pr90916.C b/gcc/testsuite/g++.dg/template/pr90916.C
+new file mode 100644
+index 00000000000..bdb7e7b58ef
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/template/pr90916.C
+@@ -0,0 +1 @@
++
+-- 
+2.26.1
+
+=== 2004-amdgcn-Check-HSA-return-codes-PR94629.patch ===
+From 966de09be91c639d66d252c9ae6ab8da5ebfca18 Mon Sep 17 00:00:00 2001
+From: Andrew Stubbs <ams@codesourcery.com>
+Date: Mon, 20 Apr 2020 15:25:31 +0100
+Subject: [PATCH 2004/2034] amdgcn: Check HSA return codes [PR94629]
+
+Ensure that the returned status values are not ignored.  The old code was
+not broken, but this is both safer and satisfies static analysis.
+
+2020-04-23  Andrew Stubbs  <ams@codesourcery.com>
+
+	PR other/94629
+
+	libgomp/
+	* plugin/plugin-gcn.c (init_hsa_context): Check return value from
+	hsa_iterate_agents.
+	(GOMP_OFFLOAD_init_device): Check return values from both calls to
+	hsa_agent_iterate_regions.
+---
+ libgomp/ChangeLog           | 9 +++++++++
+ libgomp/plugin/plugin-gcn.c | 8 ++++++++
+ 2 files changed, 17 insertions(+)
+
+diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
+index c524abbbfb6..ee1764d4ae3 100644
+--- a/libgomp/ChangeLog
++++ b/libgomp/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/libgomp/plugin/plugin-gcn.c b/libgomp/plugin/plugin-gcn.c
+index dc72c90962c..4c6a4c03b6e 100644
+--- a/libgomp/plugin/plugin-gcn.c
++++ b/libgomp/plugin/plugin-gcn.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0198-Change-recursive-prepare_block_for_update-to-use-a-w.patch ===
+From 6fc2f9337311c11dabcc464c808cbef205f17a52 Mon Sep 17 00:00:00 2001
+From: Andrew Pinski <apinski@marvell.com>
+Date: Tue, 21 Jan 2020 08:34:42 +0000
+Subject: [PATCH 0198/2034] Change recursive prepare_block_for_update to use a
+ worklist
+
+Reported as PR 93321, prepare_block_for_update with some huge
+recusive inlining can go past the stack limit. Transforming this
+recursive into worklist improves the stack usage here and we no
+longer seg fault for the testcase.  Note the order we walk the siblings
+change.
+
+ChangeLog:
+	PR tree-opt/93321
+	* tree-into-ssa.c (prepare_block_for_update_1): Split out from ...
+	(prepare_block_for_update): This.  Use a worklist instead of recursing.
+---
+ gcc/ChangeLog       |  8 ++++++
+ gcc/tree-into-ssa.c | 59 ++++++++++++++++++++++++++++++++++++---------
+ 2 files changed, 55 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 8c17e5992d2..262f0d6506f 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/tree-into-ssa.c b/gcc/tree-into-ssa.c
+index c27bf2ce121..6528acac31a 100644
+--- a/gcc/tree-into-ssa.c
++++ b/gcc/tree-into-ssa.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0184-PR-80005-Fix-__has_include.patch ===
+From ad1a3914ae8d67c94b0d2428e3f9672e7db491a1 Mon Sep 17 00:00:00 2001
+From: Nathan Sidwell <nathan@acm.org>
+Date: Mon, 20 Jan 2020 05:39:59 -0800
+Subject: [PATCH 0184/2034] [PR 80005]  Fix __has_include
+
+__has_include is funky in that it is macro-like from the POV of #ifdef and
+friends, but lexes its parenthesize argument #include-like.  We were
+failing the second part of that, because we used a forwarding macro to an
+internal name, and hence always lexed the argument in macro-parameter
+context.  We componded that by not setting the right flag when lexing, so
+it didn't even know.  Mostly users got lucky.
+
+This reimplements the handline.
+1) Remove the forwarding, but declare object-like macros that
+expand to themselves.  This satisfies the #ifdef requirement
+
+2) Correctly set angled_brackets when lexing the parameter.  This tells
+the lexer (a) <...> is a header name and (b) "..." is too (not a string).
+
+3) Remove the in__has_include lexer state, just tell find_file that that's
+what's happenning, so it doesn't emit an error.
+
+We lose the (undocumented) ability to #undef __has_include.  That may well
+have been an accident of implementation.  There are no tests for it.
+
+We gain __has_include behaviour for all users of the preprocessors -- not
+just the C-family ones that defined a forwarding macro.
+
+	libcpp/
+	PR preprocessor/80005
+	* include/cpplib.h (BT_HAS_ATTRIBUTE): Fix comment.
+	* internal.h (struct lexer_state): Delete in__has_include field.
+	(struct spec_nodes): Rename n__has_include{,_next}__ fields.
+	(_cpp_defined_macro_p): New.
+	(_cpp_find_file): Add has_include parm.
+	* directives.c (lex_macro_node): Combine defined,
+	__has_inline{,_next} checking.
+	(do_ifdef, do_ifndef): Use _cpp_defined_macro_p.
+	(_cpp_init_directives): Refactor.
+	* expr.c (parse_defined): Use _cpp_defined_macro_p.
+	(eval_token): Adjust parse_has_include calls.
+	(parse_has_include): Add OP parameter.  Reimplement.
+	* files.c (_cpp_find_file): Add HAS_INCLUDE parm.  Use it to
+	inhibit error message.
+	(_cpp_stack_include): Adjust _cpp_find_file call.
+	(_cpp_fake_include, _cpp_compare_file_date): Likewise.
+	(open_file_failed): Remove in__has_include check.
+	(_cpp_has_header): Adjust _cpp_find_file call.
+	* identifiers.c (_cpp_init_hashtable): Don't init
+	__has_include{,_next} here ...
+	* init.c (cpp_init_builtins): ... init them here.  Define as
+	macros.
+	(cpp_read_main_file): Adjust _cpp_find_file call.
+	* pch.c (cpp_read_state): Adjust __has_include{,_next} access.
+	* traditional.c (_cpp_scan_out_locgical_line): Likewise.
+
+	gcc/c-family/
+	PR preprocessor/80005
+	* c-cppbuiltins.c (c_cpp_builtins): Don't define __has_include{,_next}.
+
+	gcc/testsuite/
+	PR preprocessor/80005
+	* g++.dg/cpp1y/feat-cxx14.C: Adjust.
+	* g++.dg/cpp1z/feat-cxx17.C: Adjust.
+	* g++.dg/cpp2a/feat-cxx2a.C: Adjust.
+	* g++.dg/cpp/pr80005.C: New.
+---
+ gcc/c-family/ChangeLog                  |  5 ++++
+ gcc/c-family/c-cppbuiltin.c             |  6 -----
+ gcc/testsuite/ChangeLog                 |  8 +++++++
+ gcc/testsuite/g++.dg/cpp/pr80005.C      | 24 +++++++++++++++++++
+ gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C | 10 ++------
+ gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C | 10 ++------
+ gcc/testsuite/g++.dg/cpp2a/feat-cxx2a.C | 10 ++------
+ libcpp/ChangeLog                        | 29 +++++++++++++++++++++-
+ libcpp/directives.c                     | 29 ++++++++--------------
+ libcpp/expr.c                           | 32 ++++++++++++-------------
+ libcpp/files.c                          | 27 +++++++++++----------
+ libcpp/identifiers.c                    |  3 +--
+ libcpp/include/cpplib.h                 |  2 +-
+ libcpp/init.c                           | 14 ++++++++++-
+ libcpp/internal.h                       | 20 +++++++++++-----
+ libcpp/pch.c                            |  4 ++--
+ libcpp/traditional.c                    |  8 +++----
+ 17 files changed, 146 insertions(+), 95 deletions(-)
+ create mode 100644 gcc/testsuite/g++.dg/cpp/pr80005.C
+
+diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
+index 09ba2c8b40f..fdddb98a74d 100644
+--- a/gcc/c-family/ChangeLog
++++ b/gcc/c-family/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/c-family/c-cppbuiltin.c b/gcc/c-family/c-cppbuiltin.c
+index a6308921dc9..70a12055e27 100644
+--- a/gcc/c-family/c-cppbuiltin.c
++++ b/gcc/c-family/c-cppbuiltin.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index a526e32ac89..67d5f2e9e28 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/cpp/pr80005.C b/gcc/testsuite/g++.dg/cpp/pr80005.C
+new file mode 100644
+index 00000000000..cc752616782
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/cpp/pr80005.C
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C b/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C
+index a2a93f437b3..a78b6a36f36 100644
+--- a/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C
++++ b/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C b/gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C
+index 55e56a06fe8..e6f456b2415 100644
+--- a/gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C
++++ b/gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/cpp2a/feat-cxx2a.C b/gcc/testsuite/g++.dg/cpp2a/feat-cxx2a.C
+index dd15cd6af3c..82fd602f9f1 100644
+--- a/gcc/testsuite/g++.dg/cpp2a/feat-cxx2a.C
++++ b/gcc/testsuite/g++.dg/cpp2a/feat-cxx2a.C
+@@ -1 +1,2 @@
+
++
+diff --git a/libcpp/ChangeLog b/libcpp/ChangeLog
+index 3249b93fe88..27a841bbdce 100644
+--- a/libcpp/ChangeLog
++++ b/libcpp/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/libcpp/directives.c b/libcpp/directives.c
+index 983206a5838..10735c8c668 100644
+--- a/libcpp/directives.c
++++ b/libcpp/directives.c
+@@ -1 +1,2 @@
+
++
+diff --git a/libcpp/expr.c b/libcpp/expr.c
+index 317faf50208..df21a4b9fb9 100644
+--- a/libcpp/expr.c
++++ b/libcpp/expr.c
+@@ -1 +1,2 @@
+
++
+diff --git a/libcpp/files.c b/libcpp/files.c
+index 7abae7ae6ec..260e787c329 100644
+--- a/libcpp/files.c
++++ b/libcpp/files.c
+@@ -1 +1,2 @@
+
++
+diff --git a/libcpp/identifiers.c b/libcpp/identifiers.c
+index 562d8fee3b5..9627e1bf4b0 100644
+--- a/libcpp/identifiers.c
++++ b/libcpp/identifiers.c
+@@ -1 +1,2 @@
+
++
+diff --git a/libcpp/include/cpplib.h b/libcpp/include/cpplib.h
+index 1c26c365347..56cbbd82750 100644
+--- a/libcpp/include/cpplib.h
++++ b/libcpp/include/cpplib.h
+@@ -1 +1,2 @@
+
++
+diff --git a/libcpp/init.c b/libcpp/init.c
+index 2b4923e1451..e798140ef8b 100644
+--- a/libcpp/init.c
++++ b/libcpp/init.c
+@@ -1 +1,2 @@
+
++
+diff --git a/libcpp/internal.h b/libcpp/internal.h
+index 3623baf8191..5453c3bff85 100644
+--- a/libcpp/internal.h
++++ b/libcpp/internal.h
+@@ -1 +1,2 @@
+
++
+diff --git a/libcpp/pch.c b/libcpp/pch.c
+index 607f805bebe..e631050936b 100644
+--- a/libcpp/pch.c
++++ b/libcpp/pch.c
+@@ -1 +1,2 @@
+
++
+diff --git a/libcpp/traditional.c b/libcpp/traditional.c
+index 21c63b47dd5..ff06d31a897 100644
+--- a/libcpp/traditional.c
++++ b/libcpp/traditional.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== long-lines.patch ===
+From eb7c7c524556df5364f03adc20f6a9db20858484 Mon Sep 17 00:00:00 2001
+From: Jakub Jelinek <jakub@redhat.com>
+Date: Mon, 13 Jan 2020 14:14:57 +0100
+Subject: [PATCH 0004/2034] tree-opt: Fix bootstrap failure in
+ tree-ssa-forwprop.c some more PR90838
+
+2020-01-13  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/90838
+	* tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
+	SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro and and SCALAR_INT_TYPE_MODE directly in and so
+	argument rather than to initialize temporary for targets that
+	don't use the mode argument at all.  Initialize ctzval to avoid
+	warning at -O0.
+---
+ gcc/ChangeLog           | 9 +++++++++
+ gcc/tree-ssa-forwprop.c | 6 +++---
+ 2 files changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index a195863212e..f7df07343d1 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c
+index aac31d02b6c..56c470f6ecf 100644
+--- a/gcc/tree-ssa-forwprop.c
++++ b/gcc/tree-ssa-forwprop.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0735-PR-87488-Add-with-diagnostics-urls-configuration-opt.patch ===
+From 458c8d6459c4005fc9886b6e25d168a6535ac415 Mon Sep 17 00:00:00 2001
+From: Bernd Edlinger <bernd.edlinger@hotmail.de>
+Date: Wed, 29 Jan 2020 15:31:10 +0100
+Subject: [PATCH 0735/2034] PR 87488: Add --with-diagnostics-urls configuration
+ option
+
+2020-02-15  David Malcolm  <dmalcolm@redhat.com>
+	    Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	PR 87488
+	PR other/93168
+	* config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
+	* configure.ac (--with-diagnostics-urls): New configuration
+	option, based on --with-diagnostics-color.
+	(DIAGNOSTICS_URLS_DEFAULT): New define.
+	* config.h: Regenerate.
+	* configure: Regenerate.
+	* diagnostic.c (diagnostic_urls_init): Handle -1 for
+	DIAGNOSTICS_URLS_DEFAULT from configure-time
+	--with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
+	and TERM_URLS environment variable.
+	* diagnostic-url.h (diagnostic_url_format): New enum type.
+	(diagnostic_urls_enabled_p): rename to...
+	(determine_url_format): ... this, and change return type.
+	* diagnostic-color.c (parse_env_vars_for_urls): New helper function.
+	(auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
+	the linux console, and mingw.
+	(diagnostic_urls_enabled_p): rename to...
+	(determine_url_format): ... this, and adjust.
+	* pretty-print.h (pretty_printer::show_urls): rename to...
+	(pretty_printer::url_format): ... this, and change to enum.
+	* pretty-print.c (pretty_printer::pretty_printer,
+	pp_begin_url, pp_end_url, test_urls): Adjust.
+	* doc/install.texi (--with-diagnostics-urls): Document the new
+	configuration option.
+	(--with-diagnostics-color): Document the existing interaction
+	with GCC_COLORS better.
+	* doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
+	vindex reference.  Update description of defaults based on the above.
+	(-fdiagnostics-color): Update description of how -fdiagnostics-color
+	interacts with GCC_COLORS.
+---
+ gcc/ChangeLog          |  36 +++++++++++++++
+ gcc/config.in          |   6 +++
+ gcc/configure          |  41 ++++++++++++++++-
+ gcc/configure.ac       |  28 ++++++++++++
+ gcc/diagnostic-color.c | 101 ++++++++++++++++++++++++++++++++++++++---
+ gcc/diagnostic-url.h   |  18 +++++++-
+ gcc/diagnostic.c       |  21 +++++++--
+ gcc/doc/install.texi   |  15 ++++--
+ gcc/doc/invoke.texi    |  39 ++++++++++++++--
+ gcc/pretty-print.c     |  44 +++++++++++++++---
+ gcc/pretty-print.h     |   5 +-
+ 11 files changed, 328 insertions(+), 26 deletions(-)
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index e6eb6ab4c21..22f990a3088 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config.in b/gcc/config.in
+index 48292861842..01fb18dbbb5 100644
+--- a/gcc/config.in
++++ b/gcc/config.in
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/configure b/gcc/configure
+index 5fa565a40a4..f55cdb8c77f 100755
+--- a/gcc/configure
++++ b/gcc/configure
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/configure.ac b/gcc/configure.ac
+index 671b9a67d81..0e6e475950d 100644
+--- a/gcc/configure.ac
++++ b/gcc/configure.ac
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/diagnostic-color.c b/gcc/diagnostic-color.c
+index d5547952921..b1baded2c9e 100644
+--- a/gcc/diagnostic-color.c
++++ b/gcc/diagnostic-color.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/diagnostic-url.h b/gcc/diagnostic-url.h
+index 6be056941f1..d28460b928b 100644
+--- a/gcc/diagnostic-url.h
++++ b/gcc/diagnostic-url.h
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/diagnostic.c b/gcc/diagnostic.c
+index 3386f070256..e4a08f76def 100644
+--- a/gcc/diagnostic.c
++++ b/gcc/diagnostic.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
+index 6ffafacff50..8ddebbb6267 100644
+--- a/gcc/doc/install.texi
++++ b/gcc/doc/install.texi
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index bd9ecebf103..597151670be 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/pretty-print.c b/gcc/pretty-print.c
+index 817c1059e08..dde138b0533 100644
+--- a/gcc/pretty-print.c
++++ b/gcc/pretty-print.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/pretty-print.h b/gcc/pretty-print.h
+index 001468c966e..22892f12ab7 100644
+--- a/gcc/pretty-print.h
++++ b/gcc/pretty-print.h
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0031-Fix-typo-and-avoid-possible-memory-leak-in-average_n.patch ===
+From b38e86ddb7a9b6d7e87d7cc0b23983d027fcbd96 Mon Sep 17 00:00:00 2001
+From: Kewen Lin <linkw@linux.ibm.com>
+Date: Tue, 14 Jan 2020 02:34:10 -0600
+Subject: [PATCH 0031/2034] Fix typo and avoid possible memory leak in
+ average_num_loop_insns
+
+Function average_num_loop_insns forgets to free loop body in early
+return.  Besides, overflow comparison checks 1000000 (e6) but the
+return value is 100000 (e5), fix this typo.
+
+gcc/ChangeLog
+
+2020-01-14  Kewen Lin  <linkw@gcc.gnu.org>
+
+    * cfgloopanal.c (average_num_loop_insns): Free bbs when early
+    return, fix typo on return value.
+---
+ gcc/ChangeLog     | 5 +++++
+ gcc/cfgloopanal.c | 5 ++++-
+ 2 files changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 07e5bebe909..f3301b16464 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c
+index 392b1c337c4..0b33e8272a7 100644
+--- a/gcc/cfgloopanal.c
++++ b/gcc/cfgloopanal.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0735-PR-87488-Add-with-diagnostics-urls-configuration-opt.patch ===
+From 458c8d6459c4005fc9886b6e25d168a6535ac415 Mon Sep 17 00:00:00 2001
+From: Bernd Edlinger <bernd.edlinger@hotmail.de>
+Date: Wed, 29 Jan 2020 15:31:10 +0100
+Subject: [PATCH 0735/2034] PR 87488: Add --with-diagnostics-urls configuration
+ option
+
+2020-02-15  David Malcolm  <dmalcolm@redhat.com>
+	    Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	PR 87488
+	PR other/93168
+	* config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
+	* configure.ac (--with-diagnostics-urls): New configuration
+	option, based on --with-diagnostics-color.
+	(DIAGNOSTICS_URLS_DEFAULT): New define.
+	* config.h: Regenerate.
+	* configure: Regenerate.
+	* diagnostic.c (diagnostic_urls_init): Handle -1 for
+	DIAGNOSTICS_URLS_DEFAULT from configure-time
+	--with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
+	and TERM_URLS environment variable.
+	* diagnostic-url.h (diagnostic_url_format): New enum type.
+	(diagnostic_urls_enabled_p): rename to...
+	(determine_url_format): ... this, and change return type.
+	* diagnostic-color.c (parse_env_vars_for_urls): New helper function.
+	(auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
+	the linux console, and mingw.
+	(diagnostic_urls_enabled_p): rename to...
+	(determine_url_format): ... this, and adjust.
+	* pretty-print.h (pretty_printer::show_urls): rename to...
+	(pretty_printer::url_format): ... this, and change to enum.
+	* pretty-print.c (pretty_printer::pretty_printer,
+	pp_begin_url, pp_end_url, test_urls): Adjust.
+	* doc/install.texi (--with-diagnostics-urls): Document the new
+	configuration option.
+	(--with-diagnostics-color): Document the existing interaction
+	with GCC_COLORS better.
+	* doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
+	vindex reference.  Update description of defaults based on the above.
+	(-fdiagnostics-color): Update description of how -fdiagnostics-color
+	interacts with GCC_COLORS.
+---
+ gcc/ChangeLog          |  36 +++++++++++++++
+ gcc/config.in          |   6 +++
+ gcc/configure          |  41 ++++++++++++++++-
+ gcc/configure.ac       |  28 ++++++++++++
+ gcc/diagnostic-color.c | 101 ++++++++++++++++++++++++++++++++++++++---
+ gcc/diagnostic-url.h   |  18 +++++++-
+ gcc/diagnostic.c       |  21 +++++++--
+ gcc/doc/install.texi   |  15 ++++--
+ gcc/doc/invoke.texi    |  39 ++++++++++++++--
+ gcc/pretty-print.c     |  44 +++++++++++++++---
+ gcc/pretty-print.h     |   5 +-
+ 11 files changed, 328 insertions(+), 26 deletions(-)
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index e6eb6ab4c21..22f990a3088 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config.in b/gcc/config.in
+index 48292861842..01fb18dbbb5 100644
+--- a/gcc/config.in
++++ b/gcc/config.in
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/configure b/gcc/configure
+index 5fa565a40a4..f55cdb8c77f 100755
+--- a/gcc/configure
++++ b/gcc/configure
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/configure.ac b/gcc/configure.ac
+index 671b9a67d81..0e6e475950d 100644
+--- a/gcc/configure.ac
++++ b/gcc/configure.ac
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/diagnostic-color.c b/gcc/diagnostic-color.c
+index d5547952921..b1baded2c9e 100644
+--- a/gcc/diagnostic-color.c
++++ b/gcc/diagnostic-color.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/diagnostic-url.h b/gcc/diagnostic-url.h
+index 6be056941f1..d28460b928b 100644
+--- a/gcc/diagnostic-url.h
++++ b/gcc/diagnostic-url.h
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/diagnostic.c b/gcc/diagnostic.c
+index 3386f070256..e4a08f76def 100644
+--- a/gcc/diagnostic.c
++++ b/gcc/diagnostic.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
+index 6ffafacff50..8ddebbb6267 100644
+--- a/gcc/doc/install.texi
++++ b/gcc/doc/install.texi
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index bd9ecebf103..597151670be 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/pretty-print.c b/gcc/pretty-print.c
+index 817c1059e08..dde138b0533 100644
+--- a/gcc/pretty-print.c
++++ b/gcc/pretty-print.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/pretty-print.h b/gcc/pretty-print.h
+index 001468c966e..22892f12ab7 100644
+--- a/gcc/pretty-print.h
++++ b/gcc/pretty-print.h
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== co-authored-by.patch ===
+From d7a65edb629a010f7ef907d457343abcb569fab7 Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Thu, 16 Apr 2020 15:39:22 +0200
+Subject: [PATCH 1850/2034] List valid pairs for new and delete operators.
+
+	PR c++/94314
+	* cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
+	DECL_IS_REPLACEABLE_OPERATOR during cloning.
+	* tree-ssa-dce.c (valid_new_delete_pair_p): New function.
+	(propagate_necessity): Check operator names.
+
+	PR c++/94314
+	* g++.dg/pr94314.C: Do not use dg-additional-options
+	and remove not needed stdio.h include.
+	* g++.dg/pr94314-2.C: Likewise.
+	* g++.dg/pr94314-3.C: Likewise.
+	* g++.dg/pr94314-4.C: New test.
+
+co-authored-By: Jakub Jelinek <jakub@redhat.com>
+Co-Authored-by: John Miller <jm@example.com>
+co-authored-by: John Miller2 <jm2@example.com>
+---
+ gcc/ChangeLog                    |  9 +++
+ gcc/cgraphclones.c               |  2 +
+ gcc/testsuite/ChangeLog          | 10 ++++
+ gcc/testsuite/g++.dg/pr94314-2.C |  5 +-
+ gcc/testsuite/g++.dg/pr94314-3.C |  5 +-
+ gcc/testsuite/g++.dg/pr94314-4.C | 30 ++++++++++
+ gcc/testsuite/g++.dg/pr94314.C   |  5 +-
+ gcc/tree-ssa-dce.c               | 98 ++++++++++++++++++++++++++++----
+ 8 files changed, 142 insertions(+), 22 deletions(-)
+ create mode 100644 gcc/testsuite/g++.dg/pr94314-4.C
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 74dbeeb44c6..9e499ec9c86 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/cgraphclones.c b/gcc/cgraphclones.c
+index c73b8f810f0..8f541a28b6e 100644
+--- a/gcc/cgraphclones.c
++++ b/gcc/cgraphclones.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 756f1d759e6..94d2312022d 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/pr94314-2.C b/gcc/testsuite/g++.dg/pr94314-2.C
+index 36b93ed6d4d..998ce601767 100644
+--- a/gcc/testsuite/g++.dg/pr94314-2.C
++++ b/gcc/testsuite/g++.dg/pr94314-2.C
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/pr94314-3.C b/gcc/testsuite/g++.dg/pr94314-3.C
+index 575ba9d8ad8..846a5d6a3d8 100644
+--- a/gcc/testsuite/g++.dg/pr94314-3.C
++++ b/gcc/testsuite/g++.dg/pr94314-3.C
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/pr94314-4.C b/gcc/testsuite/g++.dg/pr94314-4.C
+new file mode 100644
+index 00000000000..d097f29d4ad
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/pr94314-4.C
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/g++.dg/pr94314.C b/gcc/testsuite/g++.dg/pr94314.C
+index 86e651d10ba..4e5ae122e9f 100644
+--- a/gcc/testsuite/g++.dg/pr94314.C
++++ b/gcc/testsuite/g++.dg/pr94314.C
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/tree-ssa-dce.c b/gcc/tree-ssa-dce.c
+index fd5f24c746c..757cfad5b5e 100644
+--- a/gcc/tree-ssa-dce.c
++++ b/gcc/tree-ssa-dce.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 1699-combine-Fix-split_i2i3-ICE-PR94291.patch ===
+From c23c899aedf11069e992eed7358802b262d62f98 Mon Sep 17 00:00:00 2001
+From: Jakub Jelinek <jakub@redhat.com>
+Date: Tue, 7 Apr 2020 21:30:12 +0200
+Subject: [PATCH 1699/2034] combine: Fix split_i2i3 ICE [PR94291]
+
+The following testcase ICEs on armv7hl-linux-gnueabi.
+try_combine is called on:
+(gdb) p debug_rtx (i3)
+(insn 20 12 22 2 (set (mem/c:SI (plus:SI (reg/f:SI 102 sfp)
+                (const_int -4 [0xfffffffffffffffc])) [1 x+0 S4 A32])
+        (reg:SI 125)) "pr94291.c":7:8 241 {*arm_movsi_insn}
+     (expr_list:REG_DEAD (reg:SI 125)
+        (nil)))
+(gdb) p debug_rtx (i2)
+(insn 12 7 20 2 (parallel [
+            (set (reg:CC 100 cc)
+                (compare:CC (reg:SI 121 [ <retval> ])
+                    (const_int 0 [0])))
+            (set (reg:SI 125)
+                (reg:SI 121 [ <retval> ]))
+        ]) "pr94291.c":7:8 248 {*movsi_compare0}
+     (expr_list:REG_UNUSED (reg:CC 100 cc)
+        (nil)))
+and tries to recognize cc = r121 cmp 0; [sfp-4] = r121 parallel,
+but that isn't recognized, so it splits it into two: split_i2i3
+[sfp-4] = r121 followed by cc = r121 cmp 0 which is recognized, but
+ICEs because the code below insist that the SET_DEST of newi2pat
+(or first set in PARALLEL thereof) must be a REG or SUBREG of REG,
+but it is a MEM in this case.  I don't see any condition that would
+guarantee that, perhaps for the swap_i2i3 case it was somehow guaranteed.
+
+As the code just wants to update LOG_LINKS and LOG_LINKS are only for
+registers, not for MEM or anything else, the patch just doesn't update those
+if it isn't a REG or SUBREG of REG.
+
+2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/94291
+	PR rtl-optimization/84169
+	* combine.c (try_combine): For split_i2i3, don't assume SET_DEST
+	must be a REG or SUBREG of REG; if it is not one of these, don't
+	update LOG_LINKs.
+
+	* gcc.dg/pr94291.c: New test.
+---
+ gcc/ChangeLog                  |  8 +++++++
+ gcc/combine.c                  | 42 +++++++++++++++++++---------------
+ gcc/testsuite/ChangeLog        |  6 +++++
+ gcc/testsuite/gcc.dg/pr94291.c | 14 ++++++++++++
+ 4 files changed, 51 insertions(+), 19 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.dg/pr94291.c
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index a1ab9fb4ef3..12803e90b0a 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/combine.c b/gcc/combine.c
+index 58366a6d331..cff76cd3303 100644
+--- a/gcc/combine.c
++++ b/gcc/combine.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 71b5a14bcbe..3cbf891d58d 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.dg/pr94291.c b/gcc/testsuite/gcc.dg/pr94291.c
+new file mode 100644
+index 00000000000..7daa2b01166
+--- /dev/null
++++ b/gcc/testsuite/gcc.dg/pr94291.c
+@@ -0,0 +1 @@
++
+-- 
+2.26.1
+
+=== 0001-Add-patch_area_size-and-patch_area_entry-to-crtl.patch ===
+From 6607bdd99994c834f92fce924abdaea3405f62dc Mon Sep 17 00:00:00 2001
+From: "H.J. Lu" <hjl.tools@gmail.com>
+Date: Fri, 1 May 2020 21:03:10 -0700
+Subject: [PATCH] Add patch_area_size and patch_area_entry to crtl
+
+Currently patchable area is at the wrong place.  It is placed immediately
+after function label and before .cfi_startproc.  A backend should be able
+to add a pseudo patchable area instruction durectly into RTL.  This patch
+adds patch_area_size and patch_area_entry to crtl so that the patchable
+area info is available in RTL passes.
+
+It also limits patch_area_size and patch_area_entry to 65535, which is
+a reasonable maximum size for patchable area.
+
+gcc/
+
+	PR target/93492
+	* cfgexpand.c (pass_expand::execute): Set crtl->patch_area_size
+	and crtl->patch_area_entry.
+	* emit-rtl.h (rtl_data): Add patch_area_size and patch_area_entry.
+	* opts.c (common_handle_option): Limit
+	function_entry_patch_area_size and function_entry_patch_area_start
+	to USHRT_MAX.  Fix a typo in error message.
+	* varasm.c (assemble_start_function): Use crtl->patch_area_size
+	and crtl->patch_area_entry.
+	* doc/invoke.texi: Document the maximum value for
+	-fpatchable-function-entry.
+
+gcc/c-family/
+
+	PR target/12345
+	* c-attribs.c (handle_patchable_function_entry_attribute): Limit
+	value to USHRT_MAX (65535).
+
+---
+ gcc/ChangeLog                                 | 14 ++++++++
+ gcc/c-family/ChangeLog                        |  6 ++++
+ gcc/c-family/c-attribs.c                      |  9 +++++
+ gcc/cfgexpand.c                               | 33 +++++++++++++++++++
+ gcc/doc/invoke.texi                           |  1 +
+ gcc/emit-rtl.h                                |  6 ++++
+ gcc/opts.c                                    |  4 ++-
+ gcc/testsuite/ChangeLog                       |  7 ++++
+ .../patchable_function_entry-error-1.c        |  9 +++++
+ .../patchable_function_entry-error-2.c        |  9 +++++
+ .../patchable_function_entry-error-3.c        | 17 ++++++++++
+ gcc/varasm.c                                  | 30 ++---------------
+ 12 files changed, 116 insertions(+), 29 deletions(-)
+ create mode 100644 gcc/testsuite/c-c++-common/patchable_function_entry-error-1.c
+ create mode 100644 gcc/testsuite/c-c++-common/patchable_function_entry-error-2.c
+ create mode 100644 gcc/testsuite/c-c++-common/patchable_function_entry-error-3.c
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index e85a8e8813e..fb776ba5a0e 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
+index c429b49e68c..69ea1fdc4f3 100644
+--- a/gcc/c-family/ChangeLog
++++ b/gcc/c-family/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/c-family/c-attribs.c b/gcc/c-family/c-attribs.c
+index ac936d5bbbb..a101312c581 100644
+--- a/gcc/c-family/c-attribs.c
++++ b/gcc/c-family/c-attribs.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
+index a7ec77d5c85..86efa22bf60 100644
+--- a/gcc/cfgexpand.c
++++ b/gcc/cfgexpand.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index 527d362533a..767d1f07801 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/emit-rtl.h b/gcc/emit-rtl.h
+index a878efe3cf7..3d6565c8a30 100644
+--- a/gcc/emit-rtl.h
++++ b/gcc/emit-rtl.h
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/opts.c b/gcc/opts.c
+index c212a1a57dc..3dccef39701 100644
+--- a/gcc/opts.c
++++ b/gcc/opts.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 176aa117904..185f9ea725e 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/c-c++-common/patchable_function_entry-error-1.c b/gcc/testsuite/c-c++-common/patchable_function_entry-error-1.c
+new file mode 100644
+index 00000000000..f60bf46cfe3
+--- /dev/null
++++ b/gcc/testsuite/c-c++-common/patchable_function_entry-error-1.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/c-c++-common/patchable_function_entry-error-2.c b/gcc/testsuite/c-c++-common/patchable_function_entry-error-2.c
+new file mode 100644
+index 00000000000..90f88c78be7
+--- /dev/null
++++ b/gcc/testsuite/c-c++-common/patchable_function_entry-error-2.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/c-c++-common/patchable_function_entry-error-3.c b/gcc/testsuite/c-c++-common/patchable_function_entry-error-3.c
+new file mode 100644
+index 00000000000..4490e5c15ca
+--- /dev/null
++++ b/gcc/testsuite/c-c++-common/patchable_function_entry-error-3.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/varasm.c b/gcc/varasm.c
+index 271a67abf56..f062e48071f 100644
+--- a/gcc/varasm.c
++++ b/gcc/varasm.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.2
+
+=== 1957-c-generic-lambda-forwarding-function-PR94546.patch ===
+From aedd04caa945260ea77fd22f29b77292f7dba72e Mon Sep 17 00:00:00 2001
+From: Jason Merrill <jason@redhat.com>
+Date: Wed, 22 Apr 2020 02:27:54 -0400
+Subject: [PATCH 1957/2034] c++: generic lambda forwarding function [PR94546]
+
+While instantiating test(Plot) we partially instantiate the generic lambda.
+We look at forward<T>(rest)... and see that it's just replacing parameter
+packs with new parameter packs and tries to do a direct substitution.  But
+because register_parameter_specializations had built up a
+NONTYPE_ARGUMENT_PACK around the new parameter pack, the substitution
+failed.  So let's not wrap it that way.
+
+gcc/cp/ChangeLog
+2020-04-22  Jason Merrill  <jason@redhat.com>
+
+	PR c++/94546
+	* pt.c (register_parameter_specializations): If the instantiation is
+	still a parameter pack, don't wrap it in a NONTYPE_ARGUMENT_PACK.
+	(tsubst_pack_expansion, tsubst_expr): Adjust.
+---
+ gcc/cp/ChangeLog                              |  7 +++++
+ gcc/cp/pt.c                                   | 28 +++++++------------
+ .../g++.dg/cpp2a/lambda-generic-variadic20.C  | 23 +++++++++++++++
+ 3 files changed, 40 insertions(+), 18 deletions(-)
+ create mode 100644 gcc/testsuite/g++.dg/cpp2a/lambda-generic-variadic20.C
+
+diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
+index 640e4948130..4b6691a77f0 100644
+--- a/gcc/cp/ChangeLog
++++ b/gcc/cp/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
+index 7bf249cee5c..2fe7b66707c 100644
+--- a/gcc/cp/pt.c
++++ b/gcc/cp/pt.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/cpp2a/lambda-generic-variadic20.C b/gcc/testsuite/g++.dg/cpp2a/lambda-generic-variadic20.C
+new file mode 100644
+index 00000000000..3d69dbb8e98
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/cpp2a/lambda-generic-variadic20.C
+@@ -0,0 +1 @@
++
+-- 
+2.26.1
+
+=== 0030-PR-c-92746-ICE-with-noexcept-of-function-concept-che.patch ===
+From edabbec31e3bfc9a9757f80c8610706ed00e5a1a Mon Sep 17 00:00:00 2001
+From: Jason Merrill <jason@redhat.com>
+Date: Mon, 13 Jan 2020 18:13:46 -0500
+Subject: [PATCH 0030/2034] 	PR c++/92746 - ICE with noexcept of function
+ concept check.
+
+Another place that needs to specially handle Concepts TS function-style
+concepts.
+
+	* except.c (check_noexcept_r): Handle concept-check.
+---
+ gcc/cp/ChangeLog                            | 3 +++
+ gcc/cp/except.c                             | 2 ++
+ gcc/testsuite/g++.dg/concepts/fn-concept3.C | 6 ++++++
+ 3 files changed, 11 insertions(+)
+ create mode 100644 gcc/testsuite/g++.dg/concepts/fn-concept3.C
+
+diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
+index 59646c70fa4..4729e3d331d 100644
+--- a/gcc/cp/ChangeLog
++++ b/gcc/cp/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/cp/except.c b/gcc/cp/except.c
+index e073bd4d2bc..55b4b6af442 100644
+--- a/gcc/cp/except.c
++++ b/gcc/cp/except.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/concepts/fn-concept3.C b/gcc/testsuite/g++.dg/concepts/fn-concept3.C
+new file mode 100644
+index 00000000000..ecb7f6b12f7
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/concepts/fn-concept3.C
+@@ -0,0 +1 @@
++
+-- 
+2.26.1
+
+=== 0129-Add-PR-number-to-change-log.patch ===
+From f788c2d66a6ee1ded65dafccbc5e485d42af4808 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Fri, 17 Jan 2020 12:22:58 +0000
+Subject: [PATCH 0129/2034] Add PR number to change log
+
+---
+ gcc/ChangeLog | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 6c6d586ca75..49ca5f92dec 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0577-aarch64-Add-an-and.patch ===
+From bba0c624c8b1d6e54dc58091dd21b0c2ab000434 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Mon, 3 Feb 2020 21:43:44 +0000
+Subject: [PATCH 0577/2034] aarch64: Add an and/ior-based movk pattern
+ [PR87763]
+
+This patch adds a second movk pattern that models the instruction
+as a "normal" and/ior operation rather than an insertion.  It fixes
+the third insv_1.c failure in PR87763, which was a regression from
+GCC 8.
+
+2020-02-06  Richard Sandiford  <richard.sandiford@arm.com>
+
+gcc/
+	PR target/87763
+	* config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare.
+	* config/aarch64/aarch64.c (aarch64_movk_shift): New function.
+	* config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern.
+
+gcc/testsuite/
+	PR target/87763
+	* gcc.target/aarch64/movk_2.c: New test.
+---
+ gcc/ChangeLog                             |  7 ++
+ gcc/config/aarch64/aarch64-protos.h       |  1 +
+ gcc/config/aarch64/aarch64.c              | 24 +++++++
+ gcc/config/aarch64/aarch64.md             | 17 +++++
+ gcc/testsuite/ChangeLog                   |  5 ++
+ gcc/testsuite/gcc.target/aarch64/movk_2.c | 78 +++++++++++++++++++++++
+ 6 files changed, 132 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/movk_2.c
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index efbbbf08225..cea8ffee99c 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
+index 24cc65a383a..d29975a8921 100644
+--- a/gcc/config/aarch64/aarch64-protos.h
++++ b/gcc/config/aarch64/aarch64-protos.h
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
+index 6581e4cb075..6a1b4099af1 100644
+--- a/gcc/config/aarch64/aarch64.c
++++ b/gcc/config/aarch64/aarch64.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
+index 90eebce85c0..9c1f17d0f85 100644
+--- a/gcc/config/aarch64/aarch64.md
++++ b/gcc/config/aarch64/aarch64.md
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 601bc336290..cdb26581b9c 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/aarch64/movk_2.c b/gcc/testsuite/gcc.target/aarch64/movk_2.c
+new file mode 100644
+index 00000000000..a0477ad5d42
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/movk_2.c
+@@ -0,0 +1 @@
++
+-- 
+2.26.1
+
+=== 1975-S-390-Fix-several-test-cases.patch ===
+From 803596fe9591026a50b59ff961ebc114097677b5 Mon Sep 17 00:00:00 2001
+From: Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+Date: Tue, 10 Mar 2020 10:49:28 +0100
+Subject: [PATCH 1975/2034] S/390: Fix several test cases
+
+gcc/ChangeLog:
+
+2020-04-21  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
+
+	* config/s390/s390.md ("*<risbg_n>_ior_and_sr_ze<mode>"): Lift from SI
+	mode to DSI. ("*trunc_sidi_and_subreg_ze<clobbercc_or_nocc>"): New
+	insn pattern.
+
+gcc/testsuite/ChangeLog:
+
+2020-04-21  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
+
+	* gcc.target/s390/addsub-signed-overflow-1.c: Fix options.
+	* gcc.target/s390/addsub-signed-overflow-2.c: Fix options.
+	* gcc.target/s390/bswap-1.c: Fix scan assembler regex.
+	* gcc.target/s390/global-array-element-pic2.c: Fix scan assembler regex.
+	* gcc.target/s390/load-relative-check.c: Fix options.
+	* gcc.target/s390/morestack.c: Fix options.
+	* gcc.target/s390/nobp-return-mem-z900.c: Temporarily silence this case.
+	* gcc.target/s390/risbg-ll-1.c: Fix scan assembler regex.
+	* gcc.target/s390/risbg-ll-2.c: Fix scan assembler regex.
+	* gcc.target/s390/risbg-ll-3.c: Fix scan assembler regex.
+	* gcc.target/s390/target-attribute/pr82012.c: Fix error message.
+---
+ gcc/config/s390/s390.md                       | 39 ++++++++++++-------
+ .../s390/addsub-signed-overflow-1.c           |  2 +-
+ .../s390/addsub-signed-overflow-2.c           |  2 +-
+ gcc/testsuite/gcc.target/s390/bswap-1.c       |  8 ++--
+ .../s390/global-array-element-pic2.c          |  4 +-
+ .../gcc.target/s390/load-relative-check.c     |  2 +-
+ gcc/testsuite/gcc.target/s390/morestack.c     |  2 +-
+ .../gcc.target/s390/nobp-return-mem-z900.c    | 17 ++++++--
+ gcc/testsuite/gcc.target/s390/risbg-ll-1.c    | 13 +++----
+ gcc/testsuite/gcc.target/s390/risbg-ll-2.c    |  6 +--
+ gcc/testsuite/gcc.target/s390/risbg-ll-3.c    |  2 +-
+ .../s390/target-attribute/pr82012.c           |  2 +-
+ 12 files changed, 59 insertions(+), 40 deletions(-)
+
+diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
+index 44b59659e20..cf53ef1b791 100644
+--- a/gcc/config/s390/s390.md
++++ b/gcc/config/s390/s390.md
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c
+index 143220d5541..ebc02479587 100644
+--- a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c
++++ b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c
+index 798e489cece..8bd1a764bc6 100644
+--- a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c
++++ b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/bswap-1.c b/gcc/testsuite/gcc.target/s390/bswap-1.c
+index edfcdf888c0..c11a0ea780b 100644
+--- a/gcc/testsuite/gcc.target/s390/bswap-1.c
++++ b/gcc/testsuite/gcc.target/s390/bswap-1.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/global-array-element-pic2.c b/gcc/testsuite/gcc.target/s390/global-array-element-pic2.c
+index b9398a8042f..72b87d40b85 100644
+--- a/gcc/testsuite/gcc.target/s390/global-array-element-pic2.c
++++ b/gcc/testsuite/gcc.target/s390/global-array-element-pic2.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/load-relative-check.c b/gcc/testsuite/gcc.target/s390/load-relative-check.c
+index 3d4671a6b3f..a55bc2442f1 100644
+--- a/gcc/testsuite/gcc.target/s390/load-relative-check.c
++++ b/gcc/testsuite/gcc.target/s390/load-relative-check.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/morestack.c b/gcc/testsuite/gcc.target/s390/morestack.c
+index aa28b72aa6c..4cfa220e737 100644
+--- a/gcc/testsuite/gcc.target/s390/morestack.c
++++ b/gcc/testsuite/gcc.target/s390/morestack.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/nobp-return-mem-z900.c b/gcc/testsuite/gcc.target/s390/nobp-return-mem-z900.c
+index 0b318115a8f..3d6aca1f95f 100644
+--- a/gcc/testsuite/gcc.target/s390/nobp-return-mem-z900.c
++++ b/gcc/testsuite/gcc.target/s390/nobp-return-mem-z900.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-1.c b/gcc/testsuite/gcc.target/s390/risbg-ll-1.c
+index 30350d04c45..1cac15820c0 100644
+--- a/gcc/testsuite/gcc.target/s390/risbg-ll-1.c
++++ b/gcc/testsuite/gcc.target/s390/risbg-ll-1.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
+index 754c17311dd..8bf1a0ff88b 100644
+--- a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
++++ b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-3.c b/gcc/testsuite/gcc.target/s390/risbg-ll-3.c
+index 2a2db543cd9..90d37f2c1ce 100644
+--- a/gcc/testsuite/gcc.target/s390/risbg-ll-3.c
++++ b/gcc/testsuite/gcc.target/s390/risbg-ll-3.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/s390/target-attribute/pr82012.c b/gcc/testsuite/gcc.target/s390/target-attribute/pr82012.c
+index 2e1f7ae57be..ad1bf76d4d2 100644
+--- a/gcc/testsuite/gcc.target/s390/target-attribute/pr82012.c
++++ b/gcc/testsuite/gcc.target/s390/target-attribute/pr82012.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 1999-rs6000-Fix-C-14-vs.-C-17-ABI-bug-on-powerpc64le-PR94.patch ===
+From a39ed81b8a0b46320a7c6ece3f7ad4c3f8519609 Mon Sep 17 00:00:00 2001
+From: Jakub Jelinek <jakub@redhat.com>
+Date: Thu, 23 Apr 2020 09:59:57 +0200
+Subject: [PATCH 1999/2034] rs6000: Fix C++14 vs. C++17 ABI bug on powerpc64le
+ [PR94707]
+
+As mentioned in the PR and on IRC, the recently added struct-layout-1.exp
+new tests FAIL on powerpc64le-linux (among other targets).
+FAIL: tmpdir-g++.dg-struct-layout-1/t032 cp_compat_x_tst.o-cp_compat_y_tst.o execute
+FAIL: tmpdir-g++.dg-struct-layout-1/t058 cp_compat_x_tst.o-cp_compat_y_tst.o execute
+FAIL: tmpdir-g++.dg-struct-layout-1/t059 cp_compat_x_tst.o-cp_compat_y_tst.o execute
+in particular.  The problem is that the presence or absence of the C++17
+artificial empty base fields, which have non-zero TYPE_SIZE, but zero
+DECL_SIZE, change the ABI decisions, if it is present (-std=c++17), the type
+might not be considered homogeneous, while if it is absent (-std=c++14), it
+can be.
+
+The following patch fixes that and emits a -Wpsabi inform; perhaps more
+often than it could, because the fact that rs6000_discover_homogeneous_aggregate
+returns true when it didn't in in GCC 7/8/9 with -std=c++17 doesn't still
+mean it will make a different ABI decision, but the warning triggered only
+on the test I've changed (the struct-layout-1.exp tests use -w -Wno-psabi
+already).
+
+2020-04-23  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94707
+	* config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add
+	cxx17_empty_base_seen argument.  Pass it to recursive calls.
+	Ignore cxx17_empty_base_field_p fields after setting
+	*cxx17_empty_base_seen to true.
+	(rs6000_discover_homogeneous_aggregate): Adjust
+	rs6000_aggregate_candidate caller.  With -Wpsabi, diagnose homogeneous
+	aggregates with C++17 empty base fields.
+
+	* g++.dg/tree-ssa/pr27830.C: Use -Wpsabi -w for -std=c++17 and higher.
+---
+ gcc/ChangeLog                           | 13 ++++++++++
+ gcc/config/rs6000/rs6000-call.c         | 34 +++++++++++++++++++++----
+ gcc/testsuite/ChangeLog                 |  3 +++
+ gcc/testsuite/g++.dg/tree-ssa/pr27830.C |  2 ++
+ 4 files changed, 47 insertions(+), 5 deletions(-)
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 06f7eda0033..93c3076eb86 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
+index e08621ace27..a9ae7ab70ca 100644
+--- a/gcc/config/rs6000/rs6000-call.c
++++ b/gcc/config/rs6000/rs6000-call.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 684e408c1a5..245c1512c76 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr27830.C b/gcc/testsuite/g++.dg/tree-ssa/pr27830.C
+index 01c7fc18783..551ebc428cd 100644
+--- a/gcc/testsuite/g++.dg/tree-ssa/pr27830.C
++++ b/gcc/testsuite/g++.dg/tree-ssa/pr27830.C
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== 0001-Add-patch_area_size-and-patch_area_entry-to-crtl.patch ===
+From 6607bdd99994c834f92fce924abdaea3405f62dc Mon Sep 17 00:00:00 2001
+From: "H.J. Lu" <hjl.tools@gmail.com>
+Date: Fri, 1 May 2020 21:03:10 -0700
+Subject: [PATCH] Add patch_area_size and patch_area_entry to crtl
+
+Currently patchable area is at the wrong place.  It is placed immediately
+after function label and before .cfi_startproc.  A backend should be able
+to add a pseudo patchable area instruction durectly into RTL.  This patch
+adds patch_area_size and patch_area_entry to crtl so that the patchable
+area info is available in RTL passes.
+
+It also limits patch_area_size and patch_area_entry to 65535, which is
+a reasonable maximum size for patchable area.
+
+gcc/
+
+	PR target/93492
+	* cfgexpand.c (pass_expand::execute): Set crtl->patch_area_size
+	and crtl->patch_area_entry.
+	* emit-rtl.h (rtl_data): Add patch_area_size and patch_area_entry.
+	* opts.c (common_handle_option): Limit
+	function_entry_patch_area_size and function_entry_patch_area_start
+	to USHRT_MAX.  Fix a typo in error message.
+	* varasm.c (assemble_start_function): Use crtl->patch_area_size
+	and crtl->patch_area_entry.
+	* doc/invoke.texi: Document the maximum value for
+	-fpatchable-function-entry.
+
+gcc/c-family/
+
+	PR target/12345
+	* c-attribs.c (handle_patchable_function_entry_attribute): Limit
+	value to USHRT_MAX (65535).
+
+---
+ gcc/ChangeLog                                 | 14 ++++++++
+ gcc/c-family/ChangeLog                        |  6 ++++
+ gcc/c-family/c-attribs.c                      |  9 +++++
+ gcc/cfgexpand.c                               | 33 +++++++++++++++++++
+ gcc/doc/invoke.texi                           |  1 +
+ gcc/emit-rtl.h                                |  6 ++++
+ gcc/opts.c                                    |  4 ++-
+ gcc/testsuite/ChangeLog                       |  7 ++++
+ .../patchable_function_entry-error-1.c        |  9 +++++
+ .../patchable_function_entry-error-2.c        |  9 +++++
+ .../patchable_function_entry-error-3.c        | 17 ++++++++++
+ gcc/varasm.c                                  | 30 ++---------------
+ 12 files changed, 116 insertions(+), 29 deletions(-)
+ create mode 100644 gcc/testsuite/c-c++-common/patchable_function_entry-error-1.c
+ create mode 100644 gcc/testsuite/c-c++-common/patchable_function_entry-error-2.c
+ create mode 100644 gcc/testsuite/c-c++-common/patchable_function_entry-error-3.c
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index e85a8e8813e..fb776ba5a0e 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
+index c429b49e68c..69ea1fdc4f3 100644
+--- a/gcc/c-family/ChangeLog
++++ b/gcc/c-family/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/c-family/c-attribs.c b/gcc/c-family/c-attribs.c
+index ac936d5bbbb..a101312c581 100644
+--- a/gcc/c-family/c-attribs.c
++++ b/gcc/c-family/c-attribs.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
+index a7ec77d5c85..86efa22bf60 100644
+--- a/gcc/cfgexpand.c
++++ b/gcc/cfgexpand.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index 527d362533a..767d1f07801 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/emit-rtl.h b/gcc/emit-rtl.h
+index a878efe3cf7..3d6565c8a30 100644
+--- a/gcc/emit-rtl.h
++++ b/gcc/emit-rtl.h
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/opts.c b/gcc/opts.c
+index c212a1a57dc..3dccef39701 100644
+--- a/gcc/opts.c
++++ b/gcc/opts.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 176aa117904..185f9ea725e 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/c-c++-common/patchable_function_entry-error-1.c b/gcc/testsuite/c-c++-common/patchable_function_entry-error-1.c
+new file mode 100644
+index 00000000000..f60bf46cfe3
+--- /dev/null
++++ b/gcc/testsuite/c-c++-common/patchable_function_entry-error-1.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/c-c++-common/patchable_function_entry-error-2.c b/gcc/testsuite/c-c++-common/patchable_function_entry-error-2.c
+new file mode 100644
+index 00000000000..90f88c78be7
+--- /dev/null
++++ b/gcc/testsuite/c-c++-common/patchable_function_entry-error-2.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/c-c++-common/patchable_function_entry-error-3.c b/gcc/testsuite/c-c++-common/patchable_function_entry-error-3.c
+new file mode 100644
+index 00000000000..4490e5c15ca
+--- /dev/null
++++ b/gcc/testsuite/c-c++-common/patchable_function_entry-error-3.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/varasm.c b/gcc/varasm.c
+index 271a67abf56..f062e48071f 100644
+--- a/gcc/varasm.c
++++ b/gcc/varasm.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.2
+
+=== 0002-Bump-date.patch ===
+From a139bafeec76732d964b99e8be3d61b3cab0359d Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Tue, 12 May 2020 09:27:51 +0200
+Subject: [PATCH 2/2] Bump date.
+
+---
+ gcc/DATESTAMP | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
+index c3d42a6f89a..b03d4a0feab 100644
+--- a/gcc/DATESTAMP
++++ b/gcc/DATESTAMP
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.2
+
+=== 0001-Just-test-it.patch ===
+From 6b10b909c0b49ac7ace2cd53021b3ff7ffb2d3f4 Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Tue, 12 May 2020 09:25:54 +0200
+Subject: [PATCH 1/2] Just test it.
+
+gcc/ChangeLog:
+
+2020-05-12  Martin Liska  <mliska@suse.cz>
+
+	PR ipa/12345
+	* tree-vrp.c: Done.
+	* tree.c: Done.
+---
+ gcc/tree-vrp.c | 2 ++
+ gcc/tree.c     | 3 +++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/gcc/tree-vrp.c b/gcc/tree-vrp.c
+index a8861670790..32722d2c714 100644
+--- a/gcc/tree-vrp.c
++++ b/gcc/tree-vrp.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/tree.c b/gcc/tree.c
+index 0ddf002e9eb..fa7c6b28a4e 100644
+--- a/gcc/tree.c
++++ b/gcc/tree.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.2
+
+=== trailing-whitespaces.patch ===
+From eb7c7c524556df5364f03adc20f6a9db20858484 Mon Sep 17 00:00:00 2001
+From: Jakub Jelinek <jakub@redhat.com>
+Date: Mon, 13 Jan 2020 14:14:57 +0100
+Subject: [PATCH 0004/2034] tree-opt: Fix bootstrap failure in
+ tree-ssa-forwprop.c some more PR90838
+
+2020-01-13  Jakub Jelinek  <jakub@redhat.com>   
+
+	PR tree-optimization/90838
+	* tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
+	SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro      
+	argument rather than to initialize temporary for targets that
+	don't use the mode argument at all.  Initialize ctzval to avoid  
+	warning at -O0.
+---
+ gcc/ChangeLog           | 9 +++++++++
+ gcc/tree-ssa-forwprop.c | 6 +++---
+ 2 files changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index a195863212e..f7df07343d1 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c
+index aac31d02b6c..56c470f6ecf 100644
+--- a/gcc/tree-ssa-forwprop.c
++++ b/gcc/tree-ssa-forwprop.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.1
+
+=== pr-check1.patch ===
+From 5194b51ed9714808d88827531e91474895b6c706 Mon Sep 17 00:00:00 2001
+From: Jason Merrill <jason@redhat.com>
+Date: Thu, 16 Jan 2020 16:55:39 -0500
+Subject: [PATCH 0121/2034] PR c++/93286 - ICE with __is_constructible and
+ variadic template.
+
+Here we had been recursing in tsubst_copy_and_build if type2 was a TREE_LIST
+because that function knew how to deal with pack expansions, and tsubst
+didn't.  But tsubst_copy_and_build expects to be dealing with expressions,
+so we crash when trying to convert_from_reference a type.
+
+gcc/cp/ChangeLog:
+	PR ipa/12345
+	* pt.c (tsubst) [TREE_LIST]: Handle pack expansion.
+	(tsubst_copy_and_build) [TRAIT_EXPR]: Always use tsubst for type2.
+
+gcc/testsuite/ChangeLog:
+	* g++.dg/ext/is_constructible4.C: New file.
+---
+ gcc/cp/ChangeLog                             |  4 ++
+ gcc/cp/pt.c                                  | 74 ++++++++++++++++++--
+ gcc/testsuite/g++.dg/ext/is_constructible4.C | 18 +++++
+ 3 files changed, 89 insertions(+), 7 deletions(-)
+ create mode 100644 gcc/testsuite/g++.dg/ext/is_constructible4.C
+
+diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
+index 3ca5d7a11b4..c37e461bcc5 100644
+--- a/gcc/cp/ChangeLog
++++ b/gcc/cp/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
+index 9bb8cc13e5f..872f8ff8f52 100644
+--- a/gcc/cp/pt.c
++++ b/gcc/cp/pt.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/ext/is_constructible4.C b/gcc/testsuite/g++.dg/ext/is_constructible4.C
+new file mode 100644
+index 00000000000..6dfe3c01661
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/ext/is_constructible4.C
+@@ -0,0 +1 @@
++
+-- 
+2.26.1
+
+=== 0020-IPA-Avoid-segfault-in-devirtualization_time_bonus-PR.patch ===
+From 8472660b98a31b32b7d030c2cdc4d41d326364d5 Mon Sep 17 00:00:00 2001
+From: Martin Jambor <mjambor@suse.cz>
+Date: Mon, 13 Jan 2020 19:13:46 +0100
+Subject: [PATCH 0020/2034] IPA: Avoid segfault in devirtualization_time_bonus
+ (PR 93223)
+
+2020-01-13  Martin Jambor  <mjambor@suse.cz>
+
+	PR ipa/93223
+	* ipa-cp.c (devirtualization_time_bonus): Check whether isummary is
+	NULL.
+
+	testsuite/
+	* g++.dg/ipa/pr93223.C: New test.
+---
+ gcc/ipa-cp.c                       |  2 +-
+ gcc/testsuite/g++.dg/ipa/pr93223.C | 62 ++++++++++++++++++++++++++++++
+ 2 files changed, 63 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/g++.dg/ipa/pr93223.C
+
+diff --git a/gcc/ipa-cp.c b/gcc/ipa-cp.c
+index 612f3d0a89b..17da1d8e8a7 100644
+--- a/gcc/ipa-cp.c
++++ b/gcc/ipa-cp.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/ipa/pr93223.C b/gcc/testsuite/g++.dg/ipa/pr93223.C
+new file mode 100644
+index 00000000000..87f98b5e244
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/ipa/pr93223.C
+@@ -0,0 +1 @@
++
+-- 
+2.26.1
+
+=== 0043-Compare-TREE_ADDRESSABLE-and-TYPE_MODE-when-ODR-chec.patch ===
+From 288c5324bf6e418dd94d718d1619464a4f68ff8e Mon Sep 17 00:00:00 2001
+From: Jan Hubicka <jh@suse.cz>
+Date: Tue, 14 Jan 2020 21:45:03 +0100
+Subject: [PATCH 0043/2034] Compare TREE_ADDRESSABLE and TYPE_MODE when ODR
+ checking types.
+
+	PR lto/91576
+	* ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and
+	TYPE_MODE.
+
+	* testsuite/g++.dg/lto/odr-8_0.C: New testcase.
+	* testsuite/g++.dg/lto/odr-8_1.C: New testcase.
+---
+ gcc/ChangeLog                      |  6 ++++++
+ gcc/ipa-devirt.c                   | 21 +++++++++++++++++++++
+ gcc/testsuite/ChangeLog            |  6 ++++++
+ gcc/testsuite/g++.dg/lto/odr-8_0.C |  7 +++++++
+ gcc/testsuite/g++.dg/lto/odr-8_1.C | 12 ++++++++++++
+ 5 files changed, 52 insertions(+)
+ create mode 100644 gcc/testsuite/g++.dg/lto/odr-8_0.C
+ create mode 100644 gcc/testsuite/g++.dg/lto/odr-8_1.C
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 38165123654..33ca91a6467 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/ipa-devirt.c b/gcc/ipa-devirt.c
+index f0031957375..b609a77701d 100644
+--- a/gcc/ipa-devirt.c
++++ b/gcc/ipa-devirt.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 8e3b9105188..dc42601794b 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/g++.dg/lto/odr-8_0.C b/gcc/testsuite/g++.dg/lto/odr-8_0.C
+new file mode 100644
+index 00000000000..59f51399fac
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/lto/odr-8_0.C
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/g++.dg/lto/odr-8_1.C b/gcc/testsuite/g++.dg/lto/odr-8_1.C
+new file mode 100644
+index 00000000000..742df8cc906
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/lto/odr-8_1.C
+@@ -0,0 +1 @@
++
+-- 
+2.26.1
+
+=== 0096-GCC-PATCH-AArch64-Add-ACLE-intrinsics-for-dot-produc.patch ===
+From 8c197c851e7528baba7cb837f34c05ba2242f705 Mon Sep 17 00:00:00 2001
+From: Stam Markianos-Wright <stam.markianos-wright@arm.com>
+Date: Thu, 16 Jan 2020 14:20:48 +0000
+Subject: [PATCH 0096/2034] [GCC][PATCH][AArch64]Add ACLE intrinsics for dot
+ product (usdot - vector, <us/su>dot - by element) for AArch64 AdvSIMD ARMv8.6
+ Extension
+
+gcc/ChangeLog:
+
+2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
+	New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
+	TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
+	(aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
+	(aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
+	* config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
+	usdot_laneq, sudot_lane,sudot_laneq): New.
+	* config/aarch64/aarch64-simd.md (aarch64_usdot): New.
+	(aarch64_<sur>dot_lane): New.
+	* config/aarch64/arm_neon.h (vusdot_s32): New.
+	(vusdotq_s32): New.
+	(vusdot_lane_s32): New.
+	(vsudot_lane_s32): New.
+	* config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
+	(UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.
+
+gcc/testsuite/ChangeLog:
+
+2020-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-1.c: New test.
+	* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-2.c: New test.
+	* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-3.c: New test.
+	* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-3-4.c: New test.
+---
+ gcc/ChangeLog                                 |  18 +++
+ gcc/config/aarch64/aarch64-builtins.c         |  45 +++++-
+ gcc/config/aarch64/aarch64-simd-builtins.def  |   5 +
+ gcc/config/aarch64/aarch64-simd.md            |  34 +++++
+ gcc/config/aarch64/arm_neon.h                 |  83 +++++++++++
+ gcc/config/aarch64/iterators.md               |   7 +
+ gcc/testsuite/ChangeLog                       |   7 +
+ .../aarch64/advsimd-intrinsics/vdot-3-1.c     | 136 +++++++++++++++++
+ .../aarch64/advsimd-intrinsics/vdot-3-2.c     | 137 ++++++++++++++++++
+ .../aarch64/advsimd-intrinsics/vdot-3-3.c     |  31 ++++
+ .../aarch64/advsimd-intrinsics/vdot-3-4.c     |  31 ++++
+ 11 files changed, 531 insertions(+), 3 deletions(-)
+ create mode 100755 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-1.c
+ create mode 100755 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-2.c
+ create mode 100755 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-3.c
+ create mode 100755 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-4.c
+
+diff --git a/gcc/ChangeLog b/gcc/ChangeLog
+index 9a949980699..49dcecb6777 100644
+--- a/gcc/ChangeLog
++++ b/gcc/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
+index f0e0461b7f0..f50c4857e1c 100644
+--- a/gcc/config/aarch64/aarch64-builtins.c
++++ b/gcc/config/aarch64/aarch64-builtins.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
+index 57fc5933b43..4744dd1f6b2 100644
+--- a/gcc/config/aarch64/aarch64-simd-builtins.def
++++ b/gcc/config/aarch64/aarch64-simd-builtins.def
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 2989096b170..9e56e8caf35 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
+index eaba156e26c..c96214003dd 100644
+--- a/gcc/config/aarch64/arm_neon.h
++++ b/gcc/config/aarch64/arm_neon.h
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
+index b9843b83c5f..83720d9802a 100644
+--- a/gcc/config/aarch64/iterators.md
++++ b/gcc/config/aarch64/iterators.md
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
+index 0d8aa6063a7..8b01aa06a40 100644
+--- a/gcc/testsuite/ChangeLog
++++ b/gcc/testsuite/ChangeLog
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-1.c
+new file mode 100755
+index 00000000000..ac4f821e771
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-1.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-2.c
+new file mode 100755
+index 00000000000..96bca2356e4
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-2.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-3.c
+new file mode 100755
+index 00000000000..18ecabef8dc
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-3.c
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-4.c
+new file mode 100755
+index 00000000000..66c87d48694
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-4.c
+@@ -0,0 +1 @@
++
+-- 
+2.26.1
+
+=== 0001-c-Alias.patch ===
+From 3f1a149fc35cdba988464562e2fb824b10652d6b Mon Sep 17 00:00:00 2001
+From: Nathan Sidwell <nathan@acm.org>
+Date: Tue, 19 May 2020 13:29:19 -0700
+Subject: [PATCH] c++: Alias template instantiation template info
+
+I discovered that the alias instantiation machinery would setup
+template_info, and then sometime later overwrite that with equivalent
+info.  This broke modules, because the template info, once set, is
+logically immutable.  Let's just not do that.
+
+	* pt.c (lookup_template_class_1): Do not reinit template_info of an
+	alias here.
+
+(cherry picked from commit 74744bb1f2847b5b9ce3e97e0fec9c23bb0e499f)
+---
+ gcc/cp/pt.c | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
+index b8f03d18541..7230ac724ba 100644
+--- a/gcc/cp/pt.c
++++ b/gcc/cp/pt.c
+@@ -1 +1,2 @@
+
++
+-- 
+2.26.2
+=== 0001-RISC-V-Make-unique.patch ===
+From adce62f53d8ad00e8110a6a2de7962d7a850de16 Mon Sep 17 00:00:00 2001
+From: Keith Packard <keithp@keithp.com>
+Date: Wed, 29 Apr 2020 09:49:56 -0700
+Subject: [PATCH] RISC-V: Make unique SECCAT_SRODATA names start with .srodata
+ (not .sdata2)
+
+default_unique_section uses ".sdata2" as a prefix for SECCAT_SRODATA
+unique sections, but RISC-V uses ".srodata" instead. Override the
+TARGET_ASM_UNIQUE_SECTION function to catch this case, allowing the
+default to be used for all other sections.
+
+gcc/
+	* config/riscv/riscv.c (riscv_unique_section): New.
+	(TARGET_ASM_UNIQUE_SECTION): New.
+
+Signed-off-by: Keith Packard <keithp@keithp.com>
+Reviewed-by: Keith Packard <keithp@keithp.com>
+Reviewed-on: Keith Packard <keithp@keithp.com>
+Co-Authored-by: Keith Packard <keithp@keithp.com>
+Acked-By: Keith Packard <keithp@keithp.com>
+Tested-by: Keith Packard <keithp@keithp.com>
+Reported-by: Keith Packard <keithp@keithp.com>
+Suggested-by: Keith Packard <keithp@keithp.com>
+---
+ gcc/ChangeLog            |  5 +++++
+ gcc/config/riscv/riscv.c | 40 ++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 45 insertions(+)
+
+diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
+index e4c08d780db..1ad9799fce4 100644
+--- a/gcc/config/riscv/riscv.c
++++ b/gcc/config/riscv/riscv.c
+@@ -1 +1,2 @@
+
++
+
+-- 
+2.26.2
+
+=== 0001-Fortran-ProcPtr-function.patch ===
+From eb069ae8819c3a84d7f78becc5501e21ee3a9554 Mon Sep 17 00:00:00 2001
+From: Mark Eggleston <markeggleston@gcc.gnu.org>
+Date: Thu, 7 May 2020 08:02:02 +0100
+Subject: [PATCH] Fortran  : ProcPtr function results: 'ppr@' in error message
+ PR39695
+
+The value 'ppr@' is set in the name of result symbol, the actual
+name of the symbol is in the procedure name symbol pointed
+to by the result symbol's namespace (ns). When reporting errors for
+symbols that have the proc_pointer attribute check whether the
+result attribute is set and set the name accordingly.
+
+2020-05-20  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+gcc/fortran/
+
+	PR fortran/39695
+	* resolve.c (resolve_fl_procedure): Set name depending on
+	whether the result attribute is set.  For PROCEDURE/RESULT
+	conflict use the name in sym->ns->proc_name->name.
+	* symbol.c (gfc_add_type): Add check for function and result
+	attributes use sym->ns->proc_name->name if both are set.
+	Where the symbol cannot have a type use the name in
+	sym->ns->proc_name->name.
+
+2020-05-20  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+gcc/testsuite/
+
+	PR fortran/39695
+	* gfortran.dg/pr39695_1.f90: New test.
+	* gfortran.dg/pr39695_2.f90: New test.
+	* gfortran.dg/pr39695_3.f90: New test.
+	* gfortran.dg/pr39695_4.f90: New test.
+---
+ gcc/fortran/ChangeLog                   | 11 +++++++++++
+ gcc/fortran/resolve.c                   |  6 ++++--
+ gcc/fortran/symbol.c                    |  7 +++++--
+ gcc/testsuite/ChangeLog                 |  8 ++++++++
+ gcc/testsuite/gfortran.dg/pr39695_1.f90 |  8 ++++++++
+ gcc/testsuite/gfortran.dg/pr39695_2.f90 | 12 ++++++++++++
+ gcc/testsuite/gfortran.dg/pr39695_3.f90 | 11 +++++++++++
+ gcc/testsuite/gfortran.dg/pr39695_4.f90 | 14 ++++++++++++++
+ 8 files changed, 73 insertions(+), 4 deletions(-)
+ create mode 100644 gcc/testsuite/gfortran.dg/pr39695_1.f90
+ create mode 100644 gcc/testsuite/gfortran.dg/pr39695_2.f90
+ create mode 100644 gcc/testsuite/gfortran.dg/pr39695_3.f90
+ create mode 100644 gcc/testsuite/gfortran.dg/pr39695_4.f90
+
+diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
+index f6e10ea379c..aaee5eb6b9b 100644
+--- a/gcc/fortran/resolve.c
++++ b/gcc/fortran/resolve.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/fortran/symbol.c b/gcc/fortran/symbol.c
+index 59f602d80d5..b96706138c9 100644
+--- a/gcc/fortran/symbol.c
++++ b/gcc/fortran/symbol.c
+@@ -1 +1,2 @@
+
++
+diff --git a/gcc/testsuite/gfortran.dg/pr39695_1.f90 b/gcc/testsuite/gfortran.dg/pr39695_1.f90
+new file mode 100644
+index 00000000000..4c4b3045f69
+--- /dev/null
++++ b/gcc/testsuite/gfortran.dg/pr39695_1.f90
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gfortran.dg/pr39695_2.f90 b/gcc/testsuite/gfortran.dg/pr39695_2.f90
+new file mode 100644
+index 00000000000..8534724959a
+--- /dev/null
++++ b/gcc/testsuite/gfortran.dg/pr39695_2.f90
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gfortran.dg/pr39695_3.f90 b/gcc/testsuite/gfortran.dg/pr39695_3.f90
+new file mode 100644
+index 00000000000..661e2540bb3
+--- /dev/null
++++ b/gcc/testsuite/gfortran.dg/pr39695_3.f90
+@@ -0,0 +1 @@
++
+diff --git a/gcc/testsuite/gfortran.dg/pr39695_4.f90 b/gcc/testsuite/gfortran.dg/pr39695_4.f90
+new file mode 100644
+index 00000000000..ecb0a43929f
+--- /dev/null
++++ b/gcc/testsuite/gfortran.dg/pr39695_4.f90
+@@ -0,0 +1 @@
++
+-- 
+2.26.2
+
+=== 0001-c-C-20-DR-2237.patch ===
+From 4b38d56dbac6742b038551a36ec80200313123a1 Mon Sep 17 00:00:00 2001
+From: Marek Polacek <polacek@redhat.com>
+Date: Sat, 4 Apr 2020 18:09:53 -0400
+Subject: [PATCH] c++: C++20 DR 2237, disallow simple-template-id in cdtor.
+
+This patch implements DR 2237 which says that a simple-template-id is
+no longer valid as the declarator-id of a constructor or destructor;
+see [diff.cpp17.class]#2.  It is not explicitly stated but out-of-line
+destructors with a simple-template-id are also meant to be ill-formed
+now.  (Out-of-line constructors like that are invalid since DR1435 I
+think.)  This change only applies to C++20; it is not a DR against C++17.
+
+I'm not crazy about the diagnostic in constructors but ISTM that
+cp_parser_constructor_declarator_p shouldn't print errors.
+
+	DR 2237
+	* parser.c (cp_parser_unqualified_id): Reject simple-template-id as
+	the declarator-id of a destructor.
+---
+diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
+index a6a5d975af3..a8082d39aca 100644
+--- a/gcc/cp/parser.c
++++ b/gcc/cp/parser.c
+@@ -1 +1,2 @@
+
++
+
+=== 0001-go-in-ignored-location.patch ===
+From 81994eab700da7fea6644541c163aa0f0f3b8cf1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Cl=C3=A9ment=20Chigot?= <chigot.c@gmail.com>
+Date: Tue, 19 May 2020 16:03:54 +0200
+Subject: libgo: update x/sys/cpu after gccgo support added
+
+Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/234597
+---
+ gcc/go/gofrontend/MERGE                       |  2 +-
+ .../sys/cpu/{cpu_aix_ppc64.go => cpu_aix.go}  |  2 +-
+ .../golang.org/x/sys/cpu/syscall_aix_gccgo.go | 27 +++++++++++++++++++
+ 3 files changed, 29 insertions(+), 2 deletions(-)
+ rename libgo/go/golang.org/x/sys/cpu/{cpu_aix_ppc64.go => cpu_aix.go} (96%)
+ create mode 100644 libgo/go/golang.org/x/sys/cpu/syscall_aix_gccgo.go
+
+diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE
+index bc9c1f07eda..284374820b0 100644
+--- a/gcc/go/gofrontend/MERGE
++++ b/gcc/go/gofrontend/MERGE
+@@ -1 +1,2 @@
+
++
+diff --git a/libgo/go/golang.org/x/sys/cpu/cpu_aix_ppc64.go b/libgo/go/golang.org/x/sys/cpu/cpu_aix.go
+similarity index 96%
+rename from libgo/go/golang.org/x/sys/cpu/cpu_aix_ppc64.go
+rename to libgo/go/golang.org/x/sys/cpu/cpu_aix.go
+index b0ede112d4e..02d03129e50 100644
+--- a/libgo/go/golang.org/x/sys/cpu/cpu_aix_ppc64.go
++++ b/libgo/go/golang.org/x/sys/cpu/cpu_aix.go
+@@ -1 +1,2 @@
+
++
+diff --git a/libgo/go/golang.org/x/sys/cpu/syscall_aix_gccgo.go b/libgo/go/golang.org/x/sys/cpu/syscall_aix_gccgo.go
+new file mode 100644
+index 00000000000..2609cc49ae7
+--- /dev/null
++++ b/libgo/go/golang.org/x/sys/cpu/syscall_aix_gccgo.go
+@@ -0,0 +1 @@
++
+
+-- 
+2.27.0.rc0.183.gde8f92d652-goog
+=== 0001-Update-merge.sh-to-reflect.patch  ===
+From b3d566f570f4416299240b51654b70c74f6cba6a Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Mon, 25 May 2020 20:55:29 +0200
+Subject: [PATCH] Update merge.sh to reflect usage of git.
+
+After switching to GIT, we should use it in libsanitizer
+merge script. I'll do merge from master as soon as
+PR95311 gets fixed.
+
+I'm going to install the patch.
+
+libsanitizer/ChangeLog:
+
+	* LOCAL_PATCHES: Use git hash instead of SVN id.
+	* merge.sh: Use git instead of VCS.  Update paths
+	relative to upstream git repository.
+---
+ libsanitizer/LOCAL_PATCHES |  2 +-
+ libsanitizer/merge.sh      | 10 ++++------
+ 2 files changed, 5 insertions(+), 7 deletions(-)
+
+diff --git a/libsanitizer/LOCAL_PATCHES b/libsanitizer/LOCAL_PATCHES
+index 292b7a6e489..7732de3d436 100644
+--- a/libsanitizer/LOCAL_PATCHES
++++ b/libsanitizer/LOCAL_PATCHES
+@@ -1 +1,2 @@
+
++
+diff --git a/libsanitizer/merge.sh b/libsanitizer/merge.sh
+index dfa7bf3d196..3f4f1629a22 100755
+--- a/libsanitizer/merge.sh
++++ b/libsanitizer/merge.sh
+@@ -1 +1,2 @@
+
++
+ 
+-- 
+2.26.2
+=== 0001-Ada-Reuse-Is_Package_Or_Generic_Package-where-possib.patch ===
+From 557b268fffffdeb0980a17411f458eee333f55c6 Mon Sep 17 00:00:00 2001
+From: Piotr Trojanek <trojanek@adacore.com>
+Date: Thu, 12 Dec 2019 11:45:24 +0100
+Subject: [PATCH] [Ada] Reuse Is_Package_Or_Generic_Package where possible
+
+2020-05-26  Piotr Trojanek  <trojanek@adacore.com>
+
+gcc/ada/
+
+	* contracts.adb, einfo.adb, exp_ch9.adb, sem_ch12.adb,
+	sem_ch4.adb, sem_ch7.adb, sem_ch8.adb, sem_elab.adb,
+	sem_type.adb, sem_util.adb: Reuse Is_Package_Or_Generic_Package
+	where possible (similarly, reuse Is_Concurrent_Type if it was
+	possible in the same expressions).
+---
+ gcc/ada/contracts.adb |  2 +-
+ gcc/ada/einfo.adb     | 22 +++++++++++-----------
+ gcc/ada/exp_ch9.adb   |  2 +-
+ gcc/ada/sem_ch12.adb  |  2 +-
+ gcc/ada/sem_ch4.adb   |  2 +-
+ gcc/ada/sem_ch7.adb   |  6 +++---
+ gcc/ada/sem_ch8.adb   |  6 +++---
+ gcc/ada/sem_elab.adb  |  2 +-
+ gcc/ada/sem_type.adb  |  2 +-
+ gcc/ada/sem_util.adb  |  6 +++---
+ 10 files changed, 26 insertions(+), 26 deletions(-)
+
+diff --git a/gcc/ada/contracts.adb b/gcc/ada/contracts.adb
+index 981bb91..d58f136 100644
+--- a/gcc/ada/contracts.adb
++++ b/gcc/ada/contracts.adb
+@@ -0,0 +1 @@
++
+diff --git a/gcc/ada/einfo.adb b/gcc/ada/einfo.adb
+index 98b508f..1df8ed0 100644
+--- a/gcc/ada/einfo.adb
++++ b/gcc/ada/einfo.adb
+@@ -0,0 +1 @@
++
+diff --git a/gcc/ada/exp_ch9.adb b/gcc/ada/exp_ch9.adb
+index 64ac353..392a221 100644
+--- a/gcc/ada/exp_ch9.adb
++++ b/gcc/ada/exp_ch9.adb
+@@ -0,0 +1 @@
++
+diff --git a/gcc/ada/sem_ch12.adb b/gcc/ada/sem_ch12.adb
+index dc3a3c2..209e060 100644
+--- a/gcc/ada/sem_ch12.adb
++++ b/gcc/ada/sem_ch12.adb
+@@ -0,0 +1 @@
++
+diff --git a/gcc/ada/sem_ch4.adb b/gcc/ada/sem_ch4.adb
+index 5910112..702f265 100644
+--- a/gcc/ada/sem_ch4.adb
++++ b/gcc/ada/sem_ch4.adb
+@@ -0,0 +1 @@
++
+diff --git a/gcc/ada/sem_ch7.adb b/gcc/ada/sem_ch7.adb
+index 6d9a1db..f217dfd 100644
+--- a/gcc/ada/sem_ch7.adb
++++ b/gcc/ada/sem_ch7.adb
+@@ -0,0 +1 @@
++
+diff --git a/gcc/ada/sem_ch8.adb b/gcc/ada/sem_ch8.adb
+index f083f7c..7f50b40 100644
+--- a/gcc/ada/sem_ch8.adb
++++ b/gcc/ada/sem_ch8.adb
+@@ -0,0 +1 @@
++
+diff --git a/gcc/ada/sem_elab.adb b/gcc/ada/sem_elab.adb
+index f3cac46..dbf3fac 100644
+--- a/gcc/ada/sem_elab.adb
++++ b/gcc/ada/sem_elab.adb
+@@ -0,0 +1 @@
++
+diff --git a/gcc/ada/sem_type.adb b/gcc/ada/sem_type.adb
+index e5d01dd..1868568 100644
+--- a/gcc/ada/sem_type.adb
++++ b/gcc/ada/sem_type.adb
+@@ -0,0 +1 @@
++
+diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
+index b980b4c..c1b1d9e 100644
+--- a/gcc/ada/sem_util.adb
++++ b/gcc/ada/sem_util.adb
+@@ -0,0 +1 @@
++
+-- 
+2.1.4
+
+=== 0001-Ada-Add-support-for-XDR-streaming-in-the-default-run.patch ===
+From ed248d9bc3b72b6888a1b9cd84a8ef26809249f0 Mon Sep 17 00:00:00 2001
+From: Arnaud Charlet <charlet@adacore.com>
+Date: Thu, 23 Apr 2020 05:46:29 -0400
+Subject: [PATCH] [Ada] Add support for XDR streaming in the default runtime
+
+--!# FROM: /homes/derodat/tron/gnat2fsf/gnat
+--!# COMMIT: 5ad4cabb9f70114eb61c025e91406d4fba253f95
+--!# Change-Id: I21f92cad27933747495cdfa544a048f62f944cbd
+--!# TN: T423-014
+
+Currently we provide a separate implementation of Stream_Attributes via
+s-stratt__xdr.adb which needs to be recompiled manually.
+
+This change introduces instead a new binder switch to choose at bind
+time which stream implementation to use and replaces s-stratt__xdr.adb
+by a new unit System.Stream_Attributes.XDR.
+
+2020-05-04  Arnaud Charlet  <charlet@adacore.com>
+
+gcc/ada/
+
+	* Makefile.rtl: Add s-statxd.o.
+	* bindgen.adb (Gen_Adainit): Add support for XDR_Stream.
+	* bindusg.adb (Display): Add mention of -xdr.
+	* gnatbind.adb: Process -xdr switch.
+	* init.c (__gl_xdr_stream): New.
+	* opt.ads (XDR_Stream): New.
+	* libgnat/s-stratt__xdr.adb: Rename to...
+	* libgnat/s-statxd.adb: this and adjust.
+	* libgnat/s-statxd.ads: New.
+	* libgnat/s-stratt.ads, libgnat/s-stratt.adb: Choose between
+	default and XDR implementation at runtime.
+	* libgnat/s-ststop.ads: Update comments.
+	* doc/gnat_rm/implementation_advice.rst: Update doc on XDR
+	streaming.
+	* gnat_rm.texi: Regenerate.
+---
+ gcc/ada/Makefile.rtl                          |   1 +
+ gcc/ada/bindgen.adb                           |  29 +-
+ gcc/ada/bindusg.adb                           |   5 +
+ gcc/ada/doc/gnat_rm/implementation_advice.rst |  35 +--
+ gcc/ada/gnat_rm.texi                          |  36 +--
+ gcc/ada/gnatbind.adb                          |   5 +
+ gcc/ada/init.c                                |   1 +
+ .../{s-stratt__xdr.adb => s-statxd.adb}       |  63 ++--
+ gcc/ada/libgnat/s-statxd.ads                  | 117 +++++++
+ gcc/ada/libgnat/s-stratt.adb                  | 286 +++++++++++++++---
+ gcc/ada/libgnat/s-stratt.ads                  |   7 +-
+ gcc/ada/libgnat/s-ststop.ads                  |   4 +-
+ gcc/ada/opt.ads                               |   6 +-
+ 13 files changed, 428 insertions(+), 167 deletions(-)
+ rename gcc/ada/libgnat/{s-stratt__xdr.adb => s-statxd.adb} (96%)
+ create mode 100644 gcc/ada/libgnat/s-statxd.ads
+
+diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
+index b340a9ef919..15e4f68ccdb 100644
+--- a/gcc/ada/Makefile.rtl
++++ b/gcc/ada/Makefile.rtl
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/bindgen.adb b/gcc/ada/bindgen.adb
+index 99ad3009d13..91b4cb38486 100644
+--- a/gcc/ada/bindgen.adb
++++ b/gcc/ada/bindgen.adb
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/bindusg.adb b/gcc/ada/bindusg.adb
+index 45215d2ebea..6fd55ee8721 100644
+--- a/gcc/ada/bindusg.adb
++++ b/gcc/ada/bindusg.adb
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/doc/gnat_rm/implementation_advice.rst b/gcc/ada/doc/gnat_rm/implementation_advice.rst
+index 31376d92461..998d0c597df 100644
+--- a/gcc/ada/doc/gnat_rm/implementation_advice.rst
++++ b/gcc/ada/doc/gnat_rm/implementation_advice.rst
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/gnat_rm.texi b/gcc/ada/gnat_rm.texi
+index c174073d508..d72f905a2df 100644
+--- a/gcc/ada/gnat_rm.texi
++++ b/gcc/ada/gnat_rm.texi
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/gnatbind.adb b/gcc/ada/gnatbind.adb
+index 4907082a42c..4372152b439 100644
+--- a/gcc/ada/gnatbind.adb
++++ b/gcc/ada/gnatbind.adb
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/init.c b/gcc/ada/init.c
+index f9f627ebcff..e76aa79c5a8 100644
+--- a/gcc/ada/init.c
++++ b/gcc/ada/init.c
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/libgnat/s-stratt__xdr.adb b/gcc/ada/libgnat/s-statxd.adb
+similarity index 96%
+rename from gcc/ada/libgnat/s-stratt__xdr.adb
+rename to gcc/ada/libgnat/s-statxd.adb
+index 7e32fcf9b91..fcefae7e6f2 100644
+--- a/gcc/ada/libgnat/s-stratt__xdr.adb
++++ b/gcc/ada/libgnat/s-statxd.adb
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/libgnat/s-statxd.ads b/gcc/ada/libgnat/s-statxd.ads
+new file mode 100644
+index 00000000000..cca5e5471bd
+--- /dev/null
++++ b/gcc/ada/libgnat/s-statxd.ads
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/libgnat/s-stratt.adb b/gcc/ada/libgnat/s-stratt.adb
+index 64f3f040081..366dabdc7b6 100644
+--- a/gcc/ada/libgnat/s-stratt.adb
++++ b/gcc/ada/libgnat/s-stratt.adb
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/libgnat/s-stratt.ads b/gcc/ada/libgnat/s-stratt.ads
+index 73369490146..c8c453aad2a 100644
+--- a/gcc/ada/libgnat/s-stratt.ads
++++ b/gcc/ada/libgnat/s-stratt.ads
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/libgnat/s-ststop.ads b/gcc/ada/libgnat/s-ststop.ads
+index d0da0609d9d..321460b89d8 100644
+--- a/gcc/ada/libgnat/s-ststop.ads
++++ b/gcc/ada/libgnat/s-ststop.ads
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/ada/opt.ads b/gcc/ada/opt.ads
+index 9e0263b431d..37f3d030e3f 100644
+--- a/gcc/ada/opt.ads
++++ b/gcc/ada/opt.ads
+@@ -1 +1,2 @@
+ 
++
+-- 
+2.20.1
+=== 0001-Fortran-type-is-real-kind-1.patch ===
+From 3ea6977d0f1813d982743a09660eec1760e981ec Mon Sep 17 00:00:00 2001
+From: Mark Eggleston <markeggleston@gcc.gnu.org>
+Date: Wed, 1 Apr 2020 09:52:41 +0100
+Subject: [PATCH] Fortran  : "type is( real(kind(1.)) )" spurious syntax error
+ PR94397
+
+Based on a patch in the comments of the PR. That patch fixed this
+problem but caused the test cases for PR93484 to fail. It has been
+changed to reduce initialisation expressions if the expression is
+not EXPR_VARIABLE and not EXPR_CONSTANT.
+
+2020-05-28  Steven G. Kargl  <kargl@gcc.gnu.org>
+	    Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+gcc/fortran/
+
+	PR fortran/94397
+	* match.c (gfc_match_type_spec): New variable ok initialised
+	to true. Set ok with the return value of gfc_reduce_init_expr
+	called only if the expression is not EXPR_CONSTANT and is not
+	EXPR_VARIABLE. Add !ok to the check for type not being integer
+	or the rank being greater than zero.
+
+2020-05-28  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+gcc/testsuite/
+
+	PR fortran/94397
+	* gfortran.dg/pr94397.F90: New test.
+---
+ gcc/fortran/match.c                   |  5 ++++-
+ gcc/testsuite/gfortran.dg/pr94397.F90 | 26 ++++++++++++++++++++++++++
+ 2 files changed, 30 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gfortran.dg/pr94397.F90
+
+diff --git a/gcc/fortran/match.c b/gcc/fortran/match.c
+index 8ae34a94a95..82d2b5087e5 100644
+--- a/gcc/fortran/match.c
++++ b/gcc/fortran/match.c
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/testsuite/gfortran.dg/pr94397.F90 b/gcc/testsuite/gfortran.dg/pr94397.F90
+new file mode 100644
+index 00000000000..fda10c1a88b
+--- /dev/null
++++ b/gcc/testsuite/gfortran.dg/pr94397.F90
+@@ -0,0 +1 @@
++
+-- 
+2.26.2
+
+=== 0001-Missing-change-description.patch ===
+From 8ec655bd94615ba45adabae9b50df299edb74eda Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Fri, 29 May 2020 13:42:57 +0200
+Subject: [PATCH] Test me.
+
+gcc/ChangeLog:
+
+	* ipa-icf-gimple.c (compare_gimple_asm):
+	* ipa-icf-gimple2.c (compare_gimple_asm): Good.
+	* ipa-icf-gimple3.c (compare_gimple_asm):
+---
+ contrib/gcc-changelog/git_commit.py | 10 ++++++++++
+ gcc/ipa-icf-gimple.c                |  1 +
+ 2 files changed, 11 insertions(+)
+
+diff --git a/gcc/ipa-icf-gimple.c b/gcc/ipa-icf-gimple.c
+index 1cd5872c03d..6f95aedb3d3 100644
+--- a/gcc/ipa-icf-gimple.c
++++ b/gcc/ipa-icf-gimple.c
+@@ -850,3 +850,4 @@
+ }
+ 
+ } // ipa_icf_gimple namespace
++
+-- 
+2.26.2
+
+=== 0001-Fix-text-of-hyperlink-in-manual.patch ===
+From c7904d9e08a0ca3f733be3c2e8a3b912fa851fc5 Mon Sep 17 00:00:00 2001
+From: Jonathan Wakely <jwakely@redhat.com>
+Date: Fri, 8 Mar 2019 13:56:53 +0000
+Subject: [PATCH] Fix text of hyperlink in manual
+
+	* doc/xml/manual/using.xml: Use link element instead of xref.
+	* doc/html/*: Regenerate.
+
+---
+ libstdc++-v3/ChangeLog                         | 3 +++
+ libstdc++-v3/doc/html/manual/using_macros.html | 3 ++-
+ libstdc++-v3/doc/xml/manual/using.xml          | 4 ++--
+ 3 files changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/libstdc++-v3/doc/html/manual/using_macros.html b/libstdc++-v3/doc/html/manual/using_macros.html
+index 7030bd2d0fd..dad6564a97d 100644
+--- a/libstdc++-v3/doc/html/manual/using_macros.html
++++ b/libstdc++-v3/doc/html/manual/using_macros.html
+@@ -1 +1,2 @@
+ 
++
+diff --git a/libstdc++-v3/doc/xml/manual/using.xml b/libstdc++-v3/doc/xml/manual/using.xml
+index 2d44a739406..7647e9b8dad 100644
+--- a/libstdc++-v3/doc/xml/manual/using.xml
++++ b/libstdc++-v3/doc/xml/manual/using.xml
+@@ -1 +1,2 @@
+ 
++
+-- 
+2.25.4
+
+=== 0002-libstdc-Fake-test-change-1.patch ===
+From fe4ade6778d1d97214db12bf2c40d0f40e7f953a Mon Sep 17 00:00:00 2001
+From: Jonathan Wakely <jwakely@redhat.com>
+Date: Tue, 2 Jun 2020 11:52:34 +0100
+Subject: [PATCH] libstdc++: Fake change for testing git_commit.py
+
+libstdc++-v3/ChangeLog:
+
+	* doc/xml/faq.xml: Fake change.
+	* doc/html/*: Regenerated.
+---
+ libstdc++-v3/doc/xml/faq.xml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/libstdc++-v3/doc/xml/faq.xml b/libstdc++-v3/doc/xml/faq.xml
+index e419d3c22a0..bcc14dd6d90 100644
+--- a/libstdc++-v3/doc/xml/faq.xml
++++ b/libstdc++-v3/doc/xml/faq.xml
+@@ -1 +1,2 @@
+ 
++
+-- 
+2.25.4
+
+=== 0003-libstdc-Fake-test-change-2.patch ===
+From e460effb3a42c1c046b682fe266da418f2693ef3 Mon Sep 17 00:00:00 2001
+From: Jonathan Wakely <jwakely@redhat.com>
+Date: Tue, 2 Jun 2020 11:52:34 +0100
+Subject: [PATCH] libstdc++: Fake change for testing 2
+
+libstdc++-v3/ChangeLog:
+
+	* doc/xml/faq.xml: Fake change.
+---
+ libstdc++-v3/doc/html/faq.html | 2 +-
+ libstdc++-v3/doc/xml/faq.xml   | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/libstdc++-v3/doc/html/faq.html b/libstdc++-v3/doc/html/faq.html
+index 967e5f5f348..95d21b5bf9f 100644
+--- a/libstdc++-v3/doc/html/faq.html
++++ b/libstdc++-v3/doc/html/faq.html
+@@ -1 +1,2 @@
+ 
++
+--- a/libstdc++-v3/doc/xml/faq.xml
++++ b/libstdc++-v3/doc/xml/faq.xml
+@@ -1 +1,2 @@
+ 
++
+-- 
+2.25.4
+=== 0001-configure.patch ===
+From dbe341cf6a77bb28c5fdf8b32dcb0ff1c2a27348 Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Tue, 9 Jun 2020 09:39:36 +0200
+Subject: [PATCH] c++: Fix --disable-bootstrap with older g++.
+
+Previously I had AX_CXX_COMPILE_STDCXX in the gcc directory configure, which
+added -std=c++11 to CXX if needed, but then CXX is overridden from the
+toplevel directory, so it didn't have the desired effect.  Fixed by moving
+the check to the toplevel.  Currently it is only used when building GCC
+without bootstrapping; other packages that share the toplevel directory
+can adjust the condition if they also want to require C++11 support.
+
+ChangeLog:
+
+	* configure.ac: Check AX_CXX_COMPILE_STDCXX if not bootstrapping.
+	* configure: Regenerate.
+
+gcc/ChangeLog:
+
+	* aclocal.m4: Remove ax_cxx_compile_stdcxx.m4.
+	* configure.ac: Remove AX_CXX_COMPILE_STDCXX.
+	* configure: Regenerate.
+
+---
+ configure        | 999 ++++++++++++++++++++++++++++++++++++++++++++++-
+ configure.ac     |   6 +-
+ gcc/aclocal.m4   |   1 -
+ gcc/configure    | 997 +---------------------------------------------
+ gcc/configure.ac |   2 -
+ 5 files changed, 1004 insertions(+), 1001 deletions(-)
+
+diff --git a/configure b/configure
+index b7897446c70..a0c5aca9e8d 100755
+--- a/configure
++++ b/configure
+@@ -1 +1,2 @@
+ 
++
+diff --git a/configure.ac b/configure.ac
+index 59bd92a3e53..1a53ed418e4 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/aclocal.m4 b/gcc/aclocal.m4
+index e93c1535063..1737d59d1cb 100644
+--- a/gcc/aclocal.m4
++++ b/gcc/aclocal.m4
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/configure b/gcc/configure
+index 46850710424..629c7c7e153 100755
+--- a/gcc/configure
++++ b/gcc/configure
+@@ -1 +1,2 @@
+ 
++
+diff --git a/gcc/configure.ac b/gcc/configure.ac
+index 60d83c30771..9e7efd13ecc 100644
+--- a/gcc/configure.ac
++++ b/gcc/configure.ac
+@@ -1 +1,2 @@
+ 
++
+-- 
+2.26.2
+
+=== 0001-asan-fix-RTX-emission.patch ===
+From e1d68582022cfa2b1dc76646724b397ba2739439 Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Thu, 11 Jun 2020 09:34:41 +0200
+Subject: [PATCH] asan: fix RTX emission for ilp32
+
+gcc/ChangeLog:
+
+	PR sanitizer/95634
+	* asan.c (asan_emit_stack_protection): Fix emission for ilp32
+	by using Pmode instead of ptr_mode.
+
+Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
+(cherry picked from commit 8cff672cb9a132d3d3158c2edfc9a64b55292b80)
+---
+ gcc/asan.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/asan.c b/gcc/asan.c
+index 823eb539993..4ec22162c12 100644
+--- a/gcc/asan.c
++++ b/gcc/asan.c
+@@ -1 +1,2 @@
+ 
++
+-- 
+2.27.0
+

commit 10b028c2813f683a8ebab7d36c9d0d05b49a710b
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Mon Jun 29 15:15:49 2020 +0200

    PR fortran/71706 - ICE on using sync images with -fcheck=bounds
    
    The run-time checking code did not properly convert the kind of the
    argument to SYNC IMAGES, leading to an error in verify_gimple.  Fix that.
    
    gcc/fortran/
            PR fortran/71706
            * trans-stmt.c (gfc_trans_sync): Do proper kind conversion in
            bounds-checking code.
    
    (cherry picked from commit e6cc67f6616c96f3e18a434e0c74ba2f3818cb6d)

diff --git a/gcc/fortran/trans-stmt.c b/gcc/fortran/trans-stmt.c
index 32eb25dce79..acc975b87b3 100644
--- a/gcc/fortran/trans-stmt.c
+++ b/gcc/fortran/trans-stmt.c
@@ -1213,6 +1213,7 @@ gfc_trans_sync (gfc_code *code, gfc_exec_op type)
   if (code->expr1 && (gfc_option.rtcheck & GFC_RTCHECK_BOUNDS)
       && code->expr1->rank == 0)
     {
+      tree images2 = fold_convert (integer_type_node, images);
       tree cond;
       if (flag_coarray != GFC_FCOARRAY_LIB)
 	cond = fold_build2_loc (input_location, NE_EXPR, logical_type_node,
@@ -1224,7 +1225,7 @@ gfc_trans_sync (gfc_code *code, gfc_exec_op type)
 				     2, integer_zero_node,
 				     build_int_cst (integer_type_node, -1));
 	  cond = fold_build2_loc (input_location, GT_EXPR, logical_type_node,
-				  images, tmp);
+				  images2, tmp);
 	  cond2 = fold_build2_loc (input_location, LT_EXPR, logical_type_node,
 				   images,
 				   build_int_cst (TREE_TYPE (images), 1));
@@ -1233,8 +1234,7 @@ gfc_trans_sync (gfc_code *code, gfc_exec_op type)
 	}
       gfc_trans_runtime_check (true, false, cond, &se.pre,
 			       &code->expr1->where, "Invalid image number "
-			       "%d in SYNC IMAGES",
-			       fold_convert (integer_type_node, images));
+			       "%d in SYNC IMAGES", images2);
     }
 
   /* Per F2008, 8.5.1, a SYNC MEMORY is implied by calling the
diff --git a/gcc/testsuite/gfortran.dg/pr71706.f90 b/gcc/testsuite/gfortran.dg/pr71706.f90
new file mode 100644
index 00000000000..860c1c8be80
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr71706.f90
@@ -0,0 +1,10 @@
+! { dg-do compile }
+! { dg-options "-fcoarray=lib -fcheck=all -fdefault-integer-8" }
+! PR fortran/71706 - ICE on using sync images with -fcheck=bounds
+
+program p
+  integer, volatile :: me = 1
+  sync images (me)
+  sync images (int (me, 2))
+  sync images (int (me, 8))
+end

commit 5dd0c2aa6755ef44815a10bb09b713a8132acc21
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jul 3 00:17:34 2020 +0000

    Daily bump.

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index 3e0a7a4a147..806fef51eb2 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,13 @@
+2020-07-02  Martin Liska  <mliska@suse.cz>
+
+	* gcc-changelog/git_check_commit.py: New file.
+	* gcc-changelog/git_commit.py: New file.
+	* gcc-changelog/git_email.py: New file.
+	* gcc-changelog/git_repository.py: New file.
+	* gcc-changelog/git_update_version.py: New file.
+	* gcc-changelog/test_email.py: New file.
+	* gcc-changelog/test_patches.txt: New file.
+
 2020-05-29  Martin Liska  <mliska@suse.cz>
 
 	* git-backport.py: The script did 'git co HEAD~' when
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d5b9f0ff5db..58c9c6a0cb0 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200702
+20200703
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index ec4b0704aad..8aac12f270c 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,12 @@
+2020-07-02  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-06-29  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/71706
+	* trans-stmt.c (gfc_trans_sync): Do proper kind conversion in
+	bounds-checking code.
+
 2020-07-01  Mark Eggleston  <markeggleston@gcc.gnu.org>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4ca1e01ea61..6af91bba332 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-07-02  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-06-29  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/71706
+	* gfortran.dg/pr71706.f90: New file.
+
 2020-07-01  Mark Eggleston  <markeggleston@gcc.gnu.org>
 
 	Backported from master:

commit 9b4d6ceaa9846ce02538b84f2269ef171ee4d0e3
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jul 4 00:17:36 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 58c9c6a0cb0..a1f0455476f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200703
+20200704

commit e51bef33bd29712e44a3e9051bb21d91efa5a65b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jul 5 00:17:31 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a1f0455476f..2aa6fb451c7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200704
+20200705

commit 56ce663146b436ff1a267ee2a9701b7d5e190e62
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Tue Jun 30 23:36:56 2020 +0200

    PR fortran/88379 - ICE with allocatable coarray, class and associate
    
    Catch NULL pointer dereference for ASSOCIATE on allocatable coarray variable.
    
    gcc/fortran/
            PR fortran/88379
            * resolve.c (resolve_assoc_var): Avoid NULL pointer dereference.
    
    (cherry picked from commit 267f84c6035c9380c8d1e9cb83ffe299c23e3a85)

diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
index e3212ff55d2..462d07351ad 100644
--- a/gcc/fortran/resolve.c
+++ b/gcc/fortran/resolve.c
@@ -8731,7 +8731,7 @@ resolve_assoc_var (gfc_symbol* sym, bool resolve_target)
 	  as = NULL;
 	  sym->ts = *ts;
 	  sym->ts.type = BT_CLASS;
-	  attr = CLASS_DATA (sym)->attr;
+	  attr = CLASS_DATA (sym) ? CLASS_DATA (sym)->attr : sym->attr;
 	  attr.class_ok = 0;
 	  attr.associate_var = 1;
 	  attr.dimension = attr.codimension = 0;
diff --git a/gcc/testsuite/gfortran.dg/pr88379.f90 b/gcc/testsuite/gfortran.dg/pr88379.f90
new file mode 100644
index 00000000000..48a23af50c5
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr88379.f90
@@ -0,0 +1,11 @@
+! { dg-do compile }
+! { dg-options "-fcoarray=single" }
+! PR fortran/88379 - ICE with allocatable coarray, class and associate
+
+program p
+  type t
+  end type t
+  class(t), allocatable :: x[:]
+  associate (y => x)
+  end associate
+end

commit 45edf0015ae61857f5d28787e844dc4372fdb67b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jul 6 00:17:42 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2aa6fb451c7..8a714f144c0 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200705
+20200706
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 8aac12f270c..537473fa8ae 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,11 @@
+2020-07-05  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-06-30  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/88379
+	* resolve.c (resolve_assoc_var): Avoid NULL pointer dereference.
+
 2020-07-02  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6af91bba332..82ab48d32c2 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-07-05  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-06-30  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/88379
+	* gfortran.dg/pr88379.f90: New file.
+
 2020-07-02  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:

commit 5131f42d776eda08b3309c6596df9104b69987e9
Author: Will Schmidt <will_schmidt@vnet.ibm.com>
Date:   Wed Jul 1 15:04:13 2020 -0500

    [PATCH v2, PR target/94954] Fix wrong codegen for vec_pack_to_short_fp32() builtin
    
    PR TARGET/94954
    
    2020-07-06  Will Schmidt  <will_schmidt@vnet.ibm.com>
    
    gcc/ChangeLog:
            * config/rs6000/altivec.h (vec_pack_to_short_fp32): Update.
            * config/rs6000/altivec.md (UNSPEC_CONVERT_4F32_8F16): New unspec.
            (convert_4f32_8f16): New define_expand
            * config/rs6000/rs6000-builtin.def (convert_4f32_8f16): New builtin define
            and overload.
            * config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_CONVERT_4F32_8F16): New
            overloaded builtin entry.
            * config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPHP): New unspec.
            (vsx_xvcvsphp): New define_insn.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/powerpc/builtins-1-p9-runnable.c: Update.

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 9ae1a354fc5..5a9e76b75e3 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -431,7 +431,7 @@
 #define vec_first_match_or_eos_index __builtin_vec_first_match_or_eos_index
 #define vec_first_mismatch_index __builtin_vec_first_mismatch_index
 #define vec_first_mismatch_or_eos_index __builtin_vec_first_mismatch_or_eos_index
-#define vec_pack_to_short_fp32 __builtin_vec_convert_4f32_8i16
+#define vec_pack_to_short_fp32 __builtin_vec_convert_4f32_8f16
 #define vec_parity_lsbb __builtin_vec_vparity_lsbb
 #define vec_vctz __builtin_vec_vctz
 #define vec_cnttz __builtin_vec_vctz
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index fb262236b0a..500401c3087 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -80,6 +80,7 @@
    UNSPEC_VUPKHPX
    UNSPEC_VUPKLPX
    UNSPEC_CONVERT_4F32_8I16
+   UNSPEC_CONVERT_4F32_8F16
    UNSPEC_DST
    UNSPEC_DSTT
    UNSPEC_DSTST
@@ -3240,6 +3241,37 @@
   DONE;
 })
 
+;; Convert two vector F32 to packed vector F16.
+;; This builtin packs 32-bit floating-point values into a packed
+;; 16-bit floating point values (stored in 16bit integer type).
+;; (vector unsigned short r = vec_pack_to_short_fp32 (a, b);
+;; The expected codegen for this builtin is
+;;    xvcvsphp t, a
+;;    xvcvsphp u, b
+;;    if (little endian)
+;;      vpkuwum r, t, u
+;;    else
+;;      vpkuwum r, u, t
+
+(define_expand "convert_4f32_8f16"
+  [(set (match_operand:V8HI 0 "register_operand" "=v")
+	(unspec:V8HI [(match_operand:V4SF 1 "register_operand" "v")
+		      (match_operand:V4SF 2 "register_operand" "v")]
+		     UNSPEC_CONVERT_4F32_8F16))]
+  "TARGET_P9_VECTOR"
+{
+  rtx rtx_tmp_hi = gen_reg_rtx (V4SImode);
+  rtx rtx_tmp_lo = gen_reg_rtx (V4SImode);
+
+  emit_insn (gen_vsx_xvcvsphp (rtx_tmp_hi, operands[1]));
+  emit_insn (gen_vsx_xvcvsphp (rtx_tmp_lo, operands[2]));
+  if (!BYTES_BIG_ENDIAN)
+    emit_insn (gen_altivec_vpkuwum (operands[0], rtx_tmp_hi, rtx_tmp_lo));
+  else
+    emit_insn (gen_altivec_vpkuwum (operands[0], rtx_tmp_lo, rtx_tmp_hi));
+  DONE;
+})
+
 ;; Generate
 ;;    xxlxor/vxor SCRATCH0,SCRATCH0,SCRATCH0
 ;;    vsubu?m SCRATCH2,SCRATCH1,%1
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index fa0f3f1e8a5..6fe18eed6d6 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -2069,6 +2069,7 @@ BU_P8V_OVERLOAD_3 (VPERMXOR,   "vpermxor")
 BU_P9V_AV_2 (VSLV,		"vslv",			CONST, vslv)
 BU_P9V_AV_2 (VSRV,		"vsrv",			CONST, vsrv)
 BU_P9V_AV_2 (CONVERT_4F32_8I16, "convert_4f32_8i16", CONST, convert_4f32_8i16)
+BU_P9V_AV_2 (CONVERT_4F32_8F16, "convert_4f32_8f16", CONST, convert_4f32_8f16)
 
 BU_P9V_AV_2 (VFIRSTMATCHINDEX_V16QI, "first_match_index_v16qi",
 	     CONST, first_match_index_v16qi)
@@ -2099,6 +2100,7 @@ BU_P9V_AV_2 (VFIRSTMISMATCHOREOSINDEX_V4SI, "first_mismatch_or_eos_index_v4si",
 BU_P9V_OVERLOAD_2 (VSLV,	"vslv")
 BU_P9V_OVERLOAD_2 (VSRV,	"vsrv")
 BU_P9V_OVERLOAD_2 (CONVERT_4F32_8I16, "convert_4f32_8i16")
+BU_P9V_OVERLOAD_2 (CONVERT_4F32_8F16, "convert_4f32_8f16")
 
 /* 2 argument vector functions added in ISA 3.0 (power9). */
 BU_P9V_AV_2 (VADUB,		"vadub",		CONST,  vaduv16qi3)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index eb19c75bfa4..c2cc219ddc0 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2491,6 +2491,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
 
   { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
+  { P9V_BUILTIN_VEC_CONVERT_4F32_8F16, P9V_BUILTIN_CONVERT_4F32_8F16,
+    RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 
   { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
     RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ea2f2226a31..c5c948c9ef0 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -390,6 +390,7 @@
    UNSPEC_VSX_SIGN_EXTEND
    UNSPEC_VSX_XVCVSPSXWS
    UNSPEC_VSX_XVCVSPSXDS
+   UNSPEC_VSX_XVCVSPHP
    UNSPEC_VSX_VSLO
    UNSPEC_VSX_EXTRACT
    UNSPEC_VSX_SXEXPDP
@@ -2256,6 +2257,15 @@
   "xvcvhpsp %x0,%x1"
   [(set_attr "type" "vecfloat")])
 
+;; Generate xvcvsphp
+(define_insn "vsx_xvcvsphp"
+  [(set (match_operand:V4SI 0 "register_operand" "=wa")
+	(unspec:V4SI [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
+		     UNSPEC_VSX_XVCVSPHP))]
+  "TARGET_P9_VECTOR"
+  "xvcvsphp %x0,%x1"
+[(set_attr "type" "vecfloat")])
+
 ;; xscvdpsp used for splat'ing a scalar to V4SF, knowing that the internal SF
 ;; format of scalars is actually DF.
 (define_insn "vsx_xscvdpsp_scalar"
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c
index acaebb60f1c..5c35b049623 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c
@@ -1,26 +1,52 @@
-/* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
+
+/* { dg-do run { target { powerpc*-*-linux* && p9vector_hw } } } */
+/* { dg-require-effective-target p9vector_hw } */
 /* { dg-options "-O2 -mcpu=power9" } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 
 #include <altivec.h>
+#include <stdio.h>
 
 void abort (void);
 
 int main() {
   int i;
   vector float vfa, vfb;
-  vector unsigned short vur, vuexpt;
+  vector unsigned short vresult, vexpected;
+
+  vfa = (vector float){0.4, 1.6, 20.0, 99.9 };
+  vfb = (vector float){10.0, -2.0, 70.0, 999.0 };
+
+  /* Expected results.  */
+  vexpected = (vector unsigned short) { 0x3666, 0x3e66, 0x4d00, 0x563e,
+					0x4900, 0xc000, 0x5460, 0x63ce};
+
+/*
+     vresult = vec_pack_to_short_fp32 (vfa, vfb);
+  This built-in converts a pair of vector floats into a single vector of
+  packed half-precision (F16) values.  The result type is a vector of
+  signed shorts.
+  The expected codegen for this builtin is
+    xvcvsphp t, vfa
+    xvcvsphp u, vfb
+    if (little endian)
+      vpkuwum vresult, t, u
+    else
+      vpkuwum vresult, u, t
+*/
 
-  vfa = (vector float){3.4, 5.0, 20.0, 50.9 };
-  vfb = (vector float){10.0, 40.0, 70.0, 100.0 };
-  vuexpt = (vector unsigned short){ 3, 5, 20, 50,
-                                    10, 40, 70, 100};
+  vresult = vec_pack_to_short_fp32 (vfa, vfb);
 
-  vur = vec_pack_to_short_fp32 (vfa, vfb);
+#ifdef DEBUG
+  for(i = 0; i< 4; i++) { printf("i=[%d] %f  \n",i,vfa[i]); }
+  for(i = 0; i< 4; i++) { printf("i=[%d] %f  \n",i+4,vfb[i]); }
+  for(i = 0; i< 8; i++) { printf("i=[%d] %d  \n",i,vresult[i]); }
+#endif
 
   for(i = 0; i< 8; i++) {
-    if (vur[i] != vuexpt[i])
-      abort();
+    if (vresult[i] != vexpected[i]) {
+	printf("i=[%d] 0x%x != 0x%x \n",i,vresult[i],vexpected[i]);
+	abort();
+    }
   }
 }

commit 25a37d567df36bbae6b4fee940ece3fc6d4d7140
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jul 7 00:17:47 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5c5a1a9ac63..c0ba4e2112d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2020-07-06  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* config/rs6000/altivec.h (vec_pack_to_short_fp32): Update.
+	* config/rs6000/altivec.md (UNSPEC_CONVERT_4F32_8F16): New unspec.
+	(convert_4f32_8f16): New define_expand
+	* config/rs6000/rs6000-builtin.def (convert_4f32_8f16): New builtin define
+	and overload.
+	* config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_CONVERT_4F32_8F16): New
+	overloaded builtin entry.
+	* config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPHP): New unspec.
+	(vsx_xvcvsphp): New define_insn.
+
 2020-06-30  Alex Coplan  <alex.coplan@arm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 8a714f144c0..c0ce1b47903 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200706
+20200707
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 82ab48d32c2..ac75ca5f882 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2020-07-06  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* gcc.target/powerpc/builtins-1-p9-runnable.c: Update.
+
 2020-07-05  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:

commit d32be852172f3a9dc5a3fb531d229717740b1bd1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jul 8 00:17:52 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c0ce1b47903..f2f90c2763f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200707
+20200708

commit 978bacb758ddbbdee71772a5acafa1db4683950a
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Tue Jul 7 09:02:01 2020 +0200

    accept <case> and [cond] in ChangeLog
    
    Only '(' and ':' currently terminate file lists in ChangeLog entries
    in the ChangeLog parser.  This rules out such legitimate entries as:
    
    * filename <CASE>:
    * filename [COND]:
    
    This patch extends the ChangeLog parser to recognize these forms.
    
    for  contrib/ChangeLog
    
            * gcc-changelog/git_commit.py: Support CASE and COND.
            * gcc-changelog/test_patches.txt: Add test.
            * gcc-changelog/test_email.py: Add test.
    
    Co-Authored-By: Martin Liska <mliska@suse.cz>
    (cherry picked from commit a759bfc7cf238b9fc5bf97884297fc69d8cdf2b5)

diff --git a/contrib/gcc-changelog/git_commit.py b/contrib/gcc-changelog/git_commit.py
index 4d003ccf496..827976c2f84 100755
--- a/contrib/gcc-changelog/git_commit.py
+++ b/contrib/gcc-changelog/git_commit.py
@@ -154,6 +154,7 @@ changelog_regex = re.compile(r'^(?:[fF]or +)?([a-z0-9+-/]*)ChangeLog:?')
 pr_regex = re.compile(r'\tPR (?P<component>[a-z+-]+\/)?([0-9]+)$')
 dr_regex = re.compile(r'\tDR ([0-9]+)$')
 star_prefix_regex = re.compile(r'\t\*(?P<spaces>\ *)(?P<content>.*)')
+end_of_location_regex = re.compile(r'[\[<(:]')
 
 LINE_LIMIT = 100
 TAB_WIDTH = 8
@@ -204,14 +205,13 @@ class ChangeLogEntry:
                 line = m.group('content')
 
             if in_location:
-                # Strip everything that is not a filename in "line": entities
-                # "(NAME)", entry text (the colon, if present, and anything
-                # that follows it).
-                if '(' in line:
-                    line = line[:line.index('(')]
-                    in_location = False
-                if ':' in line:
-                    line = line[:line.index(':')]
+                # Strip everything that is not a filename in "line":
+                # entities "(NAME)", cases "<PATTERN>", conditions
+                # "[COND]", entry text (the colon, if present, and
+                # anything that follows it).
+                m = end_of_location_regex.search(line)
+                if m:
+                    line = line[:m.start()]
                     in_location = False
 
                 # At this point, all that's left is a list of filenames
diff --git a/contrib/gcc-changelog/test_email.py b/contrib/gcc-changelog/test_email.py
index 1c9f8847fe7..b6fbe6a5303 100755
--- a/contrib/gcc-changelog/test_email.py
+++ b/contrib/gcc-changelog/test_email.py
@@ -361,3 +361,7 @@ class TestGccChangelog(unittest.TestCase):
         assert '\tBackported from master:' in entry
         assert '\t2020-06-11  Martin Liska  <mliska@suse.cz>' in entry
         assert '\t\t    Jakub Jelinek  <jakub@redhat.com>' in entry
+
+    def test_square_and_lt_gt(self):
+        email = self.from_patch_glob('0001-Check-for-more-missing')
+        assert not email.errors
diff --git a/contrib/gcc-changelog/test_patches.txt b/contrib/gcc-changelog/test_patches.txt
index 1463fb94936..2bf5d1aefaa 100644
--- a/contrib/gcc-changelog/test_patches.txt
+++ b/contrib/gcc-changelog/test_patches.txt
@@ -3160,3 +3160,38 @@ index 823eb539993..4ec22162c12 100644
 -- 
 2.27.0
 
+=== 0001-Check-for-more-missing-math-decls-on-vxworks.patch ===
+From 0edfc1fd22405ee8e946101e44cd8edc0ee12047 Mon Sep 17 00:00:00 2001
+From: Douglas B Rupp <douglas.b.rupp@gmail.com>
+Date: Sun, 31 May 2020 13:25:28 -0700
+Subject: [PATCH] Check for more missing math decls on vxworks.
+
+Use the GLIBCXX_CHECK_MATH_DECL macro to check for the full list of
+vxworks math decls.
+
+for libstdc++-v3/ChangeLog:
+
+	* crossconfig.m4 <*-vxworks>: Check for more math decls.
+	* configure [FAKEPATCH]: Rebuild.
+---
+ libstdc++-v3/configure      | 255 ++++++++++++++++++++++++++++++++++++++++++++
+ libstdc++-v3/crossconfig.m4 |   3 +-
+ 2 files changed, 257 insertions(+), 1 deletion(-)
+
+diff --git a/libstdc++-v3/configure b/libstdc++-v3/configure
+index b5beb45..4ef678e 100755
+--- a/libstdc++-v3/configure
++++ b/libstdc++-v3/configure
+@@ -1 +1,2 @@
+ 
++
+diff --git a/libstdc++-v3/crossconfig.m4 b/libstdc++-v3/crossconfig.m4
+index fe18288..313f84d 100644
+--- a/libstdc++-v3/crossconfig.m4
++++ b/libstdc++-v3/crossconfig.m4
+@@ -1 +1,2 @@
+ 
++
+-- 
+2.7.4
+

commit 3081f87604c66545bad3deec07465ca3ea9a6d4e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jul 9 00:17:59 2020 +0000

    Daily bump.

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index 806fef51eb2..3fb46492c22 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,13 @@
+2020-07-08  Alexandre Oliva  <oliva@adacore.com>
+
+	Backported from master:
+	2020-07-07  Alexandre Oliva  <oliva@adacore.com>
+		    Martin Liska  <mliska@suse.cz>
+
+	* gcc-changelog/git_commit.py: Support CASE and COND.
+	* gcc-changelog/test_patches.txt: Add test.
+	* gcc-changelog/test_email.py: Add test.
+
 2020-07-02  Martin Liska  <mliska@suse.cz>
 
 	* gcc-changelog/git_check_commit.py: New file.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f2f90c2763f..7f5c70d7c31 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200708
+20200709

commit 9c55b3924be9bc3aa8c056a362b53702b8d05554
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jul 10 00:17:42 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7f5c70d7c31..ffe0f79eae4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200709
+20200710

commit 4452f8309d253244d781b90c5f5d5b598d44737f
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jul 11 00:17:42 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ffe0f79eae4..ff113b92e7d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200710
+20200711

commit 89bb73d540656fc887178330ae8e21a2218f82ab
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jul 12 00:17:28 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ff113b92e7d..3e86f6473e8 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200711
+20200712

commit 92432d97445b26e2c09645474006e80a74cbb53a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jul 13 00:17:27 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3e86f6473e8..f6f6326f811 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200712
+20200713

commit 28621720e0490b8d7646b4dfdda45ca93197ac28
Author: Will Schmidt <will_schmidt@vnet.ibm.com>
Date:   Fri Jul 10 17:13:24 2020 -0500

    [PATCH, rs6000]Add support to enable vmsumudm behind vec_msum builtin.
    
    2020-07-08  Will Schmidt  <will_schmidt@vnet.ibm.com>
    
    gcc/ChangeLog:
    
            * config/rs6000/altivec.h (vec_vmsumudm): New define.
            * config/rs6000/altivec.md (UNSPEC_VMSUMUDM): New unspec.
              (altivec_vmsumudm): New define_insn.
            * config/rs6000/rs6000-builtin.def (altivec_vmsumudm): New BU_ALTIVEC_3
              entry. (vmsumudm): New BU_ALTIVEC_OVERLOAD_3 entry.
            * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
              entries for ALTIVEC_BUILTIN_VMSUMUDM variants of vec_msum.
            * doc/extend.texi: Add document for vmsumudm behind vmsum.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/powerpc/builtins-msum-runnable.c: New test.
            * gcc.target/powerpc/vsx-builtin-msum.c: New test.
    
            Modified from ...
            (cherry picked from commit c1a57681a64150d2fc336ba8e055c5f82e3737e8)

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 5a9e76b75e3..f0592e39d1a 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -159,6 +159,7 @@
 #define vec_vmsumubm __builtin_vec_vmsumubm
 #define vec_vmsumshs __builtin_vec_vmsumshs
 #define vec_vmsumuhs __builtin_vec_vmsumuhs
+#define vec_vmsumudm __builtin_vec_vmsumudm
 #define vec_vmulesb __builtin_vec_vmulesb
 #define vec_vmulesh __builtin_vec_vmulesh
 #define vec_vmuleuh __builtin_vec_vmuleuh
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 500401c3087..603baac42c6 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -21,6 +21,7 @@
 (define_c_enum "unspec"
   [UNSPEC_VCMPBFP
    UNSPEC_VMSUMU
+   UNSPEC_VMSUMUDM
    UNSPEC_VMSUMM
    UNSPEC_VMSUMSHM
    UNSPEC_VMSUMUHS
@@ -811,6 +812,16 @@
   "vmsumu<VI_char>m %0,%1,%2,%3"
   [(set_attr "type" "veccomplex")])
 
+(define_insn "altivec_vmsumudm"
+  [(set (match_operand:V1TI 0 "register_operand" "=v")
+	(unspec:V1TI [(match_operand:V2DI 1 "register_operand" "v")
+		      (match_operand:V2DI 2 "register_operand" "v")
+		      (match_operand:V1TI 3 "register_operand" "v")]
+		     UNSPEC_VMSUMUDM))]
+  "TARGET_P8_VECTOR"
+  "vmsumudm %0,%1,%2,%3"
+  [(set_attr "type" "veccomplex")])
+
 (define_insn "altivec_vmsumm<VI_char>m"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 6fe18eed6d6..5c517c0eda9 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -993,6 +993,7 @@ BU_ALTIVEC_3 (VMLADDUHM,      "vmladduhm",      CONST, 	fmav8hi4)
 BU_ALTIVEC_3 (VMSUMUBM,       "vmsumubm",       CONST, 	altivec_vmsumubm)
 BU_ALTIVEC_3 (VMSUMMBM,       "vmsummbm",       CONST, 	altivec_vmsummbm)
 BU_ALTIVEC_3 (VMSUMUHM,       "vmsumuhm",       CONST, 	altivec_vmsumuhm)
+BU_ALTIVEC_3 (VMSUMUDM,       "vmsumudm",       CONST, 	altivec_vmsumudm)
 BU_ALTIVEC_3 (VMSUMSHM,       "vmsumshm",       CONST, 	altivec_vmsumshm)
 BU_ALTIVEC_3 (VMSUMUHS,       "vmsumuhs",       SAT,   	altivec_vmsumuhs)
 BU_ALTIVEC_3 (VMSUMSHS,       "vmsumshs",       SAT,   	altivec_vmsumshs)
@@ -1303,6 +1304,7 @@ BU_ALTIVEC_OVERLOAD_3 (VMSUMSHM,   "vmsumshm")
 BU_ALTIVEC_OVERLOAD_3 (VMSUMSHS,   "vmsumshs")
 BU_ALTIVEC_OVERLOAD_3 (VMSUMUBM,   "vmsumubm")
 BU_ALTIVEC_OVERLOAD_3 (VMSUMUHM,   "vmsumuhm")
+BU_ALTIVEC_OVERLOAD_3 (VMSUMUDM,   "vmsumudm")
 BU_ALTIVEC_OVERLOAD_3 (VMSUMUHS,   "vmsumuhs")
 
 /* Altivec DST overloaded builtins.  */
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index c2cc219ddc0..c6753fbfa6c 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -3588,6 +3588,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
+
+  { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUDM,
+    RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V1TI },
+  { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUDM,
+    RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI },
+
   { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
   { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index bef02fc0b29..5cd33772104 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -16213,6 +16213,13 @@ bool scalar_test_neg (float source);
 bool scalar_test_neg (double source);
 bool scalar_test_neg (__ieee128 source);
 
+vector _uint128_t vec_msum (vector unsigned long long,
+                           vector unsigned long long,
+                           vector _uint128_t);
+vector _int128_t vec_msum (vector signed long long,
+                          vector signed long long,
+                          vector _int128_t);
+
 int __builtin_byte_in_set (unsigned char u, unsigned long long set);
 int __builtin_byte_in_range (unsigned char u, unsigned int range);
 int __builtin_byte_in_either_range (unsigned char u, unsigned int ranges);
@@ -16263,6 +16270,9 @@ Note that the sign of the significand is not represented in the result
 returned from the @code{scalar_extract_sig} function.  Use the
 @code{scalar_test_neg} function to test the sign of its @code{double}
 argument.
+The @code{vec_msum} functions perform a vector multiply-sum, returning
+the result of arg1*arg2+arg3.  ISA 3.0 adds support for vec_msum returning
+a vector int128 result.
 
 The @code{scalar_insert_exp}
 functions require a 64-bit environment supporting ISA 3.0 or later.
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-msum-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-msum-runnable.c
new file mode 100644
index 00000000000..d94380b4bc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-msum-runnable.c
@@ -0,0 +1,74 @@
+/* { dg-do run { target { p9vector_hw } } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+#include <altivec.h>
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+void abort (void);
+
+int
+main()
+{
+  vector __uint128_t arg_uint128, result_uint128, expected_uint128;
+  vector __int128_t arg_int128, result_int128, expected_int128;
+
+  arg_uint128[0] = 0x1627384950617243;
+  arg_uint128[0] = arg_uint128[0] << 64;
+  arg_uint128[0] |= 0x9405182930415263;
+  expected_uint128[0] = 0x1627384950617243;
+  expected_uint128[0] = expected_uint128[0] << 64;
+  expected_uint128[0] |= 0xb6b07e42a570e5fe;
+  vector unsigned long long arg_vull2 = {0x12345678,0x44445555};
+  vector unsigned long long arg_vull3 = {0x6789abcd,0x66667777};
+  result_uint128 = vec_msum (arg_vull2, arg_vull3, arg_uint128);
+
+  if (result_uint128[0] != expected_uint128[0])
+    {
+#ifdef DEBUG
+       printf("result_uint128[0] doesn't match expected_u128[0]\n");
+       printf("arg_vull2  %llx %llx \n",  arg_vull2[0], arg_vull2[1]);
+       printf("arg_vull3  %llx %llx \n",  arg_vull3[0], arg_vull3[1]);
+       printf("arg_uint128[0] =  %llx ", arg_uint128[0] >> 64);
+       printf(" %llx\n",	 arg_uint128[0] & 0xFFFFFFFFFFFFFFFF);
+
+       printf("result_uint128[0] =  %llx ", result_uint128[0] >> 64);
+       printf(" %llx\n", result_uint128[0] & 0xFFFFFFFFFFFFFFFF);
+
+       printf("expected_uint128[0] =  %llx ", expected_uint128[0] >> 64);
+       printf(" %llx\n", expected_uint128[0] & 0xFFFFFFFFFFFFFFFF);
+#else
+       abort();
+#endif
+    }
+
+  arg_int128[0] = 0x1627384950617283;
+  arg_int128[0] = arg_int128[0] << 64;
+  arg_int128[0] |= 0x9405182930415263;
+  expected_int128[0] = 0x1627384950617283;
+  expected_int128[0] = expected_int128[0] << 64;
+  expected_int128[0] |= 0xd99f35969c11cbfa;
+  vector signed long long arg_vll2 = { 0x567890ab, 0x1233456 };
+  vector signed long long arg_vll3 = { 0xcdef0123, 0x9873451 };
+  result_int128 = vec_msum (arg_vll2, arg_vll3, arg_int128);
+
+  if (result_int128[0] != expected_int128[0])
+    {
+#ifdef DEBUG
+       printf("result_int128[0] doesn't match expected128[0]\n");
+       printf("arg_int128[0] =  %llx ", arg_int128[0] >> 64);
+       printf(" %llx\n",	 arg_int128[0] & 0xFFFFFFFFFFFFFFFF);
+
+       printf("result_int128[0] =  %llx ", result_int128[0] >> 64);
+       printf(" %llx\n", result_int128[0] & 0xFFFFFFFFFFFFFFFF);
+
+       printf("expected_int128[0] =  %llx ", expected_int128[0] >> 64);
+       printf(" %llx\n", expected_int128[0] & 0xFFFFFFFFFFFFFFFF);
+#else
+       abort();
+#endif
+    }
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-msum.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-msum.c
new file mode 100644
index 00000000000..a45052e2b03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-msum.c
@@ -0,0 +1,26 @@
+/* Verify that overloaded built-ins for vec_msum with __int128
+   inputs generate the proper code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-mcpu=power9  -O3" } */
+
+#include <altivec.h>
+
+vector signed __int128
+test_msum_si (vector signed long long vsll_1, vector signed long long vsll_2,
+	   vector signed __int128 vsi128)
+{
+  return vec_msum (vsll_1, vsll_2, vsi128);
+}
+
+vector unsigned __int128
+test_msum_ui (vector unsigned long long vull_1, vector unsigned long long vull_2,
+	   vector unsigned __int128 vui128)
+{
+  return vec_msum (vull_1, vull_2, vui128);
+}
+
+/* { dg_final { scan_assembler_times "vmsumudm" 2 } } */
+

commit fb578967933d523fc15f89a91e815e274131752f
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jul 14 00:17:46 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c0ba4e2112d..62e2856cc91 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-07-13  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* config/rs6000/altivec.h (vec_vmsumudm): New define.
+	* config/rs6000/altivec.md (UNSPEC_VMSUMUDM): New unspec.
+	  (altivec_vmsumudm): New define_insn.
+	* config/rs6000/rs6000-builtin.def (altivec_vmsumudm): New BU_ALTIVEC_3
+	  entry. (vmsumudm): New BU_ALTIVEC_OVERLOAD_3 entry.
+	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
+	  entries for ALTIVEC_BUILTIN_VMSUMUDM variants of vec_msum.
+	* doc/extend.texi: Add document for vmsumudm behind vmsum.
+
 2020-07-06  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	* config/rs6000/altivec.h (vec_pack_to_short_fp32): Update.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f6f6326f811..93b25f7329d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200713
+20200714
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ac75ca5f882..48755299701 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-07-13  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* gcc.target/powerpc/builtins-msum-runnable.c: New test.
+	* gcc.target/powerpc/vsx-builtin-msum.c: New test.
+	Modified from ...
+	(cherry picked from commit c1a57681a64150d2fc336ba8e055c5f82e3737e8)
+
 2020-07-06  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	* gcc.target/powerpc/builtins-1-p9-runnable.c: Update.

commit ff4a27d225f22b8e3a89957421c126c1cbe10cde
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jul 15 00:17:47 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 93b25f7329d..579ecf278ad 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200714
+20200715

commit d60223eeecfac2bc1675a8f723518fc724b132b0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jul 16 00:17:53 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 579ecf278ad..788faba5246 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200715
+20200716

commit 6412f8716f914b7cb1b886deef03c17e66b956b6
Author: Andreas Krebbel <krebbel@linux.ibm.com>
Date:   Wed Nov 21 07:48:49 2018 +0000

    S/390: Support vector load/store alignment hints
    
    The IBM z14 POP adds an optional alignment operand to the vl, vst,
    vlm, and vstm instruction (vector loads and stores). Vectors residing
    on 8 or 16 byte boundaries might get loaded or stored faster on some
    models given the instruction uses the proper hint operand.  A wrong
    hint will hurt performance though.
    
    The attached testcase align-1 currently fails due to:
    https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88085
    
    gcc/ChangeLog:
    
    2018-11-21  Andreas Krebbel  <krebbel@linux.ibm.com>
    
            * configure.ac: Add check for Binutils to determine whether vector
            load/store alignments hints are being supported.
            * config.in: Regenerate.
            * configure: Regenerate.
            * config/s390/s390.c (print_operand): Support new output
            modifier A.
            * config/s390/s390.md ("movti"): Append alignment hint output
            using the new output modifier 'A'.
            * config/s390/vector.md ("mov<mode>", "*vec_tf_to_v1tf")
            ("*vec_ti_to_v1ti"): Likewise.
    
    gcc/testsuite/ChangeLog:
    
    2018-11-21  Andreas Krebbel  <krebbel@linux.ibm.com>
    
            * gcc.target/s390/vector/align-1.c: New test.
            * gcc.target/s390/vector/align-2.c: New test.
    
    (cherry picked from commit b8923037ef1b229326b7f238580d91bbbb76b8ff)

diff --git a/gcc/config.in b/gcc/config.in
index 5bccb408016..4924b8a0c32 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -717,6 +717,13 @@
 #endif
 
 
+/* Define if your assembler supports vl/vst/vlm/vstm with an optional
+   alignment hint argument. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS
+#endif
+
+
 /* Define if your assembler supports VSX instructions. */
 #ifndef USED_FOR_TARGET
 #undef HAVE_AS_VSX
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 9e7fd2b04dd..83abcaaf30d 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -7697,6 +7697,8 @@ print_operand_address (FILE *file, rtx addr)
    CODE specified the format flag.  The following format flags
    are recognized:
 
+    'A': On z14 or higher: If operand is a mem print the alignment
+	 hint usable with vl/vst prefixed by a comma.
     'C': print opcode suffix for branch condition.
     'D': print opcode suffix for inverse branch condition.
     'E': print opcode suffix for branch on index instruction.
@@ -7734,6 +7736,17 @@ print_operand (FILE *file, rtx x, int code)
 
   switch (code)
     {
+    case 'A':
+#ifdef HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS
+      if (TARGET_ARCH12 && MEM_P (x))
+	{
+	  if (MEM_ALIGN (x) >= 128)
+	    fprintf (file, ",4");
+	  else if (MEM_ALIGN (x) == 64)
+	    fprintf (file, ",3");
+	}
+#endif
+      return;
     case 'C':
       fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
       return;
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 93b1ff0b8db..7114609b676 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -1516,8 +1516,8 @@
    vone\t%v0
    vlvgp\t%v0,%1,%N1
    #
-   vl\t%v0,%1
-   vst\t%v1,%0
+   vl\t%v0,%1%A1
+   vst\t%v1,%0%A0
    #
    #"
   [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 24b200e0c57..0fcb8d2e158 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -198,8 +198,8 @@
   ""
   "@
    vlr\t%v0,%v1
-   vl\t%v0,%1
-   vst\t%v1,%0
+   vl\t%v0,%1%A1
+   vst\t%v1,%0%A0
    vzero\t%v0
    vone\t%v0
    vgbm\t%v0,%t1
@@ -549,8 +549,8 @@
   "TARGET_VX"
   "@
    vmrhg\t%v0,%1,%N1
-   vl\t%v0,%1
-   vst\t%v1,%0
+   vl\t%v0,%1%A1
+   vst\t%v1,%0%A0
    vzero\t%v0
    vlvgp\t%v0,%1,%N1"
   [(set_attr "op_type" "VRR,VRX,VRX,VRI,VRR")])
@@ -561,8 +561,8 @@
   "TARGET_VX"
   "@
    vlr\t%v0,%v1
-   vl\t%v0,%1
-   vst\t%v1,%0
+   vl\t%v0,%1%A1
+   vst\t%v1,%0%A0
    vzero\t%v0
    vone\t%v0
    vlvgp\t%v0,%1,%N1"
diff --git a/gcc/configure b/gcc/configure
index 97ba7d7d69c..4dd81d24241 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -27753,6 +27753,42 @@ $as_echo "#define HAVE_AS_ARCHITECTURE_MODIFIERS 1" >>confdefs.h
 
 fi
 
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for vector load/store alignment hints" >&5
+$as_echo_n "checking assembler for vector load/store alignment hints... " >&6; }
+if ${gcc_cv_as_s390_vector_loadstore_alignment_hints+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  gcc_cv_as_s390_vector_loadstore_alignment_hints=no
+    if test $in_tree_gas = yes; then
+    if test $gcc_cv_gas_vers -ge `expr \( \( 2 \* 1000 \) + 31 \) \* 1000 + 0`
+  then gcc_cv_as_s390_vector_loadstore_alignment_hints=yes
+fi
+  elif test x$gcc_cv_as != x; then
+    $as_echo '	vl %v24,0(%r15),3 ' > conftest.s
+    if { ac_try='$gcc_cv_as $gcc_cv_as_flags  -o conftest.o conftest.s >&5'
+  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; }
+    then
+	gcc_cv_as_s390_vector_loadstore_alignment_hints=yes
+    else
+      echo "configure: failed program was" >&5
+      cat conftest.s >&5
+    fi
+    rm -f conftest.o conftest.s
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_s390_vector_loadstore_alignment_hints" >&5
+$as_echo "$gcc_cv_as_s390_vector_loadstore_alignment_hints" >&6; }
+if test $gcc_cv_as_s390_vector_loadstore_alignment_hints = yes; then
+
+$as_echo "#define HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS 1" >>confdefs.h
+
+fi
+
+
     ;;
 esac
 
diff --git a/gcc/configure.ac b/gcc/configure.ac
index d6f2d5b2ed0..6173a1c4f23 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -4878,6 +4878,12 @@ pointers into PC-relative form.])
       [	.machine z13+vx ],,
       [AC_DEFINE(HAVE_AS_ARCHITECTURE_MODIFIERS, 1,
 	  [Define if your assembler supports architecture modifiers.])])
+    gcc_GAS_CHECK_FEATURE([vector load/store alignment hints],
+      gcc_cv_as_s390_vector_loadstore_alignment_hints, [2,31,0],,
+      [	vl %v24,0(%r15),3 ],,
+      [AC_DEFINE(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS, 1,
+	  [Define if your assembler supports vl/vst/vlm/vstm with an optional alignment hint argument.])])
+
     ;;
 esac
 
diff --git a/gcc/testsuite/gcc.target/s390/vector/align-1.c b/gcc/testsuite/gcc.target/s390/vector/align-1.c
new file mode 100644
index 00000000000..cc7777ad22a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/align-1.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mzarch -march=z14" } */
+
+/* The user alignment ends up in DECL_ALIGN of the VAR_DECL and is
+   currently ignored if it is smaller than the alignment of the type.
+   In this testcase an alignment hint ",3" is emitted also for
+   accessing a4 which is wrong.
+   Hence this testcase currently fails:
+   https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88085 */
+
+typedef int __attribute__((vector_size(16))) v4si;
+
+v4si a4 __attribute__((aligned(4)));
+v4si a8 __attribute__((aligned(8)));
+v4si a16 __attribute__((aligned(16)));
+v4si a32 __attribute__((aligned(32)));
+
+void
+foo (v4si a)
+{
+  a4 += a;  /* vl ...   vst ... */
+  a8 += a;  /* vl ...,3 vst ...,3 */
+  a16 += a; /* vl ...,4 vst ...,4 */
+  a32 += a; /* vl ...,4 vst ...,4 */
+}
+
+/* { dg-final { scan-assembler-times "vl\t%v\[0-9\]*,\[0-9\]*\\(%r\[0-9\]*\\),3\n" 1 } } */
+/* { dg-final { scan-assembler-times "vl\t%v\[0-9\]*,\[0-9\]*\\(%r\[0-9\]*\\),4\n" 2 } } */
+/* { dg-final { scan-assembler-times "vst\t%v\[0-9\]*,\[0-9\]*\\(%r\[0-9\]*\\),3\n" 1 } } */
+/* { dg-final { scan-assembler-times "vst\t%v\[0-9\]*,\[0-9\]*\\(%r\[0-9\]*\\),4" 2 } } */
diff --git a/gcc/testsuite/gcc.target/s390/vector/align-2.c b/gcc/testsuite/gcc.target/s390/vector/align-2.c
new file mode 100644
index 00000000000..e4e2fba6a58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/align-2.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mzarch -march=z14" } */
+
+/* The user alignment ends up in TYPE_ALIGN of the type of the
+   VAR_DECL.  */
+
+typedef int __attribute__((vector_size(16),aligned(4))) v4si_4;
+typedef int __attribute__((vector_size(16),aligned(8))) v4si_8;
+typedef int __attribute__((vector_size(16),aligned(16))) v4si_16;
+typedef int __attribute__((vector_size(16),aligned(32))) v4si_32;
+
+v4si_4 a4;
+v4si_8 a8;
+v4si_16 a16;
+v4si_32 a32;
+
+void
+foo (v4si_8 a)
+{
+  a4 += a;  /* vl ...   vst ... */
+  a8 += a;  /* vl ...,3 vst ...,3 */
+  a16 += a; /* vl ...,4 vst ...,4 */
+  a32 += a; /* vl ...,4 vst ...,4 */
+}
+
+/* { dg-final { scan-assembler-times "vl\t%v\[0-9\]*,\[0-9\]*\\(%r\[0-9\]*\\),3\n" 1 } } */
+/* { dg-final { scan-assembler-times "vl\t%v\[0-9\]*,\[0-9\]*\\(%r\[0-9\]*\\),4\n" 2 } } */
+/* { dg-final { scan-assembler-times "vst\t%v\[0-9\]*,\[0-9\]*\\(%r\[0-9\]*\\),3\n" 1 } } */
+/* { dg-final { scan-assembler-times "vst\t%v\[0-9\]*,\[0-9\]*\\(%r\[0-9\]*\\),4" 2 } } */

commit 385b9589e455c2e98369e4c4d4dcc75a7d0b278e
Author: Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
Date:   Tue May 26 18:21:52 2020 +0200

    S/390: Emit vector alignment hints for z13 if AS accepts them
    
    Squashed with commit 87cb9423add08743d8bb3368f0af61ddc9572837
    
    gcc/ChangeLog:
    
            * config.in: Regenerate.
            * config/s390/s390.c (print_operand): Emit vector alignment hints
            for target z13, if AS accepts them.  For other targets the logic
            stays the same.
            * config/s390/s390.h (TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS): Define
            macro.
            * configure: Regenerate.
            * configure.ac: Check HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/s390/vector/align-1.c: Change target architecture
            to z13.
            * gcc.target/s390/vector/align-2.c: Change target architecture
            to z13.
    
    (cherry picked from commit 929fd91ba975eebf9e57f7f092041271dcaf0c34)

diff --git a/gcc/config.in b/gcc/config.in
index 4924b8a0c32..051e6afb097 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -724,6 +724,13 @@
 #endif
 
 
+/* Define if your assembler supports vl/vst/vlm/vstm with an optional
+   alignment hint argument on z13. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13
+#endif
+
+
 /* Define if your assembler supports VSX instructions. */
 #ifndef USED_FOR_TARGET
 #undef HAVE_AS_VSX
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 83abcaaf30d..9057154be07 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -7737,15 +7737,13 @@ print_operand (FILE *file, rtx x, int code)
   switch (code)
     {
     case 'A':
-#ifdef HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS
-      if (TARGET_ARCH12 && MEM_P (x))
+      if (TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS && MEM_P (x))
 	{
 	  if (MEM_ALIGN (x) >= 128)
 	    fprintf (file, ",4");
 	  else if (MEM_ALIGN (x) == 64)
 	    fprintf (file, ",3");
 	}
-#endif
       return;
     case 'C':
       fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 71a12b8c92e..c5307755aa1 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -154,6 +154,13 @@ enum processor_flags
 	(TARGET_VX && TARGET_CPU_VXE)
 #define TARGET_VXE_P(opts)						\
 	(TARGET_VX_P (opts) && TARGET_CPU_VXE_P (opts))
+#if defined(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13)
+#define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS TARGET_Z13
+#elif defined(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS)
+#define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS TARGET_ARCH12
+#else
+#define TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS 0
+#endif
 
 #ifdef HAVE_AS_MACHINE_MACHINEMODE
 #define S390_USE_TARGET_ATTRIBUTE 1
diff --git a/gcc/configure b/gcc/configure
index 4dd81d24241..aa37763d6d4 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -27786,6 +27786,37 @@ if test $gcc_cv_as_s390_vector_loadstore_alignment_hints = yes; then
 
 $as_echo "#define HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS 1" >>confdefs.h
 
+fi
+
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for vector load/store alignment hints on z13" >&5
+$as_echo_n "checking assembler for vector load/store alignment hints on z13... " >&6; }
+if ${gcc_cv_as_s390_vector_loadstore_alignment_hints_on_z13+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  gcc_cv_as_s390_vector_loadstore_alignment_hints_on_z13=no
+  if test x$gcc_cv_as != x; then
+    $as_echo '	vl %v24,0(%r15),3 ' > conftest.s
+    if { ac_try='$gcc_cv_as $gcc_cv_as_flags -mzarch -march=z13 -o conftest.o conftest.s >&5'
+  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; }
+    then
+	gcc_cv_as_s390_vector_loadstore_alignment_hints_on_z13=yes
+    else
+      echo "configure: failed program was" >&5
+      cat conftest.s >&5
+    fi
+    rm -f conftest.o conftest.s
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_s390_vector_loadstore_alignment_hints_on_z13" >&5
+$as_echo "$gcc_cv_as_s390_vector_loadstore_alignment_hints_on_z13" >&6; }
+if test $gcc_cv_as_s390_vector_loadstore_alignment_hints_on_z13 = yes; then
+
+$as_echo "#define HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13 1" >>confdefs.h
+
 fi
 
 
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 6173a1c4f23..a3211db36c0 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -4883,6 +4883,11 @@ pointers into PC-relative form.])
       [	vl %v24,0(%r15),3 ],,
       [AC_DEFINE(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS, 1,
 	  [Define if your assembler supports vl/vst/vlm/vstm with an optional alignment hint argument.])])
+    gcc_GAS_CHECK_FEATURE([vector load/store alignment hints on z13],
+      gcc_cv_as_s390_vector_loadstore_alignment_hints_on_z13,, [-mzarch -march=z13],
+      [	vl %v24,0(%r15),3 ],,
+      [AC_DEFINE(HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13, 1,
+	  [Define if your assembler supports vl/vst/vlm/vstm with an optional alignment hint argument on z13.])])
 
     ;;
 esac
diff --git a/gcc/testsuite/gcc.target/s390/vector/align-1.c b/gcc/testsuite/gcc.target/s390/vector/align-1.c
index cc7777ad22a..6997af2ddcd 100644
--- a/gcc/testsuite/gcc.target/s390/vector/align-1.c
+++ b/gcc/testsuite/gcc.target/s390/vector/align-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -mzarch -march=z14" } */
+/* { dg-options "-O3 -mzarch -march=z13" } */
 
 /* The user alignment ends up in DECL_ALIGN of the VAR_DECL and is
    currently ignored if it is smaller than the alignment of the type.
diff --git a/gcc/testsuite/gcc.target/s390/vector/align-2.c b/gcc/testsuite/gcc.target/s390/vector/align-2.c
index e4e2fba6a58..00e09d3eadb 100644
--- a/gcc/testsuite/gcc.target/s390/vector/align-2.c
+++ b/gcc/testsuite/gcc.target/s390/vector/align-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -mzarch -march=z14" } */
+/* { dg-options "-O3 -mzarch -march=z13" } */
 
 /* The user alignment ends up in TYPE_ALIGN of the type of the
    VAR_DECL.  */

commit da8fd11388922aa04220fb101338ce2f1ec8690d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jul 17 00:17:36 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 62e2856cc91..b651b866833 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,33 @@
+2020-07-16  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
+
+	Backported from master:
+	2020-06-16  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
+
+	* config.in: Regenerate.
+	* config/s390/s390.c (print_operand): Emit vector alignment hints
+	for target z13, if AS accepts them.  For other targets the logic
+	stays the same.
+	* config/s390/s390.h (TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS): Define
+	macro.
+	* configure: Regenerate.
+	* configure.ac: Check HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13.
+
+2020-07-16  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	Backported from master:
+	2018-11-21  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	* configure.ac: Add check for Binutils to determine whether vector
+	load/store alignments hints are being supported.
+	* config.in: Regenerate.
+	* configure: Regenerate.
+	* config/s390/s390.c (print_operand): Support new output
+	modifier A.
+	* config/s390/s390.md ("movti"): Append alignment hint output
+	using the new output modifier 'A'.
+	* config/s390/vector.md ("mov<mode>", "*vec_tf_to_v1tf")
+	("*vec_ti_to_v1ti"): Likewise.
+
 2020-07-13  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	* config/rs6000/altivec.h (vec_vmsumudm): New define.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 788faba5246..9e40331a3cc 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200716
+20200717
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 48755299701..3ea6f67a0ca 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2020-07-16  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
+
+	Backported from master:
+	2020-06-16  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
+
+	* gcc.target/s390/vector/align-1.c: Change target architecture
+	to z13.
+	* gcc.target/s390/vector/align-2.c: Change target architecture
+	to z13.
+
+2020-07-16  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	Backported from master:
+	2018-11-21  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	* gcc.target/s390/vector/align-1.c: New test.
+	* gcc.target/s390/vector/align-2.c: New test.
+
 2020-07-13  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	* gcc.target/powerpc/builtins-msum-runnable.c: New test.

commit eba1113dbdf4b1d0d88755b2538327a1d09837b3
Author: Will Schmidt <will_schmidt@vnet.ibm.com>
Date:   Mon Jul 13 13:38:17 2020 -0500

    [PATCH] rs6000 improve handling of built-in initialization [PR95952]
    
      Handle a scenario with a combination of old hardware, gcc-8 and
    binutils where gcc will ICE during it's selftest.  This ICE was exposed
    when the builtin processing for better #pragma support was added, where
    we no longer skip builtin initialization based on the current mask.
    
    Per the bug report and assorted debug, the ICE occurrs when building
    the gcc-8 branch on a 970* based system with an old binutils.  (gcc-9 and
    newer is OK.  binutils 2.34 is reported to allow success).
    
    The attached patch adds a clause to the builtin initialization to skip
    initialization of a builtin when the builtin mask is set but the icode
    value is zero.   The subsequent assert check remains in place.
    
    2020-07-13  Will Schmidt  <will_schmidt@vnet.ibm.com>
    
    gcc/ChangeLog:
    
            PR target/95952
    
            * config/rs6000/rs6000.c (altivec_init_builtins): Add continue clause to
            predicate builtin handling.

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 75d40367a98..53490f796cd 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -18017,6 +18017,22 @@ altivec_init_builtins (void)
 	mode1 = VOIDmode;
       else
 	{
+	  /* PR95952:  Gracefully skip builtins that do not have the icode properly
+	  set, but do have the builtin mask set.  This has occurred in older gcc
+	  builds with older binutils support when binutils refuses code generation
+	  for instructions that it does not support.  This was exposed by changes
+	  allowing all builtins being initialized for better #pragma support.  */
+	  if (d->icode == CODE_FOR_nothing && d->mask)
+	    {
+	      HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
+	      if (TARGET_DEBUG_BUILTIN)
+		{
+		  fprintf (stderr, "altivec predicate builtin %s skipped", d->name);
+		  fprintf (stderr, " (icode:%d, mask:%lx, builtin_mask:0x%lx\n",
+			   d->icode, d->mask, builtin_mask);
+		}
+	      continue;
+	    }
 	  /* Cannot define builtin if the instruction is disabled.  */
 	  gcc_assert (d->icode != CODE_FOR_nothing);
 	  mode1 = insn_data[d->icode].operand[1].mode;

commit cf3dd7cf1ccb0f9b8f7fe0b0b0ecc2a4b35c628d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jul 18 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b651b866833..2f8b2d6361e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-07-17  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	PR target/95952
+	* config/rs6000/rs6000.c (altivec_init_builtins): Add continue clause to
+	predicate builtin handling.
+
 2020-07-16  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 9e40331a3cc..3e86f30bbb2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200717
+20200718

commit ac766bc9369490b9b927baf3acf154a00fc18595
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jul 19 00:17:33 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3e86f30bbb2..2cb2dfa4ee9 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200718
+20200719

commit 0c1ead4ca67c500cfd75e8613dbc3cdb93eebed8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jul 20 00:17:33 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2cb2dfa4ee9..7ffcb878589 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200719
+20200720

commit 65e85d4d89dc447e879639fbc70725e7249fb0a3
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jul 21 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7ffcb878589..3afbc9c5f92 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200720
+20200721

commit c54d4e218f18c66ce1ad9d7e7762357fd7edacb7
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Mon Jan 28 23:58:57 2019 +0000

    PR libstdc++/68737 Do not use vsnprintf on HPUX
    
    It doesn't conform to the spec, so use vsprintf with a large buffer
    instead.
    
            PR libstdc++/68737
            * config/locale/generic/c_locale.h (__convert_from_v)
            [_GLIBCXX_USE_C99_STDIO]: Also check _GLIBCXX_HAVE_BROKEN_VSNPRINTF.
            * config/os/hpux/os_defines.h: Define _GLIBCXX_HAVE_BROKEN_VSNPRINTF.
            * include/bits/locale_facets.tcc (num_put::_M_insert_float)
            [_GLIBCXX_USE_C99_STDIO]: Also check _GLIBCXX_HAVE_BROKEN_VSNPRINTF.
    
    (cherry picked from commit c98f255154798847bdd1fc6ce33266c1a1ddc13a)

diff --git a/libstdc++-v3/config/locale/generic/c_locale.h b/libstdc++-v3/config/locale/generic/c_locale.h
index 0d208166063..3045931c840 100644
--- a/libstdc++-v3/config/locale/generic/c_locale.h
+++ b/libstdc++-v3/config/locale/generic/c_locale.h
@@ -70,7 +70,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
     __builtin_va_list __args;
     __builtin_va_start(__args, __fmt);
 
-#if _GLIBCXX_USE_C99_STDIO
+#if _GLIBCXX_USE_C99_STDIO && !_GLIBCXX_HAVE_BROKEN_VSNPRINTF
     const int __ret = __builtin_vsnprintf(__out, __size, __fmt, __args);
 #else
     const int __ret = __builtin_vsprintf(__out, __fmt, __args);
diff --git a/libstdc++-v3/config/os/hpux/os_defines.h b/libstdc++-v3/config/os/hpux/os_defines.h
index 1003477fe35..5a9c4faf75d 100644
--- a/libstdc++-v3/config/os/hpux/os_defines.h
+++ b/libstdc++-v3/config/os/hpux/os_defines.h
@@ -109,4 +109,9 @@ typedef long int __padding_type;
 #if defined (__hppa__)
 #define _GLIBCXX_HAVE_BROKEN_STRTOLD 1
 #endif
+
+// The vnsprintf function returns -1 when the buffer is too small.
+// See PR libstdc++/68737.
+#define _GLIBCXX_HAVE_BROKEN_VSNPRINTF 1
+
 #endif
diff --git a/libstdc++-v3/include/bits/locale_facets.tcc b/libstdc++-v3/include/bits/locale_facets.tcc
index 39da5766075..d5fa91e97d6 100644
--- a/libstdc++-v3/include/bits/locale_facets.tcc
+++ b/libstdc++-v3/include/bits/locale_facets.tcc
@@ -992,7 +992,7 @@ _GLIBCXX_BEGIN_NAMESPACE_LDBL
 	char __fbuf[16];
 	__num_base::_S_format_float(__io, __fbuf, __mod);
 
-#if _GLIBCXX_USE_C99_STDIO
+#if _GLIBCXX_USE_C99_STDIO && !_GLIBCXX_HAVE_BROKEN_VSNPRINTF
 	// Precision is always used except for hexfloat format.
 	const bool __use_prec =
 	  (__io.flags() & ios_base::floatfield) != ios_base::floatfield;

commit eb2a8a9e14f4b86fc6d3d1578364381d4a4ffb54
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jul 22 00:17:35 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3afbc9c5f92..71fc8c18748 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200721
+20200722
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 675ac448998..8e62b793cac 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,15 @@
+2020-07-21  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2019-01-28  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/68737
+	* config/locale/generic/c_locale.h (__convert_from_v)
+	[_GLIBCXX_USE_C99_STDIO]: Also check _GLIBCXX_HAVE_BROKEN_VSNPRINTF.
+	* config/os/hpux/os_defines.h: Define _GLIBCXX_HAVE_BROKEN_VSNPRINTF.
+	* include/bits/locale_facets.tcc (num_put::_M_insert_float)
+	[_GLIBCXX_USE_C99_STDIO]: Also check _GLIBCXX_HAVE_BROKEN_VSNPRINTF.
+
 2020-05-06  Jonathan Wakely  <jwakely@redhat.com>
 
 	* doc/xml/manual/abi.xml (abi.versioning.history): Update 8.0.0 to

commit a946595a750c72307eb3cdbc89dec7445c79bb47
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jul 23 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 71fc8c18748..659a031602d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200722
+20200723

commit dfe4408535008fb5ceddadccfba1d35469655db2
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Fri Jul 17 09:53:19 2020 +0100

    gcc-changelog: Fix typo in output
    
    contrib/ChangeLog:
    
            * gcc-changelog/git_update_version.py: Fix typo.
    
    (cherry picked from commit 0c1d1c01039a96c191a7aded40e5df40b14d387a)

diff --git a/contrib/gcc-changelog/git_update_version.py b/contrib/gcc-changelog/git_update_version.py
index ac1b206d238..d2cadb8811c 100755
--- a/contrib/gcc-changelog/git_update_version.py
+++ b/contrib/gcc-changelog/git_update_version.py
@@ -39,7 +39,7 @@ def prepend_to_changelog_files(repo, folder, git_commit, add_to_git):
         raise AssertionError()
     for entry, output in git_commit.to_changelog_entries(use_commit_ts=True):
         full_path = os.path.join(folder, entry, 'ChangeLog')
-        print('writting to %s' % full_path)
+        print('writing to %s' % full_path)
         if os.path.exists(full_path):
             with open(full_path) as f:
                 content = f.read()

commit 3cbdea2dbbaeab1c76255cd4631a9e9fcc67b112
Author: Martin Liska <mliska@suse.cz>
Date:   Thu Jul 23 10:39:00 2020 +0200

    gcc-changelog: fix when somebody reverts a backport
    
    contrib/ChangeLog:
    
            * gcc-changelog/git_commit.py: When reverting a backport,
            we should print only Revert header.
    
    (cherry picked from commit 02cada26e4783b4bfeaf6512a6c22df24d7a25fc)

diff --git a/contrib/gcc-changelog/git_commit.py b/contrib/gcc-changelog/git_commit.py
index 827976c2f84..5a9cc4c7563 100755
--- a/contrib/gcc-changelog/git_commit.py
+++ b/contrib/gcc-changelog/git_commit.py
@@ -628,7 +628,11 @@ class GitCommit:
         for entry in self.changelog_entries:
             output = ''
             timestamp = entry.datetime
-            if self.cherry_pick_commit:
+            if self.revert_commit:
+                timestamp = current_timestamp
+                orig_date = self.original_info.date
+                current_timestamp = orig_date.strftime(DATE_FORMAT)
+            elif self.cherry_pick_commit:
                 info = self.commit_to_info_hook(self.cherry_pick_commit)
                 # it can happen that it is a cherry-pick for a different
                 # repository
@@ -636,10 +640,6 @@ class GitCommit:
                     timestamp = info.date.strftime(DATE_FORMAT)
                 else:
                     timestamp = current_timestamp
-            elif self.revert_commit:
-                timestamp = current_timestamp
-                orig_date = self.original_info.date
-                current_timestamp = orig_date.strftime(DATE_FORMAT)
             elif not timestamp or use_commit_ts:
                 timestamp = current_timestamp
             authors = entry.authors if entry.authors else [self.info.author]
@@ -649,12 +649,13 @@ class GitCommit:
                     authors.append(author)
 
             if self.cherry_pick_commit or self.revert_commit:
-                output += self.format_authors_in_changelog([self.info.author],
+                original_author = self.original_info.author
+                output += self.format_authors_in_changelog([original_author],
                                                            current_timestamp)
-                if self.cherry_pick_commit:
-                    output += '\tBackported from master:\n'
-                else:
+                if self.revert_commit:
                     output += '\tRevert:\n'
+                else:
+                    output += '\tBackported from master:\n'
                 output += self.format_authors_in_changelog(authors,
                                                            timestamp, '\t')
             else:

commit 41c072bded24642d6b4a38e3f5e2890c1aa8c5a1
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Tue Jul 21 21:37:30 2020 +0200

    PR fortran/89574 - ICE in conv_function_val, at fortran/trans-expr.c:3792
    
    When checking for an external procedure from the same file, do not
    consider symbols from different modules.
    
    gcc/fortran/
            PR fortran/89574
            * trans-decl.c (gfc_get_extern_function_decl): Check whether a
            symbol belongs to a different module.
    
    (cherry picked from commit 28f2a080cc27531a8c78aec9f44aeff4961c2a4c)

diff --git a/gcc/fortran/trans-decl.c b/gcc/fortran/trans-decl.c
index 3780d27a9f6..46cc742e23f 100644
--- a/gcc/fortran/trans-decl.c
+++ b/gcc/fortran/trans-decl.c
@@ -2064,12 +2064,17 @@ gfc_get_extern_function_decl (gfc_symbol * sym, gfc_actual_arglist *actual_args)
       if (gsym && !gsym->bind_c)
 	gsym = NULL;
     }
-  else
+  else if (sym->module == NULL)
     {
       gsym = gfc_find_gsymbol (gfc_gsym_root, sym->name);
       if (gsym && gsym->bind_c)
 	gsym = NULL;
     }
+  else
+    {
+      /* Procedure from a different module.  */
+      gsym = NULL;
+    }
 
   if (gsym && !gsym->defined)
     gsym = NULL;
diff --git a/gcc/testsuite/gfortran.dg/pr89574.f90 b/gcc/testsuite/gfortran.dg/pr89574.f90
new file mode 100644
index 00000000000..48dd0680a48
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr89574.f90
@@ -0,0 +1,29 @@
+! { dg-do compile }
+! PR fortran/89574 - ICE in conv_function_val, at fortran/trans-expr.c:3792
+
+module mod1
+contains
+  subroutine init
+  end subroutine
+end module
+
+module mod2
+contains
+  subroutine init
+  end subroutine
+end module
+
+module init
+  use mod1, only : test_init1 => init
+  use mod2, only : test_init2 => init
+  implicit none
+contains
+  subroutine sub
+    call test_init1
+    call test_init2
+    call init
+  contains
+    subroutine init
+    end subroutine
+  end subroutine
+end module

commit ea22267f7bebdfa06f567177c270f7f5f456e468
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jul 24 00:17:33 2020 +0000

    Daily bump.

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index 3fb46492c22..d53c71e206b 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,18 @@
+2020-07-23  Martin Liska  <mliska@suse.cz>
+
+	Backported from master:
+	2020-07-23  Martin Liska  <mliska@suse.cz>
+
+	* gcc-changelog/git_commit.py: When reverting a backport,
+	we should print only Revert header.
+
+2020-07-23  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-07-17  Jonathan Wakely  <jwakely@redhat.com>
+
+	* gcc-changelog/git_update_version.py: Fix typo.
+
 2020-07-08  Alexandre Oliva  <oliva@adacore.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 659a031602d..09a13ab3781 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200723
+20200724
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 537473fa8ae..3dac343f4d8 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,12 @@
+2020-07-23  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-07-21  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/89574
+	* trans-decl.c (gfc_get_extern_function_decl): Check whether a
+	symbol belongs to a different module.
+
 2020-07-05  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3ea6f67a0ca..ca83f5c7a07 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-07-23  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-07-21  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/89574
+	* gfortran.dg/pr89574.f90: New file.
+
 2020-07-16  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 
 	Backported from master:

commit c940e808b4813aa018de6ce1e1400e69ec8b8124
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Jul 25 00:17:33 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 09a13ab3781..ca1a68b03b7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200724
+20200725

commit 1757a63809d6c6073c87978c22dcfffe85753c0f
Author: Dominique d'Humieres <dhumieres.dominique@free.fr>
Date:   Fri Jul 24 20:07:12 2020 +0200

    PR 93592 - Invalid UP/DOWN rounding with EN descriptor.
    
    The fix is obvious (I have added a comment). The tests are probably
    an overkill, but it does not hurt.
    
    libgfortran/ChangeLog:
    
            PR fortran/93592
            * io/write_float.def (build_float_string): Do not reset
              nbefore for FMT_F and FMT_EN.
    
    gcc/testsuite/ChangeLog:
    
            PR fortran/93592
            * gfortran.dg/fmt_en.f90: Adjust test.
            * gfortran.dg/fmt_en_rd.f90: New test.
            * gfortran.dg/fmt_en_rn.f90: New test.
            * gfortran.dg/fmt_en_ru.f90: New test.
            * gfortran.dg/fmt_en_rz.f90: New test.
    
    (cherry picked from commit 05e0971bcf94a481cbfa2731484f024a67dbd4a5)

diff --git a/gcc/testsuite/gfortran.dg/fmt_en.f90 b/gcc/testsuite/gfortran.dg/fmt_en.f90
index b3597e4a423..c8f61cbc369 100644
--- a/gcc/testsuite/gfortran.dg/fmt_en.f90
+++ b/gcc/testsuite/gfortran.dg/fmt_en.f90
@@ -10,7 +10,6 @@ use ISO_FORTRAN_ENV
     integer :: n_tst = 0, n_cnt = 0, n_skip = 0
     character(len=20) :: s, s1
 
-    open (unit = 10, file = 'fmt_en.res')
 !   Check that the default rounding mode is to nearest and to even on tie.
     do i=1,size(real_kinds)
       if (i == 1) then
@@ -149,8 +148,7 @@ use ISO_FORTRAN_ENV
 
     ! print *, n_tst, n_cnt, n_skip
     if (n_cnt /= 0) STOP 1
-    if (all(.not. l_skip)) write (10, *) "All kinds rounded to nearest"
-    close (10)
+    if (all(.not. l_skip)) print *, "All kinds rounded to nearest"
 
 contains
     subroutine checkfmt(fmt, x, cmp)
@@ -182,4 +180,4 @@ contains
         
     end subroutine
 end program
-! { dg-final { scan-file fmt_en.res "All kinds rounded to nearest" { xfail hppa*-*-hpux* } } }
+! { dg-output "All kinds rounded to nearest" { xfail { i?86-*-solaris2.9* hppa*-*-hpux* } } }
diff --git a/gcc/testsuite/gfortran.dg/fmt_en_rd.f90 b/gcc/testsuite/gfortran.dg/fmt_en_rd.f90
new file mode 100644
index 00000000000..ea914e0901c
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/fmt_en_rd.f90
@@ -0,0 +1,185 @@
+! { dg-do run }
+! PR60128 Invalid outputs with EN descriptors
+! Test case provided by Walt Brainerd.
+program pr60128
+use ISO_FORTRAN_ENV
+    implicit none
+    integer, parameter :: j(size(real_kinds)+4)=[REAL_KINDS, [4, 4, 4, 4]]
+    logical :: l_skip(4) = .false.
+    integer :: i
+    integer :: n_tst = 0, n_cnt = 0, n_skip = 0
+    character(len=20,kind=4) :: s, s1
+
+!   Check that the default rounding mode is to nearest and to even on tie.
+    do i=1,size(real_kinds)
+      if (i == 1) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(1)), &
+                                  real(9.49999905,kind=j(1)),  &
+                                  real(9.5,kind=j(1)), real(8.5,kind=j(1))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(1)), &
+                                       real(98765.0,kind=j(1))
+      else if (i == 2) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(2)), &
+                                  real(9.49999905,kind=j(2)),  &
+                                  real(9.5,kind=j(2)), real(8.5,kind=j(2))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(2)), &
+                                       real(98765.0,kind=j(2))
+      else if (i == 3) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(3)), &
+                                  real(9.49999905,kind=j(3)),  &
+                                  real(9.5,kind=j(3)), real(8.5,kind=j(3))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(3)), &
+                                       real(98765.0,kind=j(3))
+      else if (i == 4) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(4)), &
+                                  real(9.49999905,kind=j(4)),  &
+                                  real(9.5,kind=j(4)), real(8.5,kind=j(4))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(4)), &
+                                       real(98765.0,kind=j(4))
+      end if
+      if (s /= 4_'-9.5 9.5 10.  8.' .or. s1 /= 4_' 987.4E+03 98.76E+03') then
+        l_skip(i) = .true.
+        print "('Unsupported rounding for real(',i0,')')", j(i)
+      end if
+    end do
+        
+
+! Original test.
+    call checkfmt("(en15.2)", -.44444,    4_"    -444.44E-03")
+
+! Test for the bug in comment 6.
+    call checkfmt("(rd,en15.0)", 1.0,        4_"         1.E+00")
+    call checkfmt("(rd,en15.0)", 1.00000012, 4_"         1.E+00")
+    call checkfmt("(rd,en15.0)", 0.99999994, 4_"       999.E-03")
+    call checkfmt("(rd,en15.0)", 10.0,       4_"        10.E+00")
+    call checkfmt("(rd,en15.0)", 10.0000010, 4_"        10.E+00")
+    call checkfmt("(rd,en15.0)", 9.99999905, 4_"         9.E+00")
+    call checkfmt("(ru,en15.0)", 100.0,      4_"       100.E+00")
+    call checkfmt("(rd,en15.0)", 100.000008, 4_"       100.E+00")
+    call checkfmt("(rd,en15.0)", 99.9999924, 4_"        99.E+00")
+    call checkfmt("(rd,en15.0)", 1000.0,     4_"         1.E+03")
+    call checkfmt("(rd,en15.0)", 1000.00006, 4_"         1.E+03")
+    call checkfmt("(rd,en15.0)", 999.999939, 4_"       999.E+00")
+    call checkfmt("(rd,en15.0)", 9.5,        4_"         9.E+00")
+    call checkfmt("(rd,en15.0)", 9.50000095, 4_"         9.E+00")
+    call checkfmt("(rd,en15.0)", 9.49999905, 4_"         9.E+00")
+    call checkfmt("(rd,en15.0)", 99.5,       4_"        99.E+00")
+    call checkfmt("(rd,en15.0)", 99.5000076, 4_"        99.E+00")
+    call checkfmt("(rd,en15.0)", 99.4999924, 4_"        99.E+00")
+    call checkfmt("(rd,en15.0)", 999.5,      4_"       999.E+00")
+    call checkfmt("(rd,en15.0)", 999.500061, 4_"       999.E+00")
+    call checkfmt("(rd,en15.0)", 999.499939, 4_"       999.E+00")
+    call checkfmt("(rd,en15.0)", 9500.0,     4_"         9.E+03")
+    call checkfmt("(rd,en15.0)", 9500.00098, 4_"         9.E+03")
+    call checkfmt("(rd,en15.0)", 9499.99902, 4_"         9.E+03")
+    call checkfmt("(rd,en15.1)", 9950.0,     4_"        9.9E+03")
+    call checkfmt("(rd,en15.2)", 9995.0,     4_"       9.99E+03")
+    call checkfmt("(rd,en15.3)", 9999.5,     4_"      9.999E+03")
+    call checkfmt("(rd,en15.1)", 9.5,        4_"        9.5E+00")
+    call checkfmt("(rd,en15.1)", 9.50000095, 4_"        9.5E+00")
+    call checkfmt("(rd,en15.1)", 9.49999905, 4_"        9.4E+00")
+    call checkfmt("(rd,en15.1)", 0.099951,   4_"       99.9E-03")
+    call checkfmt("(rd,en15.1)", 0.009951,   4_"        9.9E-03")
+    call checkfmt("(rd,en15.1)", 0.000999951,4_"      999.9E-06")
+
+    call checkfmt("(rd,en15.0)", -1.0,        4_"        -1.E+00")
+    call checkfmt("(rd,en15.0)", -1.00000012, 4_"        -2.E+00")
+    call checkfmt("(rd,en15.0)", -0.99999994, 4_"        -1.E+00")
+    call checkfmt("(rd,en15.0)", -10.0,       4_"       -10.E+00")
+    call checkfmt("(rd,en15.0)", -10.0000010, 4_"       -11.E+00")
+    call checkfmt("(rd,en15.0)", -9.99999905, 4_"       -10.E+00")
+    call checkfmt("(rd,en15.0)", -100.0,      4_"      -100.E+00")
+    call checkfmt("(rd,en15.0)", -100.000008, 4_"      -101.E+00")
+    call checkfmt("(rd,en15.0)", -99.9999924, 4_"      -100.E+00")
+    call checkfmt("(rd,en15.0)", -1000.0,     4_"        -1.E+03")
+    call checkfmt("(rd,en15.0)", -1000.00006, 4_"        -2.E+03")
+    call checkfmt("(rd,en15.0)", -999.999939, 4_"        -1.E+03")
+    call checkfmt("(rd,en15.0)", -9.5,        4_"       -10.E+00")
+    call checkfmt("(rd,en15.0)", -9.50000095, 4_"       -10.E+00")
+    call checkfmt("(rd,en15.0)", -9.49999905, 4_"       -10.E+00")
+    call checkfmt("(rd,en15.0)", -99.5,       4_"      -100.E+00")
+    call checkfmt("(rd,en15.0)", -99.5000076, 4_"      -100.E+00")
+    call checkfmt("(rd,en15.0)", -99.4999924, 4_"      -100.E+00")
+    call checkfmt("(rd,en15.0)", -999.5,      4_"        -1.E+03")
+    call checkfmt("(rd,en15.0)", -999.500061, 4_"        -1.E+03")
+    call checkfmt("(rd,en15.0)", -999.499939, 4_"        -1.E+03")
+    call checkfmt("(rd,en15.0)", -9500.0,     4_"       -10.E+03")
+    call checkfmt("(rd,en15.0)", -9500.00098, 4_"       -10.E+03")
+    call checkfmt("(rd,en15.0)", -9499.99902, 4_"       -10.E+03")
+    call checkfmt("(rd,en15.1)", -9950.0,     4_"      -10.0E+03")
+    call checkfmt("(rd,en15.2)", -9995.0,     4_"     -10.00E+03")
+    call checkfmt("(rd,en15.3)", -9999.5,     4_"    -10.000E+03")
+    call checkfmt("(rd,en15.1)", -9.5,        4_"       -9.5E+00")
+    call checkfmt("(rd,en15.1)", -9.50000095, 4_"       -9.6E+00")
+    call checkfmt("(rd,en15.1)", -9.49999905, 4_"       -9.5E+00")
+    call checkfmt("(rd,en15.1)", -0.099951,   4_"     -100.0E-03")
+    call checkfmt("(rd,en15.1)", -0.009951,   4_"      -10.0E-03")
+    call checkfmt("(rd,en15.1)", -0.000999951,4_"       -1.0E-03")
+
+    call checkfmt("(rd,en15.1)", 987350.,     4_"      987.3E+03")
+    call checkfmt("(rd,en15.2)", 98735.,      4_"      98.73E+03")
+    call checkfmt("(rd,en15.3)", 9873.5,      4_"      9.873E+03")
+    call checkfmt("(rd,en15.1)", 987650.,     4_"      987.6E+03")
+    call checkfmt("(rd,en15.2)", 98765.,      4_"      98.76E+03")
+    call checkfmt("(rd,en15.3)", 9876.5,      4_"      9.876E+03")
+    call checkfmt("(rd,en15.1)", 3.125E-02,   4_"       31.2E-03")
+    call checkfmt("(rd,en15.1)", 9.375E-02,   4_"       93.7E-03")
+    call checkfmt("(rd,en15.2)", 1.5625E-02,  4_"      15.62E-03")
+    call checkfmt("(rd,en15.2)", 4.6875E-02,  4_"      46.87E-03")
+    call checkfmt("(rd,en15.3)", 7.8125E-03,  4_"      7.812E-03")
+    call checkfmt("(rd,en15.3)", 2.34375E-02, 4_"     23.437E-03")
+    call checkfmt("(rd,en15.3)", 9.765625E-04,4_"    976.562E-06")
+    call checkfmt("(rd,en15.6)", 2.9296875E-03,4_"   2.929687E-03")
+
+    call checkfmt("(rd,en15.1)", -987350.,     4_"     -987.4E+03")
+    call checkfmt("(rd,en15.2)", -98735.,      4_"     -98.74E+03")
+    call checkfmt("(rd,en15.3)", -9873.5,      4_"     -9.874E+03")
+    call checkfmt("(rd,en15.1)", -987650.,     4_"     -987.7E+03")
+    call checkfmt("(rd,en15.2)", -98765.,      4_"     -98.77E+03")
+    call checkfmt("(rd,en15.3)", -9876.5,      4_"     -9.877E+03")
+    call checkfmt("(rd,en15.1)", -3.125E-02,   4_"      -31.3E-03")
+    call checkfmt("(rd,en15.1)", -9.375E-02,   4_"      -93.8E-03")
+    call checkfmt("(rd,en15.2)", -1.5625E-02,  4_"     -15.63E-03")
+    call checkfmt("(rd,en15.2)", -4.6875E-02,  4_"     -46.88E-03")
+    call checkfmt("(rd,en15.3)", -7.8125E-03,  4_"     -7.813E-03")
+    call checkfmt("(rd,en15.3)", -2.34375E-02, 4_"    -23.438E-03")
+    call checkfmt("(rd,en15.3)", -9.765625E-04,4_"   -976.563E-06")
+    call checkfmt("(rd,en15.6)", -2.9296875E-03,4_"  -2.929688E-03")
+
+    print *, n_tst, n_cnt, n_skip
+    if (n_cnt /= 0) stop n_cnt
+    if (all(.not. l_skip)) print *, "All kinds rounded down"
+
+contains
+    subroutine checkfmt(fmt, x, cmp)
+        implicit none
+        integer :: i
+        character(len=*), intent(in) :: fmt
+        real, intent(in) :: x
+        character(len=*, kind=4), intent(in) :: cmp
+        do i=1,size(real_kinds)
+          if (l_skip(i)) cycle
+          if (i == 1) then
+            write(s, fmt) real(x,kind=j(1))
+          else if (i == 2) then
+            write(s, fmt) real(x,kind=j(2))
+          else if (i == 3) then
+            write(s, fmt) real(x,kind=j(3))
+          else if (i == 4) then
+            write(s, fmt) real(x,kind=j(4))
+          end if
+          n_tst = n_tst + 1
+          if (s /= cmp) then
+            if (l_skip(i)) then
+              n_skip = n_skip + 1
+            else
+              print "(a,1x,a,' expected: ',1x,a)", fmt, s, cmp
+              n_cnt = n_cnt + 1
+            end if
+          end if
+        end do
+        
+    end subroutine
+end program
+! { dg-output "All kinds rounded down" { xfail { i?86-*-solaris2.9* hppa*-*-hpux* } } }
+! { dg-final { cleanup-saved-temps } }
diff --git a/gcc/testsuite/gfortran.dg/fmt_en_rn.f90 b/gcc/testsuite/gfortran.dg/fmt_en_rn.f90
new file mode 100644
index 00000000000..b0ada5c672d
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/fmt_en_rn.f90
@@ -0,0 +1,185 @@
+! { dg-do run }
+! PR60128 Invalid outputs with EN descriptors
+! Test case provided by Walt Brainerd.
+program pr60128
+use ISO_FORTRAN_ENV
+    implicit none
+    integer, parameter :: j(size(real_kinds)+4)=[REAL_KINDS, [4, 4, 4, 4]]
+    logical :: l_skip(4) = .false.
+    integer :: i
+    integer :: n_tst = 0, n_cnt = 0, n_skip = 0
+    character(len=20,kind=4) :: s, s1
+
+!   Check that the default rounding mode is to nearest and to even on tie.
+    do i=1,size(real_kinds)
+      if (i == 1) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(1)), &
+                                  real(9.49999905,kind=j(1)),  &
+                                  real(9.5,kind=j(1)), real(8.5,kind=j(1))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(1)), &
+                                       real(98765.0,kind=j(1))
+      else if (i == 2) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(2)), &
+                                  real(9.49999905,kind=j(2)),  &
+                                  real(9.5,kind=j(2)), real(8.5,kind=j(2))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(2)), &
+                                       real(98765.0,kind=j(2))
+      else if (i == 3) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(3)), &
+                                  real(9.49999905,kind=j(3)),  &
+                                  real(9.5,kind=j(3)), real(8.5,kind=j(3))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(3)), &
+                                       real(98765.0,kind=j(3))
+      else if (i == 4) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(4)), &
+                                  real(9.49999905,kind=j(4)),  &
+                                  real(9.5,kind=j(4)), real(8.5,kind=j(4))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(4)), &
+                                       real(98765.0,kind=j(4))
+      end if
+      if (s /= 4_'-9.5 9.5 10.  8.' .or. s1 /= 4_' 987.4E+03 98.76E+03') then
+        l_skip(i) = .true.
+        print "('Unsupported rounding for real(',i0,')')", j(i)
+      end if
+    end do
+        
+
+! Original test.
+    call checkfmt("(en15.2)", -.44444,    4_"    -444.44E-03")
+
+! Test for the bug in comment 6.
+    call checkfmt("(rn,en15.0)", 1.0,        4_"         1.E+00")
+    call checkfmt("(rn,en15.0)", 1.00000012, 4_"         1.E+00")
+    call checkfmt("(rn,en15.0)", 0.99999994, 4_"         1.E+00")
+    call checkfmt("(rn,en15.0)", 10.0,       4_"        10.E+00")
+    call checkfmt("(rn,en15.0)", 10.0000010, 4_"        10.E+00")
+    call checkfmt("(rn,en15.0)", 9.99999905, 4_"        10.E+00")
+    call checkfmt("(rn,en15.0)", 100.0,      4_"       100.E+00")
+    call checkfmt("(rn,en15.0)", 100.000008, 4_"       100.E+00")
+    call checkfmt("(rn,en15.0)", 99.9999924, 4_"       100.E+00")
+    call checkfmt("(rn,en15.0)", 1000.0,     4_"         1.E+03")
+    call checkfmt("(rn,en15.0)", 1000.00006, 4_"         1.E+03")
+    call checkfmt("(rn,en15.0)", 999.999939, 4_"         1.E+03")
+    call checkfmt("(rn,en15.0)", 9.5,        4_"        10.E+00")
+    call checkfmt("(rn,en15.0)", 9.50000095, 4_"        10.E+00")
+    call checkfmt("(rn,en15.0)", 9.49999905, 4_"         9.E+00")
+    call checkfmt("(rn,en15.0)", 99.5,       4_"       100.E+00")
+    call checkfmt("(rn,en15.0)", 99.5000076, 4_"       100.E+00")
+    call checkfmt("(rn,en15.0)", 99.4999924, 4_"        99.E+00")
+    call checkfmt("(rn,en15.0)", 999.5,      4_"         1.E+03")
+    call checkfmt("(rn,en15.0)", 999.500061, 4_"         1.E+03")
+    call checkfmt("(rn,en15.0)", 999.499939, 4_"       999.E+00")
+    call checkfmt("(rn,en15.0)", 9500.0,     4_"        10.E+03")
+    call checkfmt("(rn,en15.0)", 9500.00098, 4_"        10.E+03")
+    call checkfmt("(rn,en15.0)", 9499.99902, 4_"         9.E+03")
+    call checkfmt("(rn,en15.1)", 9950.0,     4_"       10.0E+03")
+    call checkfmt("(rn,en15.2)", 9995.0,     4_"      10.00E+03")
+    call checkfmt("(rn,en15.3)", 9999.5,     4_"     10.000E+03")
+    call checkfmt("(rn,en15.1)", 9.5,        4_"        9.5E+00")
+    call checkfmt("(rn,en15.1)", 9.50000095, 4_"        9.5E+00")
+    call checkfmt("(rn,en15.1)", 9.49999905, 4_"        9.5E+00")
+    call checkfmt("(rn,en15.1)", 0.099951,   4_"      100.0E-03")
+    call checkfmt("(rn,en15.1)", 0.009951,   4_"       10.0E-03")
+    call checkfmt("(rn,en15.1)", 0.000999951,4_"        1.0E-03")
+
+    call checkfmt("(rn,en15.0)", -1.0,        4_"        -1.E+00")
+    call checkfmt("(rn,en15.0)", -1.00000012, 4_"        -1.E+00")
+    call checkfmt("(rn,en15.0)", -0.99999994, 4_"        -1.E+00")
+    call checkfmt("(rn,en15.0)", -10.0,       4_"       -10.E+00")
+    call checkfmt("(rn,en15.0)", -10.0000010, 4_"       -10.E+00")
+    call checkfmt("(rn,en15.0)", -9.99999905, 4_"       -10.E+00")
+    call checkfmt("(rn,en15.0)", -100.0,      4_"      -100.E+00")
+    call checkfmt("(rn,en15.0)", -100.000008, 4_"      -100.E+00")
+    call checkfmt("(rn,en15.0)", -99.9999924, 4_"      -100.E+00")
+    call checkfmt("(rn,en15.0)", -1000.0,     4_"        -1.E+03")
+    call checkfmt("(rn,en15.0)", -1000.00006, 4_"        -1.E+03")
+    call checkfmt("(rn,en15.0)", -999.999939, 4_"        -1.E+03")
+    call checkfmt("(rn,en15.0)", -9.5,        4_"       -10.E+00")
+    call checkfmt("(rn,en15.0)", -9.50000095, 4_"       -10.E+00")
+    call checkfmt("(rn,en15.0)", -9.49999905, 4_"        -9.E+00")
+    call checkfmt("(rn,en15.0)", -99.5,       4_"      -100.E+00")
+    call checkfmt("(rn,en15.0)", -99.5000076, 4_"      -100.E+00")
+    call checkfmt("(rn,en15.0)", -99.4999924, 4_"       -99.E+00")
+    call checkfmt("(rn,en15.0)", -999.5,      4_"        -1.E+03")
+    call checkfmt("(rn,en15.0)", -999.500061, 4_"        -1.E+03")
+    call checkfmt("(rn,en15.0)", -999.499939, 4_"      -999.E+00")
+    call checkfmt("(rn,en15.0)", -9500.0,     4_"       -10.E+03")
+    call checkfmt("(rn,en15.0)", -9500.00098, 4_"       -10.E+03")
+    call checkfmt("(rn,en15.0)", -9499.99902, 4_"        -9.E+03")
+    call checkfmt("(rn,en15.1)", -9950.0,     4_"      -10.0E+03")
+    call checkfmt("(rn,en15.2)", -9995.0,     4_"     -10.00E+03")
+    call checkfmt("(rn,en15.3)", -9999.5,     4_"    -10.000E+03")
+    call checkfmt("(rn,en15.1)", -9.5,        4_"       -9.5E+00")
+    call checkfmt("(rn,en15.1)", -9.50000095, 4_"       -9.5E+00")
+    call checkfmt("(rn,en15.1)", -9.49999905, 4_"       -9.5E+00")
+    call checkfmt("(rn,en15.1)", -0.099951,   4_"     -100.0E-03")
+    call checkfmt("(rn,en15.1)", -0.009951,   4_"      -10.0E-03")
+    call checkfmt("(rn,en15.1)", -0.000999951,4_"       -1.0E-03")
+
+    call checkfmt("(rn,en15.1)", 987350.,     4_"      987.4E+03")
+    call checkfmt("(rn,en15.2)", 98735.,      4_"      98.74E+03")
+    call checkfmt("(rn,en15.3)", 9873.5,      4_"      9.874E+03")
+    call checkfmt("(rn,en15.1)", 987650.,     4_"      987.6E+03")
+    call checkfmt("(rn,en15.2)", 98765.,      4_"      98.76E+03")
+    call checkfmt("(rn,en15.3)", 9876.5,      4_"      9.876E+03")
+    call checkfmt("(rn,en15.1)", 3.125E-02,   4_"       31.2E-03")
+    call checkfmt("(rn,en15.1)", 9.375E-02,   4_"       93.8E-03")
+    call checkfmt("(rn,en15.2)", 1.5625E-02,  4_"      15.62E-03")
+    call checkfmt("(rn,en15.2)", 4.6875E-02,  4_"      46.88E-03")
+    call checkfmt("(rn,en15.3)", 7.8125E-03,  4_"      7.812E-03")
+    call checkfmt("(rn,en15.3)", 2.34375E-02, 4_"     23.438E-03")
+    call checkfmt("(rn,en15.3)", 9.765625E-04,4_"    976.562E-06")
+    call checkfmt("(rn,en15.6)", 2.9296875E-03,4_"   2.929688E-03")
+
+    call checkfmt("(rn,en15.1)", -987350.,     4_"     -987.4E+03")
+    call checkfmt("(rn,en15.2)", -98735.,      4_"     -98.74E+03")
+    call checkfmt("(rn,en15.3)", -9873.5,      4_"     -9.874E+03")
+    call checkfmt("(rn,en15.1)", -987650.,     4_"     -987.6E+03")
+    call checkfmt("(rn,en15.2)", -98765.,      4_"     -98.76E+03")
+    call checkfmt("(rn,en15.3)", -9876.5,      4_"     -9.876E+03")
+    call checkfmt("(rn,en15.1)", -3.125E-02,   4_"      -31.2E-03")
+    call checkfmt("(rn,en15.1)", -9.375E-02,   4_"      -93.8E-03")
+    call checkfmt("(rn,en15.2)", -1.5625E-02,  4_"     -15.62E-03")
+    call checkfmt("(rn,en15.2)", -4.6875E-02,  4_"     -46.88E-03")
+    call checkfmt("(rn,en15.3)", -7.8125E-03,  4_"     -7.812E-03")
+    call checkfmt("(rn,en15.3)", -2.34375E-02, 4_"    -23.438E-03")
+    call checkfmt("(rn,en15.3)", -9.765625E-04,4_"   -976.562E-06")
+    call checkfmt("(rn,en15.6)", -2.9296875E-03,4_"  -2.929688E-03")
+
+    print *, n_tst, n_cnt, n_skip
+    if (n_cnt /= 0) stop n_cnt
+    if (all(.not. l_skip)) print *, "All kinds rounded to nearest"
+
+contains
+    subroutine checkfmt(fmt, x, cmp)
+        implicit none
+        integer :: i
+        character(len=*), intent(in) :: fmt
+        real, intent(in) :: x
+        character(len=*, kind=4), intent(in) :: cmp
+        do i=1,size(real_kinds)
+          if (l_skip(i)) cycle
+          if (i == 1) then
+            write(s, fmt) real(x,kind=j(1))
+          else if (i == 2) then
+            write(s, fmt) real(x,kind=j(2))
+          else if (i == 3) then
+            write(s, fmt) real(x,kind=j(3))
+          else if (i == 4) then
+            write(s, fmt) real(x,kind=j(4))
+          end if
+          n_tst = n_tst + 1
+          if (s /= cmp) then
+            if (l_skip(i)) then
+              n_skip = n_skip + 1
+            else
+              print "(a,1x,a,' expected: ',1x,a)", fmt, s, cmp
+              n_cnt = n_cnt + 1
+            end if
+          end if
+        end do
+        
+    end subroutine
+end program
+! { dg-output "All kinds rounded to nearest" { xfail { i?86-*-solaris2.9* hppa*-*-hpux* } } }
+! { dg-final { cleanup-saved-temps } }
diff --git a/gcc/testsuite/gfortran.dg/fmt_en_ru.f90 b/gcc/testsuite/gfortran.dg/fmt_en_ru.f90
new file mode 100644
index 00000000000..7834e2880bd
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/fmt_en_ru.f90
@@ -0,0 +1,185 @@
+! { dg-do run }
+! PR60128 Invalid outputs with EN descriptors
+! Test case provided by Walt Brainerd.
+program pr60128
+use ISO_FORTRAN_ENV
+    implicit none
+    integer, parameter :: j(size(real_kinds)+4)=[REAL_KINDS, [4, 4, 4, 4]]
+    logical :: l_skip(4) = .false.
+    integer :: i
+    integer :: n_tst = 0, n_cnt = 0, n_skip = 0
+    character(len=20,kind=4) :: s, s1
+
+!   Check that the default rounding mode is to nearest and to even on tie.
+    do i=1,size(real_kinds)
+      if (i == 1) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(1)), &
+                                  real(9.49999905,kind=j(1)),  &
+                                  real(9.5,kind=j(1)), real(8.5,kind=j(1))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(1)), &
+                                       real(98765.0,kind=j(1))
+      else if (i == 2) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(2)), &
+                                  real(9.49999905,kind=j(2)),  &
+                                  real(9.5,kind=j(2)), real(8.5,kind=j(2))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(2)), &
+                                       real(98765.0,kind=j(2))
+      else if (i == 3) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(3)), &
+                                  real(9.49999905,kind=j(3)),  &
+                                  real(9.5,kind=j(3)), real(8.5,kind=j(3))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(3)), &
+                                       real(98765.0,kind=j(3))
+      else if (i == 4) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(4)), &
+                                  real(9.49999905,kind=j(4)),  &
+                                  real(9.5,kind=j(4)), real(8.5,kind=j(4))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(4)), &
+                                       real(98765.0,kind=j(4))
+      end if
+      if (s /= 4_'-9.5 9.5 10.  8.' .or. s1 /= 4_' 987.4E+03 98.76E+03') then
+        l_skip(i) = .true.
+        print "('Unsupported rounding for real(',i0,')')", j(i)
+      end if
+    end do
+        
+
+! Original test.
+    call checkfmt("(en15.2)", -.44444,    4_"    -444.44E-03")
+
+! Test for the bug in comment 6.
+    call checkfmt("(ru,en15.0)", 1.0,        4_"         1.E+00")
+    call checkfmt("(ru,en15.0)", 1.00000012, 4_"         2.E+00")
+    call checkfmt("(ru,en15.0)", 0.99999994, 4_"         1.E+00")
+    call checkfmt("(ru,en15.0)", 10.0,       4_"        10.E+00")
+    call checkfmt("(ru,en15.0)", 10.0000010, 4_"        11.E+00")
+    call checkfmt("(ru,en15.0)", 9.99999905, 4_"        10.E+00")
+    call checkfmt("(ru,en15.0)", 100.0,      4_"       100.E+00")
+    call checkfmt("(ru,en15.0)", 100.000008, 4_"       101.E+00")
+    call checkfmt("(ru,en15.0)", 99.9999924, 4_"       100.E+00")
+    call checkfmt("(ru,en15.0)", 1000.0,     4_"         1.E+03")
+    call checkfmt("(ru,en15.0)", 1000.00006, 4_"         2.E+03")
+    call checkfmt("(ru,en15.0)", 999.999939, 4_"         1.E+03")
+    call checkfmt("(ru,en15.0)", 9.5,        4_"        10.E+00")
+    call checkfmt("(ru,en15.0)", 9.50000095, 4_"        10.E+00")
+    call checkfmt("(ru,en15.0)", 9.49999905, 4_"        10.E+00")
+    call checkfmt("(ru,en15.0)", 99.5,       4_"       100.E+00")
+    call checkfmt("(ru,en15.0)", 99.5000076, 4_"       100.E+00")
+    call checkfmt("(ru,en15.0)", 99.4999924, 4_"       100.E+00")
+    call checkfmt("(ru,en15.0)", 999.5,      4_"         1.E+03")
+    call checkfmt("(ru,en15.0)", 999.500061, 4_"         1.E+03")
+    call checkfmt("(ru,en15.0)", 999.499939, 4_"         1.E+03")
+    call checkfmt("(ru,en15.0)", 9500.0,     4_"        10.E+03")
+    call checkfmt("(ru,en15.0)", 9500.00098, 4_"        10.E+03")
+    call checkfmt("(ru,en15.0)", 9499.99902, 4_"        10.E+03")
+    call checkfmt("(ru,en15.1)", 9950.0,     4_"       10.0E+03")
+    call checkfmt("(ru,en15.2)", 9995.0,     4_"      10.00E+03")
+    call checkfmt("(ru,en15.3)", 9999.5,     4_"     10.000E+03")
+    call checkfmt("(ru,en15.1)", 9.5,        4_"        9.5E+00")
+    call checkfmt("(ru,en15.1)", 9.50000095, 4_"        9.6E+00")
+    call checkfmt("(ru,en15.1)", 9.49999905, 4_"        9.5E+00")
+    call checkfmt("(ru,en15.1)", 0.099951,   4_"      100.0E-03")
+    call checkfmt("(ru,en15.1)", 0.009951,   4_"       10.0E-03")
+    call checkfmt("(ru,en15.1)", 0.000999951,4_"        1.0E-03")
+
+    call checkfmt("(ru,en15.0)", -1.0,        4_"        -1.E+00")
+    call checkfmt("(ru,en15.0)", -1.00000012, 4_"        -1.E+00")
+    call checkfmt("(ru,en15.0)", -0.99999994, 4_"      -999.E-03")
+    call checkfmt("(ru,en15.0)", -10.0,       4_"       -10.E+00")
+    call checkfmt("(ru,en15.0)", -10.0000010, 4_"       -10.E+00")
+    call checkfmt("(ru,en15.0)", -9.99999905, 4_"        -9.E+00")
+    call checkfmt("(ru,en15.0)", -100.0,      4_"      -100.E+00")
+    call checkfmt("(ru,en15.0)", -100.000008, 4_"      -100.E+00")
+    call checkfmt("(ru,en15.0)", -99.9999924, 4_"       -99.E+00")
+    call checkfmt("(ru,en15.0)", -1000.0,     4_"        -1.E+03")
+    call checkfmt("(ru,en15.0)", -1000.00006, 4_"        -1.E+03")
+    call checkfmt("(ru,en15.0)", -999.999939, 4_"      -999.E+00")
+    call checkfmt("(ru,en15.0)", -9.5,        4_"        -9.E+00")
+    call checkfmt("(ru,en15.0)", -9.50000095, 4_"        -9.E+00")
+    call checkfmt("(ru,en15.0)", -9.49999905, 4_"        -9.E+00")
+    call checkfmt("(ru,en15.0)", -99.5,       4_"       -99.E+00")
+    call checkfmt("(ru,en15.0)", -99.5000076, 4_"       -99.E+00")
+    call checkfmt("(ru,en15.0)", -99.4999924, 4_"       -99.E+00")
+    call checkfmt("(ru,en15.0)", -999.5,      4_"      -999.E+00")
+    call checkfmt("(ru,en15.0)", -999.500061, 4_"      -999.E+00")
+    call checkfmt("(ru,en15.0)", -999.499939, 4_"      -999.E+00")
+    call checkfmt("(ru,en15.0)", -9500.0,     4_"        -9.E+03")
+    call checkfmt("(ru,en15.0)", -9500.00098, 4_"        -9.E+03")
+    call checkfmt("(ru,en15.0)", -9499.99902, 4_"        -9.E+03")
+    call checkfmt("(ru,en15.1)", -9950.0,     4_"       -9.9E+03")
+    call checkfmt("(ru,en15.2)", -9995.0,     4_"      -9.99E+03")
+    call checkfmt("(ru,en15.3)", -9999.5,     4_"     -9.999E+03")
+    call checkfmt("(ru,en15.1)", -9.5,        4_"       -9.5E+00")
+    call checkfmt("(ru,en15.1)", -9.50000095, 4_"       -9.5E+00")
+    call checkfmt("(ru,en15.1)", -9.49999905, 4_"       -9.4E+00")
+    call checkfmt("(ru,en15.1)", -0.099951,   4_"      -99.9E-03")
+    call checkfmt("(ru,en15.1)", -0.009951,   4_"       -9.9E-03")
+    call checkfmt("(ru,en15.1)", -0.000999951,4_"     -999.9E-06")
+
+    call checkfmt("(ru,en15.1)", 987350.,     4_"      987.4E+03")
+    call checkfmt("(ru,en15.2)", 98735.,      4_"      98.74E+03")
+    call checkfmt("(ru,en15.3)", 9873.5,      4_"      9.874E+03")
+    call checkfmt("(ru,en15.1)", 987650.,     4_"      987.7E+03")
+    call checkfmt("(ru,en15.2)", 98765.,      4_"      98.77E+03")
+    call checkfmt("(ru,en15.3)", 9876.5,      4_"      9.877E+03")
+    call checkfmt("(ru,en15.1)", 3.125E-02,   4_"       31.3E-03")
+    call checkfmt("(ru,en15.1)", 9.375E-02,   4_"       93.8E-03")
+    call checkfmt("(ru,en15.2)", 1.5625E-02,  4_"      15.63E-03")
+    call checkfmt("(ru,en15.2)", 4.6875E-02,  4_"      46.88E-03")
+    call checkfmt("(ru,en15.3)", 7.8125E-03,  4_"      7.813E-03")
+    call checkfmt("(ru,en15.3)", 2.34375E-02, 4_"     23.438E-03")
+    call checkfmt("(ru,en15.3)", 9.765625E-04,4_"    976.563E-06")
+    call checkfmt("(ru,en15.6)", 2.9296875E-03,4_"   2.929688E-03")
+
+    call checkfmt("(ru,en15.1)", -987350.,     4_"     -987.3E+03")
+    call checkfmt("(ru,en15.2)", -98735.,      4_"     -98.73E+03")
+    call checkfmt("(ru,en15.3)", -9873.5,      4_"     -9.873E+03")
+    call checkfmt("(ru,en15.1)", -987650.,     4_"     -987.6E+03")
+    call checkfmt("(ru,en15.2)", -98765.,      4_"     -98.76E+03")
+    call checkfmt("(ru,en15.3)", -9876.5,      4_"     -9.876E+03")
+    call checkfmt("(ru,en15.1)", -3.125E-02,   4_"      -31.2E-03")
+    call checkfmt("(ru,en15.1)", -9.375E-02,   4_"      -93.7E-03")
+    call checkfmt("(ru,en15.2)", -1.5625E-02,  4_"     -15.62E-03")
+    call checkfmt("(ru,en15.2)", -4.6875E-02,  4_"     -46.87E-03")
+    call checkfmt("(ru,en15.3)", -7.8125E-03,  4_"     -7.812E-03")
+    call checkfmt("(ru,en15.3)", -2.34375E-02, 4_"    -23.437E-03")
+    call checkfmt("(ru,en15.3)", -9.765625E-04,4_"   -976.562E-06")
+    call checkfmt("(ru,en15.6)", -2.9296875E-03,4_"  -2.929687E-03")
+
+    print *, n_tst, n_cnt, n_skip
+    if (n_cnt /= 0) stop n_cnt
+    if (all(.not. l_skip)) print *, "All kinds rounded up"
+
+contains
+    subroutine checkfmt(fmt, x, cmp)
+        implicit none
+        integer :: i
+        character(len=*), intent(in) :: fmt
+        real, intent(in) :: x
+        character(len=*, kind=4), intent(in) :: cmp
+        do i=1,size(real_kinds)
+          if (l_skip(i)) cycle
+          if (i == 1) then
+            write(s, fmt) real(x,kind=j(1))
+          else if (i == 2) then
+            write(s, fmt) real(x,kind=j(2))
+          else if (i == 3) then
+            write(s, fmt) real(x,kind=j(3))
+          else if (i == 4) then
+            write(s, fmt) real(x,kind=j(4))
+          end if
+          n_tst = n_tst + 1
+          if (s /= cmp) then
+            if (l_skip(i)) then
+              n_skip = n_skip + 1
+            else
+              print "(a,1x,a,' expected: ',1x,a)", fmt, s, cmp
+              n_cnt = n_cnt + 1
+            end if
+          end if
+        end do
+        
+    end subroutine
+end program
+! { dg-output "All kinds rounded up" { xfail { i?86-*-solaris2.9* hppa*-*-hpux* } } }
+! { dg-final { cleanup-saved-temps } }
diff --git a/gcc/testsuite/gfortran.dg/fmt_en_rz.f90 b/gcc/testsuite/gfortran.dg/fmt_en_rz.f90
new file mode 100644
index 00000000000..c07847cad6d
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/fmt_en_rz.f90
@@ -0,0 +1,185 @@
+! { dg-do run }
+! PR60128 Invalid outputs with EN descriptors
+! Test case provided by Walt Brainerd.
+program pr60128
+use ISO_FORTRAN_ENV
+    implicit none
+    integer, parameter :: j(size(real_kinds)+4)=[REAL_KINDS, [4, 4, 4, 4]]
+    logical :: l_skip(4) = .false.
+    integer :: i
+    integer :: n_tst = 0, n_cnt = 0, n_skip = 0
+    character(len=20,kind=4) :: s, s1
+
+!   Check that the default rounding mode is to nearest and to even on tie.
+    do i=1,size(real_kinds)
+      if (i == 1) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(1)), &
+                                  real(9.49999905,kind=j(1)),  &
+                                  real(9.5,kind=j(1)), real(8.5,kind=j(1))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(1)), &
+                                       real(98765.0,kind=j(1))
+      else if (i == 2) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(2)), &
+                                  real(9.49999905,kind=j(2)),  &
+                                  real(9.5,kind=j(2)), real(8.5,kind=j(2))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(2)), &
+                                       real(98765.0,kind=j(2))
+      else if (i == 3) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(3)), &
+                                  real(9.49999905,kind=j(3)),  &
+                                  real(9.5,kind=j(3)), real(8.5,kind=j(3))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(3)), &
+                                       real(98765.0,kind=j(3))
+      else if (i == 4) then
+        write(s, '(2F4.1,2F4.0)') real(-9.49999905,kind=j(4)), &
+                                  real(9.49999905,kind=j(4)),  &
+                                  real(9.5,kind=j(4)), real(8.5,kind=j(4))
+        write(s1, '(3PE10.3,2PE10.3)') real(987350.,kind=j(4)), &
+                                       real(98765.0,kind=j(4))
+      end if
+      if (s /= 4_'-9.5 9.5 10.  8.' .or. s1 /= 4_' 987.4E+03 98.76E+03') then
+        l_skip(i) = .true.
+        print "('Unsupported rounding for real(',i0,')')", j(i)
+      end if
+    end do
+        
+
+! Original test.
+    call checkfmt("(en15.2)", -.44444,    4_"    -444.44E-03")
+
+! Test for the bug in comment 6.
+    call checkfmt("(rz,en15.0)", 1.0,        4_"         1.E+00")
+    call checkfmt("(rz,en15.0)", 1.00000012, 4_"         1.E+00")
+    call checkfmt("(rz,en15.0)", 0.99999994, 4_"       999.E-03")
+    call checkfmt("(rz,en15.0)", 10.0,       4_"        10.E+00")
+    call checkfmt("(rz,en15.0)", 10.0000010, 4_"        10.E+00")
+    call checkfmt("(rz,en15.0)", 9.99999905, 4_"         9.E+00")
+    call checkfmt("(rz,en15.0)", 100.0,      4_"       100.E+00")
+    call checkfmt("(rz,en15.0)", 100.000008, 4_"       100.E+00")
+    call checkfmt("(rz,en15.0)", 99.9999924, 4_"        99.E+00")
+    call checkfmt("(rz,en15.0)", 1000.0,     4_"         1.E+03")
+    call checkfmt("(rz,en15.0)", 1000.00006, 4_"         1.E+03")
+    call checkfmt("(rz,en15.0)", 999.999939, 4_"       999.E+00")
+    call checkfmt("(rz,en15.0)", 9.5,        4_"         9.E+00")
+    call checkfmt("(rz,en15.0)", 9.50000095, 4_"         9.E+00")
+    call checkfmt("(rz,en15.0)", 9.49999905, 4_"         9.E+00")
+    call checkfmt("(rz,en15.0)", 99.5,       4_"        99.E+00")
+    call checkfmt("(rz,en15.0)", 99.5000076, 4_"        99.E+00")
+    call checkfmt("(rz,en15.0)", 99.4999924, 4_"        99.E+00")
+    call checkfmt("(rz,en15.0)", 999.5,      4_"       999.E+00")
+    call checkfmt("(rz,en15.0)", 999.500061, 4_"       999.E+00")
+    call checkfmt("(rz,en15.0)", 999.499939, 4_"       999.E+00")
+    call checkfmt("(rz,en15.0)", 9500.0,     4_"         9.E+03")
+    call checkfmt("(rz,en15.0)", 9500.00098, 4_"         9.E+03")
+    call checkfmt("(rz,en15.0)", 9499.99902, 4_"         9.E+03")
+    call checkfmt("(rz,en15.1)", 9950.0,     4_"        9.9E+03")
+    call checkfmt("(rz,en15.2)", 9995.0,     4_"       9.99E+03")
+    call checkfmt("(rz,en15.3)", 9999.5,     4_"      9.999E+03")
+    call checkfmt("(rz,en15.1)", 9.5,        4_"        9.5E+00")
+    call checkfmt("(rz,en15.1)", 9.50000095, 4_"        9.5E+00")
+    call checkfmt("(rz,en15.1)", 9.49999905, 4_"        9.4E+00")
+    call checkfmt("(rz,en15.1)", 0.099951,   4_"       99.9E-03")
+    call checkfmt("(rz,en15.1)", 0.009951,   4_"        9.9E-03")
+    call checkfmt("(rz,en15.1)", 0.000999951,4_"      999.9E-06")
+
+    call checkfmt("(rz,en15.0)", -1.0,        4_"        -1.E+00")
+    call checkfmt("(rz,en15.0)", -1.00000012, 4_"        -1.E+00")
+    call checkfmt("(rz,en15.0)", -0.99999994, 4_"      -999.E-03")
+    call checkfmt("(rz,en15.0)", -10.0,       4_"       -10.E+00")
+    call checkfmt("(rz,en15.0)", -10.0000010, 4_"       -10.E+00")
+    call checkfmt("(rz,en15.0)", -9.99999905, 4_"        -9.E+00")
+    call checkfmt("(rz,en15.0)", -100.0,      4_"      -100.E+00")
+    call checkfmt("(rz,en15.0)", -100.000008, 4_"      -100.E+00")
+    call checkfmt("(rz,en15.0)", -99.9999924, 4_"       -99.E+00")
+    call checkfmt("(rz,en15.0)", -1000.0,     4_"        -1.E+03")
+    call checkfmt("(rz,en15.0)", -1000.00006, 4_"        -1.E+03")
+    call checkfmt("(rz,en15.0)", -999.999939, 4_"      -999.E+00")
+    call checkfmt("(rz,en15.0)", -9.5,        4_"        -9.E+00")
+    call checkfmt("(rz,en15.0)", -9.50000095, 4_"        -9.E+00")
+    call checkfmt("(rz,en15.0)", -9.49999905, 4_"        -9.E+00")
+    call checkfmt("(rz,en15.0)", -99.5,       4_"       -99.E+00")
+    call checkfmt("(rz,en15.0)", -99.5000076, 4_"       -99.E+00")
+    call checkfmt("(rz,en15.0)", -99.4999924, 4_"       -99.E+00")
+    call checkfmt("(rz,en15.0)", -999.5,      4_"      -999.E+00")
+    call checkfmt("(rz,en15.0)", -999.500061, 4_"      -999.E+00")
+    call checkfmt("(rz,en15.0)", -999.499939, 4_"      -999.E+00")
+    call checkfmt("(rz,en15.0)", -9500.0,     4_"        -9.E+03")
+    call checkfmt("(rz,en15.0)", -9500.00098, 4_"        -9.E+03")
+    call checkfmt("(rz,en15.0)", -9499.99902, 4_"        -9.E+03")
+    call checkfmt("(rz,en15.1)", -9950.0,     4_"       -9.9E+03")
+    call checkfmt("(rz,en15.2)", -9995.0,     4_"      -9.99E+03")
+    call checkfmt("(rz,en15.3)", -9999.5,     4_"     -9.999E+03")
+    call checkfmt("(rz,en15.1)", -9.5,        4_"       -9.5E+00")
+    call checkfmt("(rz,en15.1)", -9.50000095, 4_"       -9.5E+00")
+    call checkfmt("(rz,en15.1)", -9.49999905, 4_"       -9.4E+00")
+    call checkfmt("(rz,en15.1)", -0.099951,   4_"      -99.9E-03")
+    call checkfmt("(rz,en15.1)", -0.009951,   4_"       -9.9E-03")
+    call checkfmt("(rz,en15.1)", -0.000999951,4_"     -999.9E-06")
+
+    call checkfmt("(rz,en15.1)", 987350.,     4_"      987.3E+03")
+    call checkfmt("(rz,en15.2)", 98735.,      4_"      98.73E+03")
+    call checkfmt("(rz,en15.3)", 9873.5,      4_"      9.873E+03")
+    call checkfmt("(rz,en15.1)", 987650.,     4_"      987.6E+03")
+    call checkfmt("(rz,en15.2)", 98765.,      4_"      98.76E+03")
+    call checkfmt("(rz,en15.3)", 9876.5,      4_"      9.876E+03")
+    call checkfmt("(rz,en15.1)", 3.125E-02,   4_"       31.2E-03")
+    call checkfmt("(rz,en15.1)", 9.375E-02,   4_"       93.7E-03")
+    call checkfmt("(rz,en15.2)", 1.5625E-02,  4_"      15.62E-03")
+    call checkfmt("(rz,en15.2)", 4.6875E-02,  4_"      46.87E-03")
+    call checkfmt("(rz,en15.3)", 7.8125E-03,  4_"      7.812E-03")
+    call checkfmt("(rz,en15.3)", 2.34375E-02, 4_"     23.437E-03")
+    call checkfmt("(rz,en15.3)", 9.765625E-04,4_"    976.562E-06")
+    call checkfmt("(rz,en15.6)", 2.9296875E-03,4_"   2.929687E-03")
+
+    call checkfmt("(rz,en15.1)", -987350.,     4_"     -987.3E+03")
+    call checkfmt("(rz,en15.2)", -98735.,      4_"     -98.73E+03")
+    call checkfmt("(rz,en15.3)", -9873.5,      4_"     -9.873E+03")
+    call checkfmt("(rz,en15.1)", -987650.,     4_"     -987.6E+03")
+    call checkfmt("(rz,en15.2)", -98765.,      4_"     -98.76E+03")
+    call checkfmt("(rz,en15.3)", -9876.5,      4_"     -9.876E+03")
+    call checkfmt("(rz,en15.1)", -3.125E-02,   4_"      -31.2E-03")
+    call checkfmt("(rz,en15.1)", -9.375E-02,   4_"      -93.7E-03")
+    call checkfmt("(rz,en15.2)", -1.5625E-02,  4_"     -15.62E-03")
+    call checkfmt("(rz,en15.2)", -4.6875E-02,  4_"     -46.87E-03")
+    call checkfmt("(rz,en15.3)", -7.8125E-03,  4_"     -7.812E-03")
+    call checkfmt("(rz,en15.3)", -2.34375E-02, 4_"    -23.437E-03")
+    call checkfmt("(rz,en15.3)", -9.765625E-04,4_"   -976.562E-06")
+    call checkfmt("(rz,en15.6)", -2.9296875E-03,4_"  -2.929687E-03")
+
+    print *, n_tst, n_cnt, n_skip
+    if (n_cnt /= 0) stop n_cnt
+    if (all(.not. l_skip)) print *, "All kinds rounded to zero"
+
+contains
+    subroutine checkfmt(fmt, x, cmp)
+        implicit none
+        integer :: i
+        character(len=*), intent(in) :: fmt
+        real, intent(in) :: x
+        character(len=*, kind=4), intent(in) :: cmp
+        do i=1,size(real_kinds)
+          if (l_skip(i)) cycle
+          if (i == 1) then
+            write(s, fmt) real(x,kind=j(1))
+          else if (i == 2) then
+            write(s, fmt) real(x,kind=j(2))
+          else if (i == 3) then
+            write(s, fmt) real(x,kind=j(3))
+          else if (i == 4) then
+            write(s, fmt) real(x,kind=j(4))
+          end if
+          n_tst = n_tst + 1
+          if (s /= cmp) then
+            if (l_skip(i)) then
+              n_skip = n_skip + 1
+            else
+              print "(a,1x,a,' expected: ',1x,a)", fmt, s, cmp
+              n_cnt = n_cnt + 1
+            end if
+          end if
+        end do
+        
+    end subroutine
+end program
+! { dg-output "All kinds rounded to zero" { xfail { i?86-*-solaris2.9* hppa*-*-hpux* } } }
+! { dg-final { cleanup-saved-temps } }
diff --git a/libgfortran/io/write_float.def b/libgfortran/io/write_float.def
index a749f64b796..8b27b036ce5 100644
--- a/libgfortran/io/write_float.def
+++ b/libgfortran/io/write_float.def
@@ -389,7 +389,8 @@ build_float_string (st_parameter_dt *dtp, const fnode *f, char *buffer,
   updown:
 
   rchar = '0';
-  if (ft != FMT_F && w > 0 && d == 0 && p == 0)
+  /* Do not reset nbefore for FMT_F and FMT_EN.  */
+  if (ft != FMT_F && ft !=FMT_EN && w > 0 && d == 0 && p == 0)
     nbefore = 1;
   /* Scan for trailing zeros to see if we really need to round it.  */
   for(i = nbefore + nafter; i < ndigits; i++)

commit cec3ae95129ff7aceba415c8ec4ff5c668acc0f7
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Jul 26 00:17:28 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ca1a68b03b7..22878d584d2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200725
+20200726
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ca83f5c7a07..19b86837173 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2020-07-25  Dominique d'Humieres  <dhumieres.dominique@free.fr>
+
+	Backported from master:
+	2020-07-24  Dominique d'Humieres  <dhumieres.dominique@free.fr>
+
+	PR fortran/93592
+	* gfortran.dg/fmt_en.f90: Adjust test.
+	* gfortran.dg/fmt_en_rd.f90: New test.
+	* gfortran.dg/fmt_en_rn.f90: New test.
+	* gfortran.dg/fmt_en_ru.f90: New test.
+	* gfortran.dg/fmt_en_rz.f90: New test.
+
 2020-07-23  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:
diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog
index b4825c78c45..65a16d1525c 100644
--- a/libgfortran/ChangeLog
+++ b/libgfortran/ChangeLog
@@ -1,3 +1,12 @@
+2020-07-25  Dominique d'Humieres  <dhumieres.dominique@free.fr>
+
+	Backported from master:
+	2020-07-24  Dominique d'Humieres  <dhumieres.dominique@free.fr>
+
+	PR fortran/93592
+	* io/write_float.def (build_float_string): Do not reset
+	  nbefore for FMT_F and FMT_EN.
+
 2020-04-19  Uroš Bizjak  <ubizjak@gmail.com>
 
 	* config/fpu-387.h (local_feraiseexcept) [__SSE_MATH__]:

commit 3b3e52aff2feecaa607940e05ca69a5ddbd7dd60
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Jul 27 00:17:30 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 22878d584d2..244a45a8404 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200726
+20200727

commit 1c2494fcf24f1cec0535b054f5a76fcd80f9afdb
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jul 28 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 244a45a8404..75ec474bf8f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200727
+20200728

commit 34dc998ce9d963545a9d6cfaa9590cc8818e8463
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jul 29 00:17:33 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 75ec474bf8f..273bf0e001a 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200728
+20200729

commit e89b5340c0696209f5802cebdcdc106557d342a7
Author: Martin Liska <mliska@suse.cz>
Date:   Wed Jul 29 14:13:42 2020 +0200

    gcc-changelog: fix combining of arguments.
    
    contrib/ChangeLog:
    
    2020-07-29  Martin Liska  <mliska@suse.cz>
    
            * git-backport.py: fix how are ChangeLog paths combined.

diff --git a/contrib/git-backport.py b/contrib/git-backport.py
index 3a9413dcd27..2b8e4686719 100755
--- a/contrib/git-backport.py
+++ b/contrib/git-backport.py
@@ -46,7 +46,7 @@ if __name__ == '__main__':
         conflicts = out.strip().split('\n')
         changelogs = [c for c in conflicts if c.endswith('ChangeLog')]
         if changelogs:
-            cmd = 'git checkout --theirs %s' % '\n'.join(changelogs)
+            cmd = 'git checkout --theirs %s' % ' '.join(changelogs)
             subprocess.check_output(cmd, shell=True)
         # 2) remove all ChangeLog files from index
         cmd = 'git diff --name-only --diff-filter=M HEAD'

commit 4c482062f1cf1febd7571b7fd77516d9c4f38081
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Jul 30 00:17:33 2020 +0000

    Daily bump.

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index d53c71e206b..af24fca9886 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,7 @@
+2020-07-29  Martin Liska  <mliska@suse.cz>
+
+	* git-backport.py: fix how are ChangeLog paths combined.
+
 2020-07-23  Martin Liska  <mliska@suse.cz>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 273bf0e001a..35e844018cf 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200729
+20200730

commit da01a92da503c123b532051cb34ba040a76dceff
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Jul 31 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 35e844018cf..675c0b9e6b0 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200730
+20200731

commit b3f17f1bdd96bfc8a69f230685f8b855a27f8f6b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Aug 1 00:17:37 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 675c0b9e6b0..b4bc243c22b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200731
+20200801

commit 1719d142419274e560c6832dd5aca4c9b1c44c63
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Aug 2 00:17:33 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b4bc243c22b..6eab4709860 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200801
+20200802

commit 165277b9695dc24069ac230c95afe929cf57ef98
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Aug 3 00:17:30 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6eab4709860..72167a445ca 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200802
+20200803

commit 5eda65b5c509d694d5741845d570f39d1e8083b8
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Mon Aug 3 21:16:50 2020 +0100

    cpp: Do not use @dots for ... tokens in code examples
    
    This prevents a ... token in code examples from being turned into a
    single HORIZONTAL ELLIPSIS glyph (e.g. via the HTML &hellip; entity).
    
    gcc/ChangeLog:
    
            * doc/cpp.texi (Variadic Macros): Use the exact ... token in
            code examples.
    
    (cherry picked from commit 2ac7fe2769890fe4c146da9cfa6d0eabb185d7db)

diff --git a/gcc/doc/cpp.texi b/gcc/doc/cpp.texi
index 4297c0ca9ce..6c6ab06b407 100644
--- a/gcc/doc/cpp.texi
+++ b/gcc/doc/cpp.texi
@@ -1632,7 +1632,7 @@ a function can.  The syntax for defining the macro is similar to that of
 a function.  Here is an example:
 
 @smallexample
-#define eprintf(@dots{}) fprintf (stderr, __VA_ARGS__)
+#define eprintf(...) fprintf (stderr, __VA_ARGS__)
 @end smallexample
 
 This kind of macro is called @dfn{variadic}.  When the macro is invoked,
@@ -1656,11 +1656,11 @@ below for an important special case for @samp{##}.)
 If your macro is complicated, you may want a more descriptive name for
 the variable argument than @code{@w{__VA_ARGS__}}.  CPP permits
 this, as an extension.  You may write an argument name immediately
-before the @samp{@dots{}}; that name is used for the variable argument.
+before the @samp{...}; that name is used for the variable argument.
 The @code{eprintf} macro above could be written
 
 @smallexample
-#define eprintf(args@dots{}) fprintf (stderr, args)
+#define eprintf(args...) fprintf (stderr, args)
 @end smallexample
 
 @noindent
@@ -1671,7 +1671,7 @@ You can have named arguments as well as variable arguments in a variadic
 macro.  We could define @code{eprintf} like this, instead:
 
 @smallexample
-#define eprintf(format, @dots{}) fprintf (stderr, format, __VA_ARGS__)
+#define eprintf(format, ...) fprintf (stderr, format, __VA_ARGS__)
 @end smallexample
 
 @noindent
@@ -1710,7 +1710,7 @@ invocation expands to its argument; but if the variable argument does
 not have any tokens, the @code{@w{__VA_OPT__}} expands to nothing:
 
 @smallexample
-#define eprintf(format, @dots{}) \
+#define eprintf(format, ...) \
   fprintf (stderr, format __VA_OPT__(,) __VA_ARGS__)
 @end smallexample
 
@@ -1723,7 +1723,7 @@ the introduction of @code{@w{__VA_OPT__}}, this extension remains
 supported in GNU CPP, for backward compatibility.  If you write
 
 @smallexample
-#define eprintf(format, @dots{}) fprintf (stderr, format, ##__VA_ARGS__)
+#define eprintf(format, ...) fprintf (stderr, format, ##__VA_ARGS__)
 @end smallexample
 
 @noindent
@@ -1759,7 +1759,7 @@ replacement list of a variadic macro.
 Variadic macros became a standard part of the C language with C99.  
 GNU CPP previously supported them
 with a named variable argument
-(@samp{args@dots{}}, not @samp{@dots{}} and @code{@w{__VA_ARGS__}}), which
+(@samp{args...}, not @samp{...} and @code{@w{__VA_ARGS__}}), which
 is still supported for backward compatibility.
 
 @node Predefined Macros

commit 1d317f4315ef3983fad37427887581761e3491c2
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Aug 4 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2f8b2d6361e..3467348f814 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-08-03  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-08-03  Jonathan Wakely  <jwakely@redhat.com>
+
+	* doc/cpp.texi (Variadic Macros): Use the exact ... token in
+	code examples.
+
 2020-07-17  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	PR target/95952
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 72167a445ca..f01da8770ae 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200803
+20200804

commit c96fe73b73583b8fe39898a1fae57166c3f559dc
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Aug 5 00:17:56 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f01da8770ae..3a7230a5cf2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200804
+20200805

commit 9801353c9d8651808880f3550de52edaae74c2f2
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Aug 6 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3a7230a5cf2..c2e265fc4e9 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200805
+20200806

commit 8b692f8b4c0e47bc8e11d9c3ab83049f68b2edbc
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Thu Aug 6 18:44:50 2020 +0100

    libstdc++: Fix unnecessary allocations in read_symlink [PR 96484]
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/96484
            * src/filesystem/ops.cc (fs::read_symlink): Return an error
            immediately for non-symlinks.
            * src/filesystem/std-ops.cc (fs::read_symlink): Likewise.
    
    (cherry picked from commit 6a13a4e3f29fc4ce5eff96d74ba965c9fdc02184)

diff --git a/libstdc++-v3/src/filesystem/ops.cc b/libstdc++-v3/src/filesystem/ops.cc
index f04b4c5fc17..4a14251cfe8 100644
--- a/libstdc++-v3/src/filesystem/ops.cc
+++ b/libstdc++-v3/src/filesystem/ops.cc
@@ -987,6 +987,12 @@ fs::path fs::read_symlink(const path& p, error_code& ec)
       ec.assign(errno, std::generic_category());
       return result;
     }
+  else if (!fs::is_symlink(make_file_status(st)))
+    {
+      ec.assign(EINVAL, std::generic_category());
+      return result;
+    }
+
   std::string buf(st.st_size ? st.st_size + 1 : 128, '\0');
   do
     {
diff --git a/libstdc++-v3/src/filesystem/std-ops.cc b/libstdc++-v3/src/filesystem/std-ops.cc
index 6d0bec48d44..8f3191c1a71 100644
--- a/libstdc++-v3/src/filesystem/std-ops.cc
+++ b/libstdc++-v3/src/filesystem/std-ops.cc
@@ -1248,6 +1248,12 @@ fs::path fs::read_symlink(const path& p, error_code& ec)
       ec.assign(errno, std::generic_category());
       return result;
     }
+  else if (!fs::is_symlink(make_file_status(st)))
+    {
+      ec.assign(EINVAL, std::generic_category());
+      return result;
+    }
+
   std::string buf(st.st_size ? st.st_size + 1 : 128, '\0');
   do
     {

commit 566304a863e86bd894ee8a06527395da22c919b1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Aug 7 00:17:48 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c2e265fc4e9..007638ea22c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200806
+20200807
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 8e62b793cac..1f65999f6e0 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,13 @@
+2020-08-06  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-08-06  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/96484
+	* src/filesystem/ops.cc (fs::read_symlink): Return an error
+	immediately for non-symlinks.
+	* src/filesystem/std-ops.cc (fs::read_symlink): Likewise.
+
 2020-07-21  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit 39a5a04daa09c711caeb6aaff12f1d03406fe29f
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Sat Mar 21 21:51:07 2020 +0000

    libstdc++: Fix path::generic_string allocator handling (PR 94242)
    
    It's not possible to construct a path::string_type from an allocator of
    a different type. Create the correct specialization of basic_string, and
    adjust path::_S_str_convert to use a basic_string_view so that it is
    independent of the allocator type.
    
            PR libstdc++/94242
            * include/bits/fs_path.h (path::_S_str_convert): Replace first
            parameter with basic_string_view so that strings with different
            allocators can be accepted.
            (path::generic_string<C,T,A>()): Use basic_string object that uses the
            right allocator type.
            * testsuite/27_io/filesystem/path/generic/94242.cc: New test.
            * testsuite/27_io/filesystem/path/generic/generic_string.cc: Improve
            test coverage.
    
    (cherry picked from commit 9fc985118d9f5014afc1caf32a411ee5803fba61)

diff --git a/libstdc++-v3/include/bits/fs_path.h b/libstdc++-v3/include/bits/fs_path.h
index 7ae68f623d1..f121d82c032 100644
--- a/libstdc++-v3/include/bits/fs_path.h
+++ b/libstdc++-v3/include/bits/fs_path.h
@@ -477,7 +477,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
 
     template<typename _CharT, typename _Traits, typename _Allocator>
       static basic_string<_CharT, _Traits, _Allocator>
-      _S_str_convert(const string_type&, const _Allocator& __a);
+      _S_str_convert(basic_string_view<value_type>, const _Allocator&);
 
     static bool _S_is_dir_sep(value_type __ch)
     {
@@ -873,7 +873,8 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
 
   template<typename _CharT, typename _Traits, typename _Allocator>
     std::basic_string<_CharT, _Traits, _Allocator>
-    path::_S_str_convert(const string_type& __str, const _Allocator& __a)
+    path::_S_str_convert(basic_string_view<value_type> __str,
+			 const _Allocator& __a)
     {
       if (__str.size() == 0)
 	return std::basic_string<_CharT, _Traits, _Allocator>(__a);
@@ -971,7 +972,9 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
 #else
       const value_type __slash = '/';
 #endif
-      string_type __str(__a);
+      using _Alloc2 = typename allocator_traits<_Allocator>::template
+	rebind_alloc<value_type>;
+      basic_string<value_type, char_traits<value_type>, _Alloc2> __str(__a);
 
       if (_M_type == _Type::_Root_dir)
 	__str.assign(1, __slash);
@@ -983,7 +986,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
 	    {
 	      if (__add_slash)
 		__str += __slash;
-	      __str += __elem._M_pathname;
+	      __str += basic_string_view<value_type>(__elem._M_pathname);
 	      __add_slash = __elem._M_type == _Type::_Filename;
 	    }
 	}
diff --git a/libstdc++-v3/testsuite/27_io/filesystem/path/generic/94242.cc b/libstdc++-v3/testsuite/27_io/filesystem/path/generic/94242.cc
new file mode 100644
index 00000000000..4bb32f83867
--- /dev/null
+++ b/libstdc++-v3/testsuite/27_io/filesystem/path/generic/94242.cc
@@ -0,0 +1,53 @@
+// { dg-options "-std=gnu++17 -lstdc++fs" }
+// { dg-do run { target c++17 } }
+// { dg-require-filesystem-ts "" }
+
+// Copyright (C) 2020 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// C++17 30.10.7.4.7 path generic format observers [fs.path.generic.obs]
+
+#include <filesystem>
+#include <testsuite_allocator.h>
+
+using std::filesystem::path;
+using __gnu_test::SimpleAllocator;
+
+void
+test01()
+{
+  path p = "//foo//bar//.";
+  using C = path::value_type;
+  auto g = p.generic_string<C, std::char_traits<C>, SimpleAllocator<C>>();
+  VERIFY( g == path("/foo/bar/.").c_str() );
+}
+
+void
+test02()
+{
+  path p = "//foo//bar//.";
+  using C = char16_t;
+  auto g = p.generic_string<C, std::char_traits<C>, SimpleAllocator<C>>();
+  VERIFY( g == u"/foo/bar/." );
+}
+
+int
+main()
+{
+  test01();
+  test02();
+}
diff --git a/libstdc++-v3/testsuite/27_io/filesystem/path/generic/generic_string.cc b/libstdc++-v3/testsuite/27_io/filesystem/path/generic/generic_string.cc
index 16335443c76..c813987ca42 100644
--- a/libstdc++-v3/testsuite/27_io/filesystem/path/generic/generic_string.cc
+++ b/libstdc++-v3/testsuite/27_io/filesystem/path/generic/generic_string.cc
@@ -22,6 +22,7 @@
 // C++17 30.10.7.4.7 path generic format observers [fs.path.generic.obs]
 
 #include <filesystem>
+#include <testsuite_fs.h>
 #include <testsuite_hooks.h>
 
 using std::filesystem::path;
@@ -35,11 +36,15 @@ test01()
 #ifdef __CYGWIN__
   VERIFY( path("//a").generic_string() == "//a" );
   VERIFY( path("//a/").generic_string() == "//a/" );
+  VERIFY( path("//a//").generic_string() == "//a/" );
   VERIFY( path("//a/b").generic_string() == "//a/b" );
+  VERIFY( path("//a//b").generic_string() == "//a/b" );
 #else
   VERIFY( path("//a").generic_string() == "/a" );
   VERIFY( path("//a/").generic_string() == "/a/" );
+  VERIFY( path("//a//").generic_string() == "/a/" );
   VERIFY( path("//a/b").generic_string() == "/a/b" );
+  VERIFY( path("//a//b").generic_string() == "/a/b" );
 #endif
   VERIFY( path("/a//b").generic_string() == "/a/b" );
   VERIFY( path("/a//b/").generic_string() == "/a/b/" );
@@ -47,8 +52,38 @@ test01()
   VERIFY( path("/a//b//.").generic_string() == "/a/b/." );
 }
 
+void
+test02()
+{
+  if constexpr (path::preferred_separator == L'\\')
+  {
+    // PR libstdc++/93244
+    VERIFY( path("C:\\foo\\bar").generic_string() == "C:/foo/bar" );
+    VERIFY( path("C://foo//bar").generic_string() == "C:/foo/bar" );
+  }
+}
+
+void
+test03()
+{
+  for (path p : { "a///b//c", "/a//b//c", "a:b//c" })
+  {
+    // A path constructed from the generic format string should compare equal
+    // to the original, because they represent the same path.
+    // For GCC 8 this only works for some paths, because LWG 2936 is not
+    // implemented on the branch, so e.g. "/" and "//" compare not equal
+    VERIFY( path(p.generic_string()) == p );
+    VERIFY( path(p.generic_wstring()) == p );
+    VERIFY( path(p.generic_u8string()) == p );
+    VERIFY( path(p.generic_u16string()) == p );
+    VERIFY( path(p.generic_u32string()) == p );
+  }
+}
+
 int
 main()
 {
   test01();
+  test02();
+  test03();
 }

commit 01cbd26b022cc9d4eaf26287b48299acfce80348
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Sat Mar 21 22:11:44 2020 +0000

    libstdc++: Fix experimental::path::generic_string (PR 93245)
    
    This function was unimplemented, simply returning the native format
    string instead.
    
            PR libstdc++/93245
            * include/experimental/bits/fs_path.h (path::generic_string<C,T,A>()):
            Return the generic format not the native format.
            * testsuite/experimental/filesystem/path/generic/generic_string.cc:
            Improve test coverage.
    
    (cherry picked from commit a577c0c26931090e7c25e56ef5ffc807627961ec)

diff --git a/libstdc++-v3/include/experimental/bits/fs_path.h b/libstdc++-v3/include/experimental/bits/fs_path.h
index 705f76331b5..c212670b6ca 100644
--- a/libstdc++-v3/include/experimental/bits/fs_path.h
+++ b/libstdc++-v3/include/experimental/bits/fs_path.h
@@ -932,29 +932,51 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
   inline std::u32string
   path::u32string() const { return string<char32_t>(); }
 
-#ifndef _GLIBCXX_FILESYSTEM_IS_WINDOWS
   template<typename _CharT, typename _Traits, typename _Allocator>
     inline std::basic_string<_CharT, _Traits, _Allocator>
     path::generic_string(const _Allocator& __a) const
-    { return string<_CharT, _Traits, _Allocator>(__a); }
+    {
+#ifdef _GLIBCXX_FILESYSTEM_IS_WINDOWS
+      const _CharT __slash = is_same<_CharT, wchar_t>::value
+	? _CharT(L'/')
+	: _CharT('/'); // Assume value is correct for the encoding.
+#else
+      const _CharT __slash = _CharT('/');
+#endif
+      basic_string<_CharT, _Traits, _Allocator> __str(__a);
+      __str.reserve(_M_pathname.size());
+      bool __add_slash = false;
+      for (auto& __elem : *this)
+	{
+	  if (__elem._M_type == _Type::_Root_dir)
+	    {
+	      __str += __slash;
+	      continue;
+	    }
+	  if (__add_slash)
+	    __str += __slash;
+	  __str += __elem.string<_CharT, _Traits, _Allocator>(__a);
+	  __add_slash = __elem._M_type == _Type::_Filename;
+	}
+      return __str;
+    }
 
   inline std::string
-  path::generic_string() const { return string(); }
+  path::generic_string() const { return generic_string<char>(); }
 
 #if _GLIBCXX_USE_WCHAR_T
   inline std::wstring
-  path::generic_wstring() const { return wstring(); }
+  path::generic_wstring() const { return generic_string<wchar_t>(); }
 #endif
 
   inline std::string
-  path::generic_u8string() const { return u8string(); }
+  path::generic_u8string() const { return generic_string<char>(); }
 
   inline std::u16string
-  path::generic_u16string() const { return u16string(); }
+  path::generic_u16string() const { return generic_string<char16_t>(); }
 
   inline std::u32string
-  path::generic_u32string() const { return u32string(); }
-#endif
+  path::generic_u32string() const { return generic_string<char32_t>(); }
 
   inline int
   path::compare(const string_type& __s) const { return compare(path(__s)); }
diff --git a/libstdc++-v3/testsuite/experimental/filesystem/path/generic/generic_string.cc b/libstdc++-v3/testsuite/experimental/filesystem/path/generic/generic_string.cc
index 0d852bd9b88..6fd85875a82 100644
--- a/libstdc++-v3/testsuite/experimental/filesystem/path/generic/generic_string.cc
+++ b/libstdc++-v3/testsuite/experimental/filesystem/path/generic/generic_string.cc
@@ -23,27 +23,55 @@
 
 #include <experimental/filesystem>
 #include <testsuite_fs.h>
-#include <testsuite_hooks.h>
+#include <testsuite_allocator.h>
 
 using std::experimental::filesystem::path;
 
 void
 test01()
 {
-  for (const path& p : __gnu_test::test_paths)
+  __gnu_test::compare_paths( path("///a//b///").generic_string(), "/a/b/." );
+  __gnu_test::compare_paths( path("///a//b").generic_u16string(), "/a/b" );
+  __gnu_test::compare_paths( path("//a//b").generic_u16string(), "//a/b" );
+}
+
+using __gnu_test::SimpleAllocator;
+
+void
+test02()
+{
+  path p = "//foo//bar//.";
+  using C = char16_t;
+  auto g = p.generic_string<C, std::char_traits<C>, SimpleAllocator<C>>();
+  VERIFY( g == u"//foo/bar/." );
+}
+
+
+void
+test03()
+{
+  for (path p : { "/a///b//c", "///a//b//c", "a:b//c", "a://b///c" })
   {
-    path p2(p), p3;
-    p2.swap(p3);
-    VERIFY( p2 == path() );
-    VERIFY( p3 == p );
-    p2.swap(p3);
-    VERIFY( p2 == p );
-    VERIFY( p3 == path() );
+    // A path constructed from the generic format string should compare equal
+    // to the original, because they represent the same path.
+    VERIFY( path(p.generic_string()) == p );
+    VERIFY( path(p.generic_wstring()) == p );
+    VERIFY( path(p.generic_u8string()) == p );
+    VERIFY( path(p.generic_u16string()) == p );
+    VERIFY( path(p.generic_u32string()) == p );
   }
+
+  // Except when the original consists entirely of a root-directory with
+  // multiple slashes, because path("///").native() is "///" but the
+  // generic format string is "/". In the Filesystem TS path::compare just
+  // compares native strings, so path("///") != path("/").
+  VERIFY( path("///").generic_string() == "/" );
 }
 
 int
 main()
 {
   test01();
+  test02();
+  test03();
 }

commit 3b05a417774d40cf1b9fca61630209de8338ba47
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Thu Jan 10 15:39:28 2019 +0000

    Fix filesystem::last_write_time failure with 32-bit time_t
    
            * testsuite/27_io/filesystem/operations/last_write_time.cc: Fix
            test failures on targets with 32-bit time_t.
    
    (cherry picked from commit 174f1d264274d3f77133713a3853fc016ba527b4)

diff --git a/libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc b/libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc
index 1fdf39c7e0d..c815e01a5c6 100644
--- a/libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc
+++ b/libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc
@@ -22,6 +22,7 @@
 // 15.25 Permissions [fs.op.last_write_time]
 
 #include <filesystem>
+#include <limits>
 #include <testsuite_fs.h>
 #include <testsuite_hooks.h>
 
@@ -141,14 +142,27 @@ test02()
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
 
+  if (std::numeric_limits<std::time_t>::max()
+      < std::numeric_limits<std::int64_t>::max())
+    return; // file clock's epoch is out of range for 32-bit time_t
+
   ec = bad_ec;
+  // The file clock's epoch:
   time = time_type();
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
 
   ec = bad_ec;
-  time -= std::chrono::milliseconds(1000 * 60 * 10 + 15);
+  // A time after the epoch
+  time += std::chrono::milliseconds(1000 * 60 * 10 + 15);
+  last_write_time(f.path, time, ec);
+  VERIFY( !ec );
+  VERIFY( approx_equal(last_write_time(f.path), time) );
+
+  ec = bad_ec;
+  // A time before than the epoch
+  time -= std::chrono::milliseconds(1000 * 60 * 20 + 15);
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );

commit b623cf82022d8837c228c1c9ca6a585318c24e40
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Thu Mar 12 17:39:04 2020 +0000

    libstdc++: Fix FS-dependent filesystem tests
    
    These tests were failing on XFS because it doesn't support setting file
    timestamps past 2038, so the expected overflow when reading back a huge
    timestamp into a file_time_type didn't happen.
    
    Additionally, the std::filesystem::file_time_type::clock has an
    epoch that is out of range of 32-bit time_t so testing times around that
    epoch may also fail.
    
    This fixes the tests to give up gracefully if the filesystem doesn't
    support times that can't be represented in 32-bit time_t.
    
    Backport from mainline
    2020-02-28  Jonathan Wakely  <jwakely@redhat.com>
    
            * testsuite/27_io/filesystem/operations/last_write_time.cc: Fixes for
            filesystems that silently truncate timestamps.
            * testsuite/experimental/filesystem/operations/last_write_time.cc:
            Likewise.
    
    (cherry picked from commit 2fa3247fef79ede9ec3638605ea137b0e4d76075)

diff --git a/libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc b/libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc
index c815e01a5c6..cedddd1606f 100644
--- a/libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc
+++ b/libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc
@@ -32,9 +32,12 @@
 #if _GLIBCXX_HAVE_UTIME_H
 # include <utime.h>
 #endif
+#include <stdio.h>
 
 using time_type = std::filesystem::file_time_type;
 
+namespace chrono = std::chrono;
+
 void
 test01()
 {
@@ -67,10 +70,15 @@ test01()
 
   auto end_of_time = time_type::duration::max();
   auto last_second
-    = std::chrono::duration_cast<std::chrono::seconds>(end_of_time).count();
+    = chrono::duration_cast<chrono::seconds>(end_of_time).count();
   if (last_second > std::numeric_limits<std::time_t>::max())
-    return; // can't test overflow
+  {
+    puts("Range of time_t is smaller than range of chrono::file_clock, "
+	 "can't test for overflow on this target.");
+    return;
+  }
 
+  // Set mtime to a date past the maximum possible file_time_type:
 #if _GLIBCXX_USE_UTIMENSAT
   struct ::timespec ts[2];
   ts[0].tv_sec = 0;
@@ -84,25 +92,34 @@ test01()
   times.actime = std::numeric_limits<std::time_t>::max() - 1;
   VERIFY( !::utime(p.c_str(), &times) );
 #else
+  puts("No utimensat or utime, giving up.");
   return;
 #endif
 
+  // Try to read back the impossibly-large mtime:
   mtime = last_write_time(p, ec);
-  VERIFY( ec );
-  VERIFY( ec == std::make_error_code(std::errc::value_too_large) );
-  VERIFY( mtime == time_type::min() );
+  // Some filesystems (e.g. XFS) silently truncate distant times to
+  // the time_t epochalypse, Jan 19 2038, so we won't get an error when
+  // reading it back:
+  if (ec)
+  {
+    VERIFY( ec == std::make_error_code(std::errc::value_too_large) );
+    VERIFY( mtime == time_type::min() );
+  }
+  else
+    puts("No overflow error, filesystem may not support 64-bit time_t.");
 
 #if __cpp_exceptions
-  caught = false;
+  // Once more, with exceptions:
   try {
-    mtime = last_write_time(p);
-  } catch (std::system_error const& e) {
-    caught = true;
-    ec = e.code();
+    auto mtime2 = last_write_time(p);
+    // If it didn't throw, expect to have read back the same value:
+    VERIFY( mtime2 == mtime );
+  } catch (std::filesystem::filesystem_error const& e) {
+    // If it did throw, expect the error_code to be the same:
+    VERIFY( e.code() == ec );
+    VERIFY( e.path1() == p );
   }
-  VERIFY( caught );
-  VERIFY( ec );
-  VERIFY( ec == std::make_error_code(std::errc::value_too_large) );
 #endif
 }
 
@@ -111,7 +128,7 @@ bool approx_equal(time_type file_time, time_type expected)
   auto delta = expected - file_time;
   if (delta < delta.zero())
     delta = -delta;
-  return delta < std::chrono::seconds(1);
+  return delta < chrono::seconds(1);
 }
 
 void
@@ -124,20 +141,20 @@ test02()
   std::error_code ec;
   time_type time;
 
-  time = last_write_time(f.path);
   ec = bad_ec;
+  time = last_write_time(f.path);
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
 
   ec = bad_ec;
-  time -= std::chrono::milliseconds(1000 * 60 * 10 + 15);
+  time -= chrono::milliseconds(1000 * 60 * 10 + 15);
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
 
   ec = bad_ec;
-  time += std::chrono::milliseconds(1000 * 60 * 20 + 15);
+  time += chrono::milliseconds(1000 * 60 * 20 + 15);
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
@@ -146,6 +163,28 @@ test02()
       < std::numeric_limits<std::int64_t>::max())
     return; // file clock's epoch is out of range for 32-bit time_t
 
+  using sys_time_32b
+    = chrono::time_point<chrono::system_clock, chrono::duration<std::int32_t>>;
+  auto duration_until_2038 = sys_time_32b::max() - sys_time_32b::clock::now();
+  auto file_time_2038 = time_type::clock::now() + duration_until_2038;
+
+  ec = bad_ec;
+  time = file_time_2038 - chrono::seconds(1);
+  // Assume all filesystems can store times that fit in 32-bit time_t
+  // (i.e. up to Jan 19 2038)
+  last_write_time(f.path, time, ec);
+  VERIFY( !ec );
+  VERIFY( approx_equal(last_write_time(f.path), time) );
+
+  // Check whether the filesystem supports times larger than 32-bit time_t:
+  time += chrono::seconds(60);
+  last_write_time(f.path, time, ec);
+  if (ec || !approx_equal(last_write_time(f.path), time))
+  {
+    puts("Filesystem seems to truncate times past Jan 19 2038, giving up.");
+    return; // Tests below will fail on this filesystem
+  }
+
   ec = bad_ec;
   // The file clock's epoch:
   time = time_type();
@@ -155,14 +194,14 @@ test02()
 
   ec = bad_ec;
   // A time after the epoch
-  time += std::chrono::milliseconds(1000 * 60 * 10 + 15);
+  time += chrono::milliseconds(1000 * 60 * 10 + 15);
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
 
   ec = bad_ec;
   // A time before than the epoch
-  time -= std::chrono::milliseconds(1000 * 60 * 20 + 15);
+  time -= chrono::milliseconds(1000 * 60 * 20 + 15);
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
diff --git a/libstdc++-v3/testsuite/experimental/filesystem/operations/last_write_time.cc b/libstdc++-v3/testsuite/experimental/filesystem/operations/last_write_time.cc
index 9d1752fd4fc..e43f755d4d0 100644
--- a/libstdc++-v3/testsuite/experimental/filesystem/operations/last_write_time.cc
+++ b/libstdc++-v3/testsuite/experimental/filesystem/operations/last_write_time.cc
@@ -22,6 +22,7 @@
 // 15.25 Permissions [fs.op.last_write_time]
 
 #include <experimental/filesystem>
+#include <limits>
 #include <testsuite_fs.h>
 #include <testsuite_hooks.h>
 
@@ -31,9 +32,12 @@
 #if _GLIBCXX_HAVE_UTIME_H
 # include <utime.h>
 #endif
+#include <stdio.h>
 
 using time_type = std::experimental::filesystem::file_time_type;
 
+namespace chrono = std::chrono;
+
 void
 test01()
 {
@@ -66,10 +70,15 @@ test01()
 
   auto end_of_time = time_type::duration::max();
   auto last_second
-    = std::chrono::duration_cast<std::chrono::seconds>(end_of_time).count();
+    = chrono::duration_cast<chrono::seconds>(end_of_time).count();
   if (last_second > std::numeric_limits<std::time_t>::max())
-    return; // can't test overflow
+  {
+    puts("Range of time_t is smaller than range of chrono::file_clock, "
+	 "can't test for overflow on this target.");
+    return;
+  }
 
+  // Set mtime to a date past the maximum possible file_time_type:
 #if _GLIBCXX_USE_UTIMENSAT
   struct ::timespec ts[2];
   ts[0].tv_sec = 0;
@@ -83,25 +92,34 @@ test01()
   times.actime = std::numeric_limits<std::time_t>::max() - 1;
   VERIFY( !::utime(p.c_str(), &times) );
 #else
+  puts("No utimensat or utime, giving up.");
   return;
 #endif
 
+  // Try to read back the impossibly-large mtime:
   mtime = last_write_time(p, ec);
-  VERIFY( ec );
-  VERIFY( ec == std::make_error_code(std::errc::value_too_large) );
-  VERIFY( mtime == time_type::min() );
+  // Some filesystems (e.g. XFS) silently truncate distant times to
+  // the time_t epochalypse, Jan 19 2038, so we won't get an error when
+  // reading it back:
+  if (ec)
+  {
+    VERIFY( ec == std::make_error_code(std::errc::value_too_large) );
+    VERIFY( mtime == time_type::min() );
+  }
+  else
+    puts("No overflow error, filesystem may not support 64-bit time_t.");
 
 #if __cpp_exceptions
-  caught = false;
+  // Once more, with exceptions:
   try {
-    mtime = last_write_time(p);
-  } catch (std::system_error const& e) {
-    caught = true;
-    ec = e.code();
+    auto mtime2 = last_write_time(p);
+    // If it didn't throw, expect to have read back the same value:
+    VERIFY( mtime2 == mtime );
+  } catch (std::experimental::filesystem::filesystem_error const& e) {
+    // If it did throw, expect the error_code to be the same:
+    VERIFY( e.code() == ec );
+    VERIFY( e.path1() == p );
   }
-  VERIFY( caught );
-  VERIFY( ec );
-  VERIFY( ec == std::make_error_code(std::errc::value_too_large) );
 #endif
 }
 
@@ -110,7 +128,7 @@ bool approx_equal(time_type file_time, time_type expected)
   auto delta = expected - file_time;
   if (delta < delta.zero())
     delta = -delta;
-  return delta < std::chrono::seconds(1);
+  return delta < chrono::seconds(1);
 }
 
 void
@@ -118,31 +136,37 @@ test02()
 {
   // write times
 
+  const std::error_code bad_ec = make_error_code(std::errc::invalid_argument);
   __gnu_test::scoped_file f;
   std::error_code ec;
   time_type time;
 
+  ec = bad_ec;
   time = last_write_time(f.path);
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
 
-  time -= std::chrono::milliseconds(1000 * 60 * 10 + 15);
+  ec = bad_ec;
+  time -= chrono::milliseconds(1000 * 60 * 10 + 15);
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
 
-  time += std::chrono::milliseconds(1000 * 60 * 20 + 15);
+  ec = bad_ec;
+  time += chrono::milliseconds(1000 * 60 * 20 + 15);
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
 
+  ec = bad_ec;
   time = time_type();
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );
 
-  time -= std::chrono::milliseconds(1000 * 60 * 10 + 15);
+  ec = bad_ec;
+  time -= chrono::milliseconds(1000 * 60 * 10 + 15);
   last_write_time(f.path, time, ec);
   VERIFY( !ec );
   VERIFY( approx_equal(last_write_time(f.path), time) );

commit 3e2d69ee245e5a44c53cae27a797b97ba529eb72
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Mon Aug 3 22:55:28 2020 +0200

    aarch64: Fix up __aarch64_cas16_acq_rel fallback
    
    As mentioned in the PR, the fallback path when LSE is unavailable writes
    incorrect registers to the memory if the previous content compares equal
    to x0, x1 - it writes copy of x0, x1 from the start of function, but it
    should write x2, x3.
    
    2020-08-03  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/96402
            * config/aarch64/lse.S (__aarch64_cas16_acq_rel): Use x2, x3 instead
            of x(tmp0), x(tmp1) in STXP arguments.
    
            * gcc.target/aarch64/pr96402.c: New test.
    
    (cherry picked from commit 90b43856fdff7d96d93d22970eca8a86c56e0ddc)

diff --git a/gcc/testsuite/gcc.target/aarch64/pr96402.c b/gcc/testsuite/gcc.target/aarch64/pr96402.c
new file mode 100644
index 00000000000..fa2dddfac15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr96402.c
@@ -0,0 +1,16 @@
+/* PR target/96402 */
+/* { dg-do run { target int128 } } */
+/* { dg-options "-moutline-atomics" } */
+
+int
+main ()
+{
+  __int128 a = 0;
+  __sync_val_compare_and_swap (&a, (__int128) 0, (__int128) 1);
+  if (a != 1)
+    __builtin_abort ();
+  __sync_val_compare_and_swap (&a, (__int128) 1, (((__int128) 0xdeadbeeffeedbac1ULL) << 64) | 0xabadcafe00c0ffeeULL);
+  if (a != ((((__int128) 0xdeadbeeffeedbac1ULL) << 64) | 0xabadcafe00c0ffeeULL))
+    __builtin_abort ();
+  return 0;
+}
diff --git a/libgcc/config/aarch64/lse.S b/libgcc/config/aarch64/lse.S
index f7f1c19587b..deaf66875f6 100644
--- a/libgcc/config/aarch64/lse.S
+++ b/libgcc/config/aarch64/lse.S
@@ -200,7 +200,7 @@ STARTFN	NAME(cas)
 	cmp		x0, x(tmp0)
 	ccmp		x1, x(tmp1), #0, eq
 	bne		1f
-	STXP		w(tmp2), x(tmp0), x(tmp1), [x4]
+	STXP		w(tmp2), x2, x3, [x4]
 	cbnz		w(tmp2), 0b
 1:	ret
 

commit 53e0eafd4622a03deab9687a67f502c42f6179b9
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Aug 8 00:17:46 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 007638ea22c..0aaecf38b04 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200807
+20200808
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 19b86837173..7de3483cac4 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-08-07  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-03  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/96402
+	* gcc.target/aarch64/pr96402.c: New test.
+
 2020-07-25  Dominique d'Humieres  <dhumieres.dominique@free.fr>
 
 	Backported from master:
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index bca0c1c212e..dda054d0d4f 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-08-07  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-03  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/96402
+	* config/aarch64/lse.S (__aarch64_cas16_acq_rel): Use x2, x3 instead
+	of x(tmp0), x(tmp1) in STXP arguments.
+
 2020-06-17  Samuel Thibault  <samuel.thibault@gnu.org>
 
 	Backported from master:
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 1f65999f6e0..eea7612e325 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,47 @@
+2020-08-07  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-03-12  Jonathan Wakely  <jwakely@redhat.com>
+
+	* testsuite/27_io/filesystem/operations/last_write_time.cc: Fixes for
+	filesystems that silently truncate timestamps.
+	* testsuite/experimental/filesystem/operations/last_write_time.cc:
+	Likewise.
+
+2020-08-07  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2019-01-10  Jonathan Wakely  <jwakely@redhat.com>
+
+	* testsuite/27_io/filesystem/operations/last_write_time.cc: Fix
+	test failures on targets with 32-bit time_t.
+
+2020-08-07  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-03-21  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/93245
+	* include/experimental/bits/fs_path.h (path::generic_string<C,T,A>()):
+	Return the generic format not the native format.
+	* testsuite/experimental/filesystem/path/generic/generic_string.cc:
+	Improve test coverage.
+
+2020-08-07  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-03-21  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/94242
+	* include/bits/fs_path.h (path::_S_str_convert): Replace first
+	parameter with basic_string_view so that strings with different
+	allocators can be accepted.
+	(path::generic_string<C,T,A>()): Use basic_string object that uses the
+	right allocator type.
+	* testsuite/27_io/filesystem/path/generic/94242.cc: New test.
+	* testsuite/27_io/filesystem/path/generic/generic_string.cc: Improve
+	test coverage.
+
 2020-08-06  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit ef97eb30c27cae4b9891724971229adb10f76d00
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Aug 9 00:17:48 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0aaecf38b04..c61d7749c7d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200808
+20200809

commit 755f90be5f5ab2d697a3d4b868f63b627c4a8e2b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Aug 10 00:17:44 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c61d7749c7d..58309c92ac6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200809
+20200810

commit 11bdad7ce94234d5b9e7ac5ad6c37612454b87d8
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Mon Aug 10 11:47:50 2020 +0100

    libstdc++: Remove unused Makefile.in
    
    This file was unintentionally added by r271568 when backporting a change
    from trunk.
    
            * src/c++17/Makefile.in: Remove unused file.

diff --git a/libstdc++-v3/src/c++17/Makefile.in b/libstdc++-v3/src/c++17/Makefile.in
deleted file mode 100644
index 26a4713831d..00000000000
--- a/libstdc++-v3/src/c++17/Makefile.in
+++ /dev/null
@@ -1,754 +0,0 @@
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-
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-
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-# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
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-
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commit db6447c88b18f4175624a94ff5f3a1519dcd9ca8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Aug 11 00:17:56 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 58309c92ac6..5a77e124a0f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200810
+20200811
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index eea7612e325..8cd063bfa9e 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,7 @@
+2020-08-10  Jonathan Wakely  <jwakely@redhat.com>
+
+	* src/c++17/Makefile.in: Remove unused file.
+
 2020-08-07  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit fc2b0c3ca0206d5e91ba78c47aa3ae0b0d8d01d8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Aug 12 00:17:37 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 5a77e124a0f..b81f381520c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200811
+20200812

commit 6786b369ab2851b25e8fd2aae33d3b1bf20de132
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Wed Aug 12 04:19:16 2020 -0500

    testsuite: Add -fno-common to pr82374.c [PR94077]
    
    As the PR comments show, the case gcc.dg/gomp/pr82374.c fails on
    Power7 since gcc8.  But it passes from gcc10.  By looking into
    the difference, it's due to that gcc10 sets -fno-common as default,
    which makes vectorizer force the alignment and be able to use
    aligned vector load/store on those targets which doesn't support
    unaligned vector load/store (here it's Power7).
    
    As Jakub suggested in the PR, this patch is to append -fno-common
    into dg-options.
    
    Verified with gcc8/gcc9 releases on ppc64-redhat-linux (Power7).
    
    gcc/testsuite/ChangeLog:
    
            PR testsuite/94077
            * gcc.dg/gomp/pr82374.c: Add option -fno-common.

diff --git a/gcc/testsuite/gcc.dg/gomp/pr82374.c b/gcc/testsuite/gcc.dg/gomp/pr82374.c
index 453266ed84e..e63a2f5c62d 100644
--- a/gcc/testsuite/gcc.dg/gomp/pr82374.c
+++ b/gcc/testsuite/gcc.dg/gomp/pr82374.c
@@ -1,6 +1,9 @@
 /* PR tree-optimization/82374 */
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-tree-vectorize -fdump-tree-vect-details" } */
+/* Option -fno-common makes vectorizer able to force alignment and ensures
+   vectorization can succeed even on targets lacking of unaligned vector
+   load/store.  */
+/* { dg-options "-O2 -fno-tree-vectorize -fdump-tree-vect-details -fno-common" } */
 /* { dg-additional-options "-mavx -mno-avx2" { target i?86-*-* x86_64-*-* } } */
 /* { dg-additional-options "-mvsx" { target powerpc_vsx_ok } } */
 

commit a2c5598640423f2b9679b9f3e8587fdf605f680b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Aug 13 00:17:37 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b81f381520c..faeb40f4ca8 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200812
+20200813
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7de3483cac4..2c96baf442d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-08-12  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR testsuite/94077
+	* gcc.dg/gomp/pr82374.c: Add option -fno-common.
+
 2020-08-07  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:

commit 0d5f0894b84777b7de3598d193ea549d3482aeb0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Aug 14 00:17:33 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index faeb40f4ca8..da579e6d532 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200813
+20200814

commit fa6464edd031800fab6619947dd29967afdf35d2
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Aug 15 00:17:33 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index da579e6d532..e6ef660d478 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200814
+20200815

commit 10e2ba035583c02efc281fb232fdd0d99fb4fc16
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Aug 16 00:17:31 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e6ef660d478..9b2c4cb86fd 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200815
+20200816

commit 36e677905cba2a6a97aaa82e77a08513080214bc
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Aug 17 00:17:30 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 9b2c4cb86fd..86cec8a47dc 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200816
+20200817

commit c48a50ef269c93f39f37d0b93c00a57e6ddf5e7c
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Aug 18 00:17:37 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 86cec8a47dc..3b29b8dc124 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200817
+20200818

commit bf7b9330982165e051de0962c5bc231e2d1242d9
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue Aug 18 19:48:51 2020 +0200

    i386: Fix restore_stack_nonlocal expander [PR96536].
    
    -fcf-protection code in restore_stack_nonlocal uses a branch based on
    a clobber result.  The patch adds missing compare.
    
    2020-08-18  Uroš Bizjak  <ubizjak@gmail.com>
    
    gcc/ChangeLog:
    
            PR target/96536
            * config/i386/i386.md (restore_stack_nonlocal):
            Add missing compare RTX.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2bb58236d88..11d69e997bb 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -18596,8 +18596,11 @@
       emit_insn (tmp);
 
       /* Compare and jump over adjustment code.  */
-      noadj_label = gen_label_rtx ();
+      tmp = gen_rtx_COMPARE (CCZmode, reg_ssp, const0_rtx);
       flags = gen_rtx_REG (CCZmode, FLAGS_REG);
+      emit_insn (gen_rtx_SET (flags, tmp));
+
+      noadj_label = gen_label_rtx ();
       tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx);
       tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
 				  gen_rtx_LABEL_REF (VOIDmode, noadj_label),

commit 2e0e4314b3ec7fd819d7aa65e81e614750417954
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Aug 19 00:17:38 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3467348f814..c0d756c293f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-08-18  Uroš Bizjak  <ubizjak@gmail.com>
+
+	PR target/96536
+	* config/i386/i386.md (restore_stack_nonlocal):
+	Add missing compare RTX.
+
 2020-08-03  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3b29b8dc124..a8098fbd6e3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200818
+20200819

commit c6b090a8c49532d59b7d5d7d9fbe753810459491
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Aug 20 00:17:43 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a8098fbd6e3..7829179094c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200819
+20200820

commit 185d9cb0c436b34d4d517259d563d2221a8744ff
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Aug 21 00:17:38 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7829179094c..7ead9649335 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200820
+20200821

commit 7f8f284fa760fa504116c3c29f9f522b076a6392
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Fri Jul 17 13:10:28 2020 +0100

    AArch64: Fix bugs in -mcpu=native detection.
    
    This patch fixes a couple of issues in AArch64's -mcpu=native processing:
    
    The buffer used to read the lines from /proc/cpuinfo is 128 bytes long.  While
    this was enough in the past with the increase in architecture extensions it is
    no longer enough.   It results in two bugs:
    
    1) No option string longer than 127 characters is correctly parsed.  Features
       that are supported are silently ignored.
    
    2) It incorrectly enables features that are not present on the machine:
      a) It checks for substring matching instead of full word matching.  This makes
         it incorrectly detect sb support when ssbs is provided instead.
      b) Due to the truncation at the 127 char border it also incorrectly enables
         features due to the full feature being cut off and the part that is left
         accidentally enables something else.
    
    This breaks -mcpu=native detection on some of our newer system.
    
    The patch fixes these issues by reading full lines up to the \n in a string.
    This gives us the full feature line.  Secondly it creates a set from this string
    to:
    
     1) Reduce matching complexity from O(n*m) to O(n*logm).
     2) Perform whole word matching instead of substring matching.
    
    To make this code somewhat cleaner I also changed from using char* to using
    std::string and std::set.
    
    Note that I have intentionally avoided the use of ifstream and stringstream
    to make it easier to backport.  I have also not change the substring matching
    for the initial line classification as I cannot find a documented cpuinfo format
    which leads me to believe there may be kernels out there that require this which
    may be why the original code does this.
    
    I also do not want this to break if the kernel adds a new line that is long and
    indents the file by two tabs to keep everything aligned.  In short I think an
    imprecise match is the right thing here.
    
    Test for this is added as the last thing in this series as it requires some
    changes to be made to be able to test this.
    
    gcc/ChangeLog:
    
            * config/aarch64/driver-aarch64.c (INCLUDE_SET): New.
            (parse_field): Use std::string.
            (split_words, readline, find_field): New.
            (host_detect_local_cpu): Fix truncation issues.
    
    (cherry picked from commit b399f3c6425f6c33b64e813899cbd589288ef716)

diff --git a/gcc/config/aarch64/driver-aarch64.c b/gcc/config/aarch64/driver-aarch64.c
index 823b9bd9fce..47cb97abe75 100644
--- a/gcc/config/aarch64/driver-aarch64.c
+++ b/gcc/config/aarch64/driver-aarch64.c
@@ -21,6 +21,7 @@
 
 #include "config.h"
 #define INCLUDE_STRING
+#define INCLUDE_SET
 #include "system.h"
 #include "coretypes.h"
 #include "tm.h"
@@ -119,9 +120,15 @@ valid_bL_core_p (unsigned int *core, unsigned int bL_core)
 /* Returns the hex integer that is after ':' for the FIELD.
    Returns -1 is returned if there was problem parsing the integer. */
 static unsigned
-parse_field (const char *field)
+parse_field (const std::string &field)
 {
-  const char *rest = strchr (field, ':');
+  const char *rest = strchr (field.c_str (), ':');
+
+  /* The line must be in the format of <name>:<value>, if it's not
+     then we have a weird format.  */
+  if (rest == NULL)
+    return -1;
+
   char *after;
   unsigned fint = strtol (rest + 1, &after, 16);
   if (after == rest + 1)
@@ -129,6 +136,76 @@ parse_field (const char *field)
   return fint;
 }
 
+/* Returns the index of the ':' inside the FIELD which must be found
+   after the value of KEY.  Returns string::npos if line does not contain
+   a field.  */
+
+static size_t
+find_field (const std::string &field, const std::string &key)
+{
+  size_t key_pos, sep_pos;
+  key_pos = field.find (key);
+  if (key_pos == std::string::npos)
+    return std::string::npos;
+
+  sep_pos = field.find (":", key_pos + 1);
+  if (sep_pos == std::string::npos)
+    return std::string::npos;
+
+  return sep_pos;
+}
+
+/* Splits and returns a string based on whitespace and return it as
+   part of a set. Empty strings are ignored.  */
+
+static void
+split_words (const std::string &val, std::set<std::string> &result)
+{
+  size_t cur, prev = 0;
+  std::string word;
+  while ((cur = val.find_first_of (" \n", prev)) != std::string::npos)
+    {
+      word = val.substr (prev, cur - prev);
+      /* Skip adding empty words.  */
+      if (!word.empty ())
+	result.insert (word);
+      prev = cur + 1;
+    }
+
+  if (prev != cur)
+    result.insert (val.substr (prev));
+}
+
+/* Read an entire line from F until '\n' or EOF.  */
+
+static std::string
+readline (FILE *f)
+{
+  char *buf = NULL;
+  int size = 0;
+  int last = 0;
+  const int buf_size = 128;
+
+  if (feof (f))
+    return std::string ();
+
+  do
+    {
+      size += buf_size;
+      buf = (char*) xrealloc (buf, size);
+      gcc_assert (buf);
+      fgets (buf + last, buf_size, f);
+      /* If we're not at the end of the line then override the
+	 \0 added by fgets.  */
+      last = strlen (buf) - 1;
+    }
+  while (!feof (f) && buf[last] != '\n');
+
+  std::string result (buf);
+  free (buf);
+  return result;
+}
+
 /*  Return true iff ARR contains CORE, in either of the two elements. */
 
 static bool
@@ -167,7 +244,6 @@ host_detect_local_cpu (int argc, const char **argv)
 {
   const char *res = NULL;
   static const int num_exts = ARRAY_SIZE (aarch64_extensions);
-  char buf[128];
   FILE *f = NULL;
   bool arch = false;
   bool tune = false;
@@ -181,6 +257,8 @@ host_detect_local_cpu (int argc, const char **argv)
   bool processed_exts = false;
   unsigned long extension_flags = 0;
   unsigned long default_flags = 0;
+  std::string buf;
+  size_t sep_pos = -1;
 
   gcc_assert (argc);
 
@@ -205,9 +283,9 @@ host_detect_local_cpu (int argc, const char **argv)
 
   /* Look through /proc/cpuinfo to determine the implementer
      and then the part number that identifies a particular core.  */
-  while (fgets (buf, sizeof (buf), f) != NULL)
+  while (!(buf = readline (f)).empty ())
     {
-      if (strstr (buf, "implementer") != NULL)
+      if (find_field (buf, "implementer") != std::string::npos)
 	{
 	  unsigned cimp = parse_field (buf);
 	  if (cimp == INVALID_IMP)
@@ -219,8 +297,7 @@ host_detect_local_cpu (int argc, const char **argv)
 	  else if (imp != cimp)
 	    goto not_found;
 	}
-
-      if (strstr (buf, "variant") != NULL)
+      else if (find_field (buf, "variant") != std::string::npos)
 	{
 	  unsigned cvariant = parse_field (buf);
 	  if (!contains_core_p (variants, cvariant))
@@ -232,8 +309,7 @@ host_detect_local_cpu (int argc, const char **argv)
 	    }
           continue;
         }
-
-      if (strstr (buf, "part") != NULL)
+      else if (find_field (buf, "part") != std::string::npos)
 	{
 	  unsigned ccore = parse_field (buf);
 	  if (!contains_core_p (cores, ccore))
@@ -245,39 +321,36 @@ host_detect_local_cpu (int argc, const char **argv)
 	    }
 	  continue;
 	}
-      if (!tune && !processed_exts && strstr (buf, "Features") != NULL)
+      else if (!tune && !processed_exts
+	       && (sep_pos = find_field (buf, "Features")) != std::string::npos)
 	{
+	  /* First create the list of features in the buffer.  */
+	  std::set<std::string> features;
+	  /* Drop everything till the :.  */
+	  buf = buf.substr (sep_pos + 1);
+	  split_words (buf, features);
+
 	  for (i = 0; i < num_exts; i++)
 	    {
-	      const char *p = aarch64_extensions[i].feat_string;
+	      const std::string val (aarch64_extensions[i].feat_string);
 
 	      /* If the feature contains no HWCAPS string then ignore it for the
 		 auto detection.  */
-	      if (*p == '\0')
+	      if (val.empty ())
 		continue;
 
 	      bool enabled = true;
 
 	      /* This may be a multi-token feature string.  We need
 		 to match all parts, which could be in any order.  */
-	      size_t len = strlen (buf);
-	      do
-		{
-		  const char *end = strchr (p, ' ');
-		  if (end == NULL)
-		    end = strchr (p, '\0');
-		  if (memmem (buf, len, p, end - p) == NULL)
-		    {
-		      /* Failed to match this token.  Turn off the
-			 features we'd otherwise enable.  */
-		      enabled = false;
-		      break;
-		    }
-		  if (*end == '\0')
-		    break;
-		  p = end + 1;
-		}
-	      while (1);
+	      std::set<std::string> tokens;
+	      split_words (val, tokens);
+	      std::set<std::string>::iterator it;
+
+	      /* Iterate till the first feature isn't found or all of them
+		 are found.  */
+	      for (it = tokens.begin (); enabled && it != tokens.end (); ++it)
+		enabled = enabled && features.count (*it);
 
 	      if (enabled)
 		extension_flags |= aarch64_extensions[i].flag;

commit 9c7fce1459ef1c99a168501c596d3b9c4f5955d3
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Fri Jul 17 13:10:53 2020 +0100

    AArch64: Add GCC_CPUINFO override
    
    This adds an in intentionally undocumented environment variable
    GCC_CPUINFO which can be used to test -mcpu=native.
    
    Tests using this are added later on.
    
    gcc/ChangeLog:
    
            * config/aarch64/driver-aarch64.c (host_detect_local_cpu):
            Add GCC_CPUINFO.
    
    (cherry picked from commit 55f6addc0c102eab2bf19d94de3ce52f9de0ab91)

diff --git a/gcc/config/aarch64/driver-aarch64.c b/gcc/config/aarch64/driver-aarch64.c
index 47cb97abe75..6dc7aa6d3be 100644
--- a/gcc/config/aarch64/driver-aarch64.c
+++ b/gcc/config/aarch64/driver-aarch64.c
@@ -259,6 +259,7 @@ host_detect_local_cpu (int argc, const char **argv)
   unsigned long default_flags = 0;
   std::string buf;
   size_t sep_pos = -1;
+  char *fcpu_info;
 
   gcc_assert (argc);
 
@@ -276,7 +277,11 @@ host_detect_local_cpu (int argc, const char **argv)
   if (!arch && !tune && !cpu)
     goto not_found;
 
-  f = fopen ("/proc/cpuinfo", "r");
+  fcpu_info = getenv ("GCC_CPUINFO");
+  if (fcpu_info)
+    f = fopen (fcpu_info, "r");
+  else
+    f = fopen ("/proc/cpuinfo", "r");
 
   if (f == NULL)
     goto not_found;

commit f7f6626f0398b9977a67a9e219302274c4121e3a
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Fri Jul 17 13:12:00 2020 +0100

    Arm: Add GCC_CPUINFO override
    
    This adds an in intentionally undocumented environment variable
    GCC_CPUINFO which can be used to test -mcpu=native.
    
    Tests using these are added later on.
    
    gcc/ChangeLog:
    
            * config/arm/driver-arm.c (host_detect_local_cpu): Add GCC_CPUINFO.
    
    (cherry picked from commit 34a6c43487caf3a2a0ec9c7c79c526d116abc8b9)

diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c
index dc2f1de01a8..a53c2272864 100644
--- a/gcc/config/arm/driver-arm.c
+++ b/gcc/config/arm/driver-arm.c
@@ -97,6 +97,7 @@ host_detect_local_cpu (int argc, const char **argv)
   FILE *f = NULL;
   bool arch;
   const struct vendor_cpu *cpu_table = NULL;
+  char *fcpu_info = NULL;
 
   if (argc < 1)
     goto not_found;
@@ -105,7 +106,12 @@ host_detect_local_cpu (int argc, const char **argv)
   if (!arch && strcmp (argv[0], "cpu") != 0 && strcmp (argv[0], "tune"))
     goto not_found;
 
-  f = fopen ("/proc/cpuinfo", "r");
+  fcpu_info = getenv ("GCC_CPUINFO");
+  if (fcpu_info)
+    f = fopen (fcpu_info, "r");
+  else
+    f = fopen ("/proc/cpuinfo", "r");
+
   if (f == NULL)
     goto not_found;
 

commit 8e93c77a7e0a93ecd9e068689f21b7e662e7b3cd
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Fri Jul 17 13:12:23 2020 +0100

    Testsuite: Make it easier to debug environment setting functions
    
    This adds verbose output to dg-set-compiler-env-var and dg-set-target-env-var
    so you can actually see what they're setting when you add -v -v.
    
    gcc/testsuite/ChangeLog:
    
            * lib/gcc-dg.exp (dg-set-compiler-env-var, dg-set-target-env-var): Add
            verbose output.
    
    (cherry picked from commit e410cbff5d5a408b7c64a0c426951afc2a24df93)

diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp
index 3770f698c46..81014b9a09a 100644
--- a/gcc/testsuite/lib/gcc-dg.exp
+++ b/gcc/testsuite/lib/gcc-dg.exp
@@ -429,7 +429,10 @@ proc dg-set-target-env-var { args } {
 	error "dg-set-target-env-var: need two arguments"
 	return
     }
-    lappend set_target_env_var [list [lindex $args 1] [lindex $args 2]]
+    set var [lindex $args 1]
+    set value [lindex $args 2]
+    verbose "dg-set-target-env-var $var $value" 2
+    lappend set_target_env_var [list $var $value]
 }
 
 proc set-target-env-var { } {
@@ -470,6 +473,7 @@ proc dg-set-compiler-env-var { args } {
     }
     set var [lindex $args 1]
     set value [lindex $args 2]
+    verbose "dg-set-compiler-env-var $var $value" 2
     if [info exists ::env($var)] {
       lappend saved_compiler_env_var [list $var 1 $::env($var)]
     } else {

commit b852fba56d66242b3d13719c3062c5cecaab2435
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Fri Jul 17 13:12:46 2020 +0100

    Testuite: Document environment setting directives
    
    This document some of the existing DejaGnu directives to modify
    environment variables before test or compiler invocations.
    
    gcc/ChangeLog:
    
            * doc/sourcebuild.texi (dg-set-compiler-env-var,
            dg-set-target-env-var): Document.
    
    (cherry picked from commit 7c4491e33d1be16bfb85d448862a8b956d35e4d8)

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 773ecf81c35..ad7dea3744c 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1238,6 +1238,18 @@ This DejaGnu directive compares @var{regexp} to the combined output
 that the test executable writes to @file{stdout} and @file{stderr}.
 @end table
 
+@subsubsection Specify environment variables for a test
+
+@table @code
+@item @{ dg-set-compiler-env-var @var{var_name} "@var{var_value}" @}
+Specify that the environment variable @var{var_name} needs to be set
+to @var{var_value} before invoking the compiler on the test file.
+
+@item @{ dg-set-target-env-var @var{var_name} "@var{var_value}" @}
+Specify that the environment variable @var{var_name} needs to be set
+to @var{var_value} before execution of the program created by the test.
+@end table
+
 @subsubsection Specify additional files for a test
 
 @table @code

commit 6b4efdeaa6d8aa276a17bb646f4c15a95a973de3
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Wed Jul 8 14:32:34 2020 +0100

    AArch64: Add test for -mcpu=native
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/cpunative/aarch64-cpunative.exp: New file.
            * gcc.target/aarch64/cpunative/info_0: New test.
            * gcc.target/aarch64/cpunative/info_1: New test.
            * gcc.target/aarch64/cpunative/info_10: New test.
            * gcc.target/aarch64/cpunative/info_11: New test.
            * gcc.target/aarch64/cpunative/info_12: New test.
            * gcc.target/aarch64/cpunative/info_13: New test.
            * gcc.target/aarch64/cpunative/info_14: New test.
            * gcc.target/aarch64/cpunative/info_15: New test.
            * gcc.target/aarch64/cpunative/info_2: New test.
            * gcc.target/aarch64/cpunative/info_3: New test.
            * gcc.target/aarch64/cpunative/info_4: New test.
            * gcc.target/aarch64/cpunative/info_5: New test.
            * gcc.target/aarch64/cpunative/info_6: New test.
            * gcc.target/aarch64/cpunative/info_7: New test.
            * gcc.target/aarch64/cpunative/info_8: New test.
            * gcc.target/aarch64/cpunative/info_9: New test.
            * gcc.target/aarch64/cpunative/native_cpu_0.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_1.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_10.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_13.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_14.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_2.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_3.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_4.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_5.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_6.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_7.c: New test.
            * gcc.target/aarch64/cpunative/native_cpu_8.c: New test.
    
    (cherry picked from commit 8bc83ee378e1cac65d75752b5137ec35d9e1aca1)

diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp b/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp
new file mode 100644
index 00000000000..ce80ca04b8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp
@@ -0,0 +1,35 @@
+# Copyright (C) 2014-2020 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an AArch64 target.
+if ![istarget aarch64*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_0 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_0
new file mode 100644
index 00000000000..ef4a3f606fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_0
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_1 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_1
new file mode 100644
index 00000000000..0f434bca285
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_1
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: fp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_10 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_10
new file mode 100644
index 00000000000..c6e9d7ca9e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_10
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: 
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_11 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_11
new file mode 100644
index 00000000000..fb76f7d45bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_11
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: asimd fp sb
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_12 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_12
new file mode 100644
index 00000000000..9b6aa7bc248
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_12
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: asimd fp ssbs
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_13 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_13
new file mode 100644
index 00000000000..ef4a3f606fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_13
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_14 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_14
new file mode 100644
index 00000000000..33897571513
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_14
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: Lorem ipsum dolor sit ametd rebum expetendis per at Dolor lucilius referrentur ei mei virtute eruditi eum ne Iisque verterem tacimates eu mea ei autem asimd fp asimddp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_15 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_15
new file mode 100644
index 00000000000..bc645394556
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_15
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: Lorem ipsum dolor sit ametd rebum expetendis per at Dolor lucilius referrentur ei mei virtute eruditi eum ne Iisque verter svesm4 asimd fp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_2 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_2
new file mode 100644
index 00000000000..965d37760ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_2
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: asimd
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_3 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_3
new file mode 100644
index 00000000000..0c276f884a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_3
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: asimd fp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_4 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_4
new file mode 100644
index 00000000000..716210c1417
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_4
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: asimd fp aes pmull sha1 sha2
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_5 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_5
new file mode 100644
index 00000000000..7a002e1c4c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_5
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: asimd fp fphp asimdhp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_6 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_6
new file mode 100644
index 00000000000..d341dfe86f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_6
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: asimd fp aes pmull sha1 sha2 fphp asimdhp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_7 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_7
new file mode 100644
index 00000000000..ccb784915d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_7
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: asimd pmull sha1 fp aes sha2 fphp asimdhp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_8 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_8
new file mode 100644
index 00000000000..d6d9d03a2a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_8
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: asimd sve fp
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_9 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_9
new file mode 100644
index 00000000000..c9aa4a9a07d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_9
@@ -0,0 +1,8 @@
+processor	: 0
+BogoMIPS	: 100.00
+Features	: asimd fp svesm4
+CPU implementer	: 0x41
+CPU architecture: 8
+CPU variant	: 0x0
+CPU part	: 0xd08
+CPU revision	: 2
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_0.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_0.c
new file mode 100644
index 00000000000..f155f51bae7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_0.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_0" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+crc\+dotprod} } } */
+
+/* Test a normal looking procinfo.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_1.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_1.c
new file mode 100644
index 00000000000..2cf0e89994b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_1" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+nosimd} } } */
+
+/* Test one where fp is on by default so turn off simd.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_10.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_10.c
new file mode 100644
index 00000000000..6a753965c52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_10.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_10" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+nofp\+nosimd} } } */
+
+/* Test one with no entry in feature list.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_13.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_13.c
new file mode 100644
index 00000000000..b7b3a8e13df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_13.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_13" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+crc\+dotprod} } } */
+
+/* Test one with mixed order of feature bits.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_14.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_14.c
new file mode 100644
index 00000000000..781ab1ebbfb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_14.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_14" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+dotprod} } } */
+
+/* Test one where valid feature bits are at a boundary > buffer size.   */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_2.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_2.c
new file mode 100644
index 00000000000..aad71f4347d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_2" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+nofp\+nosimd} } } */
+
+/* Test one where asimd is provided byt no fp.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_3.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_3.c
new file mode 100644
index 00000000000..50685c297db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_3.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_3" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a} } } */
+
+/* Test where asimd and fp are the only ones provided, these are default
+   and so shouldn't emit anything.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_4.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_4.c
new file mode 100644
index 00000000000..91ae809757a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_4" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+crypto} } } */
+
+/* Test one where all crypto bits are given so crypto should be enabled.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_5.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_5.c
new file mode 100644
index 00000000000..84139e58ee0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_5" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+fp16} } } */
+
+/* Test one where fp16 is available and so should be emitted.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_6.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_6.c
new file mode 100644
index 00000000000..da72052e623
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_6.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_6" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+fp16} } } */
+
+/* Test one where the feature bits for crypto and fp16 are given in
+   same order as declared in options file.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_7.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_7.c
new file mode 100644
index 00000000000..96ad4c14db1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_7.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_7" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+fp16} } } */
+
+/* Test one where the crypto and fp16 options are specified in different
+   order from what is in the options file.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_8.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_8.c
new file mode 100644
index 00000000000..7a5a2144a39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_8.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_8" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+sve} } } */
+
+/* Test one where sve is enabled.  */

commit 0dd0cfc6182f3fda92aea3930430b833bfd933ac
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Mon Aug 3 12:03:17 2020 +0100

    AArch64: Fix hwasan failure in readline.
    
    My previous fix added an unchecked call to fgets in the new function readline.
    fgets can fail when there's an error reading the file in which case it returns
    NULL.  It also returns NULL when the next character is EOF.
    
    The EOF case is already covered by the existing code but the error case isn't.
    This fixes it by returning the empty string on error.
    
    Also I now use strnlen instead of strlen to make sure we never read outside the
    buffer.
    
    This was flagged by Matthew Malcomson during his hwasan work.
    
    gcc/ChangeLog:
    
            * config/aarch64/driver-aarch64.c (readline): Check return value fgets.
    
    (cherry picked from commit 341573406b392f4d57e052ce22f80e85a7c479e9)

diff --git a/gcc/config/aarch64/driver-aarch64.c b/gcc/config/aarch64/driver-aarch64.c
index 6dc7aa6d3be..4c1e42edff8 100644
--- a/gcc/config/aarch64/driver-aarch64.c
+++ b/gcc/config/aarch64/driver-aarch64.c
@@ -194,10 +194,16 @@ readline (FILE *f)
       size += buf_size;
       buf = (char*) xrealloc (buf, size);
       gcc_assert (buf);
-      fgets (buf + last, buf_size, f);
+      /* If fgets fails it returns NULL, but if it reaches EOF
+	 with 0 characters read it also returns EOF.  However
+	 the condition on the loop would have broken out of the
+	 loop in that case,  and if we are in the first iteration
+	 then the empty string is the correct thing to return.  */
+      if (!fgets (buf + last, buf_size, f))
+	return std::string ();
       /* If we're not at the end of the line then override the
 	 \0 added by fgets.  */
-      last = strlen (buf) - 1;
+      last = strnlen (buf, size) - 1;
     }
   while (!feof (f) && buf[last] != '\n');
 

commit a1c02b7da22dae2f02af3345d3726f2dc6ecc322
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Fri Aug 21 19:07:06 2020 +0100

    Update links to Arm docs
    
    gcc/
            * doc/extend.texi: Update links to Arm docs.
            * doc/invoke.texi: Likewise.
    
    (cherry picked from commit 09698e44c766c4a05ee463d2e36bc1fdac21dce4)
    (cherry picked from commit 0fc33daacbdf993ab0d5830b0af3468b0df7c187)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 5cd33772104..08cc1fdddfc 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -13585,12 +13585,12 @@ long long __builtin_arm_wzero ()
 
 GCC implements extensions for C as described in the ARM C Language
 Extensions (ACLE) specification, which can be found at
-@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ihi0053c/IHI0053C_acle_2_0.pdf}.
+@uref{https://developer.arm.com/documentation/ihi0053/latest/}.
 
 As a part of ACLE, GCC implements extensions for Advanced SIMD as described in
 the ARM C Language Extensions Specification.  The complete list of Advanced SIMD
 intrinsics can be found at
-@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf}.
+@uref{https://developer.arm.com/documentation/ihi0073/latest/}.
 The built-in intrinsics for the Advanced SIMD extension are available when
 NEON is enabled.
 
@@ -13621,7 +13621,7 @@ void __builtin_arm_set_fpscr (unsigned int)
 GCC implements the ARMv8-M Security Extensions as described in the ARMv8-M
 Security Extensions: Requirements on Development Tools Engineering
 Specification, which can be found at
-@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf}.
+@uref{https://developer.arm.com/documentation/ecm0359818/latest/}.
 
 As part of the Security Extensions GCC implements two new function attributes:
 @code{cmse_nonsecure_entry} and @code{cmse_nonsecure_call}.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e48ccce1c6e..47126319e72 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -16745,7 +16745,7 @@ MOVT instruction.
 @opindex mcmse
 Generate secure code as per the "ARMv8-M Security Extensions: Requirements on
 Development Tools Engineering Specification", which can be found on
-@url{http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf}.
+@url{https://developer.arm.com/documentation/ecm0359818/latest/}.
 @end table
 
 @node AVR Options

commit 7cea2ec7f4e8ee39020bd0da65c5a51e87fe7515
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Aug 22 00:17:35 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c0d756c293f..98b0020e8a5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,51 @@
+2020-08-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	Backported from master:
+	2020-08-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* doc/extend.texi: Update links to Arm docs.
+	* doc/invoke.texi: Likewise.
+
+2020-08-21  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2020-08-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/aarch64/driver-aarch64.c (readline): Check return value fgets.
+
+2020-08-21  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2020-07-17  Tamar Christina  <tamar.christina@arm.com>
+
+	* doc/sourcebuild.texi (dg-set-compiler-env-var,
+	dg-set-target-env-var): Document.
+
+2020-08-21  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2020-07-17  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/arm/driver-arm.c (host_detect_local_cpu): Add GCC_CPUINFO.
+
+2020-08-21  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2020-07-17  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/aarch64/driver-aarch64.c (host_detect_local_cpu):
+	Add GCC_CPUINFO.
+
+2020-08-21  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2020-07-17  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/aarch64/driver-aarch64.c (INCLUDE_SET): New.
+	(parse_field): Use std::string.
+	(split_words, readline, find_field): New.
+	(host_detect_local_cpu): Fix truncation issues.
+
 2020-08-18  Uroš Bizjak  <ubizjak@gmail.com>
 
 	PR target/96536
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7ead9649335..faac5049dd8 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200821
+20200822
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2c96baf442d..ce527a32a78 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,46 @@
+2020-08-21  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2020-07-17  Tamar Christina  <tamar.christina@arm.com>
+
+	* gcc.target/aarch64/cpunative/aarch64-cpunative.exp: New file.
+	* gcc.target/aarch64/cpunative/info_0: New test.
+	* gcc.target/aarch64/cpunative/info_1: New test.
+	* gcc.target/aarch64/cpunative/info_10: New test.
+	* gcc.target/aarch64/cpunative/info_11: New test.
+	* gcc.target/aarch64/cpunative/info_12: New test.
+	* gcc.target/aarch64/cpunative/info_13: New test.
+	* gcc.target/aarch64/cpunative/info_14: New test.
+	* gcc.target/aarch64/cpunative/info_15: New test.
+	* gcc.target/aarch64/cpunative/info_2: New test.
+	* gcc.target/aarch64/cpunative/info_3: New test.
+	* gcc.target/aarch64/cpunative/info_4: New test.
+	* gcc.target/aarch64/cpunative/info_5: New test.
+	* gcc.target/aarch64/cpunative/info_6: New test.
+	* gcc.target/aarch64/cpunative/info_7: New test.
+	* gcc.target/aarch64/cpunative/info_8: New test.
+	* gcc.target/aarch64/cpunative/info_9: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_0.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_1.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_10.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_13.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_14.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_2.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_3.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_4.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_5.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_6.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_7.c: New test.
+	* gcc.target/aarch64/cpunative/native_cpu_8.c: New test.
+
+2020-08-21  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2020-07-17  Tamar Christina  <tamar.christina@arm.com>
+
+	* lib/gcc-dg.exp (dg-set-compiler-env-var, dg-set-target-env-var): Add
+	verbose output.
+
 2020-08-12  Kewen Lin  <linkw@linux.ibm.com>
 
 	PR testsuite/94077

commit e0a14adec0a3dd35df0aabff48143a04d78de300
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Aug 23 00:17:38 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index faac5049dd8..eec05c433b9 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200822
+20200823

commit ebc88f3958bce5d0f3f402e143a488fdf2b3e70a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Aug 24 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index eec05c433b9..d0461daaefd 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200823
+20200824

commit bb952c62eb57de20232977e42a714449d1f0e744
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Aug 25 00:17:32 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d0461daaefd..758e09d65f8 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200824
+20200825

commit 324ec2752c7e0fb09f512c4488091f17a4726f97
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Aug 26 00:17:51 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 758e09d65f8..1aa5e58d9a2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200825
+20200826

commit 7edec20c8f9a97b3c036158212b76211b7fe42df
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Aug 27 00:17:38 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1aa5e58d9a2..c7ea9e023ae 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200826
+20200827

commit d8f4b1df62154d4e46a5b0b04d8fbf6bceb767f2
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Aug 28 00:17:32 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c7ea9e023ae..7cd20fae38d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200827
+20200828

commit 1add9bf60be2e741e5c19d3547b898c3093adbd5
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Aug 29 00:17:32 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7cd20fae38d..cb50c2bdf0d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200828
+20200829

commit 3f65e214c0a7313bf30b71418c7bb40bdf0674a5
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Aug 30 00:17:32 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index cb50c2bdf0d..cf802bc822d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200829
+20200830

commit c4081a0b2574fb8e49313648f5a9dc14df94f492
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Aug 31 00:17:30 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index cf802bc822d..3db40e0a817 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200830
+20200831

commit 99f496bea7cc1107a62e0f0cc75bd40d84e672f0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Sep 1 00:17:39 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3db40e0a817..25aba91f392 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200831
+20200901

commit 16efd8a4e7df8393deda8f612b070d218283dabb
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Sep 2 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 25aba91f392..bbf1226868f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200901
+20200902

commit eeb970e1ca1685f90b10f61566ad497d0c991837
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Sep 3 00:17:39 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index bbf1226868f..38146c36fe4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200902
+20200903

commit b0d5e58993627f44ae614c2386561d8aa011855e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Sep 4 00:17:47 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 38146c36fe4..7b35a7c6950 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200903
+20200904

commit ad66fe28f3c06ba27af69a98bd6c61ba2e99c4f1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Sep 5 00:17:30 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7b35a7c6950..ed302f89446 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200904
+20200905

commit a1a04077d391ca9057f68d50a094648d190a060f
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Sep 6 00:17:32 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ed302f89446..1a5a0333d0d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200905
+20200906

commit 199467696e523a9638a7e59f427f76e1d628f773
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Sep 7 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1a5a0333d0d..1ab81bc2ef4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200906
+20200907

commit 611a899607c7e31209271c9603f3ac0d186f26a8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Sep 8 00:17:45 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1ab81bc2ef4..07b43358ffe 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200907
+20200908

commit 7ad1903e82e1f5ad4e48ceb3fe3c99b38eb77505
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Sep 9 00:17:41 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 07b43358ffe..31cfea49579 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200908
+20200909

commit b8c7eae4be6fccfe24ed36d618c0f2d67256e993
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Thu Sep 3 20:33:14 2020 +0200

    PR fortran/96890 - Wrong answer with intrinsic IALL
    
    The IALL intrinsic would always return 0 when the DIM and MASK arguments
    were present since the initial value of repeated BIT-AND operations was
    set to 0 instead of -1.
    
    libgfortran/ChangeLog:
    
            * m4/iall.m4: Initial value for result should be -1.
            * generated/iall_i1.c (miall_i1): Generated.
            * generated/iall_i16.c (miall_i16): Likewise.
            * generated/iall_i2.c (miall_i2): Likewise.
            * generated/iall_i4.c (miall_i4): Likewise.
            * generated/iall_i8.c (miall_i8): Likewise.
    
    gcc/testsuite/ChangeLog:
    
            * gfortran.dg/iall_masked.f90: New test.
    
    (cherry picked from commit 8eeeecbcc17041fdfd3ccc928161ae86e7f9b456)

diff --git a/gcc/testsuite/gfortran.dg/iall_masked.f90 b/gcc/testsuite/gfortran.dg/iall_masked.f90
new file mode 100644
index 00000000000..33cc4106a1b
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/iall_masked.f90
@@ -0,0 +1,22 @@
+! { dg-do run }
+! PR fortran/96890 - Wrong answer with intrinsic IALL
+program p
+  implicit none
+  integer :: iarr1(0), iarr2(2,2), iarr3(2,2,2)
+  logical :: mask1(0), mask2(2,2), mask3(2,2,2)
+
+  if (     iall(iarr1,    mask1) /=          -1                 ) stop 1
+  if (     iall(iarr1, 1, mask1) /=          -1                 ) stop 2
+
+  iarr2 = reshape ([  1,      2,       3,      4      ], shape (iarr2))
+  mask2 = reshape ([ .true., .false., .true., .false. ], shape (mask2))
+
+  if (any (iall(iarr2, 2, mask2) /=          [1,-1])            ) stop 3
+
+  iarr3 = reshape ([  1,      2,       3,      4,     &
+                      5,      6,       7,      8      ], shape (iarr3))
+  mask3 = reshape ([ .true., .false., .true., .false.,&
+                     .true., .false., .true., .false. ], shape (iarr3))
+
+  if (any (iall(iarr3, 2, mask3) /= reshape ([1,-1,5,-1],[2,2]))) stop 4
+end
diff --git a/libgfortran/generated/iall_i1.c b/libgfortran/generated/iall_i1.c
index 86318fc0b72..c0423aa9428 100644
--- a/libgfortran/generated/iall_i1.c
+++ b/libgfortran/generated/iall_i1.c
@@ -340,7 +340,7 @@ miall_i1 (gfc_array_i1 * const restrict retarray,
       msrc = mbase;
       {
 
-  result = 0;
+  result = (GFC_INTEGER_1) -1;
 	for (n = 0; n < len; n++, src += delta, msrc += mdelta)
 	  {
 
diff --git a/libgfortran/generated/iall_i16.c b/libgfortran/generated/iall_i16.c
index 7343306d0ff..024d9c87c9a 100644
--- a/libgfortran/generated/iall_i16.c
+++ b/libgfortran/generated/iall_i16.c
@@ -340,7 +340,7 @@ miall_i16 (gfc_array_i16 * const restrict retarray,
       msrc = mbase;
       {
 
-  result = 0;
+  result = (GFC_INTEGER_16) -1;
 	for (n = 0; n < len; n++, src += delta, msrc += mdelta)
 	  {
 
diff --git a/libgfortran/generated/iall_i2.c b/libgfortran/generated/iall_i2.c
index 4a9e7d4ddb1..38523c7eca8 100644
--- a/libgfortran/generated/iall_i2.c
+++ b/libgfortran/generated/iall_i2.c
@@ -340,7 +340,7 @@ miall_i2 (gfc_array_i2 * const restrict retarray,
       msrc = mbase;
       {
 
-  result = 0;
+  result = (GFC_INTEGER_2) -1;
 	for (n = 0; n < len; n++, src += delta, msrc += mdelta)
 	  {
 
diff --git a/libgfortran/generated/iall_i4.c b/libgfortran/generated/iall_i4.c
index 0cd0a8113b0..fb00b35d482 100644
--- a/libgfortran/generated/iall_i4.c
+++ b/libgfortran/generated/iall_i4.c
@@ -340,7 +340,7 @@ miall_i4 (gfc_array_i4 * const restrict retarray,
       msrc = mbase;
       {
 
-  result = 0;
+  result = (GFC_INTEGER_4) -1;
 	for (n = 0; n < len; n++, src += delta, msrc += mdelta)
 	  {
 
diff --git a/libgfortran/generated/iall_i8.c b/libgfortran/generated/iall_i8.c
index cbfb114300f..a88485f5812 100644
--- a/libgfortran/generated/iall_i8.c
+++ b/libgfortran/generated/iall_i8.c
@@ -340,7 +340,7 @@ miall_i8 (gfc_array_i8 * const restrict retarray,
       msrc = mbase;
       {
 
-  result = 0;
+  result = (GFC_INTEGER_8) -1;
 	for (n = 0; n < len; n++, src += delta, msrc += mdelta)
 	  {
 
diff --git a/libgfortran/m4/iall.m4 b/libgfortran/m4/iall.m4
index 89bcc732e09..da5d16bf3a4 100644
--- a/libgfortran/m4/iall.m4
+++ b/libgfortran/m4/iall.m4
@@ -35,7 +35,7 @@ ARRAY_FUNCTION(0,
 `  result &= *src;')
 
 MASKED_ARRAY_FUNCTION(0,
-`  result = 0;',
+`  result = ('rtype_name`) -1;',
 `  if (*msrc)
     result &= *src;')
 

commit 945644e2ab0cda9117deb6b66da0b24d6e75a5d8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Sep 10 00:17:38 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 31cfea49579..18b8812ec43 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200909
+20200910
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ce527a32a78..810caf53784 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-09-09  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-09-03  Harald Anlauf  <anlauf@gmx.de>
+
+	* gfortran.dg/iall_masked.f90: New test.
+
 2020-08-21  Tamar Christina  <tamar.christina@arm.com>
 
 	Backported from master:
diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog
index 65a16d1525c..e3cd3692ca8 100644
--- a/libgfortran/ChangeLog
+++ b/libgfortran/ChangeLog
@@ -1,3 +1,15 @@
+2020-09-09  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-09-03  Harald Anlauf  <anlauf@gmx.de>
+
+	* m4/iall.m4: Initial value for result should be -1.
+	* generated/iall_i1.c (miall_i1): Generated.
+	* generated/iall_i16.c (miall_i16): Likewise.
+	* generated/iall_i2.c (miall_i2): Likewise.
+	* generated/iall_i4.c (miall_i4): Likewise.
+	* generated/iall_i8.c (miall_i8): Likewise.
+
 2020-07-25  Dominique d'Humieres  <dhumieres.dominique@free.fr>
 
 	Backported from master:

commit 1fcb8430cfdbae0cf5abc1898d763bd4a3069d04
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Sep 11 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 18b8812ec43..15fb79cba7d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200910
+20200911

commit 877cdcc714704e242f477580d81397cc1d0fc90e
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Thu Sep 10 15:49:26 2020 +0100

    libstdc++: Enable assertions in constexpr string_view members [PR 71960]
    
    There is no longer any reason we can't just use __glibcxx_assert in
    constexpr functions. As long as the condition is true, there will be no
    call to std::__replacement_assert that would make the function
    ineligible for constant evaluation.
    
            PR libstdc++/71960
            * include/experimental/string_view (basic_string_view):
            Enable debug assertions.
            * include/std/string_view (basic_string_view):
            Likewise.

diff --git a/libstdc++-v3/include/experimental/string_view b/libstdc++-v3/include/experimental/string_view
index 2bbd9aa8a0a..107d801d8ee 100644
--- a/libstdc++-v3/include/experimental/string_view
+++ b/libstdc++-v3/include/experimental/string_view
@@ -178,8 +178,7 @@ inline namespace fundamentals_v1
       constexpr const _CharT&
       operator[](size_type __pos) const
       {
-	// TODO: Assert to restore in a way compatible with the constexpr.
-	// __glibcxx_assert(__pos < this->_M_len);
+	__glibcxx_assert(__pos < this->_M_len);
 	return *(this->_M_str + __pos);
       }
 
@@ -198,16 +197,14 @@ inline namespace fundamentals_v1
       constexpr const _CharT&
       front() const
       {
-	// TODO: Assert to restore in a way compatible with the constexpr.
-	// __glibcxx_assert(this->_M_len > 0);
+	__glibcxx_assert(this->_M_len > 0);
 	return *this->_M_str;
       }
 
       constexpr const _CharT&
       back() const
       {
-	// TODO: Assert to restore in a way compatible with the constexpr.
-	// __glibcxx_assert(this->_M_len > 0);
+	__glibcxx_assert(this->_M_len > 0);
 	return *(this->_M_str + this->_M_len - 1);
       }
 
diff --git a/libstdc++-v3/include/std/string_view b/libstdc++-v3/include/std/string_view
index 96962e39bf4..412cc17de24 100644
--- a/libstdc++-v3/include/std/string_view
+++ b/libstdc++-v3/include/std/string_view
@@ -169,8 +169,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
       constexpr const _CharT&
       operator[](size_type __pos) const noexcept
       {
-	// TODO: Assert to restore in a way compatible with the constexpr.
-	// __glibcxx_assert(__pos < this->_M_len);
+	__glibcxx_assert(__pos < this->_M_len);
 	return *(this->_M_str + __pos);
       }
 
@@ -187,16 +186,14 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
       constexpr const _CharT&
       front() const noexcept
       {
-	// TODO: Assert to restore in a way compatible with the constexpr.
-	// __glibcxx_assert(this->_M_len > 0);
+	__glibcxx_assert(this->_M_len > 0);
 	return *this->_M_str;
       }
 
       constexpr const _CharT&
       back() const noexcept
       {
-	// TODO: Assert to restore in a way compatible with the constexpr.
-	// __glibcxx_assert(this->_M_len > 0);
+	__glibcxx_assert(this->_M_len > 0);
 	return *(this->_M_str + this->_M_len - 1);
       }
 

commit 1521433e2b6bff583b227fe391fe9dcf02f6000e
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Wed Mar 18 23:19:12 2020 +0000

    libstdc++: Fix is_trivially_constructible (PR 94033)
    
    This attempts to make is_nothrow_constructible more robust (and
    efficient to compile) by not depending on is_constructible. Instead the
    __is_constructible intrinsic is used directly. The helper class
    __is_nt_constructible_impl which checks whether the construction is
    non-throwing now takes a bool template parameter that is substituted by
    the result of the instrinsic. This fixes the reported bug by not using
    the already-instantiated (and incorrect) value of std::is_constructible.
    I don't think it really fixes the problem in general, because
    std::is_nothrow_constructible itself could already have been
    instantiated in a context where it gives the wrong result. A proper fix
    needs to be done in the compiler.
    
    Backported to the gcc-8 and gcc-9 branches to fix PR 96999.
    
            PR libstdc++/94033
            * include/std/type_traits (__is_nt_default_constructible_atom): Remove.
            (__is_nt_default_constructible_impl): Remove.
            (__is_nothrow_default_constructible_impl): Remove.
            (__is_nt_constructible_impl): Add bool template parameter. Adjust
            partial specializations.
            (__is_nothrow_constructible_impl): Replace class template with alias
            template.
            (is_nothrow_default_constructible): Derive from alias template
            __is_nothrow_constructible_impl instead of
            __is_nothrow_default_constructible_impl.
            * testsuite/20_util/is_nothrow_constructible/94003.cc: New test.
    
    (cherry picked from commit b3341826531e80e02f194460b4fbe1b0541c0463)

diff --git a/libstdc++-v3/include/std/type_traits b/libstdc++-v3/include/std/type_traits
index e0394179963..6c32dd4a51f 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -915,55 +915,48 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
     : public __is_move_constructible_impl<_Tp>
     { };
 
-  template<typename _Tp>
-    struct __is_nt_default_constructible_atom
-    : public integral_constant<bool, noexcept(_Tp())>
+  template<bool, typename _Tp, typename... _Args>
+    struct __is_nt_constructible_impl
+    : public false_type
     { };
 
-  template<typename _Tp, bool = is_array<_Tp>::value>
-    struct __is_nt_default_constructible_impl;
+  template<typename _Tp, typename... _Args>
+    struct __is_nt_constructible_impl<true, _Tp, _Args...>
+    : public __bool_constant<noexcept(_Tp(std::declval<_Args>()...))>
+    { };
 
-  template<typename _Tp>
-    struct __is_nt_default_constructible_impl<_Tp, true>
-    : public __and_<__is_array_known_bounds<_Tp>,
-		    __is_nt_default_constructible_atom<typename
-                      remove_all_extents<_Tp>::type>>
+  template<typename _Tp, typename _Arg>
+    struct __is_nt_constructible_impl<true, _Tp, _Arg>
+    : public __bool_constant<noexcept(static_cast<_Tp>(std::declval<_Arg>()))>
     { };
 
   template<typename _Tp>
-    struct __is_nt_default_constructible_impl<_Tp, false>
-    : public __is_nt_default_constructible_atom<_Tp>
+    struct __is_nt_constructible_impl<true, _Tp>
+    : public __bool_constant<noexcept(_Tp())>
     { };
 
-  /// is_nothrow_default_constructible
-  template<typename _Tp>
-    struct is_nothrow_default_constructible
-    : public __and_<is_default_constructible<_Tp>,
-                    __is_nt_default_constructible_impl<_Tp>>
+  template<typename _Tp, size_t _Num>
+    struct __is_nt_constructible_impl<true, _Tp[_Num]>
+    : public __bool_constant<noexcept(typename remove_all_extents<_Tp>::type())>
     { };
 
   template<typename _Tp, typename... _Args>
-    struct __is_nt_constructible_impl
-    : public integral_constant<bool, noexcept(_Tp(declval<_Args>()...))>
-    { };
+    using __is_nothrow_constructible_impl
+      = __is_nt_constructible_impl<__is_constructible(_Tp, _Args...),
+				   _Tp, _Args...>;
 
-  template<typename _Tp, typename _Arg>
-    struct __is_nt_constructible_impl<_Tp, _Arg>
-    : public integral_constant<bool,
-                               noexcept(static_cast<_Tp>(declval<_Arg>()))>
+  /// is_nothrow_constructible
+  template<typename _Tp, typename... _Args>
+    struct is_nothrow_constructible
+    : public __is_nothrow_constructible_impl<_Tp, _Args...>::type
     { };
 
+  /// is_nothrow_default_constructible
   template<typename _Tp>
-    struct __is_nt_constructible_impl<_Tp>
-    : public is_nothrow_default_constructible<_Tp>
+    struct is_nothrow_default_constructible
+    : public __is_nothrow_constructible_impl<_Tp>::type
     { };
 
-  /// is_nothrow_constructible
-  template<typename _Tp, typename... _Args>
-    struct is_nothrow_constructible
-    : public __and_<is_constructible<_Tp, _Args...>,
-		    __is_nt_constructible_impl<_Tp, _Args...>>
-    { };
 
   template<typename _Tp, bool = __is_referenceable<_Tp>::value>
     struct __is_nothrow_copy_constructible_impl;
diff --git a/libstdc++-v3/testsuite/20_util/is_nothrow_constructible/94003.cc b/libstdc++-v3/testsuite/20_util/is_nothrow_constructible/94003.cc
new file mode 100644
index 00000000000..392a0878ba5
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/is_nothrow_constructible/94003.cc
@@ -0,0 +1,46 @@
+// Copyright (C) 2020 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-std=gnu++17" }
+// { dg-do compile { target c++17 } }
+
+#include <optional>
+#include <tuple>
+
+template <bool B> struct abc {};
+
+template <typename T>
+
+struct future : public abc<std::is_trivially_constructible_v<std::tuple<T>>> {};
+
+class mutation {
+  mutation();
+  friend class std::optional<mutation>;
+};
+
+using mutation_opt = std::optional<mutation>;
+
+future<mutation_opt> foo();
+
+template <typename Consumer> future<mutation_opt> consume_partitions() {
+  return foo();
+}
+
+future<mutation_opt> bar() { return consume_partitions<int>(); }
+
+future<mutation> zed();
+future<mutation> apply_counter_update() { return zed(); }
diff --git a/libstdc++-v3/testsuite/20_util/is_nothrow_default_constructible/96999.cc b/libstdc++-v3/testsuite/20_util/is_nothrow_default_constructible/96999.cc
new file mode 100644
index 00000000000..9ec42760051
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/is_nothrow_default_constructible/96999.cc
@@ -0,0 +1,54 @@
+// Copyright (C) 2020 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-std=gnu++17" }
+// { dg-do compile { target c++17 } }
+
+// PR libstdc++/96999
+
+#include <variant>
+#include <string>
+
+struct Foo {
+public:
+  explicit Foo(int) noexcept {}
+  Foo(Foo &&) noexcept = default;
+  Foo &operator=(Foo &&) = default;
+private:
+  Foo() noexcept {}
+};
+
+struct Boo {
+public:
+  explicit Boo(int) noexcept {}
+  Boo(Boo &&) noexcept = default;
+  Boo &operator=(Boo &&) = default;
+private:
+  Boo() noexcept {}
+};
+
+
+template<bool X>
+std::variant<Foo, Boo> g(int v, int x) {
+ return  v == 0 ? std::variant<Foo, Boo>{Foo{x}} :
+                                 std::variant<Foo, Boo>{Boo{x}};
+}
+
+int main()
+{
+  std::variant<std::variant<Foo, Boo>, std::string> err{std::string("aaa")};
+}

commit a46de9c7310c4927abc105e7d125c44e755bec60
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Sep 12 00:17:44 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 15fb79cba7d..c977cef8bc2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200911
+20200912
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 8cd063bfa9e..f477a26c38c 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,30 @@
+2020-09-11  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-03-18  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/94033
+	* include/std/type_traits (__is_nt_default_constructible_atom): Remove.
+	(__is_nt_default_constructible_impl): Remove.
+	(__is_nothrow_default_constructible_impl): Remove.
+	(__is_nt_constructible_impl): Add bool template parameter. Adjust
+	partial specializations.
+	(__is_nothrow_constructible_impl): Replace class template with alias
+	template.
+	(is_nothrow_default_constructible): Derive from alias template
+	__is_nothrow_constructible_impl instead of
+	__is_nothrow_default_constructible_impl.
+	* testsuite/20_util/is_nothrow_constructible/94003.cc: New test.
+	* testsuite/20_util/is_nothrow_default_constructible/96999.cc: New file.
+
+2020-09-11  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/71960
+	* include/experimental/string_view (basic_string_view):
+	Enable debug assertions.
+	* include/std/string_view (basic_string_view):
+	Likewise.
+
 2020-08-10  Jonathan Wakely  <jwakely@redhat.com>
 
 	* src/c++17/Makefile.in: Remove unused file.

commit f3a0968de4ff3be23263a0d31e4d2bcae69d2494
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Sep 13 00:17:33 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c977cef8bc2..9e832c96455 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200912
+20200913

commit 39e274a502f966c2b5841ba680a3e3edea1810ec
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Sep 14 00:17:37 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 9e832c96455..112e93fe6b5 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200913
+20200914

commit e7d3ab351008a409403f5f378c324316caa1bf47
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Sep 15 00:17:54 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 112e93fe6b5..792c97ce32d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200914
+20200915

commit db0fe2954f474e863e9c237a963b950a343612c5
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Sep 16 00:17:51 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 792c97ce32d..bc812c5fa15 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200915
+20200916

commit 2c55e6caa9432b2c1f081cb3aeddd36abec03233
Author: Sameera Deshpande <sameera.deshpande@linaro.org>
Date:   Thu May 31 08:46:20 2018 +0000

    Patch implementing vld1_*_x3, vst1_*_x2 and vst1_*_x3 intrinsics for AARCH64 for all types.
    
    2018-05-31  Sameera Deshpande  <sameera.deshpande@linaro.org>
    
    gcc/
            * config/aarch64/aarch64-simd-builtins.def (ld1x3): New.
            (st1x2): Likewise.
            (st1x3): Likewise.
            * config/aarch64/aarch64-simd.md
            (aarch64_ld1x3<VALLDIF:mode>): New pattern.
            (aarch64_ld1_x3_<mode>): Likewise
            (aarch64_st1x2<VALLDIF:mode>): Likewise
            (aarch64_st1_x2_<mode>): Likewise
            (aarch64_st1x3<VALLDIF:mode>): Likewise
            (aarch64_st1_x3_<mode>): Likewise
            * config/aarch64/arm_neon.h (vld1_u8_x3): New function.
            (vld1_s8_x3): Likewise.
            (vld1_u16_x3): Likewise.
            (vld1_s16_x3): Likewise.
            (vld1_u32_x3): Likewise.
            (vld1_s32_x3): Likewise.
            (vld1_u64_x3): Likewise.
            (vld1_s64_x3): Likewise.
            (vld1_f16_x3): Likewise.
            (vld1_f32_x3): Likewise.
            (vld1_f64_x3): Likewise.
            (vld1_p8_x3): Likewise.
            (vld1_p16_x3): Likewise.
            (vld1_p64_x3): Likewise.
            (vld1q_u8_x3): Likewise.
            (vld1q_s8_x3): Likewise.
            (vld1q_u16_x3): Likewise.
            (vld1q_s16_x3): Likewise.
            (vld1q_u32_x3): Likewise.
            (vld1q_s32_x3): Likewise.
            (vld1q_u64_x3): Likewise.
            (vld1q_s64_x3): Likewise.
            (vld1q_f16_x3): Likewise.
            (vld1q_f32_x3): Likewise.
            (vld1q_f64_x3): Likewise.
            (vld1q_p8_x3): Likewise.
            (vld1q_p16_x3): Likewise.
            (vld1q_p64_x3): Likewise.
            (vst1_s64_x2): Likewise.
            (vst1_u64_x2): Likewise.
            (vst1_f64_x2): Likewise.
            (vst1_s8_x2): Likewise.
            (vst1_p8_x2): Likewise.
            (vst1_s16_x2): Likewise.
            (vst1_p16_x2): Likewise.
            (vst1_s32_x2): Likewise.
            (vst1_u8_x2): Likewise.
            (vst1_u16_x2): Likewise.
            (vst1_u32_x2): Likewise.
            (vst1_f16_x2): Likewise.
            (vst1_f32_x2): Likewise.
            (vst1_p64_x2): Likewise.
            (vst1q_s8_x2): Likewise.
            (vst1q_p8_x2): Likewise.
            (vst1q_s16_x2): Likewise.
            (vst1q_p16_x2): Likewise.
            (vst1q_s32_x2): Likewise.
            (vst1q_s64_x2): Likewise.
            (vst1q_u8_x2): Likewise.
            (vst1q_u16_x2): Likewise.
            (vst1q_u32_x2): Likewise.
            (vst1q_u64_x2): Likewise.
            (vst1q_f16_x2): Likewise.
            (vst1q_f32_x2): Likewise.
            (vst1q_f64_x2): Likewise.
            (vst1q_p64_x2): Likewise.
            (vst1_s64_x3): Likewise.
            (vst1_u64_x3): Likewise.
            (vst1_f64_x3): Likewise.
            (vst1_s8_x3): Likewise.
            (vst1_p8_x3): Likewise.
            (vst1_s16_x3): Likewise.
            (vst1_p16_x3): Likewise.
            (vst1_s32_x3): Likewise.
            (vst1_u8_x3): Likewise.
            (vst1_u16_x3): Likewise.
            (vst1_u32_x3): Likewise.
            (vst1_f16_x3): Likewise.
            (vst1_f32_x3): Likewise.
            (vst1_p64_x3): Likewise.
            (vst1q_s8_x3): Likewise.
            (vst1q_p8_x3): Likewise.
            (vst1q_s16_x3): Likewise.
            (vst1q_p16_x3): Likewise.
            (vst1q_s32_x3): Likewise.
            (vst1q_s64_x3): Likewise.
            (vst1q_u8_x3): Likewise.
            (vst1q_u16_x3): Likewise.
            (vst1q_u32_x3): Likewise.
            (vst1q_u64_x3): Likewise.
            (vst1q_f16_x3): Likewise.
            (vst1q_f32_x3): Likewise.
            (vst1q_f64_x3): Likewise.
            (vst1q_p64_x3): Likewise.
    
    gcc/testsuite/
            * gcc.target/aarch64/advsimd-intrinsics/vld1x3.c: New test for
            vld1x3 intrinsics for aarch64.
            * gcc.target/aarch64/advsimd-intrinsics/vst1x2.c: New test for
            vst1x2 intrinsics for aarch64.
            * gcc.target/aarch64/advsimd-intrinsics/vst1x3.c: New test for
            vst1x3 intrinsics for aarch64.
    
    (cherry picked from commit 568421baa5a4cdb7bb7c5ac323c939492ee3f052)

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index b383f2485e5..2fd072a5896 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -445,6 +445,15 @@
   BUILTIN_VALL_F16 (STORE1, st1, 0)
   VAR1(STORE1P, st1, 0, v2di)
 
+  /* Implemented by aarch64_ld1x3<VALLDIF:mode>.  */
+  BUILTIN_VALLDIF (LOADSTRUCT, ld1x3, 0)
+
+  /* Implemented by aarch64_st1x2<VALLDIF:mode>.  */
+  BUILTIN_VALLDIF (STORESTRUCT, st1x2, 0)
+
+  /* Implemented by aarch64_st1x3<VALLDIF:mode>.  */
+  BUILTIN_VALLDIF (STORESTRUCT, st1x3, 0)
+
   /* Implemented by fma<mode>4.  */
   BUILTIN_VHSDF (TERNOP, fma, 4)
   VAR1 (TERNOP, fma, 4, hf)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index da664fc5d29..349337a6114 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5082,6 +5082,70 @@
     }
 })
 
+
+(define_expand "aarch64_ld1x3<VALLDIF:mode>"
+  [(match_operand:CI 0 "register_operand" "=w")
+   (match_operand:DI 1 "register_operand" "r")
+   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+  "TARGET_SIMD"
+{
+  rtx mem = gen_rtx_MEM (CImode, operands[1]);
+  emit_insn (gen_aarch64_ld1_x3_<VALLDIF:mode> (operands[0], mem));
+  DONE;
+})
+
+(define_insn "aarch64_ld1_x3_<mode>"
+  [(set (match_operand:CI 0 "register_operand" "=w")
+        (unspec:CI
+	  [(match_operand:CI 1 "aarch64_simd_struct_operand" "Utv")
+	   (unspec:VALLDIF [(const_int 3)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_LD1))]
+  "TARGET_SIMD"
+  "ld1\\t{%S0.<Vtype> - %U0.<Vtype>}, %1"
+  [(set_attr "type" "neon_load1_3reg<q>")]
+)
+
+(define_expand "aarch64_st1x2<VALLDIF:mode>"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:OI 1 "register_operand" "")
+   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+  "TARGET_SIMD"
+{
+  rtx mem = gen_rtx_MEM (OImode, operands[0]);
+  emit_insn (gen_aarch64_st1_x2_<VALLDIF:mode> (mem, operands[1]));
+  DONE;
+})
+
+(define_insn "aarch64_st1_x2_<mode>"
+   [(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv")
+	 (unspec:OI
+	  [(match_operand:OI 1 "register_operand" "w")
+          (unspec:VALLDIF [(const_int 2)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_ST1))]
+  "TARGET_SIMD"
+  "st1\\t{%S1.<Vtype> - %T1.<Vtype>}, %0"
+  [(set_attr "type" "neon_store1_2reg<q>")]
+)
+
+(define_expand "aarch64_st1x3<VALLDIF:mode>"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:CI 1 "register_operand" "")
+   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+  "TARGET_SIMD"
+{
+  rtx mem = gen_rtx_MEM (CImode, operands[0]);
+  emit_insn (gen_aarch64_st1_x3_<VALLDIF:mode> (mem, operands[1]));
+  DONE;
+})
+
+(define_insn "aarch64_st1_x3_<mode>"
+   [(set (match_operand:CI 0 "aarch64_simd_struct_operand" "=Utv")
+	(unspec:CI
+         [(match_operand:CI 1 "register_operand" "w")
+	  (unspec:VALLDIF [(const_int 3)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_ST1))]
+  "TARGET_SIMD"
+  "st1\\t{%S1.<Vtype> - %U1.<Vtype>}, %0"
+  [(set_attr "type" "neon_store1_3reg<q>")]
+)
+
 (define_insn "*aarch64_mov<mode>"
   [(set (match_operand:VSTRUCT 0 "aarch64_simd_nonimmediate_operand" "=w,Utv,w")
 	(match_operand:VSTRUCT 1 "aarch64_simd_general_operand" " w,w,Utv"))]
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 115cedcaa5b..f222811d6ef 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -17145,6 +17145,374 @@ vld1_u64 (const uint64_t *a)
   return (uint64x1_t) {*a};
 }
 
+/* vld1x3  */
+
+__extension__ extern __inline uint8x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u8_x3 (const uint8_t *__a)
+{
+  uint8x8x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = (__builtin_aarch64_simd_ci)__builtin_aarch64_ld1x3v8qi ((const __builtin_aarch64_simd_qi *) __a);
+  __i.val[0] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi  (__o, 0);
+  __i.val[1] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi  (__o, 1);
+  __i.val[2] = (uint8x8_t) __builtin_aarch64_get_dregciv8qi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline int8x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s8_x3 (const uint8_t *__a)
+{
+  int8x8x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v8qi ((const __builtin_aarch64_simd_qi *) __a);
+  __i.val[0] = (int8x8_t) __builtin_aarch64_get_dregciv8qi  (__o, 0);
+  __i.val[1] = (int8x8_t) __builtin_aarch64_get_dregciv8qi  (__o, 1);
+  __i.val[2] = (int8x8_t) __builtin_aarch64_get_dregciv8qi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline uint16x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u16_x3 (const uint16_t *__a)
+{
+  uint16x4x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v4hi ((const __builtin_aarch64_simd_hi *) __a);
+  __i.val[0] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi  (__o, 0);
+  __i.val[1] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi  (__o, 1);
+  __i.val[2] = (uint16x4_t) __builtin_aarch64_get_dregciv4hi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline int16x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s16_x3 (const int16_t *__a)
+{
+  int16x4x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v4hi ((const __builtin_aarch64_simd_hi *) __a);
+  __i.val[0] = (int16x4_t) __builtin_aarch64_get_dregciv4hi  (__o, 0);
+  __i.val[1] = (int16x4_t) __builtin_aarch64_get_dregciv4hi  (__o, 1);
+  __i.val[2] = (int16x4_t) __builtin_aarch64_get_dregciv4hi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline uint32x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u32_x3 (const uint32_t *__a)
+{
+  uint32x2x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v2si ((const __builtin_aarch64_simd_si *) __a);
+  __i.val[0] = (uint32x2_t) __builtin_aarch64_get_dregciv2si  (__o, 0);
+  __i.val[1] = (uint32x2_t) __builtin_aarch64_get_dregciv2si  (__o, 1);
+  __i.val[2] = (uint32x2_t) __builtin_aarch64_get_dregciv2si  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline int32x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s32_x3 (const uint32_t *__a)
+{
+  int32x2x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v2si ((const __builtin_aarch64_simd_si *) __a);
+  __i.val[0] = (int32x2_t) __builtin_aarch64_get_dregciv2si  (__o, 0);
+  __i.val[1] = (int32x2_t) __builtin_aarch64_get_dregciv2si  (__o, 1);
+  __i.val[2] = (int32x2_t) __builtin_aarch64_get_dregciv2si  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline uint64x1x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u64_x3 (const uint64_t *__a)
+{
+  uint64x1x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3di ((const __builtin_aarch64_simd_di *) __a);
+  __i.val[0] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+  __i.val[1] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+  __i.val[2] = (uint64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline int64x1x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s64_x3 (const int64_t *__a)
+{
+  int64x1x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3di ((const __builtin_aarch64_simd_di *) __a);
+  __i.val[0] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+  __i.val[1] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+  __i.val[2] = (int64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+
+  return __i;
+}
+
+__extension__ extern __inline float16x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f16_x3 (const float16_t *__a)
+{
+  float16x4x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v4hf ((const __builtin_aarch64_simd_hf *) __a);
+  __i.val[0] = (float16x4_t) __builtin_aarch64_get_dregciv4hf  (__o, 0);
+  __i.val[1] = (float16x4_t) __builtin_aarch64_get_dregciv4hf  (__o, 1);
+  __i.val[2] = (float16x4_t) __builtin_aarch64_get_dregciv4hf  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline float32x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f32_x3 (const float32_t *__a)
+{
+  float32x2x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v2sf ((const __builtin_aarch64_simd_sf *) __a);
+  __i.val[0] = (float32x2_t) __builtin_aarch64_get_dregciv2sf  (__o, 0);
+  __i.val[1] = (float32x2_t) __builtin_aarch64_get_dregciv2sf  (__o, 1);
+  __i.val[2] = (float32x2_t) __builtin_aarch64_get_dregciv2sf  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline float64x1x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f64_x3 (const float64_t *__a)
+{
+  float64x1x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3df ((const __builtin_aarch64_simd_df *) __a);
+  __i.val[0] = (float64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+  __i.val[1] = (float64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+  __i.val[2] = (float64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline poly8x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p8_x3 (const poly8_t *__a)
+{
+  poly8x8x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v8qi ((const __builtin_aarch64_simd_qi *) __a);
+  __i.val[0] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi  (__o, 0);
+  __i.val[1] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi  (__o, 1);
+  __i.val[2] = (poly8x8_t) __builtin_aarch64_get_dregciv8qi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline poly16x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p16_x3 (const poly16_t *__a)
+{
+  poly16x4x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v4hi ((const __builtin_aarch64_simd_hi *) __a);
+  __i.val[0] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi  (__o, 0);
+  __i.val[1] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi  (__o, 1);
+  __i.val[2] = (poly16x4_t) __builtin_aarch64_get_dregciv4hi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline poly64x1x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p64_x3 (const poly64_t *__a)
+{
+  poly64x1x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3di ((const __builtin_aarch64_simd_di *) __a);
+  __i.val[0] = (poly64x1_t) __builtin_aarch64_get_dregcidi (__o, 0);
+  __i.val[1] = (poly64x1_t) __builtin_aarch64_get_dregcidi (__o, 1);
+  __i.val[2] = (poly64x1_t) __builtin_aarch64_get_dregcidi (__o, 2);
+
+return __i;
+}
+
+__extension__ extern __inline uint8x16x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u8_x3 (const uint8_t *__a)
+{
+  uint8x16x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v16qi ((const __builtin_aarch64_simd_qi *) __a);
+  __i.val[0] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi  (__o, 0);
+  __i.val[1] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi  (__o, 1);
+  __i.val[2] = (uint8x16_t) __builtin_aarch64_get_qregciv16qi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline int8x16x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s8_x3 (const int8_t *__a)
+{
+  int8x16x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v16qi ((const __builtin_aarch64_simd_qi *) __a);
+  __i.val[0] = (int8x16_t) __builtin_aarch64_get_qregciv16qi  (__o, 0);
+  __i.val[1] = (int8x16_t) __builtin_aarch64_get_qregciv16qi  (__o, 1);
+  __i.val[2] = (int8x16_t) __builtin_aarch64_get_qregciv16qi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline uint16x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u16_x3 (const uint16_t *__a)
+{
+  uint16x8x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v8hi ((const __builtin_aarch64_simd_hi *) __a);
+  __i.val[0] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi  (__o, 0);
+  __i.val[1] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi  (__o, 1);
+  __i.val[2] = (uint16x8_t) __builtin_aarch64_get_qregciv8hi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline int16x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s16_x3 (const int16_t *__a)
+{
+  int16x8x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v8hi ((const __builtin_aarch64_simd_hi *) __a);
+  __i.val[0] = (int16x8_t) __builtin_aarch64_get_qregciv8hi  (__o, 0);
+  __i.val[1] = (int16x8_t) __builtin_aarch64_get_qregciv8hi  (__o, 1);
+  __i.val[2] = (int16x8_t) __builtin_aarch64_get_qregciv8hi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline uint32x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u32_x3 (const uint32_t *__a)
+{
+  uint32x4x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v4si ((const __builtin_aarch64_simd_si *) __a);
+  __i.val[0] = (uint32x4_t) __builtin_aarch64_get_qregciv4si  (__o, 0);
+  __i.val[1] = (uint32x4_t) __builtin_aarch64_get_qregciv4si  (__o, 1);
+  __i.val[2] = (uint32x4_t) __builtin_aarch64_get_qregciv4si  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline int32x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s32_x3 (const int32_t *__a)
+{
+  int32x4x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v4si ((const __builtin_aarch64_simd_si *) __a);
+  __i.val[0] = (int32x4_t) __builtin_aarch64_get_qregciv4si  (__o, 0);
+  __i.val[1] = (int32x4_t) __builtin_aarch64_get_qregciv4si  (__o, 1);
+  __i.val[2] = (int32x4_t) __builtin_aarch64_get_qregciv4si  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline uint64x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u64_x3 (const uint64_t *__a)
+{
+  uint64x2x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v2di ((const __builtin_aarch64_simd_di *) __a);
+  __i.val[0] = (uint64x2_t) __builtin_aarch64_get_qregciv2di  (__o, 0);
+  __i.val[1] = (uint64x2_t) __builtin_aarch64_get_qregciv2di  (__o, 1);
+  __i.val[2] = (uint64x2_t) __builtin_aarch64_get_qregciv2di  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline int64x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s64_x3 (const int64_t *__a)
+{
+  int64x2x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v2di ((const __builtin_aarch64_simd_di *) __a);
+  __i.val[0] = (int64x2_t) __builtin_aarch64_get_qregciv2di  (__o, 0);
+  __i.val[1] = (int64x2_t) __builtin_aarch64_get_qregciv2di  (__o, 1);
+  __i.val[2] = (int64x2_t) __builtin_aarch64_get_qregciv2di  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline float16x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f16_x3 (const float16_t *__a)
+{
+  float16x8x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v8hf ((const __builtin_aarch64_simd_hf *) __a);
+  __i.val[0] = (float16x8_t) __builtin_aarch64_get_qregciv8hf  (__o, 0);
+  __i.val[1] = (float16x8_t) __builtin_aarch64_get_qregciv8hf  (__o, 1);
+  __i.val[2] = (float16x8_t) __builtin_aarch64_get_qregciv8hf  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline float32x4x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f32_x3 (const float32_t *__a)
+{
+  float32x4x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v4sf ((const __builtin_aarch64_simd_sf *) __a);
+  __i.val[0] = (float32x4_t) __builtin_aarch64_get_qregciv4sf  (__o, 0);
+  __i.val[1] = (float32x4_t) __builtin_aarch64_get_qregciv4sf  (__o, 1);
+  __i.val[2] = (float32x4_t) __builtin_aarch64_get_qregciv4sf  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline float64x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f64_x3 (const float64_t *__a)
+{
+  float64x2x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v2df ((const __builtin_aarch64_simd_df *) __a);
+  __i.val[0] = (float64x2_t) __builtin_aarch64_get_qregciv2df  (__o, 0);
+  __i.val[1] = (float64x2_t) __builtin_aarch64_get_qregciv2df  (__o, 1);
+  __i.val[2] = (float64x2_t) __builtin_aarch64_get_qregciv2df  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline poly8x16x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p8_x3 (const poly8_t *__a)
+{
+  poly8x16x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v16qi ((const __builtin_aarch64_simd_qi *) __a);
+  __i.val[0] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi  (__o, 0);
+  __i.val[1] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi  (__o, 1);
+  __i.val[2] = (poly8x16_t) __builtin_aarch64_get_qregciv16qi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline poly16x8x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p16_x3 (const poly16_t *__a)
+{
+  poly16x8x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v8hi ((const __builtin_aarch64_simd_hi *) __a);
+  __i.val[0] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi  (__o, 0);
+  __i.val[1] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi  (__o, 1);
+  __i.val[2] = (poly16x8_t) __builtin_aarch64_get_qregciv8hi  (__o, 2);
+  return __i;
+}
+
+__extension__ extern __inline poly64x2x3_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p64_x3 (const poly64_t *__a)
+{
+  poly64x2x3_t __i;
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_ld1x3v2di ((const __builtin_aarch64_simd_di *) __a);
+  __i.val[0] = (poly64x2_t) __builtin_aarch64_get_qregciv2di  (__o, 0);
+  __i.val[1] = (poly64x2_t) __builtin_aarch64_get_qregciv2di  (__o, 1);
+  __i.val[2] = (poly64x2_t) __builtin_aarch64_get_qregciv2di  (__o, 2);
+  return __i;
+}
+
 /* vld1q */
 
 __extension__ extern __inline float16x8_t
@@ -27497,6 +27865,706 @@ vst1q_lane_u64 (uint64_t *__a, uint64x2_t __b, const int __lane)
   *__a = __aarch64_vget_lane_any (__b, __lane);
 }
 
+/* vst1x2 */
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s64_x2 (int64_t * __a, int64x1x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  int64x2x2_t temp;
+  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
+  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u64_x2 (uint64_t * __a, uint64x1x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  uint64x2x2_t temp;
+  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f64_x2 (float64_t * __a, float64x1x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  float64x2x2_t temp;
+  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2df ((__builtin_aarch64_simd_df *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s8_x2 (int8_t * __a, int8x8x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  int8x16x2_t temp;
+  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
+  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p8_x2 (poly8_t * __a, poly8x8x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  poly8x16x2_t temp;
+  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s16_x2 (int16_t * __a, int16x4x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  int16x8x2_t temp;
+  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
+  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p16_x2 (poly16_t * __a, poly16x4x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  poly16x8x2_t temp;
+  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s32_x2 (int32_t * __a, int32x2x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  int32x4x2_t temp;
+  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
+  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2v2si ((__builtin_aarch64_simd_si *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u8_x2 (uint8_t * __a, uint8x8x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  uint8x16x2_t temp;
+  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u16_x2 (uint16_t * __a, uint16x4x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  uint16x8x2_t temp;
+  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u32_x2 (uint32_t * __a, uint32x2x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  uint32x4x2_t temp;
+  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2v2si ((__builtin_aarch64_simd_si *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f16_x2 (float16_t * __a, float16x4x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  float16x8x2_t temp;
+  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv8hf (__o, temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv8hf (__o, temp.val[1], 1);
+  __builtin_aarch64_st1x2v4hf (__a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f32_x2 (float32_t * __a, float32x2x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  float32x4x2_t temp;
+  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p64_x2 (poly64_t * __a, poly64x1x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  poly64x2x2_t temp;
+  temp.val[0] = vcombine_p64 (val.val[0], vcreate_p64 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_p64 (val.val[1], vcreate_p64 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
+					       (poly64x2_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
+					       (poly64x2_t) temp.val[1], 1);
+  __builtin_aarch64_st1x2di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s8_x2 (int8_t * __a, int8x16x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p8_x2 (poly8_t * __a, poly8x16x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s16_x2 (int16_t * __a, int16x8x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p16_x2 (poly16_t * __a, poly16x8x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s32_x2 (int32_t * __a, int32x4x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v4si ((__builtin_aarch64_simd_si *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s64_x2 (int64_t * __a, int64x2x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v2di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u8_x2 (uint8_t * __a, uint8x16x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u16_x2 (uint16_t * __a, uint16x8x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u32_x2 (uint32_t * __a, uint32x4x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v4si ((__builtin_aarch64_simd_si *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u64_x2 (uint64_t * __a, uint64x2x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v2di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f16_x2 (float16_t * __a, float16x8x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv8hf (__o, val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv8hf (__o, val.val[1], 1);
+  __builtin_aarch64_st1x2v8hf (__a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f32_x2 (float32_t * __a, float32x4x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f64_x2 (float64_t * __a, float64x2x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v2df ((__builtin_aarch64_simd_df *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p64_x2 (poly64_t * __a, poly64x2x2_t val)
+{
+  __builtin_aarch64_simd_oi __o;
+  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
+					       (poly64x2_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregoiv2di_ssps (__o,
+					       (poly64x2_t) val.val[1], 1);
+  __builtin_aarch64_st1x2v2di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+/* vst1x3 */
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s64_x3 (int64_t * __a, int64x1x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  int64x2x3_t temp;
+  temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0)));
+  temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0)));
+  temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u64_x3 (uint64_t * __a, uint64x1x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  uint64x2x3_t temp;
+  temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0)));
+  temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f64_x3 (float64_t * __a, float64x1x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  float64x2x3_t temp;
+  temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0)));
+  temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3df ((__builtin_aarch64_simd_df *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s8_x3 (int8_t * __a, int8x8x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  int8x16x3_t temp;
+  temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0)));
+  temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0)));
+  temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p8_x3 (poly8_t * __a, poly8x8x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  poly8x16x3_t temp;
+  temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0)));
+  temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s16_x3 (int16_t * __a, int16x4x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  int16x8x3_t temp;
+  temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0)));
+  temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0)));
+  temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p16_x3 (poly16_t * __a, poly16x4x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  poly16x8x3_t temp;
+  temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0)));
+  temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s32_x3 (int32_t * __a, int32x2x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  int32x4x3_t temp;
+  temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0)));
+  temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0)));
+  temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3v2si ((__builtin_aarch64_simd_si *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u8_x3 (uint8_t * __a, uint8x8x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  uint8x16x3_t temp;
+  temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0)));
+  temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3v8qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u16_x3 (uint16_t * __a, uint16x4x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  uint16x8x3_t temp;
+  temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0)));
+  temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3v4hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u32_x3 (uint32_t * __a, uint32x2x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  uint32x4x3_t temp;
+  temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0)));
+  temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3v2si ((__builtin_aarch64_simd_si *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f16_x3 (float16_t * __a, float16x4x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  float16x8x3_t temp;
+  temp.val[0] = vcombine_f16 (val.val[0], vcreate_f16 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_f16 (val.val[1], vcreate_f16 (__AARCH64_UINT64_C (0)));
+  temp.val[2] = vcombine_f16 (val.val[2], vcreate_f16 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3v4hf ((__builtin_aarch64_simd_hf *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f32_x3 (float32_t * __a, float32x2x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  float32x4x3_t temp;
+  temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0)));
+  temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3v2sf ((__builtin_aarch64_simd_sf *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p64_x3 (poly64_t * __a, poly64x1x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  poly64x2x3_t temp;
+  temp.val[0] = vcombine_p64 (val.val[0], vcreate_p64 (__AARCH64_UINT64_C (0)));
+  temp.val[1] = vcombine_p64 (val.val[1], vcreate_p64 (__AARCH64_UINT64_C (0)));
+  temp.val[2] = vcombine_p64 (val.val[2], vcreate_p64 (__AARCH64_UINT64_C (0)));
+  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
+					       (poly64x2_t) temp.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
+					       (poly64x2_t) temp.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
+					       (poly64x2_t) temp.val[2], 2);
+  __builtin_aarch64_st1x3di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s8_x3 (int8_t * __a, int8x16x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p8_x3 (poly8_t * __a, poly8x16x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s16_x3 (int16_t * __a, int16x8x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p16_x3 (poly16_t * __a, poly16x8x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s32_x3 (int32_t * __a, int32x4x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v4si ((__builtin_aarch64_simd_si *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s64_x3 (int64_t * __a, int64x2x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v2di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u8_x3 (uint8_t * __a, uint8x16x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v16qi ((__builtin_aarch64_simd_qi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u16_x3 (uint16_t * __a, uint16x8x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v8hi ((__builtin_aarch64_simd_hi *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u32_x3 (uint32_t * __a, uint32x4x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v4si ((__builtin_aarch64_simd_si *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u64_x3 (uint64_t * __a, uint64x2x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v2di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f16_x3 (float16_t * __a, float16x8x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv8hf (__o, (float16x8_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v8hf ((__builtin_aarch64_simd_hf *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f32_x3 (float32_t * __a, float32x4x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v4sf ((__builtin_aarch64_simd_sf *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f64_x3 (float64_t * __a, float64x2x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v2df ((__builtin_aarch64_simd_df *) __a, __o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p64_x3 (poly64_t * __a, poly64x2x3_t val)
+{
+  __builtin_aarch64_simd_ci __o;
+  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
+					       (poly64x2_t) val.val[0], 0);
+  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
+					       (poly64x2_t) val.val[1], 1);
+  __o = __builtin_aarch64_set_qregciv2di_ssps (__o,
+					       (poly64x2_t) val.val[2], 2);
+  __builtin_aarch64_st1x3v2di ((__builtin_aarch64_simd_di *) __a, __o);
+}
+
 /* vstn */
 
 __extension__ extern __inline void
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
new file mode 100644
index 00000000000..6ddd507d9cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
@@ -0,0 +1,82 @@
+/* We haven't implemented these intrinsics for arm yet.  */
+/* { dg-xfail-if "" { arm*-*-* } } */
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+
+extern void abort (void);
+
+#define TESTMETH(BASE, ELTS, SUFFIX)	\
+int __attribute__ ((noinline))			\
+test_vld##SUFFIX##_x3 ()			\
+{						\
+  BASE##_t data[ELTS * 3];			\
+  BASE##_t temp[ELTS * 3];			\
+  BASE##x##ELTS##x##3##_t vectors;		\
+  int i,j;					\
+  for (i = 0; i < ELTS * 3; i++)		\
+    data [i] = (BASE##_t) 3*i;		\
+  asm volatile ("" : : : "memory");		\
+  vectors = vld1##SUFFIX##_x3 (data);		\
+  vst1##SUFFIX (temp, vectors.val[0]);		\
+  vst1##SUFFIX (&temp[ELTS], vectors.val[1]);	\
+  vst1##SUFFIX (&temp[ELTS * 2], vectors.val[2]);	\
+  asm volatile ("" : : : "memory");		\
+  for (j = 0; j < ELTS * 3; j++)		\
+    if (temp[j] != data[j]) 			\
+      return 1;					\
+  return 0;					\
+}
+
+#define VARIANTS_1(VARIANT)	\
+VARIANT (uint8, 8, _u8)		\
+VARIANT (uint16, 4, _u16)	\
+VARIANT (uint32, 2, _u32)	\
+VARIANT (uint64, 1, _u64)	\
+VARIANT (int8, 8, _s8)		\
+VARIANT (int16, 4, _s16)	\
+VARIANT (int32, 2, _s32)	\
+VARIANT (int64, 1, _s64)	\
+VARIANT (poly8, 8, _p8)		\
+VARIANT (poly16, 4, _p16)	\
+VARIANT (float16, 4, _f16)	\
+VARIANT (float32, 2, _f32)	\
+VARIANT (uint8, 16, q_u8)	\
+VARIANT (uint16, 8, q_u16)	\
+VARIANT (uint32, 4, q_u32)	\
+VARIANT (uint64, 2, q_u64)	\
+VARIANT (int8, 16, q_s8)	\
+VARIANT (int16, 8, q_s16)	\
+VARIANT (int32, 4, q_s32)	\
+VARIANT (int64, 2, q_s64)	\
+VARIANT (poly8, 16, q_p8)	\
+VARIANT (poly16, 8, q_p16)	\
+VARIANT (float16, 8, q_f16)	\
+VARIANT (float32, 4, q_f32)
+
+#ifdef __aarch64__
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (float64, 1, _f64)			\
+VARIANT (float64, 2, q_f64)
+#else
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#endif
+
+
+/* Tests of vld1_x3 and vld1q_x3.  */
+VARIANTS (TESTMETH)
+
+#define CHECKS(BASE, ELTS, SUFFIX)	\
+  if (test_vld##SUFFIX##_x3 () != 0)	\
+    fprintf (stderr, "test_vld1##SUFFIX##_x3");
+
+int
+main (int argc, char **argv)
+{
+  VARIANTS (CHECKS)
+
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
new file mode 100644
index 00000000000..cb13da0caed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
@@ -0,0 +1,80 @@
+/* We haven't implemented these intrinsics for arm yet.  */
+/* { dg-xfail-if "" { arm*-*-* } } */
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+
+extern void abort (void);
+
+#define TESTMETH(BASE, ELTS, SUFFIX)	\
+int __attribute__ ((noinline))			\
+test_vst1##SUFFIX##_x2 ()			\
+{						\
+  BASE##_t data[ELTS * 2];			\
+  BASE##_t temp[ELTS * 2];			\
+  BASE##x##ELTS##x##2##_t vectors;		\
+  int i,j;					\
+  for (i = 0; i < ELTS * 2; i++)		\
+    data [i] = (BASE##_t) 2*i;		\
+  asm volatile ("" : : : "memory");		\
+  vectors.val[0] = vld1##SUFFIX (data);		\
+  vectors.val[1] = vld1##SUFFIX (&data[ELTS]);	\
+  vst1##SUFFIX##_x2 (temp, vectors);		\
+  asm volatile ("" : : : "memory");		\
+  for (j = 0; j < ELTS * 2; j++)		\
+    if (temp[j] != data[j])			\
+      return 1;					\
+  return 0;					\
+}
+
+#define VARIANTS_1(VARIANT)	\
+VARIANT (uint8, 8, _u8)		\
+VARIANT (uint16, 4, _u16)	\
+VARIANT (uint32, 2, _u32)	\
+VARIANT (uint64, 1, _u64)	\
+VARIANT (int8, 8, _s8)		\
+VARIANT (int16, 4, _s16)	\
+VARIANT (int32, 2, _s32)	\
+VARIANT (int64, 1, _s64)	\
+VARIANT (poly8, 8, _p8)		\
+VARIANT (poly16, 4, _p16)	\
+VARIANT (float16, 4, _f16)	\
+VARIANT (float32, 2, _f32)	\
+VARIANT (uint8, 16, q_u8)	\
+VARIANT (uint16, 8, q_u16)	\
+VARIANT (uint32, 4, q_u32)	\
+VARIANT (uint64, 2, q_u64)	\
+VARIANT (int8, 16, q_s8)	\
+VARIANT (int16, 8, q_s16)	\
+VARIANT (int32, 4, q_s32)	\
+VARIANT (int64, 2, q_s64)	\
+VARIANT (poly8, 16, q_p8)	\
+VARIANT (poly16, 8, q_p16)	\
+VARIANT (float16, 8, q_f16)	\
+VARIANT (float32, 4, q_f32)
+
+#ifdef __aarch64__
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (float64, 1, _f64)			\
+VARIANT (float64, 2, q_f64)
+#else
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#endif
+
+/* Tests of vst1_x2 and vst1q_x2.  */
+VARIANTS (TESTMETH)
+
+#define CHECKS(BASE, ELTS, SUFFIX)	\
+  if (test_vst1##SUFFIX##_x2 () != 0)	\
+    fprintf (stderr, "test_vst1##SUFFIX##_x2");
+
+int
+main (int argc, char **argv)
+{
+  VARIANTS (CHECKS)
+
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
new file mode 100644
index 00000000000..3ce272a5007
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
@@ -0,0 +1,81 @@
+/* We haven't implemented these intrinsics for arm yet.  */
+/* { dg-xfail-if "" { arm*-*-* } } */
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+
+extern void abort (void);
+
+#define TESTMETH(BASE, ELTS, SUFFIX)	\
+int __attribute__ ((noinline))			\
+test_vst1##SUFFIX##_x3 ()			\
+{						\
+  BASE##_t data[ELTS * 3];			\
+  BASE##_t temp[ELTS * 3];			\
+  BASE##x##ELTS##x##3##_t vectors;		\
+  int i,j;					\
+  for (i = 0; i < ELTS * 3; i++)		\
+    data [i] = (BASE##_t) 3*i;		\
+  asm volatile ("" : : : "memory");		\
+  vectors.val[0] = vld1##SUFFIX (data);		\
+  vectors.val[1] = vld1##SUFFIX (&data[ELTS]);	\
+  vectors.val[2] = vld1##SUFFIX (&data[ELTS * 2]);	\
+  vst1##SUFFIX##_x3 (temp, vectors);		\
+  asm volatile ("" : : : "memory");		\
+  for (j = 0; j < ELTS * 3; j++)		\
+    if (temp[j] != data[j])			\
+      return 1;					\
+  return 0;					\
+}
+
+#define VARIANTS_1(VARIANT)	\
+VARIANT (uint8, 8, _u8)		\
+VARIANT (uint16, 4, _u16)	\
+VARIANT (uint32, 2, _u32)	\
+VARIANT (uint64, 1, _u64)	\
+VARIANT (int8, 8, _s8)		\
+VARIANT (int16, 4, _s16)	\
+VARIANT (int32, 2, _s32)	\
+VARIANT (int64, 1, _s64)	\
+VARIANT (poly8, 8, _p8)		\
+VARIANT (poly16, 4, _p16)	\
+VARIANT (float16, 4, _f16)	\
+VARIANT (float32, 2, _f32)	\
+VARIANT (uint8, 16, q_u8)	\
+VARIANT (uint16, 8, q_u16)	\
+VARIANT (uint32, 4, q_u32)	\
+VARIANT (uint64, 2, q_u64)	\
+VARIANT (int8, 16, q_s8)	\
+VARIANT (int16, 8, q_s16)	\
+VARIANT (int32, 4, q_s32)	\
+VARIANT (int64, 2, q_s64)	\
+VARIANT (poly8, 16, q_p8)	\
+VARIANT (poly16, 8, q_p16)	\
+VARIANT (float16, 8, q_f16)	\
+VARIANT (float32, 4, q_f32)
+
+#ifdef __aarch64__
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (float64, 1, _f64)			\
+VARIANT (float64, 2, q_f64)
+#else
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#endif
+
+/* Tests of vst1_x3 and vst1q_x3.  */
+VARIANTS (TESTMETH)
+
+#define CHECKS(BASE, ELTS, SUFFIX)	\
+  if (test_vst1##SUFFIX##_x3 () != 0)	\
+    fprintf (stderr, "test_vst1##SUFFIX##_x3");
+
+int
+main (int argc, char **argv)
+{
+  VARIANTS (CHECKS)
+
+  return 0;
+}
+

commit a4004f62d60ada3a20dbf30146ca461047a575cc
Author: Sylvia Taylor <sylvia.taylor@arm.com>
Date:   Thu Aug 22 11:28:26 2019 +0000

    add intrinsics for vld1(q)_x4 and vst1(q)_x4
    
    This patch adds the intrinsic functions for:
    - vld1_<mode>_x4
    - vst1_<mode>_x4
    - vld1q_<mode>_x4
    - vst1q_<mode>_x4
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    Committed on behalf of Sylvia Taylor.
    
    2019-08-22  Sylvia Taylor  <sylvia.taylor@arm.com>
    
    gcc/
            * config/aarch64/aarch64-simd-builtins.def:
            (ld1x4): New.
            (st1x4): Likewise.
            * config/aarch64/aarch64-simd.md:
            (aarch64_ld1x4<VALLDIF:mode>): New pattern.
            (aarch64_st1x4<VALLDIF:mode>): Likewise.
            (aarch64_ld1_x4_<mode>): Likewise.
            (aarch64_st1_x4_<mode>): Likewise.
            * config/aarch64/arm_neon.h:
            (vld1_s8_x4): New function.
            (vld1q_s8_x4): Likewise.
            (vld1_s16_x4): Likewise.
            (vld1q_s16_x4): Likewise.
            (vld1_s32_x4): Likewise.
            (vld1q_s32_x4): Likewise.
            (vld1_u8_x4): Likewise.
            (vld1q_u8_x4): Likewise.
            (vld1_u16_x4): Likewise.
            (vld1q_u16_x4): Likewise.
            (vld1_u32_x4): Likewise.
            (vld1q_u32_x4): Likewise.
            (vld1_f16_x4): Likewise.
            (vld1q_f16_x4): Likewise.
            (vld1_f32_x4): Likewise.
            (vld1q_f32_x4): Likewise.
            (vld1_p8_x4): Likewise.
            (vld1q_p8_x4): Likewise.
            (vld1_p16_x4): Likewise.
            (vld1q_p16_x4): Likewise.
            (vld1_s64_x4): Likewise.
            (vld1_u64_x4): Likewise.
            (vld1_p64_x4): Likewise.
            (vld1q_s64_x4): Likewise.
            (vld1q_u64_x4): Likewise.
            (vld1q_p64_x4): Likewise.
            (vld1_f64_x4): Likewise.
            (vld1q_f64_x4): Likewise.
            (vst1_s8_x4): Likewise.
            (vst1q_s8_x4): Likewise.
            (vst1_s16_x4): Likewise.
            (vst1q_s16_x4): Likewise.
            (vst1_s32_x4): Likewise.
            (vst1q_s32_x4): Likewise.
            (vst1_u8_x4): Likewise.
            (vst1q_u8_x4): Likewise.
            (vst1_u16_x4): Likewise.
            (vst1q_u16_x4): Likewise.
            (vst1_u32_x4): Likewise.
            (vst1q_u32_x4): Likewise.
            (vst1_f16_x4): Likewise.
            (vst1q_f16_x4): Likewise.
            (vst1_f32_x4): Likewise.
            (vst1q_f32_x4): Likewise.
            (vst1_p8_x4): Likewise.
            (vst1q_p8_x4): Likewise.
            (vst1_p16_x4): Likewise.
            (vst1q_p16_x4): Likewise.
            (vst1_s64_x4): Likewise.
            (vst1_u64_x4): Likewise.
            (vst1_p64_x4): Likewise.
            (vst1q_s64_x4): Likewise.
            (vst1q_u64_x4): Likewise.
            (vst1q_p64_x4): Likewise.
            (vst1_f64_x4): Likewise.
            (vst1q_f64_x4): Likewise.
    
    gcc/testsuite/
            * gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: New test.
            * gcc.target/aarch64/advsimd-intrinsics/vst1x4.c: New test.
    
    (cherry picked from commit 391625888d4d97f9016ab9ac04acc55d81f0c26f)

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 2fd072a5896..f71a40ef118 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -448,12 +448,18 @@
   /* Implemented by aarch64_ld1x3<VALLDIF:mode>.  */
   BUILTIN_VALLDIF (LOADSTRUCT, ld1x3, 0)
 
+  /* Implemented by aarch64_ld1x4<VALLDIF:mode>.  */
+  BUILTIN_VALLDIF (LOADSTRUCT, ld1x4, 0)
+
   /* Implemented by aarch64_st1x2<VALLDIF:mode>.  */
   BUILTIN_VALLDIF (STORESTRUCT, st1x2, 0)
 
   /* Implemented by aarch64_st1x3<VALLDIF:mode>.  */
   BUILTIN_VALLDIF (STORESTRUCT, st1x3, 0)
 
+  /* Implemented by aarch64_st1x4<VALLDIF:mode>.  */
+  BUILTIN_VALLDIF (STORESTRUCT, st1x4, 0)
+
   /* Implemented by fma<mode>4.  */
   BUILTIN_VHSDF (TERNOP, fma, 4)
   VAR1 (TERNOP, fma, 4, hf)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 349337a6114..3d21e0e48db 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5104,6 +5104,28 @@
   [(set_attr "type" "neon_load1_3reg<q>")]
 )
 
+(define_expand "aarch64_ld1x4<VALLDIF:mode>"
+  [(match_operand:XI 0 "register_operand" "=w")
+   (match_operand:DI 1 "register_operand" "r")
+   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+  "TARGET_SIMD"
+{
+  rtx mem = gen_rtx_MEM (XImode, operands[1]);
+  emit_insn (gen_aarch64_ld1_x4_<VALLDIF:mode> (operands[0], mem));
+  DONE;
+})
+
+(define_insn "aarch64_ld1_x4_<mode>"
+  [(set (match_operand:XI 0 "register_operand" "=w")
+	(unspec:XI
+	  [(match_operand:XI 1 "aarch64_simd_struct_operand" "Utv")
+	   (unspec:VALLDIF [(const_int 4)] UNSPEC_VSTRUCTDUMMY)]
+	UNSPEC_LD1))]
+  "TARGET_SIMD"
+  "ld1\\t{%S0.<Vtype> - %V0.<Vtype>}, %1"
+  [(set_attr "type" "neon_load1_4reg<q>")]
+)
+
 (define_expand "aarch64_st1x2<VALLDIF:mode>"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:OI 1 "register_operand" "")
@@ -5146,6 +5168,28 @@
   [(set_attr "type" "neon_store1_3reg<q>")]
 )
 
+(define_expand "aarch64_st1x4<VALLDIF:mode>"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:XI 1 "register_operand" "")
+   (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+  "TARGET_SIMD"
+{
+  rtx mem = gen_rtx_MEM (XImode, operands[0]);
+  emit_insn (gen_aarch64_st1_x4_<VALLDIF:mode> (mem, operands[1]));
+  DONE;
+})
+
+(define_insn "aarch64_st1_x4_<mode>"
+  [(set (match_operand:XI 0 "aarch64_simd_struct_operand" "=Utv")
+	(unspec:XI
+	   [(match_operand:XI 1 "register_operand" "w")
+	   (unspec:VALLDIF [(const_int 4)] UNSPEC_VSTRUCTDUMMY)]
+	UNSPEC_ST1))]
+  "TARGET_SIMD"
+  "st1\\t{%S1.<Vtype> - %V1.<Vtype>}, %0"
+  [(set_attr "type" "neon_store1_4reg<q>")]
+)
+
 (define_insn "*aarch64_mov<mode>"
   [(set (match_operand:VSTRUCT 0 "aarch64_simd_nonimmediate_operand" "=w,Utv,w")
 	(match_operand:VSTRUCT 1 "aarch64_simd_general_operand" " w,w,Utv"))]
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index f222811d6ef..dd53e243b52 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -17956,6 +17956,288 @@ vld1q_u64 (const uint64_t *a)
     __builtin_aarch64_ld1v2di ((const __builtin_aarch64_simd_di *) a);
 }
 
+/* vld1(q)_x4.  */
+
+__extension__ extern __inline int8x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s8_x4 (const int8_t *__a)
+{
+  union { int8x8x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v8qi ((const __builtin_aarch64_simd_qi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline int8x16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s8_x4 (const int8_t *__a)
+{
+  union { int8x16x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v16qi ((const __builtin_aarch64_simd_qi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline int16x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s16_x4 (const int16_t *__a)
+{
+  union { int16x4x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v4hi ((const __builtin_aarch64_simd_hi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline int16x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s16_x4 (const int16_t *__a)
+{
+  union { int16x8x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v8hi ((const __builtin_aarch64_simd_hi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline int32x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s32_x4 (const int32_t *__a)
+{
+  union { int32x2x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+  = __builtin_aarch64_ld1x4v2si ((const __builtin_aarch64_simd_si *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline int32x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s32_x4 (const int32_t *__a)
+{
+  union { int32x4x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+  = __builtin_aarch64_ld1x4v4si ((const __builtin_aarch64_simd_si *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline uint8x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u8_x4 (const uint8_t *__a)
+{
+  union { uint8x8x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v8qi ((const __builtin_aarch64_simd_qi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline uint8x16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u8_x4 (const uint8_t *__a)
+{
+  union { uint8x16x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v16qi ((const __builtin_aarch64_simd_qi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline uint16x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u16_x4 (const uint16_t *__a)
+{
+  union { uint16x4x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v4hi ((const __builtin_aarch64_simd_hi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline uint16x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u16_x4 (const uint16_t *__a)
+{
+  union { uint16x8x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v8hi ((const __builtin_aarch64_simd_hi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline uint32x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u32_x4 (const uint32_t *__a)
+{
+  union { uint32x2x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v2si ((const __builtin_aarch64_simd_si *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline uint32x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u32_x4 (const uint32_t *__a)
+{
+  union { uint32x4x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v4si ((const __builtin_aarch64_simd_si *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline float16x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f16_x4 (const float16_t *__a)
+{
+  union { float16x4x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v4hf ((const __builtin_aarch64_simd_hf *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline float16x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f16_x4 (const float16_t *__a)
+{
+  union { float16x8x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v8hf ((const __builtin_aarch64_simd_hf *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline float32x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f32_x4 (const float32_t *__a)
+{
+  union { float32x2x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v2sf ((const __builtin_aarch64_simd_sf *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline float32x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f32_x4 (const float32_t *__a)
+{
+  union { float32x4x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v4sf ((const __builtin_aarch64_simd_sf *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline poly8x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p8_x4 (const poly8_t *__a)
+{
+  union { poly8x8x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v8qi ((const __builtin_aarch64_simd_qi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline poly8x16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p8_x4 (const poly8_t *__a)
+{
+  union { poly8x16x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v16qi ((const __builtin_aarch64_simd_qi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline poly16x4x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p16_x4 (const poly16_t *__a)
+{
+  union { poly16x4x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v4hi ((const __builtin_aarch64_simd_hi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline poly16x8x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p16_x4 (const poly16_t *__a)
+{
+  union { poly16x8x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v8hi ((const __builtin_aarch64_simd_hi *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline int64x1x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_s64_x4 (const int64_t *__a)
+{
+  union { int64x1x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4di ((const __builtin_aarch64_simd_di *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline uint64x1x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_u64_x4 (const uint64_t *__a)
+{
+  union { uint64x1x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4di ((const __builtin_aarch64_simd_di *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline poly64x1x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_p64_x4 (const poly64_t *__a)
+{
+  union { poly64x1x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4di ((const __builtin_aarch64_simd_di *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline int64x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_s64_x4 (const int64_t *__a)
+{
+  union { int64x2x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v2di ((const __builtin_aarch64_simd_di *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline uint64x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_u64_x4 (const uint64_t *__a)
+{
+  union { uint64x2x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v2di ((const __builtin_aarch64_simd_di *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline poly64x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_p64_x4 (const poly64_t *__a)
+{
+  union { poly64x2x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v2di ((const __builtin_aarch64_simd_di *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline float64x1x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1_f64_x4 (const float64_t *__a)
+{
+  union { float64x1x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4df ((const __builtin_aarch64_simd_df *) __a);
+  return __au.__i;
+}
+
+__extension__ extern __inline float64x2x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vld1q_f64_x4 (const float64_t *__a)
+{
+  union { float64x2x4_t __i; __builtin_aarch64_simd_xi __o; } __au;
+  __au.__o
+    = __builtin_aarch64_ld1x4v2df ((const __builtin_aarch64_simd_df *) __a);
+  return __au.__i;
+}
+
 /* vld1_dup  */
 
 __extension__ extern __inline float16x4_t
@@ -28565,6 +28847,232 @@ vst1q_p64_x3 (poly64_t * __a, poly64x2x3_t val)
   __builtin_aarch64_st1x3v2di ((__builtin_aarch64_simd_di *) __a, __o);
 }
 
+/* vst1(q)_x4.  */
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s8_x4 (int8_t * __a, int8x8x4_t val)
+{
+  union { int8x8x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v8qi ((__builtin_aarch64_simd_qi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s8_x4 (int8_t * __a, int8x16x4_t val)
+{
+  union { int8x16x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v16qi ((__builtin_aarch64_simd_qi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s16_x4 (int16_t * __a, int16x4x4_t val)
+{
+  union { int16x4x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v4hi ((__builtin_aarch64_simd_hi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s16_x4 (int16_t * __a, int16x8x4_t val)
+{
+  union { int16x8x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v8hi ((__builtin_aarch64_simd_hi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s32_x4 (int32_t * __a, int32x2x4_t val)
+{
+  union { int32x2x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v2si ((__builtin_aarch64_simd_si *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s32_x4 (int32_t * __a, int32x4x4_t val)
+{
+  union { int32x4x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v4si ((__builtin_aarch64_simd_si *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u8_x4 (uint8_t * __a, uint8x8x4_t val)
+{
+  union { uint8x8x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v8qi ((__builtin_aarch64_simd_qi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u8_x4 (uint8_t * __a, uint8x16x4_t val)
+{
+  union { uint8x16x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v16qi ((__builtin_aarch64_simd_qi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u16_x4 (uint16_t * __a, uint16x4x4_t val)
+{
+  union { uint16x4x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v4hi ((__builtin_aarch64_simd_hi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u16_x4 (uint16_t * __a, uint16x8x4_t val)
+{
+  union { uint16x8x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v8hi ((__builtin_aarch64_simd_hi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u32_x4 (uint32_t * __a, uint32x2x4_t val)
+{
+  union { uint32x2x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v2si ((__builtin_aarch64_simd_si *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u32_x4 (uint32_t * __a, uint32x4x4_t val)
+{
+  union { uint32x4x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v4si ((__builtin_aarch64_simd_si *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f16_x4 (float16_t * __a, float16x4x4_t val)
+{
+  union { float16x4x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v4hf ((__builtin_aarch64_simd_hf *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f16_x4 (float16_t * __a, float16x8x4_t val)
+{
+  union { float16x8x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v8hf ((__builtin_aarch64_simd_hf *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f32_x4 (float32_t * __a, float32x2x4_t val)
+{
+  union { float32x2x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v2sf ((__builtin_aarch64_simd_sf *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f32_x4 (float32_t * __a, float32x4x4_t val)
+{
+  union { float32x4x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v4sf ((__builtin_aarch64_simd_sf *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p8_x4 (poly8_t * __a, poly8x8x4_t val)
+{
+  union { poly8x8x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v8qi ((__builtin_aarch64_simd_qi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p8_x4 (poly8_t * __a, poly8x16x4_t val)
+{
+  union { poly8x16x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v16qi ((__builtin_aarch64_simd_qi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p16_x4 (poly16_t * __a, poly16x4x4_t val)
+{
+  union { poly16x4x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v4hi ((__builtin_aarch64_simd_hi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p16_x4 (poly16_t * __a, poly16x8x4_t val)
+{
+  union { poly16x8x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v8hi ((__builtin_aarch64_simd_hi *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s64_x4 (int64_t * __a, int64x1x4_t val)
+{
+  union { int64x1x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4di ((__builtin_aarch64_simd_di *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u64_x4 (uint64_t * __a, uint64x1x4_t val)
+{
+  union { uint64x1x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4di ((__builtin_aarch64_simd_di *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p64_x4 (poly64_t * __a, poly64x1x4_t val)
+{
+  union { poly64x1x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4di ((__builtin_aarch64_simd_di *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s64_x4 (int64_t * __a, int64x2x4_t val)
+{
+  union { int64x2x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v2di ((__builtin_aarch64_simd_di *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u64_x4 (uint64_t * __a, uint64x2x4_t val)
+{
+  union { uint64x2x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v2di ((__builtin_aarch64_simd_di *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p64_x4 (poly64_t * __a, poly64x2x4_t val)
+{
+  union { poly64x2x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v2di ((__builtin_aarch64_simd_di *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f64_x4 (float64_t * __a, float64x1x4_t val)
+{
+  union { float64x1x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4df ((__builtin_aarch64_simd_df *) __a, __u.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f64_x4 (float64_t * __a, float64x2x4_t val)
+{
+  union { float64x2x4_t __i; __builtin_aarch64_simd_xi __o; } __u = { val };
+  __builtin_aarch64_st1x4v2df ((__builtin_aarch64_simd_df *) __a, __u.__o);
+}
+
 /* vstn */
 
 __extension__ extern __inline void
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
new file mode 100644
index 00000000000..451a0afc6aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
@@ -0,0 +1,83 @@
+/* We haven't implemented these intrinsics for arm yet.  */
+/* { dg-xfail-if "" { arm*-*-* } } */
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+
+extern void abort (void);
+
+#define TESTMETH(BASE, ELTS, SUFFIX)			\
+int __attribute__ ((noinline))				\
+test_vld1##SUFFIX##_x4 ()				\
+{							\
+  BASE##_t data[ELTS * 4];				\
+  BASE##_t temp[ELTS * 4];				\
+  BASE##x##ELTS##x##4##_t vectors;			\
+  int i,j;						\
+  for (i = 0; i < ELTS * 4; i++)			\
+    data [i] = (BASE##_t) 4*i;				\
+  asm volatile ("" : : : "memory");			\
+  vectors = vld1##SUFFIX##_x4 (data);			\
+  vst1##SUFFIX (temp, vectors.val[0]);			\
+  vst1##SUFFIX (&temp[ELTS], vectors.val[1]);		\
+  vst1##SUFFIX (&temp[ELTS * 2], vectors.val[2]);	\
+  vst1##SUFFIX (&temp[ELTS * 3], vectors.val[3]);	\
+  asm volatile ("" : : : "memory");			\
+  for (j = 0; j < ELTS * 4; j++)			\
+    if (temp[j] != data[j])				\
+      return 1;						\
+  return 0;						\
+}
+
+#define VARIANTS_1(VARIANT)	\
+VARIANT (uint8, 8, _u8)		\
+VARIANT (uint16, 4, _u16)	\
+VARIANT (uint32, 2, _u32)	\
+VARIANT (uint64, 1, _u64)	\
+VARIANT (int8, 8, _s8)		\
+VARIANT (int16, 4, _s16)	\
+VARIANT (int32, 2, _s32)	\
+VARIANT (int64, 1, _s64)	\
+VARIANT (poly8, 8, _p8)		\
+VARIANT (poly16, 4, _p16)	\
+VARIANT (poly64, 1, _p64)	\
+VARIANT (float16, 4, _f16)	\
+VARIANT (float32, 2, _f32)	\
+VARIANT (uint8, 16, q_u8)	\
+VARIANT (uint16, 8, q_u16)	\
+VARIANT (uint32, 4, q_u32)	\
+VARIANT (uint64, 2, q_u64)	\
+VARIANT (int8, 16, q_s8)	\
+VARIANT (int16, 8, q_s16)	\
+VARIANT (int32, 4, q_s32)	\
+VARIANT (int64, 2, q_s64)	\
+VARIANT (poly8, 16, q_p8)	\
+VARIANT (poly16, 8, q_p16)	\
+VARIANT (poly64, 2, q_p64)	\
+VARIANT (float16, 8, q_f16)	\
+VARIANT (float32, 4, q_f32)
+
+#ifdef __aarch64__
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (float64, 1, _f64)			\
+VARIANT (float64, 2, q_f64)
+#else
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#endif
+
+/* Tests of vld1_x4 and vld1q_x4.  */
+VARIANTS (TESTMETH)
+
+#define CHECKS(BASE, ELTS, SUFFIX)	\
+  if (test_vld1##SUFFIX##_x4 () != 0)	\
+    fprintf (stderr, "test_vld1##SUFFIX##_x4");
+
+int
+main (int argc, char **argv)
+{
+  VARIANTS (CHECKS)
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
new file mode 100644
index 00000000000..1f17b5342de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
@@ -0,0 +1,83 @@
+/* We haven't implemented these intrinsics for arm yet.  */
+/* { dg-xfail-if "" { arm*-*-* } } */
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+
+extern void abort (void);
+
+#define TESTMETH(BASE, ELTS, SUFFIX)			\
+int __attribute__ ((noinline))				\
+test_vst1##SUFFIX##_x4 ()				\
+{							\
+  BASE##_t data[ELTS * 4];				\
+  BASE##_t temp[ELTS * 4];				\
+  BASE##x##ELTS##x##4##_t vectors;			\
+  int i,j;						\
+  for (i = 0; i < ELTS * 4; i++)			\
+    data [i] = (BASE##_t) 4*i;				\
+  asm volatile ("" : : : "memory");			\
+  vectors.val[0] = vld1##SUFFIX (data);			\
+  vectors.val[1] = vld1##SUFFIX (&data[ELTS]);		\
+  vectors.val[2] = vld1##SUFFIX (&data[ELTS * 2]);	\
+  vectors.val[3] = vld1##SUFFIX (&data[ELTS * 3]);	\
+  vst1##SUFFIX##_x4 (temp, vectors);			\
+  asm volatile ("" : : : "memory");			\
+  for (j = 0; j < ELTS * 4; j++)			\
+    if (temp[j] != data[j])				\
+      return 1;						\
+  return 0;						\
+}
+
+#define VARIANTS_1(VARIANT)	\
+VARIANT (uint8, 8, _u8)		\
+VARIANT (uint16, 4, _u16)	\
+VARIANT (uint32, 2, _u32)	\
+VARIANT (uint64, 1, _u64)	\
+VARIANT (int8, 8, _s8)		\
+VARIANT (int16, 4, _s16)	\
+VARIANT (int32, 2, _s32)	\
+VARIANT (int64, 1, _s64)	\
+VARIANT (poly8, 8, _p8)		\
+VARIANT (poly16, 4, _p16)	\
+VARIANT (poly64, 1, _p64)	\
+VARIANT (float16, 4, _f16)	\
+VARIANT (float32, 2, _f32)	\
+VARIANT (uint8, 16, q_u8)	\
+VARIANT (uint16, 8, q_u16)	\
+VARIANT (uint32, 4, q_u32)	\
+VARIANT (uint64, 2, q_u64)	\
+VARIANT (int8, 16, q_s8)	\
+VARIANT (int16, 8, q_s16)	\
+VARIANT (int32, 4, q_s32)	\
+VARIANT (int64, 2, q_s64)	\
+VARIANT (poly8, 16, q_p8)	\
+VARIANT (poly16, 8, q_p16)	\
+VARIANT (poly64, 2, q_p64)	\
+VARIANT (float16, 8, q_f16)	\
+VARIANT (float32, 4, q_f32)
+
+#ifdef __aarch64__
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (float64, 1, _f64)			\
+VARIANT (float64, 2, q_f64)
+#else
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#endif
+
+/* Tests of vst1_x4 and vst1q_x4.  */
+VARIANTS (TESTMETH)
+
+#define CHECKS(BASE, ELTS, SUFFIX)	\
+  if (test_vst1##SUFFIX##_x4 () != 0)	\
+    fprintf (stderr, "test_vst1##SUFFIX##_x4");
+
+int
+main (int argc, char **argv)
+{
+  VARIANTS (CHECKS)
+
+  return 0;
+}

commit 74c624523bdbe4329c7cb77bff222ac695e36c95
Author: Will Schmidt <will_schmidt@vnet.ibm.com>
Date:   Wed Sep 16 11:21:04 2020 -0500

    [PATCH, rs6000] Fix vector long long subtype (PR96139)
    
    Hi,
    This corrects an issue with the powerpc vector long long subtypes.
    As reported by SjMunroe, when building some code with -Wall, and
    attempting to print an element of a "long long vector" with a
    long long printf format string, we will report an error because
    the vector sub-type was improperly defined as int.
    
    When defining a V2DI_type_node we use a TARGET_POWERPC64 ternary to
    define the V2DI_type_node with "vector long" or "vector long long".
    We also need to specify the proper sub-type when we define the type.
    
    Due to some file renames, This is a backport and rework of both
        [PATCH, rs6000] Fix vector long long subtype (PR96139)
    and
        [PATCH, rs6000] Testsuite fixup pr96139 tests
    
    
            PR target/96139
    
    gcc/ChangeLog:
            * config/rs6000/rs6000.c (rs6000_init_builtin): Update V2DI_type_node
              and unsigned_V2DI_type_node definitions.
    
    gcc/testsuite/ChangeLog:
            * gcc.target/powerpc/pr96139-a.c: New test.
            * gcc.target/powerpc/pr96139-b.c: New test.
            * gcc.target/powerpc/pr96139-c.c: New test.

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 53490f796cd..261e2aa808f 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -17275,7 +17275,7 @@ rs6000_init_builtins (void)
   V2SF_type_node = build_vector_type (float_type_node, 2);
   V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
 				       : "__vector long long",
-				       intDI_type_node, 2);
+				       long_long_integer_type_node, 2);
   V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
   V4SI_type_node = rs6000_vector_type ("__vector signed int",
 				       intSI_type_node, 4);
@@ -17294,7 +17294,7 @@ rs6000_init_builtins (void)
   unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
 				       ? "__vector unsigned long"
 				       : "__vector unsigned long long",
-				       unsigned_intDI_type_node, 2);
+				       long_long_unsigned_type_node, 2);
 
   opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
   opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
diff --git a/gcc/testsuite/gcc.target/powerpc/pr96139-a.c b/gcc/testsuite/gcc.target/powerpc/pr96139-a.c
new file mode 100644
index 00000000000..12a3383902c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr96139-a.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wall -m32 -mvsx" } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+#include <stdio.h>
+#include <altivec.h>
+
+void
+try_printing_longlong_a (
+                        __vector signed char cval,
+                        __vector signed int ival,
+                        __vector signed long long int llval,
+                        int x, int y, int z)
+{
+  printf (" %016llx \n", llval[x]);
+  printf (" %016x \n", ival[z]);
+  printf (" %c \n", cval[y]);
+}
+
+void
+try_printing_unsigned_longlong_a (
+                        __vector unsigned char cval,
+                        __vector unsigned int ival,
+                        __vector unsigned long long int llval,
+                        int x, int y, int z)
+{
+  printf (" %016llx \n", llval[x]);
+  printf (" %016x \n", ival[z]);
+  printf (" %c \n", cval[y]);
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr96139-b.c b/gcc/testsuite/gcc.target/powerpc/pr96139-b.c
new file mode 100644
index 00000000000..379849a591a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr96139-b.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wall -m64 -mvsx" } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+#include <stdio.h>
+#include <altivec.h>
+
+void
+try_printing_longlong_a (
+                        __vector signed char cval,
+                        __vector signed int ival,
+                        __vector signed long long int llval,
+                        int x, int y, int z)
+{
+  printf (" %016llx \n", llval[x]);
+  printf (" %016x \n", ival[z]);
+  printf (" %c \n", cval[y]);
+}
+
+
+void
+try_printing_unsigned_longlong_a (
+                        __vector unsigned char cval,
+                        __vector unsigned int ival,
+                        __vector unsigned long long int llval,
+                        int x, int y, int z)
+{
+  printf (" %016llx \n", llval[x]);
+  printf (" %016x \n", ival[z]);
+  printf (" %c \n", cval[y]);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr96139-c.c b/gcc/testsuite/gcc.target/powerpc/pr96139-c.c
new file mode 100644
index 00000000000..3ada2603428
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr96139-c.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -Wall -maltivec" } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+
+/*
+ * Based on test created by sjmunroe for pr96139
+ */
+
+#include <stdio.h>
+#include <altivec.h>
+
+volatile vector long long llfoo;
+
+void
+print_v2xint64_b () {
+  printf (" %016llx \n", llfoo[0]);
+  printf (" %016llx \n", llfoo[1]);
+}
+
+int 
+main() {
+llfoo[0]=12345678;
+llfoo[1]=34567890;
+print_v2xint64_b();
+return 0;
+}

commit e1fdce3a0d7064957639949a1ab0fe4a282012c8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Sep 17 00:17:46 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 98b0020e8a5..7275a7d4567 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,180 @@
+2020-09-16  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	PR target/96139
+	* config/rs6000/rs6000.c (rs6000_init_builtin): Update V2DI_type_node
+	  and unsigned_V2DI_type_node definitions.
+
+2020-09-16  Sylvia Taylor  <sylvia.taylor@arm.com>
+
+	Backported from master:
+	2019-08-22  Sylvia Taylor  <sylvia.taylor@arm.com>
+
+	* config/aarch64/aarch64-simd-builtins.def:
+	(ld1x4): New.
+	(st1x4): Likewise.
+	* config/aarch64/aarch64-simd.md:
+	(aarch64_ld1x4<VALLDIF:mode>): New pattern.
+	(aarch64_st1x4<VALLDIF:mode>): Likewise.
+	(aarch64_ld1_x4_<mode>): Likewise.
+	(aarch64_st1_x4_<mode>): Likewise.
+	* config/aarch64/arm_neon.h:
+	(vld1_s8_x4): New function.
+	(vld1q_s8_x4): Likewise.
+	(vld1_s16_x4): Likewise.
+	(vld1q_s16_x4): Likewise.
+	(vld1_s32_x4): Likewise.
+	(vld1q_s32_x4): Likewise.
+	(vld1_u8_x4): Likewise.
+	(vld1q_u8_x4): Likewise.
+	(vld1_u16_x4): Likewise.
+	(vld1q_u16_x4): Likewise.
+	(vld1_u32_x4): Likewise.
+	(vld1q_u32_x4): Likewise.
+	(vld1_f16_x4): Likewise.
+	(vld1q_f16_x4): Likewise.
+	(vld1_f32_x4): Likewise.
+	(vld1q_f32_x4): Likewise.
+	(vld1_p8_x4): Likewise.
+	(vld1q_p8_x4): Likewise.
+	(vld1_p16_x4): Likewise.
+	(vld1q_p16_x4): Likewise.
+	(vld1_s64_x4): Likewise.
+	(vld1_u64_x4): Likewise.
+	(vld1_p64_x4): Likewise.
+	(vld1q_s64_x4): Likewise.
+	(vld1q_u64_x4): Likewise.
+	(vld1q_p64_x4): Likewise.
+	(vld1_f64_x4): Likewise.
+	(vld1q_f64_x4): Likewise.
+	(vst1_s8_x4): Likewise.
+	(vst1q_s8_x4): Likewise.
+	(vst1_s16_x4): Likewise.
+	(vst1q_s16_x4): Likewise.
+	(vst1_s32_x4): Likewise.
+	(vst1q_s32_x4): Likewise.
+	(vst1_u8_x4): Likewise.
+	(vst1q_u8_x4): Likewise.
+	(vst1_u16_x4): Likewise.
+	(vst1q_u16_x4): Likewise.
+	(vst1_u32_x4): Likewise.
+	(vst1q_u32_x4): Likewise.
+	(vst1_f16_x4): Likewise.
+	(vst1q_f16_x4): Likewise.
+	(vst1_f32_x4): Likewise.
+	(vst1q_f32_x4): Likewise.
+	(vst1_p8_x4): Likewise.
+	(vst1q_p8_x4): Likewise.
+	(vst1_p16_x4): Likewise.
+	(vst1q_p16_x4): Likewise.
+	(vst1_s64_x4): Likewise.
+	(vst1_u64_x4): Likewise.
+	(vst1_p64_x4): Likewise.
+	(vst1q_s64_x4): Likewise.
+	(vst1q_u64_x4): Likewise.
+	(vst1q_p64_x4): Likewise.
+	(vst1_f64_x4): Likewise.
+	(vst1q_f64_x4): Likewise.
+
+2020-09-16  Sameera Deshpande  <sameera.deshpande@linaro.org>
+
+	Backported from master:
+	2018-05-31  Sameera Deshpande  <sameera.deshpande@linaro.org>
+
+	* config/aarch64/aarch64-simd-builtins.def (ld1x3): New.
+	(st1x2): Likewise.
+	(st1x3): Likewise.
+	* config/aarch64/aarch64-simd.md
+	(aarch64_ld1x3<VALLDIF:mode>): New pattern.
+	(aarch64_ld1_x3_<mode>): Likewise
+	(aarch64_st1x2<VALLDIF:mode>): Likewise
+	(aarch64_st1_x2_<mode>): Likewise
+	(aarch64_st1x3<VALLDIF:mode>): Likewise
+	(aarch64_st1_x3_<mode>): Likewise
+	* config/aarch64/arm_neon.h (vld1_u8_x3): New function.
+	(vld1_s8_x3): Likewise.
+	(vld1_u16_x3): Likewise.
+	(vld1_s16_x3): Likewise.
+	(vld1_u32_x3): Likewise.
+	(vld1_s32_x3): Likewise.
+	(vld1_u64_x3): Likewise.
+	(vld1_s64_x3): Likewise.
+	(vld1_f16_x3): Likewise.
+	(vld1_f32_x3): Likewise.
+	(vld1_f64_x3): Likewise.
+	(vld1_p8_x3): Likewise.
+	(vld1_p16_x3): Likewise.
+	(vld1_p64_x3): Likewise.
+	(vld1q_u8_x3): Likewise.
+	(vld1q_s8_x3): Likewise.
+	(vld1q_u16_x3): Likewise.
+	(vld1q_s16_x3): Likewise.
+	(vld1q_u32_x3): Likewise.
+	(vld1q_s32_x3): Likewise.
+	(vld1q_u64_x3): Likewise.
+	(vld1q_s64_x3): Likewise.
+	(vld1q_f16_x3): Likewise.
+	(vld1q_f32_x3): Likewise.
+	(vld1q_f64_x3): Likewise.
+	(vld1q_p8_x3): Likewise.
+	(vld1q_p16_x3): Likewise.
+	(vld1q_p64_x3): Likewise.
+	(vst1_s64_x2): Likewise.
+	(vst1_u64_x2): Likewise.
+	(vst1_f64_x2): Likewise.
+	(vst1_s8_x2): Likewise.
+	(vst1_p8_x2): Likewise.
+	(vst1_s16_x2): Likewise.
+	(vst1_p16_x2): Likewise.
+	(vst1_s32_x2): Likewise.
+	(vst1_u8_x2): Likewise.
+	(vst1_u16_x2): Likewise.
+	(vst1_u32_x2): Likewise.
+	(vst1_f16_x2): Likewise.
+	(vst1_f32_x2): Likewise.
+	(vst1_p64_x2): Likewise.
+	(vst1q_s8_x2): Likewise.
+	(vst1q_p8_x2): Likewise.
+	(vst1q_s16_x2): Likewise.
+	(vst1q_p16_x2): Likewise.
+	(vst1q_s32_x2): Likewise.
+	(vst1q_s64_x2): Likewise.
+	(vst1q_u8_x2): Likewise.
+	(vst1q_u16_x2): Likewise.
+	(vst1q_u32_x2): Likewise.
+	(vst1q_u64_x2): Likewise.
+	(vst1q_f16_x2): Likewise.
+	(vst1q_f32_x2): Likewise.
+	(vst1q_f64_x2): Likewise.
+	(vst1q_p64_x2): Likewise.
+	(vst1_s64_x3): Likewise.
+	(vst1_u64_x3): Likewise.
+	(vst1_f64_x3): Likewise.
+	(vst1_s8_x3): Likewise.
+	(vst1_p8_x3): Likewise.
+	(vst1_s16_x3): Likewise.
+	(vst1_p16_x3): Likewise.
+	(vst1_s32_x3): Likewise.
+	(vst1_u8_x3): Likewise.
+	(vst1_u16_x3): Likewise.
+	(vst1_u32_x3): Likewise.
+	(vst1_f16_x3): Likewise.
+	(vst1_f32_x3): Likewise.
+	(vst1_p64_x3): Likewise.
+	(vst1q_s8_x3): Likewise.
+	(vst1q_p8_x3): Likewise.
+	(vst1q_s16_x3): Likewise.
+	(vst1q_p16_x3): Likewise.
+	(vst1q_s32_x3): Likewise.
+	(vst1q_s64_x3): Likewise.
+	(vst1q_u8_x3): Likewise.
+	(vst1q_u16_x3): Likewise.
+	(vst1q_u32_x3): Likewise.
+	(vst1q_u64_x3): Likewise.
+	(vst1q_f16_x3): Likewise.
+	(vst1q_f32_x3): Likewise.
+	(vst1q_f64_x3): Likewise.
+	(vst1q_p64_x3): Likewise.
+
 2020-08-21  Richard Sandiford  <richard.sandiford@arm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index bc812c5fa15..fae3fa1fac6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200916
+20200917
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 810caf53784..1e3dbccdb25 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,30 @@
+2020-09-16  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	PR target/96139
+	* gcc.target/powerpc/pr96139-a.c: New test.
+	* gcc.target/powerpc/pr96139-b.c: New test.
+	* gcc.target/powerpc/pr96139-c.c: New test.
+
+2020-09-16  Sylvia Taylor  <sylvia.taylor@arm.com>
+
+	Backported from master:
+	2019-08-22  Sylvia Taylor  <sylvia.taylor@arm.com>
+
+	* gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: New test.
+	* gcc.target/aarch64/advsimd-intrinsics/vst1x4.c: New test.
+
+2020-09-16  Sameera Deshpande  <sameera.deshpande@linaro.org>
+
+	Backported from master:
+	2018-05-31  Sameera Deshpande  <sameera.deshpande@linaro.org>
+
+	* gcc.target/aarch64/advsimd-intrinsics/vld1x3.c: New test for
+	vld1x3 intrinsics for aarch64.
+	* gcc.target/aarch64/advsimd-intrinsics/vst1x2.c: New test for
+	vst1x2 intrinsics for aarch64.
+	* gcc.target/aarch64/advsimd-intrinsics/vst1x3.c: New test for
+	vst1x3 intrinsics for aarch64.
+
 2020-09-09  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:

commit 3549a5cabdfd4ebb197da99f247d0abad0ba55b5
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Mar 3 10:42:34 2020 +0100

    explow: Fix ICE caused by plus_constant [PR94002]
    
    The following testcase ICEs in cross to riscv64-linux.  The problem is
    that we have a DImode integral constant (that doesn't fit into SImode),
    which is pushed into a constant pool and later access just the first half of
    it using a MEM.  When plus_constant is called on such a MEM, if the constant
    has mode, we verify the mode, but if it doesn't, we don't and ICE later on
    when we think the CONST_INT is a valid SImode constant.
    
    2020-03-03  Jakub Jelinek  <jakub@redhat.com>
    
            PR rtl-optimization/94002
            * explow.c (plus_constant): Punt if cst has VOIDmode and
            get_pool_mode is different from mode.
    
            * gcc.dg/pr94002.c: New test.
    
    (cherry picked from commit e913d4f4771e04d4254bf6c0e720fec5e324a898)

diff --git a/gcc/explow.c b/gcc/explow.c
index 72e52703c48..79c781cb390 100644
--- a/gcc/explow.c
+++ b/gcc/explow.c
@@ -129,6 +129,9 @@ plus_constant (machine_mode mode, rtx x, poly_int64 c, bool inplace)
 	      cst = gen_lowpart (mode, cst);
 	      gcc_assert (cst);
 	    }
+	  else if (GET_MODE (cst) == VOIDmode
+		   && get_pool_mode (XEXP (x, 0)) != mode)
+	    break;
 	  if (GET_MODE (cst) == VOIDmode || GET_MODE (cst) == mode)
 	    {
 	      tem = plus_constant (mode, cst, c);
diff --git a/gcc/testsuite/gcc.dg/pr94002.c b/gcc/testsuite/gcc.dg/pr94002.c
new file mode 100644
index 00000000000..05a02f3f15b
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94002.c
@@ -0,0 +1,13 @@
+/* PR rtl-optimization/94002 */
+/* { dg-do compile } */
+/* { dg-options "-O1 -fno-tree-dce -fno-tree-reassoc" } */
+/* { dg-additional-options "-fPIC" { target fpic } } */
+
+unsigned a, b;
+
+void
+foo (void)
+{
+  __builtin_sub_overflow (b, 44852956282LL, &a);
+  a += ~b;
+}

commit 5dd7682887c959a10d5d1d4d7ad7b4a0950805d2
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Mar 5 19:44:42 2020 +0100

    i386: Fix some -O0 avx2intrin.h and xopintrin.h intrinsic macros [PR94046]
    
    As the testcases show, the macros we have for -O0 for intrinsics that require
    constant argument(s) should first cast the argument to the type the -O1+
    inline uses and afterwards to whatever type e.g. a builtin needs.
    The PR reported one which violated this, and I've grepped for all double-casts
    and grepped out from that meaningful casts where the __m{128,256,512}{,d,i}
    first cast is cast to same sized __v* type and has the same kind of element
    type (float, double, integral).  These 7 macros were using different casts,
    and I've double checked them against the inline function types.
    
    2020-03-05  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94046
            * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
            SRC and MASK arguments to __m128 from __m128d.
            (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
            from __m256d.
            (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
            from __m128d.
            * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
            argument to __m128i from __m128d.
            (_mm256_permute2_pd): Fix first cast of C argument to __m256i from
            __m256d.
            (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
            (_mm256_permute2_ps): Fix first cast of C argument to __m256i from
            __m256.
    
            * g++.dg/ext/pr94046-1.C: New test.
            * g++.dg/ext/pr94046-2.C: New test.
    
    (cherry picked from commit 07d52e63d999a0a10c7598c34c48365a357d3d5a)

diff --git a/gcc/config/i386/avx2intrin.h b/gcc/config/i386/avx2intrin.h
index f6a2555de33..8906600a225 100644
--- a/gcc/config/i386/avx2intrin.h
+++ b/gcc/config/i386/avx2intrin.h
@@ -1736,10 +1736,10 @@ _mm256_mask_i64gather_epi32 (__m128i __src, int const *__base,
 					(int)SCALE)
 
 #define _mm_mask_i32gather_ps(SRC, BASE, INDEX, MASK, SCALE)	 \
-  (__m128) __builtin_ia32_gathersiv4sf ((__v4sf)(__m128d)SRC,	 \
+  (__m128) __builtin_ia32_gathersiv4sf ((__v4sf)(__m128)SRC,	 \
 					(float const *)BASE,	 \
 					(__v4si)(__m128i)INDEX,	 \
-					(__v4sf)(__m128d)MASK,	 \
+					(__v4sf)(__m128)MASK,	 \
 					(int)SCALE)
 
 #define _mm256_i32gather_ps(BASE, INDEX, SCALE)			       \
@@ -1754,7 +1754,7 @@ _mm256_mask_i64gather_epi32 (__m128i __src, int const *__base,
   (__m256) __builtin_ia32_gathersiv8sf ((__v8sf)(__m256)SRC,	\
 					(float const *)BASE,	\
 					(__v8si)(__m256i)INDEX, \
-					(__v8sf)(__m256d)MASK,	\
+					(__v8sf)(__m256)MASK,	\
 					(int)SCALE)
 
 #define _mm_i64gather_ps(BASE, INDEX, SCALE)				\
@@ -1769,7 +1769,7 @@ _mm256_mask_i64gather_epi32 (__m128i __src, int const *__base,
   (__m128) __builtin_ia32_gatherdiv4sf ((__v4sf)(__m128)SRC,	 \
 					(float const *)BASE,	 \
 					(__v2di)(__m128i)INDEX,	 \
-					(__v4sf)(__m128d)MASK,	 \
+					(__v4sf)(__m128)MASK,	 \
 					(int)SCALE)
 
 #define _mm256_i64gather_ps(BASE, INDEX, SCALE)				\
diff --git a/gcc/config/i386/xopintrin.h b/gcc/config/i386/xopintrin.h
index e7fda9abee4..f50547d389c 100644
--- a/gcc/config/i386/xopintrin.h
+++ b/gcc/config/i386/xopintrin.h
@@ -814,25 +814,25 @@ _mm256_permute2_ps (__m256 __X, __m256 __Y, __m256i __C, const int __I)
 #define _mm_permute2_pd(X, Y, C, I)					\
   ((__m128d) __builtin_ia32_vpermil2pd ((__v2df)(__m128d)(X),		\
 					(__v2df)(__m128d)(Y),		\
-					(__v2di)(__m128d)(C),		\
+					(__v2di)(__m128i)(C),		\
 					(int)(I)))
 
 #define _mm256_permute2_pd(X, Y, C, I)					\
   ((__m256d) __builtin_ia32_vpermil2pd256 ((__v4df)(__m256d)(X),	\
 					   (__v4df)(__m256d)(Y),	\
-					   (__v4di)(__m256d)(C),	\
+					   (__v4di)(__m256i)(C),	\
 					   (int)(I)))
 
 #define _mm_permute2_ps(X, Y, C, I)					\
   ((__m128) __builtin_ia32_vpermil2ps ((__v4sf)(__m128)(X),		\
 				       (__v4sf)(__m128)(Y),		\
-				       (__v4si)(__m128)(C),		\
+				       (__v4si)(__m128i)(C),		\
 				       (int)(I)))
 
 #define _mm256_permute2_ps(X, Y, C, I)					\
   ((__m256) __builtin_ia32_vpermil2ps256 ((__v8sf)(__m256)(X),		\
 					  (__v8sf)(__m256)(Y),  	\
-					  (__v8si)(__m256)(C),		\
+					  (__v8si)(__m256i)(C),		\
  					  (int)(I)))
 #endif /* __OPTIMIZE__ */
 
diff --git a/gcc/testsuite/g++.dg/ext/pr94046-1.C b/gcc/testsuite/g++.dg/ext/pr94046-1.C
new file mode 100644
index 00000000000..512eaf112c0
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/pr94046-1.C
@@ -0,0 +1,55 @@
+// PR target/94046
+// { dg-do compile { target i?86-*-* x86_64-*-* } }
+// { dg-options "-O2 -mavx2 -mxop" }
+
+#include <x86intrin.h>
+
+#define S(x) struct x { operator __##x (); };
+S (m128)
+S (m128d)
+S (m128i)
+S (m256)
+S (m256d)
+S (m256i)
+
+__m128
+f1 (m128 src, float const *base, m128i idx, m128 mask)
+{
+  return _mm_mask_i32gather_ps (src, base, idx, mask, 2);
+}
+
+__m256
+f2 (m256 src, float const *base, m256i idx, m256 mask)
+{
+  return _mm256_mask_i32gather_ps (src, base, idx, mask, 2);
+}
+
+__m128
+f3 (m128 src, float const *base, m128i idx, m128 mask)
+{
+  return _mm_mask_i64gather_ps (src, base, idx, mask, 2);
+}
+
+__m128d
+f4 (m128d x, m128d y, m128i c)
+{
+  return _mm_permute2_pd (x, y, c, 3);
+}
+
+__m128
+f5 (m128 x, m128 y, m128i c)
+{
+  return _mm_permute2_ps (x, y, c, 3);
+}
+
+__m256d
+f6 (m256d x, m256d y, m256i c)
+{
+  return _mm256_permute2_pd (x, y, c, 3);
+}
+
+__m256
+f7 (m256 x, m256 y, m256i c)
+{
+  return _mm256_permute2_ps (x, y, c, 3);
+}
diff --git a/gcc/testsuite/g++.dg/ext/pr94046-2.C b/gcc/testsuite/g++.dg/ext/pr94046-2.C
new file mode 100644
index 00000000000..9744950a838
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/pr94046-2.C
@@ -0,0 +1,5 @@
+// PR target/94046
+// { dg-do compile { target i?86-*-* x86_64-*-* } }
+// { dg-options "-O0 -mavx2 -mxop" }
+
+#include "pr94046-1.C"

commit 777fa0a232a6bfc7ed3827f35322ec740fe714e9
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Mar 4 12:59:04 2020 +0100

    inliner: Copy DECL_BY_REFERENCE in copy_decl_to_var [PR93888]
    
    In the following testcase we emit wrong debug info for the karg
    parameter in the DW_TAG_inlined_subroutine into main.
    The problem is that the karg PARM_DECL is DECL_BY_REFERENCE and thus
    in the IL has const K & type, but in the source just const K.
    When the function is inlined, we create a VAR_DECL for it, but don't
    set DECL_BY_REFERENCE, so when emitting DW_AT_location, we treat it like
    a const K & typed variable, but it has DW_AT_abstract_origin which has
    just the const K type and thus the debugger thinks the variable has
    const K type.
    
    Fixed by copying the DECL_BY_REFERENCE flag.  Not doing it in
    copy_decl_for_dup_finish, because copy_decl_no_change already copies
    that flag through copy_node and in copy_result_decl_to_var it is
    undesirable, as we handle DECL_BY_REFERENCE in that case instead
    by changing the type.
    
    2020-03-04  Jakub Jelinek  <jakub@redhat.com>
    
            PR debug/93888
            * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
    
            * g++.dg/guality/pr93888.C: New test.
    
    (cherry picked from commit d2a810ee83e2952bf351498cecf8f5db28860a24)

diff --git a/gcc/testsuite/g++.dg/guality/pr93888.C b/gcc/testsuite/g++.dg/guality/pr93888.C
new file mode 100644
index 00000000000..3113a4cbdca
--- /dev/null
+++ b/gcc/testsuite/g++.dg/guality/pr93888.C
@@ -0,0 +1,24 @@
+// PR debug/93888
+// { dg-do run }
+// { dg-options "-g -fvar-tracking -fno-inline" }
+// { dg-skip-if "" { *-*-* }  { "*" } { "-O0" } }
+
+struct K
+{
+  K () {}
+  K (K const &rhs) { k[0] = 'C'; }
+  char k[8] = {'B','B','B','B','B','B','B','B'};
+};
+
+__attribute__((always_inline)) inline bool
+foo (const K karg)
+{
+  return karg.k[0] != 'C';	// { dg-final { gdb-test 16 "karg.k\[0]" "'C'" } }
+}				// { dg-final { gdb-test 16 "karg.k\[1]" "'B'" } }
+
+int
+main ()
+{
+  K x;
+  return foo (x);
+}
diff --git a/gcc/tree-inline.c b/gcc/tree-inline.c
index ff9da78d65d..cd7e477337a 100644
--- a/gcc/tree-inline.c
+++ b/gcc/tree-inline.c
@@ -5709,6 +5709,7 @@ copy_decl_to_var (tree decl, copy_body_data *id)
   TREE_READONLY (copy) = TREE_READONLY (decl);
   TREE_THIS_VOLATILE (copy) = TREE_THIS_VOLATILE (decl);
   DECL_GIMPLE_REG_P (copy) = DECL_GIMPLE_REG_P (decl);
+  DECL_BY_REFERENCE (copy) = DECL_BY_REFERENCE (decl);
 
   return copy_decl_for_dup_finish (id, decl, copy);
 }

commit c035257d1f775f44359fe55ceb3d018a68d87114
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Mar 5 09:12:44 2020 +0100

    print-rtl: Fix printing of CONST_STRING in DEBUG_INSNs [PR93399]
    
    The following testcase fails to assemble, as CONST_STRING in the DEBUG_INSNs
    is printed as is, so if it contains \n and/or \r, we are in trouble:
            .loc 1 14 3
            # DEBUG haystack => [si]
            # DEBUG needle => "
    "
    In the gimple dumps we print those (STRING_CSTs) as
      # DEBUG haystack => D#1
      # DEBUG needle => "\n"
    so this patch uses what we use in tree printing for the CONST_STRINGs too.
    
    2020-03-05  Jakub Jelinek  <jakub@redhat.com>
    
            PR middle-end/93399
            * tree-pretty-print.h (pretty_print_string): Declare.
            * tree-pretty-print.c (pretty_print_string): Remove forward
            declaration, no longer static.  Change nbytes parameter type
            from unsigned to size_t.
            * print-rtl.c (print_value) <case CONST_STRING>: Use
            pretty_print_string and for shrink way too long strings.
    
            * gcc.dg/pr93399.c: New test.
    
    (cherry picked from commit e0d6777cda966b04fc47d544c09839c4fa94343c)

diff --git a/gcc/print-rtl.c b/gcc/print-rtl.c
index 37c0d53fae2..69ca73c3a6d 100644
--- a/gcc/print-rtl.c
+++ b/gcc/print-rtl.c
@@ -1664,7 +1664,9 @@ print_value (pretty_printer *pp, const_rtx x, int verbose)
       pp_string (pp, tmp);
       break;
     case CONST_STRING:
-      pp_printf (pp, "\"%s\"", XSTR (x, 0));
+      pp_string (pp, "\"");
+      pretty_print_string (pp, XSTR (x, 0));
+      pp_string (pp, "\"");
       break;
     case SYMBOL_REF:
       pp_printf (pp, "`%s'", XSTR (x, 0));
diff --git a/gcc/testsuite/gcc.dg/pr93399.c b/gcc/testsuite/gcc.dg/pr93399.c
new file mode 100644
index 00000000000..3d9299018be
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr93399.c
@@ -0,0 +1,17 @@
+/* PR middle-end/93399 */
+/* { dg-do assemble } */
+/* { dg-options "-fverbose-asm -dA -g -O3" } */
+
+extern inline __attribute__ ((__always_inline__, __gnu_inline__)) char *
+strstr (const char *haystack, const char *needle)
+{
+  return __builtin_strstr (haystack, needle);
+}
+
+int
+main (int argc, const char **argv)
+{
+  char *substr = strstr (argv[0], "\n");
+  char *another = strstr (argv[0], "\r\n");
+  return 0;
+}
diff --git a/gcc/tree-pretty-print.c b/gcc/tree-pretty-print.c
index 276ad00a7b2..9256fcb67fe 100644
--- a/gcc/tree-pretty-print.c
+++ b/gcc/tree-pretty-print.c
@@ -37,7 +37,6 @@ along with GCC; see the file COPYING3.  If not see
 
 /* Local functions, macros and variables.  */
 static const char *op_symbol (const_tree);
-static void pretty_print_string (pretty_printer *, const char*);
 static void newline_and_indent (pretty_printer *, int);
 static void maybe_init_pretty_print (FILE *);
 static void print_struct_decl (pretty_printer *, const_tree, int, dump_flags_t);
@@ -3842,7 +3841,7 @@ print_call_name (pretty_printer *pp, tree node, dump_flags_t flags)
 
 /* Parses the string STR and replaces new-lines by '\n', tabs by '\t', ...  */
 
-static void
+void
 pretty_print_string (pretty_printer *pp, const char *str)
 {
   if (str == NULL)
diff --git a/gcc/tree-pretty-print.h b/gcc/tree-pretty-print.h
index cf2427f9d27..c452cd9b011 100644
--- a/gcc/tree-pretty-print.h
+++ b/gcc/tree-pretty-print.h
@@ -44,6 +44,7 @@ extern void print_declaration (pretty_printer *, tree, int, dump_flags_t);
 extern int op_code_prio (enum tree_code);
 extern int op_prio (const_tree);
 extern const char *op_symbol_code (enum tree_code);
+extern void pretty_print_string (pretty_printer *, const char *);
 extern void print_call_name (pretty_printer *, tree, dump_flags_t);
 extern void percent_K_format (text_info *, tree);
 extern void pp_tree_identifier (pretty_printer *, tree);

commit 8d5332862e86edb92f27bd136ccd9fdba3524039
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Mar 11 09:32:22 2020 +0100

    ldist: Further fixes for -ftrapv [PR94114]
    
    As the testcase shows, arithmetics that for -ftrapv would need multiple
    basic blocks can show up not just in nb_bytes expressions where we
    are calling rewrite_to_non_trapping_overflow for a while already,
    but also in the pointer expression to the start of the region.
    While the testcase covers just the first hunk and I've failed to create
    a testcase for the latter, it is at least in theory possible too, so I've
    adjusted that hunk too.
    
    2020-03-11  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/94114
            * tree-loop-distribution.c (generate_memset_builtin): Call
            rewrite_to_non_trapping_overflow even on mem.
            (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
            on dest and src.
    
            * gcc.dg/pr94114.c: New test.
    
    (cherry picked from commit 2fd27691f213f2e808626c4cd492b00c801a00fa)

diff --git a/gcc/testsuite/gcc.dg/pr94114.c b/gcc/testsuite/gcc.dg/pr94114.c
new file mode 100644
index 00000000000..8d6d0eb5c2a
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94114.c
@@ -0,0 +1,13 @@
+/* PR tree-optimization/94114 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-loop-distribute-patterns -ftrapv" } */
+
+void
+foo (int *x, int *y, int *z, long int w)
+{
+  while (y + w > z)
+    {
+      x[w] = 0;
+      --w;
+    }
+}
diff --git a/gcc/tree-loop-distribution.c b/gcc/tree-loop-distribution.c
index 05766c7300d..e257c9bc433 100644
--- a/gcc/tree-loop-distribution.c
+++ b/gcc/tree-loop-distribution.c
@@ -1001,7 +1001,7 @@ generate_memset_builtin (struct loop *loop, partition *partition)
   nb_bytes = rewrite_to_non_trapping_overflow (builtin->size);
   nb_bytes = force_gimple_operand_gsi (&gsi, nb_bytes, true, NULL_TREE,
 				       false, GSI_CONTINUE_LINKING);
-  mem = builtin->dst_base;
+  mem = rewrite_to_non_trapping_overflow (builtin->dst_base);
   mem = force_gimple_operand_gsi (&gsi, mem, true, NULL_TREE,
 				  false, GSI_CONTINUE_LINKING);
 
@@ -1053,8 +1053,8 @@ generate_memcpy_builtin (struct loop *loop, partition *partition)
   nb_bytes = rewrite_to_non_trapping_overflow (builtin->size);
   nb_bytes = force_gimple_operand_gsi (&gsi, nb_bytes, true, NULL_TREE,
 				       false, GSI_CONTINUE_LINKING);
-  dest = builtin->dst_base;
-  src = builtin->src_base;
+  dest = rewrite_to_non_trapping_overflow (builtin->dst_base);
+  src = rewrite_to_non_trapping_overflow (builtin->src_base);
   if (partition->kind == PKIND_MEMCPY
       || ! ptr_derefs_may_alias_p (dest, src))
     kind = BUILT_IN_MEMCPY;

commit 8b53a85254e91903018498d70b59928b0d1dd9f9
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Mar 11 09:33:52 2020 +0100

    dfp: Fix decimal_to_binary [PR94111]
    
    As e.g. decimal_from_decnumber shows, the REAL_VALUE_TYPE representation
    contains a decimal128 embedded in ->sig only if it is rvc_normal, for
    other kinds like rvc_inf or rvc_nan, ->sig is ignored and everything is
    contained in the REAL_VALUE_TYPE flags (cl, sign, signalling and decimal).
    decimal_to_binary which is used when folding a decimal{32,64,128} constant
    to a binary floating point type ignores this and thus folds infinities and
    NaNs into +0.0.
    The following patch fixes that by only doing that for rvc_normal.
    Similarly to the binary to decimal folding, it goes through a string, in
    order to e.g. deal with canonical NaN mantissas, or binary float formats
    that don't support infinities and/or NaNs.
    
    2020-03-11  Jakub Jelinek  <jakub@redhat.com>
    
            PR middle-end/94111
            * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
            is rvc_normal, otherwise use real_to_decimal to print the number to
            string.
    
            * gcc.dg/dfp/pr94111.c: New test.
    
    (cherry picked from commit 343c467ccdc24edb9acd7c60d54914d9656ab499)

diff --git a/gcc/dfp.c b/gcc/dfp.c
index 230b1b14eaa..26efdc51901 100644
--- a/gcc/dfp.c
+++ b/gcc/dfp.c
@@ -342,9 +342,13 @@ decimal_to_binary (REAL_VALUE_TYPE *to, const REAL_VALUE_TYPE *from,
 		   const real_format *fmt)
 {
   char string[256];
-  const decimal128 *const d128 = (const decimal128 *) from->sig;
-
-  decimal128ToString (d128, string);
+  if (from->cl == rvc_normal)
+    {
+      const decimal128 *const d128 = (const decimal128 *) from->sig;
+      decimal128ToString (d128, string);
+    }
+  else
+    real_to_decimal (string, from, sizeof (string), 0, 1);
   real_from_string3 (to, string, fmt);
 }
 
diff --git a/gcc/testsuite/gcc.dg/dfp/pr94111.c b/gcc/testsuite/gcc.dg/dfp/pr94111.c
new file mode 100644
index 00000000000..ea3a132270a
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/dfp/pr94111.c
@@ -0,0 +1,12 @@
+/* PR middle-end/94111 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+int
+main ()
+{
+  _Decimal32 d = (_Decimal32) __builtin_inff ();
+  if (!__builtin_isinf ((double) d))
+    __builtin_abort ();
+  return 0;
+}

commit 5f6826f724348c4e1317c15ea4cea01d5604fc39
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Mar 11 10:54:22 2020 +0100

    aarch64: Fix ICE in aarch64_add_offset_1 [PR94121]
    
    abs_hwi asserts that the argument is not HOST_WIDE_INT_MIN and as the
    (invalid) testcase shows, the function can be called with such an offset.
    The following patch is IMHO minimal fix, absu_hwi unlike abs_hwi allows even
    that value and will return (unsigned HOST_WIDE_INT) HOST_WIDE_INT_MIN
    in that case.  The function then uses moffset in two spots which wouldn't
    care if the value is (unsigned HOST_WIDE_INT) HOST_WIDE_INT_MIN or
    HOST_WIDE_INT_MIN and wouldn't accept it (!moffset and
    aarch64_uimm12_shift (moffset)), then in one spot where the signedness of
    moffset does matter and using unsigned is the right thing -
    moffset < 0x1000000 - and finally has code which will handle even this
    value right; the assembler doesn't really care for DImode immediates if
            mov     x1, -9223372036854775808
    or
            mov     x1, 9223372036854775808
    is used and similarly it doesn't matter if we add or sub it in DImode.
    
    2020-03-11  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94121
            * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
            instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
    
            * gcc.dg/pr94121.c: New test.
    
    (cherry picked from commit a644079a702a6228df2ffaace1d88a5f74e4bb9f)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 14ed69f460d..7e16b6c59c3 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2541,7 +2541,7 @@ aarch64_add_offset_1 (scalar_int_mode mode, rtx dest,
   gcc_assert (emit_move_imm || temp1 != NULL_RTX);
   gcc_assert (temp1 == NULL_RTX || !reg_overlap_mentioned_p (temp1, src));
 
-  HOST_WIDE_INT moffset = abs_hwi (offset);
+  unsigned HOST_WIDE_INT moffset = absu_hwi (offset);
   rtx_insn *insn;
 
   if (!moffset)
diff --git a/gcc/testsuite/gcc.dg/pr94121.c b/gcc/testsuite/gcc.dg/pr94121.c
new file mode 100644
index 00000000000..2a4261ae02d
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94121.c
@@ -0,0 +1,16 @@
+/* PR target/94121 */
+/* { dg-do compile { target pie } } */
+/* { dg-options "-O2 -fpie -w" } */
+
+#define DIFF_MAX __PTRDIFF_MAX__
+#define DIFF_MIN (-DIFF_MAX - 1)
+
+extern void foo (char *);
+extern char v[];
+
+void
+bar (void)
+{
+  char *p = v;
+  foo (&p[DIFF_MIN]);
+}

commit 4910b2e4cfe25c95fef18cf54125b788c190cfb2
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Mar 11 18:35:13 2020 +0100

    pdp11: Fix handling of common (local and global) vars [PR94134]
    
    As mentioned in the PR, the generic code decides to put the a variable into
    lcomm_section, which is a NOSWITCH section and thus the generic code doesn't
    switch into a particular section before using
    ASM_OUTPUT{_ALIGNED{,_DECL}_}_LOCAL, on many targets that results just in
    .lcomm (or for non-local .comm) directives which don't need a switch to some
    section, other targets put switch_to_section (bss_section) at the start of
    that macro.
    pdp11 doesn't do that (and doesn't have bss_section), and so emits the
    lcomm/comm variables in whatever section is current (it has only .text/.data
    and for DEC assembler rodata).
    
    The following patch fixes that by putting it always into data section, and
    additionally avoids emitting an empty line in the assembly for the lcomm
    vars.
    
    2020-03-11  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94134
            * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
            at the start to switch to data section.  Don't print extra newline if
            .globl directive has not been emitted.
    
            * gcc.c-torture/execute/pr94134.c: New test.
    
    (cherry picked from commit f1125cf88ac0c97d819e4f81d556fbcd1161270e)

diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 38c55fbb3df..3c4351477e9 100644
--- a/gcc/config/pdp11/pdp11.c
+++ b/gcc/config/pdp11/pdp11.c
@@ -720,14 +720,15 @@ void
 pdp11_asm_output_var (FILE *file, const char *name, int size,
 		      int align, bool global)
 {
+  switch_to_section (data_section);
   if (align > 8)
     fprintf (file, "\n\t.even\n");
   if (global)
     {
       fprintf (file, ".globl ");
       assemble_name (file, name);
+      fprintf (file, "\n");
     }
-  fprintf (file, "\n");
   assemble_name (file, name);
   fprintf (file, ": .=.+ %#ho\n", (unsigned short)size);
 }
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr94134.c b/gcc/testsuite/gcc.c-torture/execute/pr94134.c
new file mode 100644
index 00000000000..b1b44c3b184
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr94134.c
@@ -0,0 +1,14 @@
+/* PR target/94134 */
+
+static volatile int a = 0;
+static volatile int b = 1;
+
+int
+main ()
+{
+  a++;
+  b++;
+  if (a != 1 || b != 2)
+    __builtin_abort ();
+  return 0;
+}

commit 9001bc36447e015283a5f1a0a924bd355f9d9df3
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Mar 12 09:34:00 2020 +0100

    tree-dse: Fix mem* head trimming if call has lhs [PR94130]
    
    As the testcase shows, if DSE decides to head trim {mem{set,cpy,move},strncpy}
    and the call has lhs, it is incorrect to leave the lhs as is, because it
    will then point to the adjusted address (base + head_trim) instead of the
    original base.
    The following patch fixes that by dropping the lhs of the call and assigning
    lhs the original base in a following statement.
    
    2020-03-12  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/94130
            * tree-ssa-dse.c: Include gimplify.h.
            (increment_start_addr): If stmt has lhs, drop the lhs from call and
            set it after the call to the original value of the first argument.
            Formatting fixes.
            (decrement_count): Formatting fix.
    
            * gcc.c-torture/execute/pr94130.c: New test.
    
    (cherry picked from commit a545ffafa380fa958393e1dfbf7f5f8f129bc5cf)

diff --git a/gcc/testsuite/gcc.c-torture/execute/pr94130.c b/gcc/testsuite/gcc.c-torture/execute/pr94130.c
new file mode 100644
index 00000000000..044e578d373
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr94130.c
@@ -0,0 +1,16 @@
+/* PR tree-optimization/94130 */
+
+int
+main ()
+{
+  int a[8];
+  char *b = __builtin_memset (a, 0, sizeof (a));
+  a[0] = 1;
+  a[1] = 2;
+  a[2] = 3;
+  if (b != (char *) a)
+    __builtin_abort ();
+  else
+    asm volatile ("" : : "g" (a) : "memory");
+  return 0;
+}
diff --git a/gcc/tree-ssa-dse.c b/gcc/tree-ssa-dse.c
index 9220fea7f2e..d6cb0ed6f4e 100644
--- a/gcc/tree-ssa-dse.c
+++ b/gcc/tree-ssa-dse.c
@@ -35,6 +35,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "tree-cfgcleanup.h"
 #include "params.h"
 #include "alias.h"
+#include "gimplify.h"
 
 /* This file implements dead store elimination.
 
@@ -373,29 +374,38 @@ decrement_count (gimple *stmt, int decrement)
   gcc_assert (TREE_CODE (*countp) == INTEGER_CST);
   *countp = wide_int_to_tree (TREE_TYPE (*countp), (TREE_INT_CST_LOW (*countp)
 						    - decrement));
-
 }
 
 static void
 increment_start_addr (gimple *stmt, tree *where, int increment)
 {
+  if (tree lhs = gimple_call_lhs (stmt))
+    if (where == gimple_call_arg_ptr (stmt, 0))
+      {
+	gassign *newop = gimple_build_assign (lhs, unshare_expr (*where));
+	gimple_stmt_iterator gsi = gsi_for_stmt (stmt);
+	gsi_insert_after (&gsi, newop, GSI_SAME_STMT);
+	gimple_call_set_lhs (stmt, NULL_TREE);
+	update_stmt (stmt);
+      }
+
   if (TREE_CODE (*where) == SSA_NAME)
     {
       tree tem = make_ssa_name (TREE_TYPE (*where));
       gassign *newop
-        = gimple_build_assign (tem, POINTER_PLUS_EXPR, *where,
+	= gimple_build_assign (tem, POINTER_PLUS_EXPR, *where,
 			       build_int_cst (sizetype, increment));
       gimple_stmt_iterator gsi = gsi_for_stmt (stmt);
       gsi_insert_before (&gsi, newop, GSI_SAME_STMT);
       *where = tem;
-      update_stmt (gsi_stmt (gsi));
+      update_stmt (stmt);
       return;
     }
 
   *where = build_fold_addr_expr (fold_build2 (MEM_REF, char_type_node,
-                                             *where,
-                                             build_int_cst (ptr_type_node,
-                                                            increment)));
+					      *where,
+					      build_int_cst (ptr_type_node,
+							     increment)));
 }
 
 /* STMT is builtin call that writes bytes in bitmap ORIG, some bytes are dead

commit 51ef2c2c0f3d59f14b8aeb909ebcc2d85f6c6618
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Mar 12 09:35:30 2020 +0100

    doc: Fix up ASM_OUTPUT_ALIGNED_DECL_LOCAL description
    
    When looking into PR94134, I've noticed bugs in the
    ASM_OUTPUT_ALIGNED_DECL_LOCAL documentation.  varasm.c has:
      #if defined ASM_OUTPUT_ALIGNED_DECL_LOCAL
        unsigned int align = symtab_node::get (decl)->definition_alignment ();
        ASM_OUTPUT_ALIGNED_DECL_LOCAL (asm_out_file, decl, name,
                                       size, align);
        return true;
      #elif defined ASM_OUTPUT_ALIGNED_LOCAL
        unsigned int align = symtab_node::get (decl)->definition_alignment ();
        ASM_OUTPUT_ALIGNED_LOCAL (asm_out_file, name, size, align);
        return true;
      #else
        ASM_OUTPUT_LOCAL (asm_out_file, name, size, rounded);
        return false;
      #endif
    and the ASM_OUTPUT_ALIGNED_LOCAL documentation properly mentions:
    Like @code{ASM_OUTPUT_LOCAL} and mentions the same macro in another place.
    The ASM_OUTPUT_ALIGNED_DECL_LOCAL description mentions non-existing macros
    ASM_OUTPUT_ALIGNED_DECL and ASM_OUTPUT_DECL instead of the right ones
    ASM_OUTPUT_ALIGNED_LOCAL and ASM_OUTPUT_LOCAL.
    
    2020-03-12  Jakub Jelinek  <jakub@redhat.com>
    
            * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
            ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
            and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
            * doc/tm.texi: Regenerated.
    
    (cherry picked from commit 9a8af207d7d03149a438185a2a0c50eeeb96a402)

diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index bd8b917ba82..340e856c4da 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -8208,11 +8208,11 @@ as the number of bits.
 @end defmac
 
 @defmac ASM_OUTPUT_ALIGNED_DECL_LOCAL (@var{stream}, @var{decl}, @var{name}, @var{size}, @var{alignment})
-Like @code{ASM_OUTPUT_ALIGNED_DECL} except that @var{decl} of the
+Like @code{ASM_OUTPUT_ALIGNED_LOCAL} except that @var{decl} of the
 variable to be output, if there is one, or @code{NULL_TREE} if there
 is no corresponding variable.  If you define this macro, GCC will use it
-in place of both @code{ASM_OUTPUT_DECL} and
-@code{ASM_OUTPUT_ALIGNED_DECL}.  Define this macro when you need to see
+in place of both @code{ASM_OUTPUT_LOCAL} and
+@code{ASM_OUTPUT_ALIGNED_LOCAL}.  Define this macro when you need to see
 the variable's decl in order to chose what to output.
 @end defmac
 
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index b0207146e8c..70e0d7f8e01 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -5342,11 +5342,11 @@ as the number of bits.
 @end defmac
 
 @defmac ASM_OUTPUT_ALIGNED_DECL_LOCAL (@var{stream}, @var{decl}, @var{name}, @var{size}, @var{alignment})
-Like @code{ASM_OUTPUT_ALIGNED_DECL} except that @var{decl} of the
+Like @code{ASM_OUTPUT_ALIGNED_LOCAL} except that @var{decl} of the
 variable to be output, if there is one, or @code{NULL_TREE} if there
 is no corresponding variable.  If you define this macro, GCC will use it
-in place of both @code{ASM_OUTPUT_DECL} and
-@code{ASM_OUTPUT_ALIGNED_DECL}.  Define this macro when you need to see
+in place of both @code{ASM_OUTPUT_LOCAL} and
+@code{ASM_OUTPUT_ALIGNED_LOCAL}.  Define this macro when you need to see
 the variable's decl in order to chose what to output.
 @end defmac
 

commit 7fb0f17a66c8a6f91d82c136954edc181e3df9d3
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Mar 12 18:30:16 2020 +0100

    maintainer-scripts: Fix up gcc_release without -l, where mkdir was using umask 077 after migration
    
    2020-03-12  Jakub Jelinek  <jakub@redhat.com>
    
            * gcc_release (upload_files): Without -l, pass -m 755 to the mkdir
            command invoked through ssh.
    
    (cherry picked from commit 3739894d0cfc88b6d84134b827f33b31d646d32a)

diff --git a/maintainer-scripts/gcc_release b/maintainer-scripts/gcc_release
index 74cce1af18d..2456908d716 100755
--- a/maintainer-scripts/gcc_release
+++ b/maintainer-scripts/gcc_release
@@ -398,7 +398,7 @@ upload_files() {
   # Make sure the directory exists on the server.
   if [ $LOCAL -eq 0 ]; then
     ${SSH} -l ${GCC_USERNAME} ${GCC_HOSTNAME} \
-      mkdir -p "${FTP_PATH}/diffs"
+      mkdir -m 755 -p "${FTP_PATH}/diffs"
     UPLOAD_PATH="${GCC_USERNAME}@${GCC_HOSTNAME}:${FTP_PATH}"
   else
     mkdir -p "${FTP_PATH}/diffs" \

commit ce8325e77d923a11dce089a7ef3a24b4737bf95f
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Fri Mar 13 11:33:16 2020 +0100

    aarch64: Fix another bug in aarch64_add_offset_1 [PR94121]
    
    > I'm getting this ICE with -mabi=ilp32:
    >
    > during RTL pass: fwprop1
    > /opt/gcc/gcc-20200312/gcc/testsuite/gcc.dg/pr94121.c: In function 'bar':
    > /opt/gcc/gcc-20200312/gcc/testsuite/gcc.dg/pr94121.c:16:1: internal compiler error: in decompose, at rtl.h:2279
    
    That is a preexisting issue, caused by another bug in the same function.
    When mode is SImode and moffset is 0x80000000 (or anything else with the
    bit 31 set), we need to sign-extend it.
    
    2020-03-13  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94121
            * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
            instead of GEN_INT.
    
    (cherry picked from commit c2f836c413b1e9ae45598338b4a2ecd33bd926fb)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 7e16b6c59c3..e20a4ccc6dc 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2585,7 +2585,8 @@ aarch64_add_offset_1 (scalar_int_mode mode, rtx dest,
   if (emit_move_imm)
     {
       gcc_assert (temp1 != NULL_RTX || can_create_pseudo_p ());
-      temp1 = aarch64_force_temporary (mode, temp1, GEN_INT (moffset));
+      temp1 = aarch64_force_temporary (mode, temp1,
+				       gen_int_mode (moffset, mode));
     }
   insn = emit_insn (offset < 0
 		    ? gen_sub3_insn (dest, src, temp1)

commit 434ddc50ba49442e655c34d85cedd358110e4266
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sun Mar 15 01:27:40 2020 +0100

    tree-nested: Fix handling of *reduction clauses with C array sections [PR93566]
    
    tree-nested.c didn't handle C array sections in {,task_,in_}reduction clauses.
    
    2020-03-14  Jakub Jelinek  <jakub@redhat.com>
    
            PR middle-end/93566
            * tree-nested.c (convert_nonlocal_omp_clauses,
            convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
            with C/C++ array sections.
    
            * testsuite/libgomp.c/pr93566.c: New test.
    
    (cherry picked from commit a8fc40fd551a60a97efbfe3fee08721accd80964)

diff --git a/gcc/tree-nested.c b/gcc/tree-nested.c
index f1557c986b7..e7ea290065b 100644
--- a/gcc/tree-nested.c
+++ b/gcc/tree-nested.c
@@ -1125,7 +1125,7 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi)
 {
   struct nesting_info *const info = (struct nesting_info *) wi->info;
   bool need_chain = false, need_stmts = false;
-  tree clause, decl;
+  tree clause, decl, *pdecl;
   int dummy;
   bitmap new_suppress;
 
@@ -1134,11 +1134,21 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi)
 
   for (clause = *pclauses; clause ; clause = OMP_CLAUSE_CHAIN (clause))
     {
+      pdecl = NULL;
       switch (OMP_CLAUSE_CODE (clause))
 	{
 	case OMP_CLAUSE_REDUCTION:
 	  if (OMP_CLAUSE_REDUCTION_PLACEHOLDER (clause))
 	    need_stmts = true;
+	  if (TREE_CODE (OMP_CLAUSE_DECL (clause)) == MEM_REF)
+	    {
+	      pdecl = &TREE_OPERAND (OMP_CLAUSE_DECL (clause), 0);
+	      if (TREE_CODE (*pdecl) == POINTER_PLUS_EXPR)
+		pdecl = &TREE_OPERAND (*pdecl, 0);
+	      if (TREE_CODE (*pdecl) == INDIRECT_REF
+		  || TREE_CODE (*pdecl) == ADDR_EXPR)
+		pdecl = &TREE_OPERAND (*pdecl, 0);
+	    }
 	  goto do_decl_clause;
 
 	case OMP_CLAUSE_LASTPRIVATE:
@@ -1164,7 +1174,9 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi)
 	case OMP_CLAUSE_USE_DEVICE_PTR:
 	case OMP_CLAUSE_IS_DEVICE_PTR:
 	do_decl_clause:
-	  decl = OMP_CLAUSE_DECL (clause);
+	  if (pdecl == NULL)
+	    pdecl = &OMP_CLAUSE_DECL (clause);
+	  decl = *pdecl;
 	  if (VAR_P (decl)
 	      && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
 	    break;
@@ -1173,7 +1185,7 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi)
 	      if (OMP_CLAUSE_CODE (clause) == OMP_CLAUSE_SHARED)
 		OMP_CLAUSE_SHARED_READONLY (clause) = 0;
 	      bitmap_set_bit (new_suppress, DECL_UID (decl));
-	      OMP_CLAUSE_DECL (clause) = get_nonlocal_debug_decl (info, decl);
+	      *pdecl = get_nonlocal_debug_decl (info, decl);
 	      if (OMP_CLAUSE_CODE (clause) != OMP_CLAUSE_PRIVATE)
 		need_chain = true;
 	    }
@@ -1821,7 +1833,7 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi)
 {
   struct nesting_info *const info = (struct nesting_info *) wi->info;
   bool need_frame = false, need_stmts = false;
-  tree clause, decl;
+  tree clause, decl, *pdecl;
   int dummy;
   bitmap new_suppress;
 
@@ -1830,11 +1842,21 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi)
 
   for (clause = *pclauses; clause ; clause = OMP_CLAUSE_CHAIN (clause))
     {
+      pdecl = NULL;
       switch (OMP_CLAUSE_CODE (clause))
 	{
 	case OMP_CLAUSE_REDUCTION:
 	  if (OMP_CLAUSE_REDUCTION_PLACEHOLDER (clause))
 	    need_stmts = true;
+	  if (TREE_CODE (OMP_CLAUSE_DECL (clause)) == MEM_REF)
+	    {
+	      pdecl = &TREE_OPERAND (OMP_CLAUSE_DECL (clause), 0);
+	      if (TREE_CODE (*pdecl) == POINTER_PLUS_EXPR)
+		pdecl = &TREE_OPERAND (*pdecl, 0);
+	      if (TREE_CODE (*pdecl) == INDIRECT_REF
+		  || TREE_CODE (*pdecl) == ADDR_EXPR)
+		pdecl = &TREE_OPERAND (*pdecl, 0);
+	    }
 	  goto do_decl_clause;
 
 	case OMP_CLAUSE_LASTPRIVATE:
@@ -1860,7 +1882,9 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi)
 	case OMP_CLAUSE_USE_DEVICE_PTR:
 	case OMP_CLAUSE_IS_DEVICE_PTR:
 	do_decl_clause:
-	  decl = OMP_CLAUSE_DECL (clause);
+	  if (pdecl == NULL)
+	    pdecl = &OMP_CLAUSE_DECL (clause);
+	  decl = *pdecl;
 	  if (VAR_P (decl)
 	      && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
 	    break;
@@ -1873,8 +1897,7 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi)
 		  if (OMP_CLAUSE_CODE (clause) == OMP_CLAUSE_SHARED)
 		    OMP_CLAUSE_SHARED_READONLY (clause) = 0;
 		  bitmap_set_bit (new_suppress, DECL_UID (decl));
-		  OMP_CLAUSE_DECL (clause)
-		    = get_local_debug_decl (info, decl, field);
+		  *pdecl = get_local_debug_decl (info, decl, field);
 		  need_frame = true;
 		}
 	    }
diff --git a/libgomp/testsuite/libgomp.c/pr93566.c b/libgomp/testsuite/libgomp.c/pr93566.c
new file mode 100644
index 00000000000..3334bd571f6
--- /dev/null
+++ b/libgomp/testsuite/libgomp.c/pr93566.c
@@ -0,0 +1,113 @@
+/* PR middle-end/93566 */
+/* { dg-additional-options "-std=c99" } */
+
+extern void abort (void);
+
+void
+foo (int *x)
+{
+  void nest (void) {
+    #pragma omp parallel for reduction(+:x[:10])
+    for (int i = 0; i < 1024; i++)
+      for (int j = 0; j < 10; j++)
+	x[j] += j * i;
+  }
+  nest ();
+  for (int i = 0; i < 10; i++)
+    if (x[i] != 1023 * 1024 / 2 * i)
+      abort ();
+}
+
+void
+bar (void)
+{
+  int x[10] = {};
+  void nest (void) {
+    #pragma omp parallel for reduction(+:x[:10])
+    for (int i = 0; i < 1024; i++)
+      for (int j = 0; j < 10; j++)
+	x[j] += j * i;
+  }
+  nest ();
+  for (int i = 0; i < 10; i++)
+    if (x[i] != 1023 * 1024 / 2 * i)
+      abort ();
+}
+
+void
+baz (void)
+{
+  int x[10] = {};
+  void nest (void) {
+    #pragma omp parallel for reduction(+:x[2:5])
+    for (int i = 0; i < 1024; i++)
+      for (int j = 2; j < 7; j++)
+	x[j] += j * i;
+  }
+  nest ();
+  for (int i = 2; i < 7; i++)
+    if (x[i] != 1023 * 1024 / 2 * i)
+      abort ();
+}
+
+void
+qux (int *x)
+{
+  void nest (void) { x++; }
+  nest ();
+  #pragma omp parallel for reduction(+:x[:9])
+  for (int i = 0; i < 1024; i++)
+    for (int j = 0; j < 9; j++)
+      x[j] += j * i;
+  nest ();
+  for (int i = 0; i < 9; i++)
+    if (x[i - 1] != 1023 * 1024 / 2 * i)
+      abort ();
+}
+
+void
+quux (void)
+{
+  int x[10];
+  void nest (void) { for (int i = 0; i < 10; i++) x[i] = 0; }
+  int nest2 (int i) { return x[i]; }
+  nest ();
+  #pragma omp parallel for reduction(+:x[:7])
+  for (int i = 0; i < 1024; i++)
+    for (int j = 0; j < 7; j++)
+      x[j] += j * i;
+  for (int i = 0; i < 7; i++)
+    if (nest2 (i) != 1023 * 1024 / 2 * i)
+      abort ();
+}
+
+void
+corge (void)
+{
+  int x[10];
+  void nest (void) { for (int i = 0; i < 10; i++) x[i] = 0; }
+  int nest2 (int i) { return x[i]; }
+  nest ();
+  #pragma omp parallel for reduction(+:x[2:4])
+  for (int i = 0; i < 1024; i++)
+    for (int j = 2; j < 6; j++)
+      x[j] += j * i;
+  for (int i = 2; i < 6; i++)
+    if (nest2 (i) != 1023 * 1024 / 2 * i)
+      abort ();
+}
+
+int
+main ()
+{
+  int a[10] = {};
+  foo (a);
+  bar ();
+  baz ();
+  for (int i = 0; i < 10; i++)
+    a[i] = 0;
+  qux (a);
+  quux ();
+  corge ();
+  return 0;
+}

commit 7fdfea793bdf47510a8ac6ff11dbf46288ae47a6
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Mon Mar 16 09:03:59 2020 +0100

    tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167]
    
    The following testcase fails with -fcompare-debug.  The problem is that
    bar is marked as address_taken only with -g and not without.
    I've tracked it down to insert_init_stmt calling gimple_regimplify_operands
    even on DEBUG_STMTs.  That function will just insert normal stmts before
    the DEBUG_STMT if the DEBUG_STMT operand isn't gimple val or invariant.
    While DCE will turn those statements into debug temporaries, it can cause
    differences in SSA_NAMEs and more importantly, the ipa references are
    generated from those before the DCE happens.
    On the testcase, the DEBUG_STMT value is (int)bar.
    
    We could generate DEBUG_STMTs with debug temporaries instead, but I fail to
    see the reason to do that, DEBUG_STMTs allow other expressions and all we
    want to ensure is that the expressions aren't too large (arbitrarily
    complex), but during inlining/function versioning I don't see why something
    would queue a DEBUG_STMT with arbitrarily complex expressions in there.
    
    2020-03-16  Jakub Jelinek  <jakub@redhat.com>
    
            PR debug/94167
            * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
            DEBUG_STMTs.
    
            * gcc.dg/pr94167.c: New test.
    
    (cherry picked from commit 378e830538afd4a02e41674cc9161fa59b5e09a9)

diff --git a/gcc/testsuite/gcc.dg/pr94167.c b/gcc/testsuite/gcc.dg/pr94167.c
new file mode 100644
index 00000000000..4b819d3a869
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94167.c
@@ -0,0 +1,33 @@
+/* PR debug/94167 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fcompare-debug" } */
+
+struct S { int g, h; signed char i; int j; signed char k; int l[4]; } a, c;
+struct T { signed char g; } e;
+int *b, d;
+static void foo ();
+
+void
+bar (void)
+{
+  while (d)
+    {
+      int k;
+      struct T f[3];
+      foo (bar, a);
+      for (k = 0;; k++)
+	f[k] = e;
+    }
+}
+
+static inline void
+foo (int x, struct S y, struct T z)
+{
+  for (z.g = 2; z.g; z.g--)
+    {
+      c = a = y;
+      *b |= 6;
+      if (y.g)
+	break;
+    }
+}
diff --git a/gcc/tree-inline.c b/gcc/tree-inline.c
index cd7e477337a..715b1a18f8d 100644
--- a/gcc/tree-inline.c
+++ b/gcc/tree-inline.c
@@ -3177,10 +3177,10 @@ insert_init_stmt (copy_body_data *id, basic_block bb, gimple *init_stmt)
 	  gimple_assign_set_rhs1 (init_stmt, rhs);
 	}
       gsi_insert_after (&si, init_stmt, GSI_NEW_STMT);
-      gimple_regimplify_operands (init_stmt, &si);
-
       if (!is_gimple_debug (init_stmt))
 	{
+	  gimple_regimplify_operands (init_stmt, &si);
+
 	  tree def = gimple_assign_lhs (init_stmt);
 	  insert_init_debug_bind (id, bb, def, def, init_stmt);
 	}

commit feb0b5e3339e3b3f710c4f82d5997c1cd6af67ae
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Mar 17 21:21:16 2020 +0100

    c++: Fix parsing of invalid enum specifiers [PR90995]
    
    The testcase shows some accepts-invalid (the ones without alignas) and
    ice-on-invalid-code (the ones with alignas) cases.
    If the enum doesn't have an underlying type and is not a definition,
    the caller retries to parse it as elaborated type specifier.
    E.g. for enum struct S s it will then pedwarn that elaborated type specifier
    shouldn't have the struct/class keywords.
    The problem is if the enum specifier is not followed by { when it has
    underlying type.  In that case we have already called
    cp_parser_parse_definitely to end the tentative parsing started at the
    beginning of cp_parser_enum_specifier.  But the
    cp_parser_error (parser, "expected %<;%> or %<{%>");
    doesn't emit any error because the whole function is called from yet another
    tentative parse and the caller starts parsing the elaborated type
    specifier where the cp_parser_enum_specifier stopped (i.e. after the
    underlying type token(s)).  The ultimate caller than commits the tentative
    parsing (and even if it wouldn't, it wouldn't know what kind of error
    to report).  I think after seeing enum {,struct,class} : type not being
    followed by { or ;, there is no reason not to report it right away, as it
    can't be valid C++, which is what the patch does.  Not sure if we shouldn't
    also return error_mark_node instead of NULL_TREE, so that the caller doesn't
    try to parse it as elaborated type specifier (the patch doesn't do that
    right now).
    
    Furthermore, while reading the code, I've noticed that
    parser->colon_corrects_to_scope_p is saved and set to false at the start
    of the function, but not restored back in some cases.  Don't have a testcase
    where this would be a problem, but it just seems wrong.  Either we can in
    the two spots replace return NULL_TREE; with { type = NULL_TREE; goto out; }
    or we could perhaps abuse warning_sentinel or create a special class with
    dtor to clean the flag up.
    
    And lastly, I've fixed some formatting issues in the function while reading
    it.
    
    2020-03-17  Jakub Jelinek  <jakub@redhat.com>
    
            PR c++/90995
            * parser.c (cp_parser_enum_specifier): Use temp_override for
            parser->colon_corrects_to_scope_p, replace goto out with return.
            If scoped enum or enum with underlying type is not followed by
            { or ;, call cp_parser_commit_to_tentative_parse before calling
            cp_parser_error and make sure to return error_mark_node instead of
            NULL_TREE.  Formatting fixes.
    
            * g++.dg/cpp0x/enum40.C: New test.
    
    (cherry picked from commit 980a7a0be5a114e285c49ab05ac70881e4f27fc3)

diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index f2983b6102d..a891b1773b8 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -18090,9 +18090,7 @@ cp_parser_enum_specifier (cp_parser* parser)
   bool is_unnamed = false;
   tree underlying_type = NULL_TREE;
   cp_token *type_start_token = NULL;
-  bool saved_colon_corrects_to_scope_p = parser->colon_corrects_to_scope_p;
-
-  parser->colon_corrects_to_scope_p = false;
+  temp_override<bool> cleanup (parser->colon_corrects_to_scope_p, false);
 
   /* Parse tentatively so that we can back up if we don't find a
      enum-specifier.  */
@@ -18132,24 +18130,24 @@ cp_parser_enum_specifier (cp_parser* parser)
 
   push_deferring_access_checks (dk_no_check);
   nested_name_specifier
-      = cp_parser_nested_name_specifier_opt (parser,
-					     /*typename_keyword_p=*/true,
-					     /*check_dependency_p=*/false,
-					     /*type_p=*/false,
-					     /*is_declaration=*/false);
+    = cp_parser_nested_name_specifier_opt (parser,
+					   /*typename_keyword_p=*/true,
+					   /*check_dependency_p=*/false,
+					   /*type_p=*/false,
+					   /*is_declaration=*/false);
 
   if (nested_name_specifier)
     {
       tree name;
 
       identifier = cp_parser_identifier (parser);
-      name =  cp_parser_lookup_name (parser, identifier,
-				     enum_type,
-				     /*is_template=*/false,
-				     /*is_namespace=*/false,
-				     /*check_dependency=*/true,
-				     /*ambiguous_decls=*/NULL,
-				     input_location);
+      name = cp_parser_lookup_name (parser, identifier,
+				    enum_type,
+				    /*is_template=*/false,
+				    /*is_namespace=*/false,
+				    /*check_dependency=*/true,
+				    /*ambiguous_decls=*/NULL,
+				    input_location);
       if (name && name != error_mark_node)
 	{
 	  type = TREE_TYPE (name);
@@ -18228,23 +18226,21 @@ cp_parser_enum_specifier (cp_parser* parser)
     {
       if (cxx_dialect < cxx11 || (!scoped_enum_p && !underlying_type))
 	{
+	  if (has_underlying_type)
+	    cp_parser_commit_to_tentative_parse (parser);
 	  cp_parser_error (parser, "expected %<{%>");
 	  if (has_underlying_type)
-	    {
-	      type = NULL_TREE;
-	      goto out;
-	    }
+	    return error_mark_node;
 	}
       /* An opaque-enum-specifier must have a ';' here.  */
       if ((scoped_enum_p || underlying_type)
 	  && cp_lexer_next_token_is_not (parser->lexer, CPP_SEMICOLON))
 	{
+	  if (has_underlying_type)
+	    cp_parser_commit_to_tentative_parse (parser);
 	  cp_parser_error (parser, "expected %<;%> or %<{%>");
 	  if (has_underlying_type)
-	    {
-	      type = NULL_TREE;
-	      goto out;
-	    }
+	    return error_mark_node;
 	}
     }
 
@@ -18260,9 +18256,7 @@ cp_parser_enum_specifier (cp_parser* parser)
 	  push_scope (nested_name_specifier);
 	}
       else if (TREE_CODE (nested_name_specifier) == NAMESPACE_DECL)
-	{
-	  push_nested_namespace (nested_name_specifier);
-	}
+	push_nested_namespace (nested_name_specifier);
     }
 
   /* Issue an error message if type-definitions are forbidden here.  */
@@ -18422,12 +18416,8 @@ cp_parser_enum_specifier (cp_parser* parser)
 	  pop_scope (nested_name_specifier);
 	}
       else if (TREE_CODE (nested_name_specifier) == NAMESPACE_DECL)
-	{
-	  pop_nested_namespace (nested_name_specifier);
-	}
+	pop_nested_namespace (nested_name_specifier);
     }
- out:
-  parser->colon_corrects_to_scope_p = saved_colon_corrects_to_scope_p;
   return type;
 }
 
diff --git a/gcc/testsuite/g++.dg/cpp0x/enum40.C b/gcc/testsuite/g++.dg/cpp0x/enum40.C
new file mode 100644
index 00000000000..cfdf2a4a18a
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/enum40.C
@@ -0,0 +1,26 @@
+// PR c++/90995
+// { dg-do compile { target c++11 } }
+
+void
+foo ()
+{
+  enum : int a alignas;		// { dg-error "expected" }
+}
+
+void
+bar ()
+{
+  enum : int a;			// { dg-error "expected" }
+}
+
+void
+baz ()
+{
+  enum class a : int b alignas;	// { dg-error "expected" }
+}
+
+void
+qux ()
+{
+  enum class a : int b;		// { dg-error "expected" }
+}

commit cac1949a51e25360a7fd7dc8f473997b7ca048a9
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Mar 17 22:32:34 2020 +0100

    c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172]
    
    The following testcases ICE, because they contain extern variable
    declarations with incomplete enum types that is later completed and after
    that those variables are accessed.  The ICEs are because the vars then may have
    incorrect DECL_MODE etc., e.g. in the first case the var has SImode
    DECL_MODE (the guessed mode for the enum), but the enum then actually has
    DImode because its enumerators don't fit into unsigned int.
    
    The following patch fixes it by using C_TYPE_INCOMPLETE_VARS not just on
    incomplete struct/union types, but also incomplete enum types.
    TYPE_VFIELD can't be used as it is TYPE_MIN_VALUE on ENUMERAL_TYPE,
    thankfully TYPE_LANG_SLOT_1 has been used in the C FE only on
    FUNCTION_TYPEs.
    
    2020-03-17  Jakub Jelinek  <jakub@redhat.com>
    
            PR c/94172
            * c-tree.h (C_TYPE_INCOMPLETE_VARS): Define to TYPE_LANG_SLOT_1
            instead of TYPE_VFIELD, and support it on {RECORD,UNION,ENUMERAL}_TYPE.
            (TYPE_ACTUAL_ARG_TYPES): Check that it is only used on FUNCTION_TYPEs.
            * c-decl.c (pushdecl): Push C_TYPE_INCOMPLETE_VARS also to
            ENUMERAL_TYPEs.
            (finish_incomplete_vars): New function, moved from finish_struct.  Use
            relayout_decl instead of layout_decl.
            (finish_struct): Remove obsolete comment about C_TYPE_INCOMPLETE_VARS
            being TYPE_VFIELD.  Use finish_incomplete_vars.
            (finish_enum): Clear C_TYPE_INCOMPLETE_VARS.  Call
            finish_incomplete_vars.
            * c-typeck.c (c_build_qualified_type): Clear C_TYPE_INCOMPLETE_VARS
            also on ENUMERAL_TYPEs.
    
            * gcc.dg/pr94172-1.c: New test.
            * gcc.dg/pr94172-2.c: New test.
    
    (cherry picked from commit 87ce34fa00cd6b87452d747235da40dfe5b6e00f)

diff --git a/gcc/c/c-decl.c b/gcc/c/c-decl.c
index c566f765899..2cdbff1a960 100644
--- a/gcc/c/c-decl.c
+++ b/gcc/c/c-decl.c
@@ -3111,7 +3111,8 @@ pushdecl (tree x)
 	element = TREE_TYPE (element);
       element = TYPE_MAIN_VARIANT (element);
 
-      if (RECORD_OR_UNION_TYPE_P (element)
+      if ((RECORD_OR_UNION_TYPE_P (element)
+	   || TREE_CODE (element) == ENUMERAL_TYPE)
 	  && (TREE_CODE (x) != TYPE_DECL
 	      || TREE_CODE (TREE_TYPE (x)) == ARRAY_TYPE)
 	  && !COMPLETE_TYPE_P (element))
@@ -7999,6 +8000,26 @@ field_decl_cmp (const void *x_p, const void *y_p)
   return 1;
 }
 
+/* If this structure or union completes the type of any previous
+   variable declaration, lay it out and output its rtl.  */
+static void
+finish_incomplete_vars (tree incomplete_vars, bool toplevel)
+{
+  for (tree x = incomplete_vars; x; x = TREE_CHAIN (x))
+    {
+      tree decl = TREE_VALUE (x);
+      if (TREE_CODE (TREE_TYPE (decl)) == ARRAY_TYPE)
+	layout_array_type (TREE_TYPE (decl));
+      if (TREE_CODE (decl) != TYPE_DECL)
+	{
+	  relayout_decl (decl);
+	  if (c_dialect_objc ())
+	    objc_check_decl (decl);
+	  rest_of_decl_compilation (decl, toplevel, 0);
+	}
+    }
+}
+
 /* Fill in the fields of a RECORD_TYPE or UNION_TYPE node, T.
    LOC is the location of the RECORD_TYPE or UNION_TYPE's definition.
    FIELDLIST is a chain of FIELD_DECL nodes for the fields.
@@ -8247,13 +8268,6 @@ finish_struct (location_t loc, tree t, tree fieldlist, tree attributes,
       }
   }
 
-  /* Note: C_TYPE_INCOMPLETE_VARS overloads TYPE_VFIELD which is used
-     in dwarf2out via rest_of_decl_compilation below and means
-     something totally different.  Since we will be clearing
-     C_TYPE_INCOMPLETE_VARS shortly after we iterate through them,
-     clear it ahead of time and avoid problems in dwarf2out.  Ideally,
-     C_TYPE_INCOMPLETE_VARS should use some language specific
-     node.  */
   tree incomplete_vars = C_TYPE_INCOMPLETE_VARS (TYPE_MAIN_VARIANT (t));
   for (x = TYPE_MAIN_VARIANT (t); x; x = TYPE_NEXT_VARIANT (x))
     {
@@ -8283,21 +8297,7 @@ finish_struct (location_t loc, tree t, tree fieldlist, tree attributes,
   /* Finish debugging output for this type.  */
   rest_of_type_compilation (t, toplevel);
 
-  /* If this structure or union completes the type of any previous
-     variable declaration, lay it out and output its rtl.  */
-  for (x = incomplete_vars; x; x = TREE_CHAIN (x))
-    {
-      tree decl = TREE_VALUE (x);
-      if (TREE_CODE (TREE_TYPE (decl)) == ARRAY_TYPE)
-	layout_array_type (TREE_TYPE (decl));
-      if (TREE_CODE (decl) != TYPE_DECL)
-	{
-	  layout_decl (decl, 0);
-	  if (c_dialect_objc ())
-	    objc_check_decl (decl);
-	  rest_of_decl_compilation (decl, toplevel, 0);
-	}
-    }
+  finish_incomplete_vars (incomplete_vars, toplevel);
 
   /* If we're inside a function proper, i.e. not file-scope and not still
      parsing parameters, then arrange for the size of a variable sized type
@@ -8576,8 +8576,10 @@ finish_enum (tree enumtype, tree values, tree attributes)
   TYPE_LANG_SPECIFIC (enumtype) = lt;
 
   /* Fix up all variant types of this enum type.  */
+  tree incomplete_vars = C_TYPE_INCOMPLETE_VARS (TYPE_MAIN_VARIANT (enumtype));
   for (tem = TYPE_MAIN_VARIANT (enumtype); tem; tem = TYPE_NEXT_VARIANT (tem))
     {
+      C_TYPE_INCOMPLETE_VARS (tem) = NULL_TREE;
       if (tem == enumtype)
 	continue;
       TYPE_VALUES (tem) = TYPE_VALUES (enumtype);
@@ -8596,6 +8598,8 @@ finish_enum (tree enumtype, tree values, tree attributes)
   /* Finish debugging output for this type.  */
   rest_of_type_compilation (enumtype, toplevel);
 
+  finish_incomplete_vars (incomplete_vars, toplevel);
+
   /* If this enum is defined inside a struct, add it to
      struct_types.  */
   if (warn_cxx_compat
diff --git a/gcc/c/c-tree.h b/gcc/c/c-tree.h
index bd7d396c67d..fb99cc7acd2 100644
--- a/gcc/c/c-tree.h
+++ b/gcc/c/c-tree.h
@@ -38,9 +38,12 @@ along with GCC; see the file COPYING3.  If not see
    nonzero if the definition of the type has already started.  */
 #define C_TYPE_BEING_DEFINED(TYPE) TYPE_LANG_FLAG_0 (TYPE)
 
-/* In an incomplete RECORD_TYPE or UNION_TYPE, a list of variable
-   declarations whose type would be completed by completing that type.  */
-#define C_TYPE_INCOMPLETE_VARS(TYPE) TYPE_VFIELD (TYPE)
+/* In an incomplete RECORD_TYPE, UNION_TYPE or ENUMERAL_TYPE, a list of
+   variable declarations whose type would be completed by completing
+   that type.  */
+#define C_TYPE_INCOMPLETE_VARS(TYPE) \
+  TYPE_LANG_SLOT_1 (TREE_CHECK4 (TYPE, RECORD_TYPE, UNION_TYPE, \
+				 QUAL_UNION_TYPE, ENUMERAL_TYPE))
 
 /* In an IDENTIFIER_NODE, nonzero if this identifier is actually a
    keyword.  C_RID_CODE (node) is then the RID_* value of the keyword.  */
@@ -107,7 +110,8 @@ along with GCC; see the file COPYING3.  If not see
 /* For FUNCTION_TYPE, a hidden list of types of arguments.  The same as
    TYPE_ARG_TYPES for functions with prototypes, but created for functions
    without prototypes.  */
-#define TYPE_ACTUAL_ARG_TYPES(NODE) TYPE_LANG_SLOT_1 (NODE)
+#define TYPE_ACTUAL_ARG_TYPES(NODE) \
+  TYPE_LANG_SLOT_1 (FUNCTION_TYPE_CHECK (NODE))
 
 /* For a CONSTRUCTOR, whether some initializer contains a
    subexpression meaning it is not a constant expression.  */
diff --git a/gcc/c/c-typeck.c b/gcc/c/c-typeck.c
index 8c4a1939f3d..eb4886b7289 100644
--- a/gcc/c/c-typeck.c
+++ b/gcc/c/c-typeck.c
@@ -14268,7 +14268,8 @@ c_build_qualified_type (tree type, int type_quals, tree orig_qual_type,
 		   : build_qualified_type (type, type_quals));
   /* A variant type does not inherit the list of incomplete vars from the
      type main variant.  */
-  if (RECORD_OR_UNION_TYPE_P (var_type)
+  if ((RECORD_OR_UNION_TYPE_P (var_type)
+       || TREE_CODE (var_type) == ENUMERAL_TYPE)
       && TYPE_MAIN_VARIANT (var_type) != var_type)
     C_TYPE_INCOMPLETE_VARS (var_type) = 0;
   return var_type;
diff --git a/gcc/testsuite/gcc.dg/pr94172-1.c b/gcc/testsuite/gcc.dg/pr94172-1.c
new file mode 100644
index 00000000000..12f84af42dd
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94172-1.c
@@ -0,0 +1,12 @@
+/* PR c/94172 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern enum E e;
+enum E { l = 0x100000000ULL };
+
+unsigned long long
+foo (void)
+{
+  return e;
+}
diff --git a/gcc/testsuite/gcc.dg/pr94172-2.c b/gcc/testsuite/gcc.dg/pr94172-2.c
new file mode 100644
index 00000000000..bb7b060d7b2
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94172-2.c
@@ -0,0 +1,19 @@
+/* PR c/94172 */
+/* { dg-do compile } */
+/* { dg-options "-Os -g -fshort-enums" } */
+
+extern enum E e;
+extern void bar (int a);
+enum E { F };
+
+void
+foo (int a)
+{
+  int l = e;
+  if (a)
+    {
+      __asm volatile ("nop");
+      l = 0;
+    }
+  bar (l);
+}

commit 2b0aaa4970a8d174b00fb98b4d24550d1c9a4e3a
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Mar 19 10:24:16 2020 +0100

    phiopt: Avoid -fcompare-debug bug in phiopt [PR94211]
    
    Two years ago, I've added support for up to 2 simple preparation statements
    in value_replacement, but the
    -      && estimate_num_insns (assign, &eni_time_weights)
    +      && estimate_num_insns (bb_seq (middle_bb), &eni_time_weights)
    change, meant that we compute the cost of all those statements rather than
    just the single assign that has been the single supported non-debug
    statement in the bb before, doesn't do what I thought would do, gimple_seq
    is just gimple * and thus it can't be really overloaded depending on whether
    we pass a single gimple * or a whole sequence.  Which means in the last
    two years it doesn't count all the statements, but only the first one.
    With -g that happens to be a DEBUG_STMT, or it could be e.g. the first
    preparation statement which could be much cheaper than the actual assign.
    
    2020-03-19  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/94211
            * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
            instead of estimate_num_insns for bb_seq (middle_bb).  Rename
            emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
            all uses.
    
            * gcc.dg/pr94211.c: New test.
    
    (cherry picked from commit 8db876e9c045c57d2dc5bd08a6e250f822efaad0)

diff --git a/gcc/testsuite/gcc.dg/pr94211.c b/gcc/testsuite/gcc.dg/pr94211.c
new file mode 100644
index 00000000000..3e160e457fe
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94211.c
@@ -0,0 +1,12 @@
+/* PR tree-optimization/94211 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fcompare-debug" } */
+
+long
+foo (long a, long b)
+{
+  if (__builtin_expect (b == 1, 1))
+    return a;
+  int e = a + 1;
+  return a / b;
+}
diff --git a/gcc/tree-ssa-phiopt.c b/gcc/tree-ssa-phiopt.c
index 53f46dc0350..c6826cb87a2 100644
--- a/gcc/tree-ssa-phiopt.c
+++ b/gcc/tree-ssa-phiopt.c
@@ -890,7 +890,7 @@ value_replacement (basic_block cond_bb, basic_block middle_bb,
   gimple *cond;
   edge true_edge, false_edge;
   enum tree_code code;
-  bool emtpy_or_with_defined_p = true;
+  bool empty_or_with_defined_p = true;
 
   /* If the type says honor signed zeros we cannot do this
      optimization.  */
@@ -907,7 +907,7 @@ value_replacement (basic_block cond_bb, basic_block middle_bb,
       gsi_next_nondebug (&gsi);
       if (!is_gimple_assign (stmt))
 	{
-	  emtpy_or_with_defined_p = false;
+	  empty_or_with_defined_p = false;
 	  continue;
 	}
       /* Now try to adjust arg0 or arg1 according to the computation
@@ -917,7 +917,7 @@ value_replacement (basic_block cond_bb, basic_block middle_bb,
 	     && jump_function_from_stmt (&arg0, stmt))
 	    || (lhs == arg1
 		&& jump_function_from_stmt (&arg1, stmt)))
-	emtpy_or_with_defined_p = false;
+	empty_or_with_defined_p = false;
     }
 
   cond = last_stmt (cond_bb);
@@ -969,7 +969,7 @@ value_replacement (basic_block cond_bb, basic_block middle_bb,
       /* If the middle basic block was empty or is defining the
 	 PHI arguments and this is a single phi where the args are different
 	 for the edges e0 and e1 then we can remove the middle basic block. */
-      if (emtpy_or_with_defined_p
+      if (empty_or_with_defined_p
 	  && single_non_singleton_phi_for_edges (phi_nodes (gimple_bb (phi)),
 						 e0, e1) == phi)
 	{
@@ -1087,7 +1087,7 @@ value_replacement (basic_block cond_bb, basic_block middle_bb,
       && profile_status_for_fn (cfun) != PROFILE_ABSENT
       && EDGE_PRED (middle_bb, 0)->probability < profile_probability::even ()
       /* If assign is cheap, there is no point avoiding it.  */
-      && estimate_num_insns (bb_seq (middle_bb), &eni_time_weights)
+      && estimate_num_insns_seq (bb_seq (middle_bb), &eni_time_weights)
 	 >= 3 * estimate_num_insns (cond, &eni_time_weights))
     return 0;
 

commit 4ef4c88af7007ff0563e65269e1807b1ba30085d
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Mar 19 12:22:47 2020 +0100

    c++: Fix up handling of captured vars in lambdas in OpenMP clauses [PR93931]
    
    Without the parser.c change we were ICEing on the testcase, because while the
    uses of the captured vars inside of the constructs were replaced with capture
    proxy decls, we didn't do that for decls in OpenMP clauses.
    
    With that fixed, we don't ICE anymore, but the testcase is miscompiled and FAILs
    at runtime.  This is because the capture proxy decls have DECL_VALUE_EXPR and
    during gimplification we were gimplifying those to their DECL_VALUE_EXPRs.
    That is fine for shared vars, but for privatized ones we must not do that.
    So that is what the cp-gimplify.c changes do.  Had to add a DECL_CONTEXT check
    before calling is_capture_proxy because some VAR_DECLs don't have DECL_CONTEXT
    set (yet) and is_capture_proxy relies on that being non-NULL always.
    
    2020-03-19  Jakub Jelinek  <jakub@redhat.com>
    
            PR c++/93931
            * parser.c (cp_parser_omp_var_list_no_open): Call process_outer_var_ref
            on outer_automatic_var_p decls.
            * cp-gimplify.c (cxx_omp_disregard_value_expr): Return true also for
            capture proxy decls.
    
            * testsuite/libgomp.c++/pr93931.C: New test.
    
    (cherry picked from commit 484206967f958fc47827a71654fe52a98adc95cb)

diff --git a/gcc/cp/cp-gimplify.c b/gcc/cp/cp-gimplify.c
index dc946b9c682..113a46a156c 100644
--- a/gcc/cp/cp-gimplify.c
+++ b/gcc/cp/cp-gimplify.c
@@ -2101,12 +2101,17 @@ cxx_omp_finish_clause (tree c, gimple_seq *)
 bool
 cxx_omp_disregard_value_expr (tree decl, bool shared)
 {
-  return !shared
-	 && VAR_P (decl)
-	 && DECL_HAS_VALUE_EXPR_P (decl)
-	 && DECL_ARTIFICIAL (decl)
-	 && DECL_LANG_SPECIFIC (decl)
-	 && DECL_OMP_PRIVATIZED_MEMBER (decl);
+  if (shared)
+    return false;
+  if (VAR_P (decl)
+      && DECL_HAS_VALUE_EXPR_P (decl)
+      && DECL_ARTIFICIAL (decl)
+      && DECL_LANG_SPECIFIC (decl)
+      && DECL_OMP_PRIVATIZED_MEMBER (decl))
+    return true;
+  if (VAR_P (decl) && DECL_CONTEXT (decl) && is_capture_proxy (decl))
+    return true;
+  return false;
 }
 
 /* Fold expression X which is used as an rvalue if RVAL is true.  */
diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index a891b1773b8..70fc1c89019 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -31684,6 +31684,8 @@ cp_parser_omp_var_list_no_open (cp_parser *parser, enum omp_clause_code kind,
 	    cp_parser_name_lookup_error (parser, name, decl, NLE_NULL,
 					 token->location);
 	}
+      if (outer_automatic_var_p (decl))
+	decl = process_outer_var_ref (decl, tf_warning_or_error);
       if (decl == error_mark_node)
 	;
       else if (kind != 0)
diff --git a/libgomp/testsuite/libgomp.c++/pr93931.C b/libgomp/testsuite/libgomp.c++/pr93931.C
new file mode 100644
index 00000000000..4d4232ef340
--- /dev/null
+++ b/libgomp/testsuite/libgomp.c++/pr93931.C
@@ -0,0 +1,120 @@
+// PR c++/93931
+// { dg-do run }
+// { dg-options "-O2 -std=c++14" }
+
+extern "C" void abort ();
+
+void
+sink (int &x)
+{
+  int *volatile p;
+  p = &x;
+  (*p)++;
+}
+
+int
+foo ()
+{
+  int r = 0;
+  [&r] () {
+#pragma omp parallel for reduction(+ : r)
+    for (int i = 0; i < 1024; ++i)
+      r += i;
+  } ();
+  return r;
+}
+
+int
+bar ()
+{
+  int l = 0;
+  [&l] () {
+#pragma omp parallel for lastprivate (l)
+    for (int i = 0; i < 1024; ++i)
+      l = i;
+  } ();
+  return l;
+}
+
+void
+baz ()
+{
+  int f = 18;
+  [&f] () {
+#pragma omp parallel for firstprivate (f)
+    for (int i = 0; i < 1024; ++i)
+      {
+	sink (f);
+	f += 3;
+	sink (f);
+	if (f != 23)
+	  abort ();
+	sink (f);
+	f -= 7;
+	sink (f);
+      }
+  } ();
+  if (f != 18)
+    abort ();
+}
+
+int
+qux ()
+{
+  int r = 0;
+  [&] () {
+#pragma omp parallel for reduction(+ : r)
+    for (int i = 0; i < 1024; ++i)
+      r += i;
+  } ();
+  return r;
+}
+
+int
+corge ()
+{
+  int l = 0;
+  [&] () {
+#pragma omp parallel for lastprivate (l)
+    for (int i = 0; i < 1024; ++i)
+      l = i;
+  } ();
+  return l;
+}
+
+void
+garply ()
+{
+  int f = 18;
+  [&] () {
+#pragma omp parallel for firstprivate (f)
+    for (int i = 0; i < 1024; ++i)
+      {
+	sink (f);
+	f += 3;
+	sink (f);
+	if (f != 23)
+	  abort ();
+	sink (f);
+	f -= 7;
+	sink (f);
+      }
+  } ();
+  if (f != 18)
+    abort ();
+}
+
+int
+main ()
+{
+  if (foo () != 1024 * 1023 / 2)
+    abort ();
+  if (bar () != 1023)
+    abort ();
+  baz ();
+  if (qux () != 1024 * 1023 / 2)
+    abort ();
+  if (corge () != 1023)
+    abort ();
+  garply ();
+}

commit c9790fa67882765eb293774e629cd071de857952
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 7 20:57:37 2020 +0200

    if-conv: Fix -fcompare-debug bugs in ifcvt_local_dce [PR94283]
    
    The following testcase shows -fcompare-debug bugs in ifcvt_local_dce,
    where the decisions what statements are needed is based also on debug stmt
    operands, which is wrong.
    So, this patch makes sure to never add debug stmt to the worklist, or never
    add an assign to worklist just because it is used in a debug stmt in another
    bb.
    
    2020-03-24  Jakub Jelinek  <jakub@redhat.com>
    
            PR debug/94283
            * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
            GF_PLF_2, but don't add them to worklist.  Don't add an assigment to
            worklist or set GF_PLF_2 just because it is used in a debug stmt in
            another bb.  Formatting improvements.
    
            * gcc.target/i386/pr94283.c: New test.
    
    (cherry picked from commit 4dcfd4e56b0d22af12750372f3e0b49249b1d473)

diff --git a/gcc/testsuite/gcc.target/i386/pr94283.c b/gcc/testsuite/gcc.target/i386/pr94283.c
new file mode 100644
index 00000000000..4982f7d01d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr94283.c
@@ -0,0 +1,5 @@
+/* PR debug/94283 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -fcompare-debug -mavx2" } */
+
+#include "../../gcc.dg/fold-bopcond-1.c"
diff --git a/gcc/tree-if-conv.c b/gcc/tree-if-conv.c
index d205e605a63..dd9bf469730 100644
--- a/gcc/tree-if-conv.c
+++ b/gcc/tree-if-conv.c
@@ -2755,9 +2755,12 @@ ifcvt_local_dce (basic_block bb)
   for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
     {
       stmt = gsi_stmt (gsi);
-      if (gimple_store_p (stmt)
-	  || gimple_assign_load_p (stmt)
-	  || is_gimple_debug (stmt))
+      if (is_gimple_debug (stmt))
+	{
+	  gimple_set_plf (stmt, GF_PLF_2, true);
+	  continue;
+	}
+      if (gimple_store_p (stmt) || gimple_assign_load_p (stmt))
 	{
 	  gimple_set_plf (stmt, GF_PLF_2, true);
 	  worklist.safe_push (stmt);
@@ -2778,7 +2781,7 @@ ifcvt_local_dce (basic_block bb)
 	  FOR_EACH_IMM_USE_FAST (use_p, imm_iter, lhs)
 	    {
 	      stmt1 = USE_STMT (use_p);
-	      if (gimple_bb (stmt1) != bb)
+	      if (!is_gimple_debug (stmt1) && gimple_bb (stmt1) != bb)
 		{
 		  gimple_set_plf (stmt, GF_PLF_2, true);
 		  worklist.safe_push (stmt);
@@ -2801,8 +2804,7 @@ ifcvt_local_dce (basic_block bb)
 	  if (TREE_CODE (use) != SSA_NAME)
 	    continue;
 	  stmt1 = SSA_NAME_DEF_STMT (use);
-	  if (gimple_bb (stmt1) != bb
-	      || gimple_plf (stmt1, GF_PLF_2))
+	  if (gimple_bb (stmt1) != bb || gimple_plf (stmt1, GF_PLF_2))
 	    continue;
 	  gimple_set_plf (stmt1, GF_PLF_2, true);
 	  worklist.safe_push (stmt1);

commit 2e4d37fcb34b16b73a9af6fa76b48ac5c554b550
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Mar 25 08:08:04 2020 +0100

    if-conv: Delete dead stmts backwards in ifcvt_local_dce [PR94283]
    
    > > This patch caused:
    > >
    > > gcc /home/marxin/Programming/gcc/gcc/testsuite/gcc.c-torture/compile/990625-2.c -O3 -g -fno-tree-dce -c
    > > during GIMPLE pass: ifcvt
    > > /home/marxin/Programming/gcc/gcc/testsuite/gcc.c-torture/compile/990625-2.c: In function ‘broken030599’:
    > > /home/marxin/Programming/gcc/gcc/testsuite/gcc.c-torture/compile/990625-2.c:2:1: internal compiler error: Segmentation fault
    >
    > Likely
    >
    >   /* Delete dead statements.  */
    >   gsi = gsi_start_bb (bb);
    >   while (!gsi_end_p (gsi))
    >     {
    >
    > needs to instead work back-to-front for debug stmt adjustment to work
    
    Indeed, that seems to work.
    
    2020-03-25  Richard Biener  <rguenther@suse.de>
                Jakub Jelinek  <jakub@redhat.com>
    
            PR debug/94283
            * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
    
            * gcc.dg/pr94283.c: New test.
    
    Co-authored-by: Richard Biener <rguenther@suse.de>
    (cherry picked from commit 8ea7970c4968517fb73f42bcca40d316adacf215)

diff --git a/gcc/testsuite/gcc.dg/pr94283.c b/gcc/testsuite/gcc.dg/pr94283.c
new file mode 100644
index 00000000000..ac162d6ac7b
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94283.c
@@ -0,0 +1,16 @@
+/* PR debug/94283 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -fno-tree-dce -fcompare-debug" } */
+
+void
+foo (int *n)
+{
+  for (int i = 0; i < 32; i++)
+    {
+      int x = 0;
+      x++;
+      if (i & 4)
+	x++;
+      x++;
+    }
+}
diff --git a/gcc/tree-if-conv.c b/gcc/tree-if-conv.c
index dd9bf469730..db38b1328ff 100644
--- a/gcc/tree-if-conv.c
+++ b/gcc/tree-if-conv.c
@@ -2811,13 +2811,15 @@ ifcvt_local_dce (basic_block bb)
 	}
     }
   /* Delete dead statements.  */
-  gsi = gsi_start_bb (bb);
+  gsi = gsi_last_bb (bb);
   while (!gsi_end_p (gsi))
     {
+      gimple_stmt_iterator gsiprev = gsi;
+      gsi_prev (&gsiprev);
       stmt = gsi_stmt (gsi);
       if (gimple_plf (stmt, GF_PLF_2))
 	{
-	  gsi_next (&gsi);
+	  gsi = gsiprev;
 	  continue;
 	}
       if (dump_file && (dump_flags & TDF_DETAILS))
@@ -2827,6 +2829,7 @@ ifcvt_local_dce (basic_block bb)
 	}
       gsi_remove (&gsi, true);
       release_defs (stmt);
+      gsi = gsiprev;
     }
 }
 

commit 0aa738f8d4469434c131dc36711a045cfd8ecd7f
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 7 20:59:37 2020 +0200

    varasm: Fix output_constructor where a RANGE_EXPR index needs to skip some elts [PR94303]
    
    The following testcase is miscompiled, because output_constructor doesn't
    output the initializer correctly.  The FE creates {[1...2] = 9} in this
    case, and we emit .long 9; long 9; .zero 8 instead of the expected
    .zero 8; .long 9; .long 9.  If the CONSTRUCTOR is {[1] = 9, [2] = 9},
    output_constructor_regular_field has code to notice that the current
    location (local->total_bytes) is smaller than the location we want to write
    to (1*sizeof(elt)) and will call assemble_zeros to skip those.  But
    RANGE_EXPRs are handled by a different function which didn't do this,
    so for RANGE_EXPRs we emitted them properly only if local->total_bytes
    was always equal to the location where the RANGE_EXPR needs to start.
    
    2020-03-25  Jakub Jelinek  <jakub@redhat.com>
    
            PR middle-end/94303
            * varasm.c (output_constructor_array_range): If local->index
            RANGE_EXPR doesn't start at the current location in the constructor,
            skip needed number of bytes using assemble_zeros or assert we don't
            go backwards.
    
            PR middle-end/94303
            * g++.dg/torture/pr94303.C: New test.
    
    (cherry picked from commit 56407bab53a514ffcd6ac011965cebdc5eb3ef54)

diff --git a/gcc/testsuite/g++.dg/torture/pr94303.C b/gcc/testsuite/g++.dg/torture/pr94303.C
new file mode 100644
index 00000000000..45b90a2249d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/torture/pr94303.C
@@ -0,0 +1,17 @@
+// PR middle-end/94303
+// { dg-do run }
+
+struct A {
+  int d = 9;
+  A () = default;
+  A (int x) : d(x) {}
+  void foo () { if (d < 1) __builtin_abort (); }
+};
+
+A a[3] = { 1 };
+
+int
+main ()
+{
+  a[2].foo ();
+}
diff --git a/gcc/varasm.c b/gcc/varasm.c
index adf279152b4..f5ca6c2d9af 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -5069,6 +5069,26 @@ struct oc_local_state {
 static void
 output_constructor_array_range (oc_local_state *local)
 {
+  /* Perform the index calculation in modulo arithmetic but
+     sign-extend the result because Ada has negative DECL_FIELD_OFFSETs
+     but we are using an unsigned sizetype.  */
+  unsigned prec = TYPE_PRECISION (sizetype);
+  offset_int idx = wi::sext (wi::to_offset (TREE_OPERAND (local->index, 0))
+			     - wi::to_offset (local->min_index), prec);
+  tree valtype = TREE_TYPE (local->val);
+  HOST_WIDE_INT fieldpos
+    = (idx * wi::to_offset (TYPE_SIZE_UNIT (valtype))).to_short_addr ();
+
+  /* Advance to offset of this element.  */
+  if (fieldpos > local->total_bytes)
+    {
+      assemble_zeros (fieldpos - local->total_bytes);
+      local->total_bytes = fieldpos;
+    }
+  else
+    /* Must not go backwards.  */
+    gcc_assert (fieldpos == local->total_bytes);
+
   unsigned HOST_WIDE_INT fieldsize
     = int_size_in_bytes (TREE_TYPE (local->type));
 

commit c53f6b6c38fd3c61257c9f311ca9dc21135223b4
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Mar 28 10:21:52 2020 +0100

    reassoc: Fix -fcompare-debug bug in reassociate_bb [PR94329]
    
    The following testcase FAILs with -fcompare-debug, because reassociate_bb
    mishandles the case when the last stmt in a bb has zero uses.  In that case
    reassoc_remove_stmt (like gsi_remove) moves the iterator to the next stmt,
    i.e. gsi_end_p is true, which means the code sets the iterator back to
    gsi_last_bb.  The problem is that the for loop does gsi_prev on that before
    handling the next statement, which means the former penultimate stmt, now
    last one, is not processed by reassociate_bb.
    Now, with -g, if there is at least one debug stmt at the end of the bb,
    reassoc_remove_stmt moves the iterator to that following debug stmt and we
    just do gsi_prev and continue with the former penultimate non-debug stmt,
    now last non-debug stmt.
    
    The following patch fixes that by not doing the gsi_prev in this case; there
    are too many continue; cases, so I didn't want to copy over the gsi_prev to
    all of them, so this patch uses a bool for that instead.  The second
    gsi_end_p check isn't needed anymore, because when we don't do the
    undesirable gsi_prev after gsi = gsi_last_bb, the loop !gsi_end_p (gsi)
    condition will catch the removal of the very last stmt from a bb.
    
    2020-03-28  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/94329
            * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
            on the last stmt in a bb, make sure gsi_prev isn't done immediately
            after gsi_last_bb.
    
            * gfortran.dg/pr94329.f90: New test.
    
    (cherry picked from commit aa9c08ef97f4df1ebb1fc8d72f2e7f9f8c1045c2)

diff --git a/gcc/testsuite/gfortran.dg/pr94329.f90 b/gcc/testsuite/gfortran.dg/pr94329.f90
new file mode 100644
index 00000000000..9efcf4b6524
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr94329.f90
@@ -0,0 +1,12 @@
+! PR tree-optimization/94329
+! { dg-do compile }
+! { dg-options "-O1 -fno-tree-loop-optimize -fwrapv -fcompare-debug" }
+
+subroutine pr94329 (s, t)
+  real :: s, t(:,:)
+  do i = 1,3
+    do j = 1,3
+      s = t(i,j)
+    end do
+  end do
+end
diff --git a/gcc/tree-ssa-reassoc.c b/gcc/tree-ssa-reassoc.c
index 9ad3581f85d..e2a08c6ad24 100644
--- a/gcc/tree-ssa-reassoc.c
+++ b/gcc/tree-ssa-reassoc.c
@@ -5829,8 +5829,11 @@ reassociate_bb (basic_block bb)
   if (stmt && !gimple_visited_p (stmt))
     cfg_cleanup_needed |= maybe_optimize_range_tests (stmt);
 
-  for (gsi = gsi_last_bb (bb); !gsi_end_p (gsi); gsi_prev (&gsi))
+  bool do_prev = false;
+  for (gsi = gsi_last_bb (bb);
+       !gsi_end_p (gsi); do_prev ? gsi_prev (&gsi) : (void) 0)
     {
+      do_prev = true;
       stmt = gsi_stmt (gsi);
 
       if (is_gimple_assign (stmt)
@@ -5856,15 +5859,12 @@ reassociate_bb (basic_block bb)
 		  release_defs (stmt);
 		  /* We might end up removing the last stmt above which
 		     places the iterator to the end of the sequence.
-		     Reset it to the last stmt in this case which might
-		     be the end of the sequence as well if we removed
-		     the last statement of the sequence.  In which case
-		     we need to bail out.  */
+		     Reset it to the last stmt in this case and make sure
+		     we don't do gsi_prev in that case.  */
 		  if (gsi_end_p (gsi))
 		    {
 		      gsi = gsi_last_bb (bb);
-		      if (gsi_end_p (gsi))
-			break;
+		      do_prev = false;
 		    }
 		}
 	      continue;

commit 6609a2a20e21f7f318655ffdecf4834d75e72d12
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 7 21:00:28 2020 +0200

    Fix vextract* masked patterns [PR93069]
    
    The AVX512F documentation clearly states that in instructions where the
    destination is a memory only merging-masking is possible, not zero-masking,
    and the assembler enforces that.
    
    The testcase in this patch fails to assemble because of
    Error: unsupported masking for `vextracti32x8'
    on
            vextracti32x8   $0x0, %zmm1, -64(%rsp){%k1}{z}
    For the vector extraction patterns, we apparently have 7 *_maskm patterns
    that only accept memory destinations and rtx_equal_p merge-masking source
    for it, 7 *<mask_name> corresponding patterns that allow memory destination
    only for the non-masked cases (through <store_mask_constraint>), then 2
    *<mask_name> patterns (lo ssehalf V16FI and lo ssehalf VI8F_256 ones) which
    do allow memory destination even for masked cases and are the cause of the
    testsuite failure, because we must not allow C constraint if the destination
    is m, and finally one pair of patterns (separate * and *_mask, hi ssehalf
    VI4F_256), which has another issue (for which I don't have a testcase
    though), where if it would match zero-masking with register destination,
    it wouldn't emit the needed {z} into assembly.
    The attached patch fixes those 3 issues only, perhaps more suitable for
    backporting.
    
    2020-03-30  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/93069
            * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
            <store_mask_constraint> instead of m in output operand constraint.
            (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
            %{%3%}.
    
            * gcc.target/i386/avx512vl-pr93069.c: New test.
            * gcc.dg/vect/pr93069.c: New test.
    
    (cherry picked from commit 57e276f3e304ef92483763ee1028e5b3e1345e0f)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 05a060d996d..94a572e897b 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -7673,7 +7673,8 @@
 })
 
 (define_insn "vec_extract_lo_<mode><mask_name>"
-  [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,v,m")
+  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
+					  "=v,v,<store_mask_constraint>")
 	(vec_select:<ssehalfvecmode>
 	  (match_operand:V16FI 1 "<store_mask_predicate>"
 				 "v,<store_mask_constraint>,v")
@@ -7730,7 +7731,8 @@
 })
 
 (define_insn "vec_extract_lo_<mode><mask_name>"
-  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,v,m")
+  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
+					  "=v,v,<store_mask_constraint>")
 	(vec_select:<ssehalfvecmode>
 	  (match_operand:VI8F_256 1 "<store_mask_predicate>"
 				    "v,<store_mask_constraint>,v")
@@ -7740,7 +7742,7 @@
    && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
 {
   if (<mask_applied>)
-    return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}";
+    return "vextract<shuffletype>64x2\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
   else
     return "#";
 }
diff --git a/gcc/testsuite/gcc.dg/vect/pr93069.c b/gcc/testsuite/gcc.dg/vect/pr93069.c
new file mode 100644
index 00000000000..45c740dbe9e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr93069.c
@@ -0,0 +1,10 @@
+/* PR target/93069 */
+/* { dg-do assemble { target vect_simd_clones } } */
+/* { dg-options "-O2 -fopenmp-simd" } */
+
+#pragma omp declare simd
+int
+foo (int x, int y)
+{
+  return x == 0 ? x : y;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c
new file mode 100644
index 00000000000..b38b5ad32bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c
@@ -0,0 +1,12 @@
+/* PR target/93069 */
+/* { dg-do assemble { target vect_simd_clones } } */
+/* { dg-options "-O2 -fopenmp-simd -mtune=skylake-avx512" } */
+/* { dg-additional-options "-mavx512vl" { target avx512vl } } */
+/* { dg-additional-options "-mavx512dq" { target avx512dq } } */
+
+#pragma omp declare simd
+int
+foo (int x, int y)
+{
+  return x == 0 ? x : y;
+}

commit ff421cb31d2d51f337dffdaf6b008fe1737d239f
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Mar 31 11:06:43 2020 +0200

    fold-const: Fix division folding with vector operands [PR94412]
    
    The following testcase is miscompiled since 4.9, we treat unsigned
    vector types as if they were signed and "optimize" negations across it.
    
    2020-03-31  Marc Glisse  <marc.glisse@inria.fr>
                Jakub Jelinek  <jakub@redhat.com>
    
            PR middle-end/94412
            * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
            ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
    
            * gcc.c-torture/execute/pr94412.c: New test.
    
    Co-authored-by: Marc Glisse <marc.glisse@inria.fr>
    (cherry picked from commit 8f99f9e6ccec167a5ba67dcc08e6c14948595b82)

diff --git a/gcc/fold-const.c b/gcc/fold-const.c
index 9183c3752ce..85b85398933 100644
--- a/gcc/fold-const.c
+++ b/gcc/fold-const.c
@@ -10416,11 +10416,11 @@ fold_binary_loc (location_t loc, enum tree_code code, tree type,
 
       /* Convert -A / -B to A / B when the type is signed and overflow is
 	 undefined.  */
-      if ((!INTEGRAL_TYPE_P (type) || TYPE_OVERFLOW_UNDEFINED (type))
+      if ((!ANY_INTEGRAL_TYPE_P (type) || TYPE_OVERFLOW_UNDEFINED (type))
 	  && TREE_CODE (op0) == NEGATE_EXPR
 	  && negate_expr_p (op1))
 	{
-	  if (INTEGRAL_TYPE_P (type))
+	  if (ANY_INTEGRAL_TYPE_P (type))
 	    fold_overflow_warning (("assuming signed overflow does not occur "
 				    "when distributing negation across "
 				    "division"),
@@ -10430,11 +10430,11 @@ fold_binary_loc (location_t loc, enum tree_code code, tree type,
 						    TREE_OPERAND (arg0, 0)),
 				  negate_expr (op1));
 	}
-      if ((!INTEGRAL_TYPE_P (type) || TYPE_OVERFLOW_UNDEFINED (type))
+      if ((!ANY_INTEGRAL_TYPE_P (type) || TYPE_OVERFLOW_UNDEFINED (type))
 	  && TREE_CODE (arg1) == NEGATE_EXPR
 	  && negate_expr_p (op0))
 	{
-	  if (INTEGRAL_TYPE_P (type))
+	  if (ANY_INTEGRAL_TYPE_P (type))
 	    fold_overflow_warning (("assuming signed overflow does not occur "
 				    "when distributing negation across "
 				    "division"),
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr94412.c b/gcc/testsuite/gcc.c-torture/execute/pr94412.c
new file mode 100644
index 00000000000..6c806bbd90c
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr94412.c
@@ -0,0 +1,28 @@
+/* PR middle-end/94412 */
+
+typedef unsigned V __attribute__ ((__vector_size__ (sizeof (unsigned) * 2)));
+
+void
+foo (V *v, V *w)
+{
+  *w = -*v / 11;
+}
+
+void
+bar (V *v, V *w)
+{
+  *w = -18 / -*v;
+}
+
+int
+main ()
+{
+  V a = (V) { 1, 0 };
+  V b = (V) { 3, __INT_MAX__ };
+  V c, d;
+  foo (&a, &c);
+  bar (&b, &d);
+  if (c[0] != -1U / 11 || c[1] != 0 || d[0] != 0 || d[1] != -18U / -__INT_MAX__)
+    __builtin_abort ();
+  return 0;
+}

commit 24a0023809f4058cf2629221ec70ce92e0db1f0f
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 7 21:01:06 2020 +0200

    objsz: Don't call replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI [PR94423]
    
    The following testcase ICEs because the objsz pass calls replace_uses_by
    on SSA_NAME_OCCURS_IN_ABNORMAL_PHI SSA_NAME.  The following patch instead
    of that calls replace_call_with_value, which will turn it into
      xyz_123(ab) = 234;
    
    2020-04-01  Jakub Jelinek  <jakub@redhat.com>
    
            PR middle-end/94423
            * tree-object-size.c (pass_object_sizes::execute): Don't call
            replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
            call replace_call_with_value.
    
            * gcc.dg/ubsan/pr94423.c: New test.
    
    (cherry picked from commit 4486a537f14bc3b05ac552c3cbe18e540e397ed7)

diff --git a/gcc/testsuite/gcc.dg/ubsan/pr94423.c b/gcc/testsuite/gcc.dg/ubsan/pr94423.c
new file mode 100644
index 00000000000..76f831f26e2
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/ubsan/pr94423.c
@@ -0,0 +1,17 @@
+/* PR middle-end/94423 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fsanitize=object-size" } */
+
+void foo (void);
+typedef struct { long buf[22]; } jmp_buf[1];
+extern int sigsetjmp (jmp_buf, int) __attribute__ ((__nothrow__));
+jmp_buf buf;
+
+void
+bar (int *c)
+{
+  while (*c)
+    foo ();
+  while (*c)
+    sigsetjmp (buf, 0);
+}
diff --git a/gcc/tree-object-size.c b/gcc/tree-object-size.c
index f9998597c49..bfcb37653c5 100644
--- a/gcc/tree-object-size.c
+++ b/gcc/tree-object-size.c
@@ -1378,7 +1378,10 @@ pass_object_sizes::execute (function *fun)
 	    }
 
 	  /* Propagate into all uses and fold those stmts.  */
-	  replace_uses_by (lhs, result);
+	  if (!SSA_NAME_OCCURS_IN_ABNORMAL_PHI (lhs))
+	    replace_uses_by (lhs, result);
+	  else
+	    replace_call_with_value (&i, result);
 	}
     }
 

commit 6fc550e75d4aac02953510215abf8a76f9adeaaa
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Fri Apr 3 19:44:42 2020 +0200

    i386: Fix vph{add,subs?}[wd] 256-bit AVX2 RTL patterns [PR94460]
    
    The following testcase is miscompiled, because the AVX2 patterns don't
    describe correctly what the insn does.  E.g. vphaddd with %ymm* operands
    (the second pattern) instruction as per:
    https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadd_epi32&expand=2941
    does { a0+a1, a2+a3, b0+b1, b2+b3, a4+a5, a6+a7, b4+b5, b6+b7 }
    but our RTL pattern did
         { a0+a1, a2+a3, a4+a5, a6+a7, b0+b1, b2+b3, b4+b5, b6+b7 }
    where the first and last 64 bits are the same and two middle 64 bits
    swapped.
    https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_hadd_epi16&expand=2939
    similarly, insn does:
         { a0+a1, a2+a3, a4+a5, a6+a7, b0+b1, b2+b3, b4+b5, b6+b7,
           a8+a9, a10+a11, a12+a13, a14+a15, b8+b9, b10+b11, b12+b13, b14+b15 }
    but RTL pattern did
         { a0+a1, a2+a3, a4+a5, a6+a7, a8+a9, a10+a11, a12+a13, a14+a15,
           b0+b1, b2+b3, b4+b5, b6+b7, b8+b9, b10+b11, b12+b13, b14+b15 }
    again, first and last 64 bits are the same and the two middle 64 bits
    swapped.
    
    2020-04-03  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94460
            * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
            avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
            second half of first lane from first lane of second operand and
            first half of second lane from second lane of first operand.
    
            * gcc.target/i386/avx2-pr94460.c: New test.
    
    (cherry picked from commit dbff1829843180dc2a6c8ce5ce7883146b5cf083)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 94a572e897b..ba6ce84da71 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -14493,22 +14493,6 @@
 		(ssse3_plusminus:HI
 		  (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
 		  (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
-	    (vec_concat:V4HI
-	      (vec_concat:V2HI
-		(ssse3_plusminus:HI
-		  (vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
-		  (vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
-		(ssse3_plusminus:HI
-		  (vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
-		  (vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
-	      (vec_concat:V2HI
-		(ssse3_plusminus:HI
-		  (vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
-		  (vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
-		(ssse3_plusminus:HI
-		  (vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
-		  (vec_select:HI (match_dup 1) (parallel [(const_int 15)]))))))
-	  (vec_concat:V8HI
 	    (vec_concat:V4HI
 	      (vec_concat:V2HI
 		(ssse3_plusminus:HI
@@ -14525,7 +14509,23 @@
 		  (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
 		(ssse3_plusminus:HI
 		  (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
-		  (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))
+		  (vec_select:HI (match_dup 2) (parallel [(const_int 7)]))))))
+	  (vec_concat:V8HI
+	    (vec_concat:V4HI
+	      (vec_concat:V2HI
+		(ssse3_plusminus:HI
+		  (vec_select:HI (match_dup 1) (parallel [(const_int 8)]))
+		  (vec_select:HI (match_dup 1) (parallel [(const_int 9)])))
+		(ssse3_plusminus:HI
+		  (vec_select:HI (match_dup 1) (parallel [(const_int 10)]))
+		  (vec_select:HI (match_dup 1) (parallel [(const_int 11)]))))
+	      (vec_concat:V2HI
+		(ssse3_plusminus:HI
+		  (vec_select:HI (match_dup 1) (parallel [(const_int 12)]))
+		  (vec_select:HI (match_dup 1) (parallel [(const_int 13)])))
+		(ssse3_plusminus:HI
+		  (vec_select:HI (match_dup 1) (parallel [(const_int 14)]))
+		  (vec_select:HI (match_dup 1) (parallel [(const_int 15)])))))
 	    (vec_concat:V4HI
 	      (vec_concat:V2HI
 		(ssse3_plusminus:HI
@@ -14639,14 +14639,6 @@
 	      (plusminus:SI
 		(vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
 		(vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
-	    (vec_concat:V2SI
-	      (plusminus:SI
-		(vec_select:SI (match_dup 1) (parallel [(const_int 4)]))
-		(vec_select:SI (match_dup 1) (parallel [(const_int 5)])))
-	      (plusminus:SI
-		(vec_select:SI (match_dup 1) (parallel [(const_int 6)]))
-		(vec_select:SI (match_dup 1) (parallel [(const_int 7)])))))
-	  (vec_concat:V4SI
 	    (vec_concat:V2SI
 	      (plusminus:SI
 		(vec_select:SI
@@ -14655,7 +14647,15 @@
 		(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
 	      (plusminus:SI
 		(vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
-		(vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))
+		(vec_select:SI (match_dup 2) (parallel [(const_int 3)])))))
+	  (vec_concat:V4SI
+	    (vec_concat:V2SI
+	      (plusminus:SI
+		(vec_select:SI (match_dup 1) (parallel [(const_int 4)]))
+		(vec_select:SI (match_dup 1) (parallel [(const_int 5)])))
+	      (plusminus:SI
+		(vec_select:SI (match_dup 1) (parallel [(const_int 6)]))
+		(vec_select:SI (match_dup 1) (parallel [(const_int 7)]))))
 	    (vec_concat:V2SI
 	      (plusminus:SI
 		(vec_select:SI (match_dup 2) (parallel [(const_int 4)]))
diff --git a/gcc/testsuite/gcc.target/i386/avx2-pr94460.c b/gcc/testsuite/gcc.target/i386/avx2-pr94460.c
new file mode 100644
index 00000000000..75b7a7bf313
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx2-pr94460.c
@@ -0,0 +1,31 @@
+/* PR target/94460 */
+/* { dg-do run { target { avx2 && int128 } } } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <x86intrin.h>
+#include "avx2-check.h"
+
+typedef __int128 v2ti __attribute__ ((__vector_size__ (32)));
+
+static inline v2ti
+foo (__v16hi b)
+{
+  return (v2ti) _mm256_hsub_epi16 ((__m256i) b, (__m256i) b);
+}
+
+static inline v2ti
+bar (__v8si b)
+{
+  return (v2ti) _mm256_hsub_epi32 ((__m256i) b, (__m256i) b);
+}
+
+static void
+avx2_test (void)
+{
+  v2ti x = foo ((__v16hi) { 1 });
+  if (x[0] != ((__int128)1 << 64 | 1) || x[1] != 0)
+    abort ();
+  x = bar ((__v8si) { 1 });
+  if (x[0] != ((__int128)1 << 64 | 1) || x[1] != 0)
+    abort ();
+}

commit bd748b6b448ef47f56922ec67244037915f721c2
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 7 21:01:40 2020 +0200

    debug: Improve debug info of c++14 deduced return type [PR94459]
    
    On the following testcase, in gdb ptype S<long>::m1 prints long as return
    type, but all the other methods show void instead.
    PR53756 added code to add_type_attribute if the return type is
    auto/decltype(auto), but we actually should look through references,
    pointers and qualifiers.
    Haven't included there DW_TAG_atomic_type, because I think at least ATM
    one can't use that in C++.  Not sure about DW_TAG_array_type or what else
    could be deduced.
    
    > http://eel.is/c++draft/dcl.spec.auto#3 says it has to appear as a
    > decl-specifier.
    >
    > http://eel.is/c++draft/temp.deduct.type#8 lists the forms where a template
    > argument can be deduced.
    >
    > Looks like you are missing arrays, pointers to members, and function return
    > types.
    
    2020-04-04  Hannes Domani  <ssbssa@yahoo.de>
                Jakub Jelinek  <jakub@redhat.com>
    
            PR debug/94459
            * dwarf2out.c (gen_subprogram_die): Look through references, pointers,
            arrays, pointer-to-members, function types and qualifiers when
            checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
            to emit type again on definition.
    
            * g++.dg/debug/pr94459.C: New test.
    
    Co-Authored-By: Hannes Domani <ssbssa@yahoo.de>
    (cherry picked from commit b5039b7259e64a92f5c077fe4d023556d6b12550)

diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index 23107c0c33f..63a56609cef 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -22937,11 +22937,22 @@ gen_subprogram_die (tree decl, dw_die_ref context_die)
 		  != (unsigned) s.column))
 	    add_AT_unsigned (subr_die, DW_AT_decl_column, s.column);
 
-	  /* If the prototype had an 'auto' or 'decltype(auto)' return type,
-	     emit the real type on the definition die.  */
+	  /* If the prototype had an 'auto' or 'decltype(auto)' in
+	     the return type, emit the real type on the definition die.  */
 	  if (is_cxx () && debug_info_level > DINFO_LEVEL_TERSE)
 	    {
 	      dw_die_ref die = get_AT_ref (old_die, DW_AT_type);
+	      while (die
+		     && (die->die_tag == DW_TAG_reference_type
+			 || die->die_tag == DW_TAG_rvalue_reference_type
+			 || die->die_tag == DW_TAG_pointer_type
+			 || die->die_tag == DW_TAG_const_type
+			 || die->die_tag == DW_TAG_volatile_type
+			 || die->die_tag == DW_TAG_restrict_type
+			 || die->die_tag == DW_TAG_array_type
+			 || die->die_tag == DW_TAG_ptr_to_member_type
+			 || die->die_tag == DW_TAG_subroutine_type))
+		die = get_AT_ref (die, DW_AT_type);
 	      if (die == auto_die || die == decltype_auto_die)
 		add_type_attribute (subr_die, TREE_TYPE (TREE_TYPE (decl)),
 				    TYPE_UNQUALIFIED, false, context_die);
diff --git a/gcc/testsuite/g++.dg/debug/pr94459.C b/gcc/testsuite/g++.dg/debug/pr94459.C
new file mode 100644
index 00000000000..ebc0cf45cc6
--- /dev/null
+++ b/gcc/testsuite/g++.dg/debug/pr94459.C
@@ -0,0 +1,58 @@
+// PR debug/94459
+// { dg-do compile { target c++14 } }
+// { dg-options "-g -dA" }
+
+template <typename T>
+struct S
+{
+  T v;
+  T w[2];
+  S () : v (0), w { 0, 0 } {}
+  static auto baz () { return (T) 0; }
+  auto m1 () { return v; }
+  auto &m2 () { return v; }
+  auto &&m3 () { return (T&&)v; }
+  const auto m4 () { return v; }
+  const auto &m5 () { return v; }
+  const auto &&m6 () { return (T&&)v; }
+  volatile auto m7 () { return v; }
+  volatile auto &m8 () { return v; }
+  volatile auto &&m9 () { return (T&&)v; }
+  volatile const auto m10 () { return v; }
+  volatile const auto &m11 () { return v; }
+  volatile const auto &&m12 () { return (T&&)v; }
+  const volatile auto m13 () { return v; }
+  const volatile auto &m14 () { return v; }
+  const volatile auto &&m15 () { return (T&&)v; }
+#ifndef __STRICT_ANSI__
+  __restrict const volatile auto &&m16 () { return (T&&)v; }
+  const __restrict auto &m17 () { return v; }
+#endif
+  auto *m18 () { return &v; }
+  auto (S::* (m19 ())) () { return &S::m1; }
+  auto (S::* (m20 ())) { return &S::v; }
+  auto (*m21 ()) () { return S::baz; }
+};
+
+S<long> s, u, v;
+
+long
+foo ()
+{
+  auto x = s.m19 ();
+  auto y = s.m20 ();
+  auto z = s.m21 ();
+  return s.m1 () + s.m2 () + s.m3 () + s.m4 () + s.m5 ()
+	 + s.m6 () + s.m7 () + s.m8 () + s.m9 () + s.m10 ()
+	 + s.m11 () + s.m12 () + s.m13 () + s.m14 () + s.m15 ()
+#ifndef __STRICT_ANSI__
+	 + u.m16 () + v.m17 ()
+#endif
+	 + *s.m18 () + (s.*x) () + s.*y + z ();
+}
+
+int
+main ()
+{
+  return foo ();
+}

commit 84d649d3c71e80269ebd9764652131c51ff4a895
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 7 10:01:16 2020 +0200

    aarch64: Fix {ash[lr],lshr}<mode>3 expanders [PR94488]
    
    The following testcase ICEs on aarch64 apparently since the introduction of
    the aarch64 port.  The reason is that the {ashl,ashr,lshr}<mode>3 expanders
    completely unnecessarily FAIL; if operands[2] is something other than
    a CONST_INT or REG or MEM and the middle-end code can't cope with the
    pattern giving up in these cases.  All the expanders use general_operand
    predicate for the shift amount operand, but then have just a special case
    for CONST_INT (if in-bound, emit an immediate shift, otherwise force into
    REG), or MEM (force into REG), or REG (that is the case it handles).
    In the testcase, operands[2] is a lowpart SUBREG of a REG, which is valid
    general_operand.
    I don't see any reason what is magic about MEMs that it should be forced
    into REG and others like SUBREGs that it shouldn't, there isn't even a
    reason to check for !REG_P because force_reg will do nothing if the operand
    is already a REG, and otherwise can handle general_operand just fine.
    
    2020-04-07  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94488
            * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
            ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
            Assume it is a REG after that instead of testing it and doing FAIL
            otherwise.  Formatting fix.
    
            * gcc.c-torture/compile/pr94488.c: New test.
    
    (cherry picked from commit 7f3ac38b3c765d49a46f65f1e5e9a812fb1da49c)

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 3d21e0e48db..816d627ce9e 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -839,31 +839,17 @@
 						     tmp));
           DONE;
         }
-      else
-        {
-          operands[2] = force_reg (SImode, operands[2]);
-        }
-    }
-  else if (MEM_P (operands[2]))
-    {
-      operands[2] = force_reg (SImode, operands[2]);
     }
 
-  if (REG_P (operands[2]))
-    {
-      rtx tmp = gen_reg_rtx (<MODE>mode);
-      emit_insn (gen_aarch64_simd_dup<mode> (tmp,
-					     convert_to_mode (<VEL>mode,
-							      operands[2],
-							      0)));
-      emit_insn (gen_aarch64_simd_reg_sshl<mode> (operands[0], operands[1],
-						  tmp));
-      DONE;
-    }
-  else
-    FAIL;
-}
-)
+  operands[2] = force_reg (SImode, operands[2]);
+
+  rtx tmp = gen_reg_rtx (<MODE>mode);
+  emit_insn (gen_aarch64_simd_dup<mode> (tmp, convert_to_mode (<VEL>mode,
+							       operands[2],
+							       0)));
+  emit_insn (gen_aarch64_simd_reg_sshl<mode> (operands[0], operands[1], tmp));
+  DONE;
+})
 
 (define_expand "lshr<mode>3"
   [(match_operand:VDQ_I 0 "register_operand" "")
@@ -886,31 +872,19 @@
 						  tmp));
 	  DONE;
 	}
-      else
-        operands[2] = force_reg (SImode, operands[2]);
-    }
-  else if (MEM_P (operands[2]))
-    {
-      operands[2] = force_reg (SImode, operands[2]);
     }
 
-  if (REG_P (operands[2]))
-    {
-      rtx tmp = gen_reg_rtx (SImode);
-      rtx tmp1 = gen_reg_rtx (<MODE>mode);
-      emit_insn (gen_negsi2 (tmp, operands[2]));
-      emit_insn (gen_aarch64_simd_dup<mode> (tmp1,
-					     convert_to_mode (<VEL>mode,
-							      tmp, 0)));
-      emit_insn (gen_aarch64_simd_reg_shl<mode>_unsigned (operands[0],
-							  operands[1],
-							  tmp1));
-      DONE;
-    }
-  else
-    FAIL;
-}
-)
+  operands[2] = force_reg (SImode, operands[2]);
+
+  rtx tmp = gen_reg_rtx (SImode);
+  rtx tmp1 = gen_reg_rtx (<MODE>mode);
+  emit_insn (gen_negsi2 (tmp, operands[2]));
+  emit_insn (gen_aarch64_simd_dup<mode> (tmp1,
+					 convert_to_mode (<VEL>mode, tmp, 0)));
+  emit_insn (gen_aarch64_simd_reg_shl<mode>_unsigned (operands[0], operands[1],
+						      tmp1));
+  DONE;
+})
 
 (define_expand "ashr<mode>3"
   [(match_operand:VDQ_I 0 "register_operand" "")
@@ -933,31 +907,19 @@
 						  tmp));
           DONE;
 	}
-      else
-        operands[2] = force_reg (SImode, operands[2]);
-    }
-  else if (MEM_P (operands[2]))
-    {
-      operands[2] = force_reg (SImode, operands[2]);
     }
 
-  if (REG_P (operands[2]))
-    {
-      rtx tmp = gen_reg_rtx (SImode);
-      rtx tmp1 = gen_reg_rtx (<MODE>mode);
-      emit_insn (gen_negsi2 (tmp, operands[2]));
-      emit_insn (gen_aarch64_simd_dup<mode> (tmp1,
-					     convert_to_mode (<VEL>mode,
-							      tmp, 0)));
-      emit_insn (gen_aarch64_simd_reg_shl<mode>_signed (operands[0],
-							operands[1],
-							tmp1));
-      DONE;
-    }
-  else
-    FAIL;
-}
-)
+  operands[2] = force_reg (SImode, operands[2]);
+
+  rtx tmp = gen_reg_rtx (SImode);
+  rtx tmp1 = gen_reg_rtx (<MODE>mode);
+  emit_insn (gen_negsi2 (tmp, operands[2]));
+  emit_insn (gen_aarch64_simd_dup<mode> (tmp1, convert_to_mode (<VEL>mode,
+								tmp, 0)));
+  emit_insn (gen_aarch64_simd_reg_shl<mode>_signed (operands[0], operands[1],
+						    tmp1));
+  DONE;
+})
 
 (define_expand "vashl<mode>3"
  [(match_operand:VDQ_I 0 "register_operand" "")
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr94488.c b/gcc/testsuite/gcc.c-torture/compile/pr94488.c
new file mode 100644
index 00000000000..6e20a4168de
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr94488.c
@@ -0,0 +1,22 @@
+/* PR target/94488 */
+
+typedef unsigned long V __attribute__((__vector_size__(16)));
+typedef long W __attribute__((__vector_size__(16)));
+
+void
+foo (V *x, unsigned long y)
+{
+  *x = *x >> (unsigned int) y;
+}
+
+void
+bar (V *x, unsigned long y)
+{
+  *x = *x << (unsigned int) y;
+}
+
+void
+baz (W *x, unsigned long y)
+{
+  *x = *x >> (unsigned int) y;
+}

commit 62138a256af79900ef9958e32806f5acc333bd93
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 7 14:39:24 2020 +0200

    i386: Fix V{64QI,32HI}mode constant permutations [PR94509]
    
    The following testcases are miscompiled, because expand_vec_perm_pshufb
    incorrectly thinks it can use vpshufb instruction for the permutations
    when it can't.
    The
              if (vmode == V32QImode)
                {
                  /* vpshufb only works intra lanes, it is not
                     possible to shuffle bytes in between the lanes.  */
                  for (i = 0; i < nelt; ++i)
                    if ((d->perm[i] ^ i) & (nelt / 2))
                      return false;
                }
    intra-lane check which is correct has been copied and adjusted for 64-byte
    modes into:
              if (vmode == V64QImode)
                {
                  /* vpshufb only works intra lanes, it is not
                     possible to shuffle bytes in between the lanes.  */
                  for (i = 0; i < nelt; ++i)
                    if ((d->perm[i] ^ i) & (nelt / 4))
                      return false;
                }
    which is not correct, because 64-byte modes have 4 lanes rather than just
    two and the above is only testing that the permutation grabs even lane elts
    from even lanes and odd lane elts from odd lanes, but not that they are
    from the same 256-bit half.
    
    The following patch fixes it by using 3 * nelt / 4 instead of nelt / 4,
    so we actually check the most significant 2 bits rather than just one.
    
    2020-04-07  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94509
            * config/i386/i386.c (expand_vec_perm_pshufb): Fix the check
            for inter-lane permutation for 64-byte modes.
    
            * gcc.target/i386/avx512bw-pr94509-1.c: New test.
            * gcc.target/i386/avx512bw-pr94509-2.c: New test.
    
    (cherry picked from commit 14192f1ed48cb3982b1b3c794e0f313835d0cdcd)

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 7ea67fe64de..2e290910f61 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -46771,7 +46771,7 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d)
 	      /* vpshufb only works intra lanes, it is not
 		 possible to shuffle bytes in between the lanes.  */
 	      for (i = 0; i < nelt; ++i)
-		if ((d->perm[i] ^ i) & (nelt / 4))
+		if ((d->perm[i] ^ i) & (3 * nelt / 4))
 		  return false;
 	    }
 	}
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-pr94509-1.c b/gcc/testsuite/gcc.target/i386/avx512bw-pr94509-1.c
new file mode 100644
index 00000000000..6cd79b7443f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-pr94509-1.c
@@ -0,0 +1,30 @@
+/* PR target/94509 */
+/* { dg-do run { target avx512bw } } */
+/* { dg-options "-O2 -mavx512bw" } */
+
+#define AVX512BW
+#include "avx512f-helper.h"
+
+typedef unsigned short __attribute__ ((__vector_size__ (64))) V;
+
+__attribute__((noipa)) V
+foo (V x)
+{
+  return __builtin_shuffle (x, (V) { 0, 0, 0, 0, 0, 0, 0, 0,
+				     15, 15, 15, 15, 15, 15, 15, 15,
+				     0, 0, 0, 0, 0, 0, 0, 0,
+				     15, 15, 15, 15, 15, 15, 15, 15 });
+}
+
+static void
+TEST (void)
+{
+  V v = foo ((V) { 1, 2, 3, 4, 5, 6, 7, 8,
+		   9, 10, 11, 12, 13, 14, 15, 16,
+		   17, 18, 19, 20, 21, 22, 23, 24,
+		   25, 26, 27, 28, 29, 30, 31, 32 });
+  unsigned int i;
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != ((i & 8) ? 16 : 1))
+      abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-pr94509-2.c b/gcc/testsuite/gcc.target/i386/avx512bw-pr94509-2.c
new file mode 100644
index 00000000000..089e3f211b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-pr94509-2.c
@@ -0,0 +1,38 @@
+/* PR target/94509 */
+/* { dg-do run { target avx512bw } } */
+/* { dg-options "-O2 -mavx512bw" } */
+
+#define AVX512BW
+#include "avx512f-helper.h"
+
+typedef unsigned char __attribute__ ((__vector_size__ (64))) V;
+
+__attribute__((noipa)) V
+foo (V x)
+{
+  return __builtin_shuffle (x, (V) { 0, 1, 0, 1, 0, 1, 0, 1,
+				     0, 1, 0, 1, 0, 1, 0, 1,
+				     30, 31, 30, 31, 30, 31, 30, 31,
+				     30, 31, 30, 31, 30, 31, 30, 31,
+				     0, 1, 0, 1, 0, 1, 0, 1,
+				     0, 1, 0, 1, 0, 1, 0, 1,
+				     30, 31, 30, 31, 30, 31, 30, 31,
+				     30, 31, 30, 31, 30, 31, 30, 31 });
+}
+
+static void
+TEST (void)
+{
+  V v = foo ((V) { 1, 2, 3, 4, 5, 6, 7, 8,
+		   9, 10, 11, 12, 13, 14, 15, 16,
+		   17, 18, 19, 20, 21, 22, 23, 24,
+		   25, 26, 27, 28, 29, 30, 31, 32,
+		   33, 34, 35, 36, 37, 38, 39, 40,
+		   41, 42, 43, 44, 45, 46, 47, 48,
+		   49, 50, 51, 52, 53, 54, 55, 56,
+		   57, 58, 59, 60, 61, 62, 63, 64 });
+  unsigned int i;
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != ((i & 16) ? 31 : 1) + (i & 1))
+      abort ();
+}

commit 1298b488c37c44abf33cca6932e760ef69dd7815
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Apr 8 15:30:16 2020 +0200

    c++: Further fix for -fsanitize=vptr [PR94325]
    
    For -fsanitize=vptr, we insert a NULL store into the vptr instead of just
    adding a CLOBBER of this.  build_clobber_this makes the CLOBBER conditional
    on in_charge (implicit) parameter whenever CLASSTYPE_VBASECLASSES, but when
    adding this conditionalization to the -fsanitize=vptr code in PR87095,
    I wanted it to catch some more cases when the class has CLASSTYPE_VBASECLASSES,
    but the vptr is still not shared with something else, otherwise the
    sanitization would be less effective.
    The following testcase shows that the chosen test that CLASSTYPE_PRIMARY_BINFO
    is non-NULL and has BINFO_VIRTUAL_P set wasn't sufficient,
    the D class has still sizeof(D) == sizeof(void*) and thus contains just
    a single vptr, but while in B::~B() this results in the vptr not being
    cleared, in C::~C() this condition isn't true, as CLASSTYPE_PRIMARY_BINFO
    in that case is B and is not BINFO_VIRTUAL_P, so it clears the vptr, but the
    D::~D() dtor after invoking C::~C() invokes A::~A() with an already cleared
    vptr, which is then reported.
    The following patch is just a shot in the dark, keep looking through
    CLASSTYPE_PRIMARY_BINFO until we find BINFO_VIRTUAL_P, but it works on the
    existing testcase as well as this new one.
    
    2020-04-08  Jakub Jelinek  <jakub@redhat.com>
    
            PR c++/94325
            * decl.c (begin_destructor_body): For CLASSTYPE_VBASECLASSES class
            dtors, if CLASSTYPE_PRIMARY_BINFO is non-NULL, but not BINFO_VIRTUAL_P,
            look at CLASSTYPE_PRIMARY_BINFO of its BINFO_TYPE if it is not
            BINFO_VIRTUAL_P, and so on.
    
            * g++.dg/ubsan/vptr-15.C: New test.
    
    (cherry picked from commit 4cf6b06cb5b02c053738e2975e3b7a4b3c577401)

diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c
index f2b52fb674e..9f1444ccff6 100644
--- a/gcc/cp/decl.c
+++ b/gcc/cp/decl.c
@@ -15592,14 +15592,20 @@ begin_destructor_body (void)
 	    /* If the vptr is shared with some virtual nearly empty base,
 	       don't clear it if not in charge, the dtor of the virtual
 	       nearly empty base will do that later.  */
-	    if (CLASSTYPE_VBASECLASSES (current_class_type)
-		&& CLASSTYPE_PRIMARY_BINFO (current_class_type)
-		&& BINFO_VIRTUAL_P
-			  (CLASSTYPE_PRIMARY_BINFO (current_class_type)))
+	    if (CLASSTYPE_VBASECLASSES (current_class_type))
 	      {
-		stmt = convert_to_void (stmt, ICV_STATEMENT,
-					tf_warning_or_error);
-		stmt = build_if_in_charge (stmt);
+		tree c = current_class_type;
+		while (CLASSTYPE_PRIMARY_BINFO (c))
+		  {
+		    if (BINFO_VIRTUAL_P (CLASSTYPE_PRIMARY_BINFO (c)))
+		      {
+			stmt = convert_to_void (stmt, ICV_STATEMENT,
+						tf_warning_or_error);
+			stmt = build_if_in_charge (stmt);
+			break;
+		      }
+		    c = BINFO_TYPE (CLASSTYPE_PRIMARY_BINFO (c));
+		  }
 	      }
 	    finish_decl_cleanup (NULL_TREE, stmt);
 	  }
diff --git a/gcc/testsuite/g++.dg/ubsan/vptr-15.C b/gcc/testsuite/g++.dg/ubsan/vptr-15.C
new file mode 100644
index 00000000000..f6f36a58bab
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ubsan/vptr-15.C
@@ -0,0 +1,14 @@
+// PR c++/94325
+// { dg-do run { target c++11 } }
+// { dg-options "-fsanitize=vptr -fno-sanitize-recover=vptr" }
+
+struct A { virtual ~A () = default; };
+struct B : public virtual A {};
+struct C : public B {};
+struct D : public C {};
+
+int
+main ()
+{
+  D a;
+}

commit 212ae35e5a9b554748c1340015968fda1d1fa0d8
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Apr 8 18:24:12 2020 +0200

    i386: Don't use AVX512F integral masks for V*TImode [PR94438]
    
    The ix86_get_mask_mode hook uses int mask for 512-bit vectors or 128/256-bit
    vectors with AVX512VL (that is correct), and only for V*[SD][IF]mode if not
    AVX512BW (also correct), but with AVX512BW it would stop checking the
    elem_size altogether and pretend the hw has masking support for V*TImode
    etc., which it doesn't.  That can lead to various ICEs later on.
    
    2020-04-08  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94438
            * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
            1, 2, 4 and 8.
    
            * gcc.target/i386/avx512bw-pr94438.c: New test.
            * gcc.target/i386/avx512vlbw-pr94438.c: New test.
    
    (cherry picked from commit 8bf5faa9c463f0d53ffe835ba03d4502edfb959d)

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 2e290910f61..b4516714465 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -50355,7 +50355,9 @@ ix86_get_mask_mode (poly_uint64 nunits, poly_uint64 vector_size)
   if ((TARGET_AVX512F && vector_size == 64)
       || (TARGET_AVX512VL && (vector_size == 32 || vector_size == 16)))
     {
-      if (elem_size == 4 || elem_size == 8 || TARGET_AVX512BW)
+      if (elem_size == 4
+	  || elem_size == 8
+	  || (TARGET_AVX512BW && (elem_size == 1 || elem_size == 2)))
 	return smallest_int_mode_for_size (nunits);
     }
 
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-pr94438.c b/gcc/testsuite/gcc.target/i386/avx512bw-pr94438.c
new file mode 100644
index 00000000000..9e56f2846ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-pr94438.c
@@ -0,0 +1,13 @@
+/* PR target/94438 */
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-mavx512bw" } */
+
+typedef __attribute__ ((__vector_size__ (4 * sizeof (__int128)))) __int128 V;
+void bar (V);
+
+void
+foo (V w)
+{
+  V v = 0 <= (0 >= w);
+  bar (v);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vlbw-pr94438.c b/gcc/testsuite/gcc.target/i386/avx512vlbw-pr94438.c
new file mode 100644
index 00000000000..a0c52e426c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vlbw-pr94438.c
@@ -0,0 +1,13 @@
+/* PR target/94438 */
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-mavx512bw -mavx512vl" } */
+
+typedef __attribute__ ((__vector_size__ (sizeof (__int128)))) __int128 V;
+void bar (V);
+
+void
+foo (V w)
+{
+  V v = 0 <= (0 >= w);
+  bar (v);
+}

commit 7146b8fd63e5107f1cf896df92fbaed99aa5ac0d
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Apr 8 21:22:05 2020 +0200

    vect: Fix up lowering of TRUNC_MOD_EXPR by negative constant [PR94524]
    
    The first testcase below is miscompiled, because for the division part
    of the lowering we canonicalize negative divisors to their absolute value
    (similarly how expmed.c canonicalizes it), but when multiplying the division
    result back by the VECTOR_CST, we use the original constant, which can
    contain negative divisors.
    
    Fixed by computing ABS_EXPR of the VECTOR_CST.  Unfortunately, fold-const.c
    doesn't support const_unop (ABS_EXPR, VECTOR_CST) and I think it is too late
    in GCC 10 cycle to add it now.
    
    Furthermore, while modulo by most negative constant happens to return the
    right value, it does that only by invoking UB in the IL, because
    we then expand division by that 1U+INT_MAX and say for INT_MIN % INT_MIN
    compute the division as -1, and then multiply by INT_MIN, which is signed
    integer overflow.  We in theory could do the computation in unsigned vector
    types instead, but is it worth bothering.  People that are doing % INT_MIN
    are either testing for standard conformance, or doing something wrong.
    So, I've also added punting on % INT_MIN, both in vect lowering and vect
    pattern recognition (we punt already for / INT_MIN).
    
    2020-04-08  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/94524
            * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
            negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
            op1 rather than op1 itself at the end.  Punt for signed modulo by
            most negative constant.
            * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
            modulo by most negative constant.
    
            * gcc.c-torture/execute/pr94524-1.c: New test.
            * gcc.c-torture/execute/pr94524-2.c: New test.
    
    (cherry picked from commit f52eb4f988992d393c69ee4ab76f236dced80e36)

diff --git a/gcc/testsuite/gcc.c-torture/execute/pr94524-1.c b/gcc/testsuite/gcc.c-torture/execute/pr94524-1.c
new file mode 100644
index 00000000000..e7365ad97fd
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr94524-1.c
@@ -0,0 +1,19 @@
+/* PR tree-optimization/94524 */
+
+typedef signed char __attribute__ ((__vector_size__ (16))) V;
+
+static __attribute__ ((__noinline__, __noclone__)) V
+foo (V c)
+{
+  c %= (signed char) -19;
+  return (V) c;
+}
+
+int
+main ()
+{
+  V x = foo ((V) { 31 });
+  if (x[0] != 12)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr94524-2.c b/gcc/testsuite/gcc.c-torture/execute/pr94524-2.c
new file mode 100644
index 00000000000..9c74b7be403
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr94524-2.c
@@ -0,0 +1,25 @@
+/* PR tree-optimization/94524 */
+
+typedef signed char __attribute__ ((__vector_size__ (16))) V;
+
+static __attribute__ ((__noinline__, __noclone__)) V
+foo (V c)
+{
+  c %= (signed char) -128;
+  return (V) c;
+}
+
+int
+main ()
+{
+  V x = foo ((V) { -128 });
+  if (x[0] != 0)
+    __builtin_abort ();
+  x = foo ((V) { -127 });
+  if (x[0] != -127)
+    __builtin_abort ();
+  x = foo ((V) { 127 });
+  if (x[0] != 127)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc/tree-vect-generic.c b/gcc/tree-vect-generic.c
index 9d6338371e9..1070403c192 100644
--- a/gcc/tree-vect-generic.c
+++ b/gcc/tree-vect-generic.c
@@ -433,6 +433,7 @@ expand_vector_divmod (gimple_stmt_iterator *gsi, tree type, tree op0,
 {
   bool use_pow2 = true;
   bool has_vector_shift = true;
+  bool use_abs_op1 = false;
   int mode = -1, this_mode;
   int pre_shift = -1, post_shift;
   unsigned int nunits = nunits_for_known_piecewise_op (type);
@@ -573,8 +574,11 @@ expand_vector_divmod (gimple_stmt_iterator *gsi, tree type, tree op0,
 
 	  /* n rem d = n rem -d */
 	  if (code == TRUNC_MOD_EXPR && d < 0)
-	    d = abs_d;
-	  else if (abs_d == HOST_WIDE_INT_1U << (prec - 1))
+	    {
+	      d = abs_d;
+	      use_abs_op1 = true;
+	    }
+	  if (abs_d == HOST_WIDE_INT_1U << (prec - 1))
 	    {
 	      /* This case is not handled correctly below.  */
 	      mode = -2;
@@ -854,6 +858,23 @@ expand_vector_divmod (gimple_stmt_iterator *gsi, tree type, tree op0,
   if (op == unknown_optab
       || optab_handler (op, TYPE_MODE (type)) == CODE_FOR_nothing)
     return NULL_TREE;
+  if (use_abs_op1)
+    {
+      tree_vector_builder elts;
+      if (!elts.new_unary_operation (type, op1, false))
+	return NULL_TREE;
+      unsigned int count = elts.encoded_nelts ();
+      for (unsigned int i = 0; i < count; ++i)
+	{
+	  tree elem1 = VECTOR_CST_ELT (op1, i);
+
+	  tree elt = const_unop (ABS_EXPR, TREE_TYPE (elem1), elem1);
+	  if (elt == NULL_TREE)
+	    return NULL_TREE;
+	  elts.quick_push (elt);
+	}
+      op1 = elts.build ();
+    }
   tem = gimplify_build2 (gsi, MULT_EXPR, type, cur_op, op1);
   op = optab_for_tree_code (MINUS_EXPR, type, optab_default);
   if (op == unknown_optab
diff --git a/gcc/tree-vect-patterns.c b/gcc/tree-vect-patterns.c
index 30c3daaa32f..de21c4bbd3f 100644
--- a/gcc/tree-vect-patterns.c
+++ b/gcc/tree-vect-patterns.c
@@ -2926,8 +2926,8 @@ vect_recog_divmod_pattern (vec<gimple *> *stmts,
 	  d = abs_d;
 	  oprnd1 = build_int_cst (itype, abs_d);
 	}
-      else if (HOST_BITS_PER_WIDE_INT >= prec
-	       && abs_d == HOST_WIDE_INT_1U << (prec - 1))
+      if (HOST_BITS_PER_WIDE_INT >= prec
+	  && abs_d == HOST_WIDE_INT_1U << (prec - 1))
 	/* This case is not handled correctly below.  */
 	return NULL;
 

commit 189c10499d796877e22c7f019a2805099fab8509
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Apr 16 07:19:57 2020 +0200

    c++: Fix pasto in structured binding diagnostics [PR94571]
    
    This snippet has been copied from the non-structured binding declaration
    parsing later in the function, and while for non-structured bindings
    it can be followed by comma or semicolon, structured bindings may be
    only followed by semicolon.
    
    Or, do we want to have a different message for the case when there is
    a comma (and keep this corrected one only if there is something else)
    that would explain better what is the bug (or add a fix-it hint)?
    Marek said in the PR that clang++ reports
    error: decomposition declaration must be the only declaration in its group
    
    There is another thing Marek noted (though, something for different spot),
    that diagnostic for auto x(1), [e,f] = test2; could also use a clearer
    wording like the above (or a fix-it hint), but the question is if we should
    assume [ after , as a structured binding or if we should do some tentative
    parsing first to figure out if it looks like a structured binding.
    
    2020-04-16  Jakub Jelinek  <jakub@redhat.com>
    
            PR c++/94571
            * parser.c (cp_parser_simple_declaration): Fix up a pasto in
            diagnostics.
    
            * g++.dg/cpp1z/decomp51.C: New test.
    
    (cherry picked from commit e4658c7dbbe88f742c96e5f58ee4a6d549d642ca)

diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index 70fc1c89019..f56273e8a54 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -13045,7 +13045,7 @@ cp_parser_simple_declaration (cp_parser* parser,
 	    if ((decl != error_mark_node
 		 && DECL_INITIAL (decl) != error_mark_node)
 		|| cp_parser_uncommitted_to_tentative_parse_p (parser))
-	      cp_parser_error (parser, "expected %<,%> or %<;%>");
+	      cp_parser_error (parser, "expected %<;%>");
 	    /* Skip tokens until we reach the end of the statement.  */
 	    cp_parser_skip_to_end_of_statement (parser);
 	    /* If the next token is now a `;', consume it.  */
diff --git a/gcc/testsuite/g++.dg/cpp1z/decomp51.C b/gcc/testsuite/g++.dg/cpp1z/decomp51.C
new file mode 100644
index 00000000000..fe8b998abc8
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1z/decomp51.C
@@ -0,0 +1,16 @@
+// PR c++/94571
+// { dg-do compile { target c++17 } }
+
+void
+foo ()
+{
+  int e[2], f[2];
+  auto [a,b] = e, [c,d] = f;	// { dg-error "expected ';' before ',' token" }
+}
+
+void
+bar ()
+{
+  int e[2];
+  auto [a, b] = e );		// { dg-error "expected ';' before '\\\)' token" }
+}

commit 00191dfc2914b2e66a3fbe50aa79ef6a5fc2be46
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Fri Apr 17 10:33:27 2020 +0200

    Fix -fcompare-debug issue in delete_insn_and_edges [PR94618]
    
    delete_insn_and_edges calls purge_dead_edges whenever deleting the last insn
    in a bb, whatever it is.  If it called it only for mandatory last insns
    in the basic block (that may not be followed by DEBUG_INSNs, dunno if that
    is control_flow_insn_p or something more complex), that wouldn't be a
    problem, but as it calls it on any last insn and can actually do something
    in the bb, if such an insn is followed by one more more DEBUG_INSNs and
    nothing else in the same bb, we don't call purge_dead_edges with -g and do
    call it with -g0.
    
    On the testcase, there are two reg-to-reg moves with REG_EH_REGION notes
    (previously memory accesses but simplified and yet not optimized), and the
    second is followed by DEBUG_INSNs; the second move is delete_insn_and_edges
    and after removing it, for -g0 purge_dead_edges removes the REG_EH_REGION
    from the now last insn in the bb (the first reg-to-reg move), while
    for -g it isn't called and things diverge from that quickly on.
    
    Fixed by calling purdge_dead_edges even if we remove the last real insn
    followed only by DEBUG_INSNs in the same bb.
    
    2020-04-17  Jakub Jelinek  <jakub@redhat.com>
    
            PR rtl-optimization/94618
            * cfgrtl.c (delete_insn_and_edges): Set purge not just when
            insn is the BB_END of its block, but also when it is only followed
            by DEBUG_INSNs in its block.
    
            * g++.dg/opt/pr94618.C: New test.
    
    (cherry picked from commit c41884a09206be0e21cad7eea71b9754daa969d4)

diff --git a/gcc/cfgrtl.c b/gcc/cfgrtl.c
index bf1504d082f..d15f94ec6dc 100644
--- a/gcc/cfgrtl.c
+++ b/gcc/cfgrtl.c
@@ -224,10 +224,20 @@ delete_insn_and_edges (rtx_insn *insn)
 {
   bool purge = false;
 
-  if (INSN_P (insn)
-      && BLOCK_FOR_INSN (insn)
-      && BB_END (BLOCK_FOR_INSN (insn)) == insn)
-    purge = true;
+  if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
+    {
+      basic_block bb = BLOCK_FOR_INSN (insn);
+      if (BB_END (bb) == insn)
+	purge = true;
+      else if (DEBUG_INSN_P (BB_END (bb)))
+	for (rtx_insn *dinsn = NEXT_INSN (insn);
+	     DEBUG_INSN_P (dinsn); dinsn = NEXT_INSN (dinsn))
+	  if (BB_END (bb) == dinsn)
+	    {
+	      purge = true;
+	      break;
+	    }
+    }
   delete_insn (insn);
   if (purge)
     return purge_dead_edges (BLOCK_FOR_INSN (insn));
diff --git a/gcc/testsuite/g++.dg/opt/pr94618.C b/gcc/testsuite/g++.dg/opt/pr94618.C
new file mode 100644
index 00000000000..e6a81d2c5ab
--- /dev/null
+++ b/gcc/testsuite/g++.dg/opt/pr94618.C
@@ -0,0 +1,25 @@
+// PR rtl-optimization/94618
+// { dg-do compile { target c++11 } }
+// { dg-options "-O2 -fnon-call-exceptions -fcompare-debug" }
+
+struct S
+{
+  int a, b, c;
+  int foo () noexcept { return a; }
+  int bar () noexcept { return b; }
+  void baz (int);
+  void qux () { if (c) for (int x = foo (); x != bar (); ) baz (x); }
+};
+
+struct T
+{
+  S s;
+  void foo ();
+};
+
+void
+T::foo ()
+{
+  s.qux ();
+  s.qux ();
+}

commit 3e8a10bb21b4c830e1884ff43edd639eae5bf5ce
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 21 17:06:31 2020 +0200

    ubsan: Avoid -Wpadded warnings [PR94641]
    
    -Wpadded warnings aren't really useful for the artificial types that GCC
    lays out for ubsan.
    
    2020-04-21  Jakub Jelinek  <jakub@redhat.com>
    
            PR c/94641
            * stor-layout.c (place_field, finalize_record_size): Don't emit
            -Wpadded warning on TYPE_ARTIFICIAL rli->t.
            * ubsan.c (ubsan_get_type_descriptor_type,
            ubsan_get_source_location_type, ubsan_create_data): Set
            TYPE_ARTIFICIAL.
            * asan.c (asan_global_struct): Likewise.
    
            * c-c++-common/ubsan/pr94641.c: New test.
    
    (cherry picked from commit 73f8e9dca5ff891ed19001b213fd1f6ce31417e3)

diff --git a/gcc/asan.c b/gcc/asan.c
index 9014df19939..220ecf64d6b 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -2539,6 +2539,7 @@ asan_global_struct (void)
   TYPE_FIELDS (ret) = fields[0];
   TYPE_NAME (ret) = type_decl;
   TYPE_STUB_DECL (ret) = type_decl;
+  TYPE_ARTIFICIAL (ret) = 1;
   layout_type (ret);
   return ret;
 }
diff --git a/gcc/stor-layout.c b/gcc/stor-layout.c
index d06e88a8135..25377232248 100644
--- a/gcc/stor-layout.c
+++ b/gcc/stor-layout.c
@@ -1314,7 +1314,8 @@ place_field (record_layout_info rli, tree field)
 	 Bump the cumulative size to multiple of field alignment.  */
 
       if (!targetm.ms_bitfield_layout_p (rli->t)
-          && DECL_SOURCE_LOCATION (field) != BUILTINS_LOCATION)
+	  && DECL_SOURCE_LOCATION (field) != BUILTINS_LOCATION
+	  && !TYPE_ARTIFICIAL (rli->t))
 	warning (OPT_Wpadded, "padding struct to align %q+D", field);
 
       /* If the alignment is still within offset_align, just align
@@ -1748,7 +1749,8 @@ finalize_record_size (record_layout_info rli)
 
   if (TREE_CONSTANT (unpadded_size)
       && simple_cst_equal (unpadded_size, TYPE_SIZE (rli->t)) == 0
-      && input_location != BUILTINS_LOCATION)
+      && input_location != BUILTINS_LOCATION
+      && !TYPE_ARTIFICIAL (rli->t))
     warning (OPT_Wpadded, "padding struct size to alignment boundary");
 
   if (warn_packed && TREE_CODE (rli->t) == RECORD_TYPE
diff --git a/gcc/testsuite/c-c++-common/ubsan/pr94641.c b/gcc/testsuite/c-c++-common/ubsan/pr94641.c
new file mode 100644
index 00000000000..b41cb06164d
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/ubsan/pr94641.c
@@ -0,0 +1,11 @@
+/* PR c/94641 */
+/* { dg-do compile } */
+/* { dg-options "-fsanitize=undefined -Wpadded" } */
+
+void foo (void *) __attribute__((nonnull));
+
+void
+bar (void *p)
+{
+  foo (p);
+}
diff --git a/gcc/ubsan.c b/gcc/ubsan.c
index 722f5702612..f859689a8d1 100644
--- a/gcc/ubsan.c
+++ b/gcc/ubsan.c
@@ -229,6 +229,7 @@ ubsan_get_type_descriptor_type (void)
   TYPE_FIELDS (ret) = fields[0];
   TYPE_NAME (ret) = type_decl;
   TYPE_STUB_DECL (ret) = type_decl;
+  TYPE_ARTIFICIAL (ret) = 1;
   layout_type (ret);
   ubsan_type_descriptor_type = ret;
   return ret;
@@ -277,6 +278,7 @@ ubsan_get_source_location_type (void)
   TYPE_FIELDS (ret) = fields[0];
   TYPE_NAME (ret) = type_decl;
   TYPE_STUB_DECL (ret) = type_decl;
+  TYPE_ARTIFICIAL (ret) = 1;
   layout_type (ret);
   ubsan_source_location_type = ret;
   return ret;
@@ -593,6 +595,7 @@ ubsan_create_data (const char *name, int loccnt, const location_t *ploc, ...)
   TYPE_FIELDS (ret) = fields[0];
   TYPE_NAME (ret) = type_decl;
   TYPE_STUB_DECL (ret) = type_decl;
+  TYPE_ARTIFICIAL (ret) = 1;
   layout_type (ret);
 
   /* Now, fill in the type.  */

commit 1dd77eeccc2941323607e88a6fe37625a2dc6698
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Apr 23 09:54:14 2020 +0200

    attribs: Don't diagnose attribute exclusions during error recovery [PR94705]
    
    On the following testcase GCC ICEs, because last_decl is error_mark_node,
    and diag_attr_exclusions assumes that if it is not NULL, it must be a decl.
    
    The following patch just doesn't diagnose attribute exclusions if the
    other decl is erroneous (and thus we've already reported errors for it).
    
    2020-04-23  Jakub Jelinek  <jakub@redhat.com>
    
            PR c/94705
            * attribs.c (decl_attribute): Don't diagnose attribute exclusions
            if last_decl is error_mark_node or has such a TREE_TYPE.
    
            * gcc.dg/pr94705.c: New test.
    
    (cherry picked from commit e2a71816b4949225498bec37e947293aa7f5841b)

diff --git a/gcc/attribs.c b/gcc/attribs.c
index fc21f799d92..4db4052ec15 100644
--- a/gcc/attribs.c
+++ b/gcc/attribs.c
@@ -702,7 +702,8 @@ decl_attributes (tree *node, tree attributes, int flags,
       bool built_in = flags & ATTR_FLAG_BUILT_IN;
       if (spec->exclude
 	  && !no_add_attrs
-	  && (flag_checking || !built_in))
+	  && (flag_checking || !built_in)
+	  && !error_operand_p (last_decl))
 	{
 	  /* Always check attributes on user-defined functions.
 	     Check them on built-ins only when -fchecking is set.
diff --git a/gcc/testsuite/gcc.dg/pr94705.c b/gcc/testsuite/gcc.dg/pr94705.c
new file mode 100644
index 00000000000..96392ab60ee
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94705.c
@@ -0,0 +1,13 @@
+/* PR c/94705 */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+void foo ();
+
+int
+bar (void)
+{
+  foo (baz);	/* { dg-error "'baz' undeclared" } */
+		/* { dg-message "only once" "" { target *-*-* } .-1 } */
+  void __attribute__ ((noinline)) baz (void);
+}

commit b3a45adc90bbbdf7a62e9ff301b32f43ba93cdad
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Apr 23 21:57:50 2020 +0200

    Shortcut identity VEC_PERM expansion [PR94710]
    
    This PR is about the rs6000 backend emitting wrong assembly
    for whole vector shift by 0, and while I think it is desirable
    to fix the backend, I don't see a point why the expander should
    try to emit that, whole vector shift by 0 is identity, we can just
    return the operand.
    
    2020-04-23  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94710
            * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx
            just return v2.
    
    (cherry picked from commit f51be2fb8653f81092f8158a0f0527275f86603b)

diff --git a/gcc/optabs.c b/gcc/optabs.c
index a74d7be0d09..51d838d4f93 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -5518,6 +5518,8 @@ expand_vec_perm_const (machine_mode mode, rtx v0, rtx v1,
       if (shift_amt)
 	{
 	  struct expand_operand ops[3];
+	  if (shift_amt == const0_rtx)
+	    return v0;
 	  if (shift_code != CODE_FOR_nothing)
 	    {
 	      create_output_operand (&ops[0], target, mode);

commit 012e366a3928303aa1082876313e0bc3ea67190e
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Apr 25 00:11:35 2020 +0200

    c++: Avoid -Wreturn-type warning if a template fn calls noreturn template fn [PR94742]
    
    finish_call_expr already has code to set current_function_returns_abnormally
    if a template calls a noreturn function, but on the following testcase it
    doesn't call a FUNCTION_DECL, but TEMPLATE_DECL instead, in which case
    we didn't check noreturn at all and just assumed it could return.
    
    2020-04-25  Jakub Jelinek  <jakub@redhat.com>
    
            PR c++/94742
            * semantics.c (finish_call_expr): When looking if all overloads
            are noreturn, use STRIP_TEMPLATE to look through TEMPLATE_DECLs.
    
            * g++.dg/warn/Wreturn-type-12.C: New test.
    
    (cherry picked from commit 4ff685a8705e8ee55fa86e75afb769ffb0975aea)

diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c
index 5099215ab5b..548e65b06e1 100644
--- a/gcc/cp/semantics.c
+++ b/gcc/cp/semantics.c
@@ -2417,7 +2417,7 @@ finish_call_expr (tree fn, vec<tree, va_gc> **args, bool disallow_virtual,
 	      bool abnormal = true;
 	      for (lkp_iterator iter (fn); abnormal && iter; ++iter)
 		{
-		  tree fndecl = *iter;
+		  tree fndecl = STRIP_TEMPLATE (*iter);
 		  if (TREE_CODE (fndecl) != FUNCTION_DECL
 		      || !TREE_THIS_VOLATILE (fndecl))
 		    abnormal = false;
diff --git a/gcc/testsuite/g++.dg/warn/Wreturn-type-12.C b/gcc/testsuite/g++.dg/warn/Wreturn-type-12.C
new file mode 100644
index 00000000000..b35d3faafb0
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Wreturn-type-12.C
@@ -0,0 +1,23 @@
+// PR c++/94742
+// { dg-do compile { target c++11 } }
+// { dg-options "-Wreturn-type" }
+
+template <class T>
+[[noreturn]] void
+foo (T const &t, char const *)
+{
+  throw T (t);
+}
+
+template <class U>
+int
+bar ()
+{
+  foo (42, __FUNCTION__);
+}	// { dg-bogus "no return statement in function returning non-void" }
+
+int
+main ()
+{
+  bar<long>();
+}

commit a8a6b29393dbc13d81fdc5d354526452bd79fb94
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Mon Apr 27 21:14:52 2020 +0200

    x86: Fix up ix86_atomic_assign_expand_fenv [PR94780]
    
    This function, because it is sometimes called even outside of function
    bodies, uses create_tmp_var_raw rather than create_tmp_var.  But in order
    for that to work, when first referenced, the VAR_DECLs need to appear in a
    TARGET_EXPR so that during gimplification the var gets the right
    DECL_CONTEXT and is added to local decls.  Without that, e.g. tree-nested.c
    ICEs on those.
    
    2020-04-27  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94780
            * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use
            TARGET_EXPR instead of MODIFY_EXPR for first assignment to
            sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var.
    
            * gcc.dg/pr94780.c: New test.
    
    (cherry picked from commit 9b8e9006bb35641865358e2df4f6b3ae185b239a)

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index b4516714465..f3c722b51e9 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -50990,11 +50990,12 @@ ix86_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
       *clear = build_call_expr (fnclex, 0);
       tree sw_var = create_tmp_var_raw (short_unsigned_type_node);
       tree fnstsw_call = build_call_expr (fnstsw, 0);
-      tree sw_mod = build2 (MODIFY_EXPR, short_unsigned_type_node,
-			    sw_var, fnstsw_call);
+      tree sw_mod = build4 (TARGET_EXPR, short_unsigned_type_node, sw_var,
+			    fnstsw_call, NULL_TREE, NULL_TREE);
       tree exceptions_x87 = fold_convert (integer_type_node, sw_var);
-      tree update_mod = build2 (MODIFY_EXPR, integer_type_node,
-				exceptions_var, exceptions_x87);
+      tree update_mod = build4 (TARGET_EXPR, integer_type_node,
+				exceptions_var, exceptions_x87,
+				NULL_TREE, NULL_TREE);
       *update = build2 (COMPOUND_EXPR, integer_type_node,
 			sw_mod, update_mod);
       tree update_fldenv = build_call_expr (fldenv, 1, fenv_addr);
@@ -51007,15 +51008,17 @@ ix86_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
       tree stmxcsr = ix86_builtins[IX86_BUILTIN_STMXCSR];
       tree ldmxcsr = ix86_builtins[IX86_BUILTIN_LDMXCSR];
       tree stmxcsr_hold_call = build_call_expr (stmxcsr, 0);
-      tree hold_assign_orig = build2 (MODIFY_EXPR, unsigned_type_node,
-				      mxcsr_orig_var, stmxcsr_hold_call);
+      tree hold_assign_orig = build4 (TARGET_EXPR, unsigned_type_node,
+				      mxcsr_orig_var, stmxcsr_hold_call,
+				      NULL_TREE, NULL_TREE);
       tree hold_mod_val = build2 (BIT_IOR_EXPR, unsigned_type_node,
 				  mxcsr_orig_var,
 				  build_int_cst (unsigned_type_node, 0x1f80));
       hold_mod_val = build2 (BIT_AND_EXPR, unsigned_type_node, hold_mod_val,
 			     build_int_cst (unsigned_type_node, 0xffffffc0));
-      tree hold_assign_mod = build2 (MODIFY_EXPR, unsigned_type_node,
-				     mxcsr_mod_var, hold_mod_val);
+      tree hold_assign_mod = build4 (TARGET_EXPR, unsigned_type_node,
+				     mxcsr_mod_var, hold_mod_val,
+				     NULL_TREE, NULL_TREE);
       tree ldmxcsr_hold_call = build_call_expr (ldmxcsr, 1, mxcsr_mod_var);
       tree hold_all = build2 (COMPOUND_EXPR, unsigned_type_node,
 			      hold_assign_orig, hold_assign_mod);
@@ -51044,8 +51047,8 @@ ix86_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 			    exceptions_assign);
 	}
       else
-	*update = build2 (MODIFY_EXPR, integer_type_node,
-			  exceptions_var, exceptions_sse);
+	*update = build4 (TARGET_EXPR, integer_type_node, exceptions_var,
+			  exceptions_sse, NULL_TREE, NULL_TREE);
       tree ldmxcsr_update_call = build_call_expr (ldmxcsr, 1, mxcsr_orig_var);
       *update = build2 (COMPOUND_EXPR, void_type_node, *update,
 			ldmxcsr_update_call);
diff --git a/gcc/testsuite/gcc.dg/pr94780.c b/gcc/testsuite/gcc.dg/pr94780.c
new file mode 100644
index 00000000000..c4b723e24b2
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94780.c
@@ -0,0 +1,13 @@
+/* PR target/94780 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+_Atomic double x;
+
+double
+foo (void)
+{
+  double bar () { return x; }
+  x /= 3;
+  return bar ();
+}

commit 1831242824752a6c51f513759830a8667a97f7f2
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 28 11:26:56 2020 +0200

    tree: Fix up TREE_SIDE_EFFECTS on internal calls [PR94809]
    
    On the following testcase, match.pd during GENERIC folding
    changes the -1U / x < y into __imag__ .MUL_OVERFLOW (x, y),
    but unfortunately unlike for normal calls nothing sets TREE_SIDE_EFFECTS on
    the call.  There is the process_call_operands function that non-internal
    call creation calls and it is usable for internal calls too,
    e.g. TREE_SIDE_EFFECTS is derived from checking whether the
    call has side-effects (non-ECF_{CONST,PURE}; we have those for internal
    calls) and from whether any of the arguments has TREE_SIDE_EFFECTS.
    
    2020-04-28  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/94809
            * tree.c (build_call_expr_internal_loc_array): Call
            process_call_operands.
    
            * gcc.c-torture/execute/pr94809.c: New test.
    
    (cherry picked from commit 34f6b14ff33e0c64b3a4a1a2cd871df715d69151)

diff --git a/gcc/testsuite/gcc.c-torture/execute/pr94809.c b/gcc/testsuite/gcc.c-torture/execute/pr94809.c
new file mode 100644
index 00000000000..ce55e8f92d4
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr94809.c
@@ -0,0 +1,12 @@
+/* PR tree-optimization/94809 */
+
+int
+main ()
+{
+  int a = 0;
+  unsigned long long one = 1;
+  ((-1ULL / one) < a++, one);
+  if (a != 1)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc/tree.c b/gcc/tree.c
index d3291a169de..3774ff4bf4b 100644
--- a/gcc/tree.c
+++ b/gcc/tree.c
@@ -10952,6 +10952,7 @@ build_call_expr_internal_loc_array (location_t loc, internal_fn ifn,
     CALL_EXPR_ARG (t, i) = args[i];
   SET_EXPR_LOCATION (t, loc);
   CALL_EXPR_IFN (t) = ifn;
+  process_call_operands (t);
   return t;
 }
 

commit 840a91477f0157a5811957b7d866489d519fb77f
Author: Haijian Zhang <z.zhanghaijian@huawei.com>
Date:   Wed Apr 29 10:23:11 2020 +0200

    pr94780.c fails with ICE on aarch64 [PR94820]
    
    This is a simple fix for pr94820.
    The PR was only fixed on i386, the same error was also reported on aarch64.
    This function, because it is sometimes called even outside of function bodies, uses create_tmp_var_raw rather than create_tmp_var.
    But in order for that to work, when first referenced, the VAR_DECLs need to appear in a TARGET_EXPR so that during gimplification
    the var gets the right DECL_CONTEXT and is added to local decls. Without that, e.g. tree-nested.c ICEs on those.
    
    2020-04-29  Haijian Zhang  <z.zhanghaijian@huawei.com>
    
            PR target/94820
            * config/aarch64/aarch64-builtins.c
            (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of
            MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and
            new_fenv_var.
    
    (cherry picked from commit d81bc2af7d2700888e414eb5a322ff5f5b0df0bb)

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 02c6738d220..ced3aa6c100 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -1751,10 +1751,12 @@ aarch64_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
   mask_sr = build_int_cst (unsigned_type_node,
 			   ~(AARCH64_FE_ALL_EXCEPT));
 
-  ld_fenv_cr = build2 (MODIFY_EXPR, unsigned_type_node,
-		       fenv_cr, build_call_expr (get_fpcr, 0));
-  ld_fenv_sr = build2 (MODIFY_EXPR, unsigned_type_node,
-		       fenv_sr, build_call_expr (get_fpsr, 0));
+  ld_fenv_cr = build4 (TARGET_EXPR, unsigned_type_node,
+		       fenv_cr, build_call_expr (get_fpcr, 0),
+		       NULL_TREE, NULL_TREE);
+  ld_fenv_sr = build4 (TARGET_EXPR, unsigned_type_node,
+		       fenv_sr, build_call_expr (get_fpsr, 0),
+		       NULL_TREE, NULL_TREE);
 
   masked_fenv_cr = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_cr, mask_cr);
   masked_fenv_sr = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_sr, mask_sr);
@@ -1786,8 +1788,9 @@ aarch64_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
        __atomic_feraiseexcept (new_fenv_var);  */
 
   new_fenv_var = create_tmp_var_raw (unsigned_type_node);
-  reload_fenv = build2 (MODIFY_EXPR, unsigned_type_node,
-			new_fenv_var, build_call_expr (get_fpsr, 0));
+  reload_fenv = build4 (TARGET_EXPR, unsigned_type_node,
+			new_fenv_var, build_call_expr (get_fpsr, 0),
+			NULL_TREE, NULL_TREE);
   restore_fnenv = build_call_expr (set_fpsr, 1, fenv_sr);
   atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
   update_call = build_call_expr (atomic_feraiseexcept, 1,

commit e031d8024aa22d31ceb85180a6607b3d6bb01481
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Apr 29 15:55:39 2020 +0200

    rs6000: Fix rs6000_atomic_assign_expand_fenv [PR94826]
    
    This is the rs6000 version of the earlier committed x86, aarch64 and arm
    fixes, as create_tmp_var_raw is used because the C FE can call this outside
    of function context, we need to make sure the first references to those
    VAR_DECLs are through a TARGET_EXPR, so that it gets gimple_add_tmp_var
    marked in whatever function it gets expanded in.  Without that DECL_CONTEXT
    is NULL and the vars aren't added as local decls of the containing function.
    
    2020-04-29  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94826
            * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use
            TARGET_EXPR instead of MODIFY_EXPR for first assignment to
            fenv_var, fenv_clear and old_fenv variables.  For fenv_addr
            take address of TARGET_EXPR of fenv_var with void_node initializer.
            Formatting fixes.
    
    (cherry picked from commit c7137fcc7cbc1f1f14f9fed75adcc6bd8f1d418c)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 261e2aa808f..aea362cdf6e 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -39710,7 +39710,9 @@ rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 
       tree fenv_var = create_tmp_var_raw (double_type_node);
       TREE_ADDRESSABLE (fenv_var) = 1;
-      tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
+      tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node,
+			       build4 (TARGET_EXPR, double_type_node, fenv_var,
+				       void_node, NULL_TREE, NULL_TREE));
 
       *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
       *clear = build_call_expr (atomic_clear_decl, 0);
@@ -39733,12 +39735,13 @@ rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 
   /* Mask to clear everything except for the rounding modes and non-IEEE
      arithmetic flag.  */
-  const unsigned HOST_WIDE_INT hold_exception_mask =
-    HOST_WIDE_INT_C (0xffffffff00000007);
+  const unsigned HOST_WIDE_INT hold_exception_mask
+    = HOST_WIDE_INT_C (0xffffffff00000007);
 
   tree fenv_var = create_tmp_var_raw (double_type_node);
 
-  tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
+  tree hold_mffs = build4 (TARGET_EXPR, double_type_node, fenv_var, call_mffs,
+			   NULL_TREE, NULL_TREE);
 
   tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
   tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
@@ -39762,12 +39765,13 @@ rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 
   /* Mask to clear everything except for the rounding modes and non-IEEE
      arithmetic flag.  */
-  const unsigned HOST_WIDE_INT clear_exception_mask =
-    HOST_WIDE_INT_C (0xffffffff00000000);
+  const unsigned HOST_WIDE_INT clear_exception_mask
+    = HOST_WIDE_INT_C (0xffffffff00000000);
 
   tree fenv_clear = create_tmp_var_raw (double_type_node);
 
-  tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
+  tree clear_mffs = build4 (TARGET_EXPR, double_type_node, fenv_clear,
+			    call_mffs, NULL_TREE, NULL_TREE);
 
   tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
   tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
@@ -39792,13 +39796,14 @@ rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
                                 (*(uint64_t*)fenv_var 0x1ff80fff);
      __builtin_mtfsf (0xff, fenv_update);  */
 
-  const unsigned HOST_WIDE_INT update_exception_mask =
-    HOST_WIDE_INT_C (0xffffffff1fffff00);
-  const unsigned HOST_WIDE_INT new_exception_mask =
-    HOST_WIDE_INT_C (0x1ff80fff);
+  const unsigned HOST_WIDE_INT update_exception_mask
+    = HOST_WIDE_INT_C (0xffffffff1fffff00);
+  const unsigned HOST_WIDE_INT new_exception_mask
+    = HOST_WIDE_INT_C (0x1ff80fff);
 
   tree old_fenv = create_tmp_var_raw (double_type_node);
-  tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
+  tree update_mffs = build4 (TARGET_EXPR, double_type_node, old_fenv,
+			     call_mffs, NULL_TREE, NULL_TREE);
 
   tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
   tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,

commit b45a7ab268df5803f6980642bc32a3c4f39d6e90
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Apr 29 17:30:22 2020 +0200

    x86: Fix -O0 intrinsic *gather*/*scatter* macros [PR94832]
    
    As reported in the PR, while most intrinsic -O0 macro argument uses
    are properly wrapped in ()s or used in context where having a complex
    expression passed as the argument doesn't pose a problem (e.g. when
    macro argument use is in between commas, or between ( and comma, or
    between comma and ) etc.), especially the gather/scatter macros don't do
    this and if one passes to some macro e.g. x + y as argument, the
    corresponding inline function would do cast on the argument, but
    the macro does (int) ARG, then it is (int) x + y rather than (int) (x + y).
    
    The following patch fixes those issues in *gather/*scatter*; additionally,
    the AVX2 macros were passing incorrect mask of e.g.
    (__v2df)_mm_set1_pd((double)(long long int) -1)
    which is IMHO equivalent to
    (__v2df){-1.0, -1.0}
    when it really wants to pass __v2df vector with all bits set.
    I've used what the inline functions use for those cases.
    
    2020-04-29  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94832
            * config/i386/avx2intrin.h (_mm_mask_i32gather_pd,
            _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd,
            _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps,
            _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps,
            _mm256_mask_i64gather_ps, _mm_i32gather_epi64,
            _mm_mask_i32gather_epi64, _mm256_i32gather_epi64,
            _mm256_mask_i32gather_epi64, _mm_i64gather_epi64,
            _mm_mask_i64gather_epi64, _mm256_i64gather_epi64,
            _mm256_mask_i64gather_epi64, _mm_i32gather_epi32,
            _mm_mask_i32gather_epi32, _mm256_i32gather_epi32,
            _mm256_mask_i32gather_epi32, _mm_i64gather_epi32,
            _mm_mask_i64gather_epi32, _mm256_i64gather_epi32,
            _mm256_mask_i64gather_epi32): Surround macro parameter uses with
            parens.
            (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd,
            _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps,
            _mm_i64gather_ps, _mm256_i64gather_ps): Likewise.  Don't use
            as mask vector containing -1.0 or -1.0f elts, but instead vector
            with all bits set using _mm*_cmpeq_p? with zero operands.
            * config/i386/avx512fintrin.h (_mm512_i32gather_ps,
            _mm512_mask_i32gather_ps, _mm512_i32gather_pd,
            _mm512_mask_i32gather_pd, _mm512_i64gather_ps,
            _mm512_mask_i64gather_ps, _mm512_i64gather_pd,
            _mm512_mask_i64gather_pd, _mm512_i32gather_epi32,
            _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64,
            _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32,
            _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64,
            _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps,
            _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd,
            _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps,
            _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd,
            _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32,
            _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64,
            _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32,
            _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64,
            _mm512_mask_i64scatter_epi64): Surround macro parameter uses with
            parens.
            * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd,
            _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd,
            _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd,
            _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd,
            _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd,
            _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd,
            _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd,
            _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd,
            _mm512_mask_prefetch_i64scatter_ps): Likewise.
            * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps,
            _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd,
            _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps,
            _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd,
            _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32,
            _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64,
            _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32,
            _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64,
            _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps,
            _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps,
            _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd,
            _mm_mask_i32scatter_pd, _mm256_i64scatter_ps,
            _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps,
            _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd,
            _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32,
            _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32,
            _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64,
            _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64,
            _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32,
            _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32,
            _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64,
            _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64,
            _mm_mask_i64scatter_epi64): Likewise.
    
    (cherry picked from commit 78cef09019cc9c80d1b39a49861f8827a2ee2e60)

diff --git a/gcc/config/i386/avx2intrin.h b/gcc/config/i386/avx2intrin.h
index 8906600a225..884c1dee817 100644
--- a/gcc/config/i386/avx2intrin.h
+++ b/gcc/config/i386/avx2intrin.h
@@ -1670,234 +1670,246 @@ _mm256_mask_i64gather_epi32 (__m128i __src, int const *__base,
 #else /* __OPTIMIZE__ */
 #define _mm_i32gather_pd(BASE, INDEX, SCALE)				\
   (__m128d) __builtin_ia32_gathersiv2df ((__v2df) _mm_setzero_pd (),	\
-					 (double const *)BASE,		\
-					 (__v4si)(__m128i)INDEX,	\
-					 (__v2df)_mm_set1_pd(		\
-					   (double)(long long int) -1), \
-					 (int)SCALE)
-
-#define _mm_mask_i32gather_pd(SRC, BASE, INDEX, MASK, SCALE)	 \
-  (__m128d) __builtin_ia32_gathersiv2df ((__v2df)(__m128d)SRC,	 \
-					 (double const *)BASE,	 \
-					 (__v4si)(__m128i)INDEX, \
-					 (__v2df)(__m128d)MASK,	 \
-					 (int)SCALE)
+					 (double const *) (BASE),	\
+					 (__v4si)(__m128i) (INDEX),	\
+					 (__v2df)			\
+					 _mm_cmpeq_pd (_mm_setzero_pd (),\
+						       _mm_setzero_pd ()),\
+					 (int) (SCALE))
+
+#define _mm_mask_i32gather_pd(SRC, BASE, INDEX, MASK, SCALE)	 	\
+  (__m128d) __builtin_ia32_gathersiv2df ((__v2df)(__m128d) (SRC),	\
+					 (double const *) (BASE),	\
+					 (__v4si)(__m128i) (INDEX),	\
+					 (__v2df)(__m128d) (MASK),	\
+					 (int) (SCALE))
 
 #define _mm256_i32gather_pd(BASE, INDEX, SCALE)				\
   (__m256d) __builtin_ia32_gathersiv4df ((__v4df) _mm256_setzero_pd (),	\
-					 (double const *)BASE,		\
-					 (__v4si)(__m128i)INDEX,	\
-					 (__v4df)_mm256_set1_pd(	\
-					   (double)(long long int) -1), \
-					 (int)SCALE)
-
-#define _mm256_mask_i32gather_pd(SRC, BASE, INDEX, MASK, SCALE)	 \
-  (__m256d) __builtin_ia32_gathersiv4df ((__v4df)(__m256d)SRC,	 \
-					 (double const *)BASE,	 \
-					 (__v4si)(__m128i)INDEX, \
-					 (__v4df)(__m256d)MASK,	 \
-					 (int)SCALE)
+					 (double const *) (BASE),	\
+					 (__v4si)(__m128i) (INDEX),	\
+					 (__v4df)			\
+					 _mm256_cmp_pd (_mm256_setzero_pd (),\
+							_mm256_setzero_pd (),\
+							_CMP_EQ_OQ),	\
+					 (int) (SCALE))
+
+#define _mm256_mask_i32gather_pd(SRC, BASE, INDEX, MASK, SCALE)		\
+  (__m256d) __builtin_ia32_gathersiv4df ((__v4df)(__m256d) (SRC),	\
+					 (double const *) (BASE),	\
+					 (__v4si)(__m128i) (INDEX),	\
+					 (__v4df)(__m256d) (MASK),	\
+					 (int) (SCALE))
 
 #define _mm_i64gather_pd(BASE, INDEX, SCALE)				\
   (__m128d) __builtin_ia32_gatherdiv2df ((__v2df) _mm_setzero_pd (),	\
-					 (double const *)BASE,		\
-					 (__v2di)(__m128i)INDEX,	\
-					 (__v2df)_mm_set1_pd(		\
-					   (double)(long long int) -1), \
-					 (int)SCALE)
-
-#define _mm_mask_i64gather_pd(SRC, BASE, INDEX, MASK, SCALE)	 \
-  (__m128d) __builtin_ia32_gatherdiv2df ((__v2df)(__m128d)SRC,	 \
-					 (double const *)BASE,	 \
-					 (__v2di)(__m128i)INDEX, \
-					 (__v2df)(__m128d)MASK,	 \
-					 (int)SCALE)
+					 (double const *) (BASE),	\
+					 (__v2di)(__m128i) (INDEX),	\
+					 (__v2df)			\
+					 _mm_cmpeq_pd (_mm_setzero_pd (),\
+						       _mm_setzero_pd ()),\
+					 (int) (SCALE))
+
+#define _mm_mask_i64gather_pd(SRC, BASE, INDEX, MASK, SCALE)		\
+  (__m128d) __builtin_ia32_gatherdiv2df ((__v2df)(__m128d) (SRC),	\
+					 (double const *) (BASE),	\
+					 (__v2di)(__m128i) (INDEX),	\
+					 (__v2df)(__m128d) (MASK),	\
+					 (int) (SCALE))
 
 #define _mm256_i64gather_pd(BASE, INDEX, SCALE)				\
   (__m256d) __builtin_ia32_gatherdiv4df ((__v4df) _mm256_setzero_pd (),	\
-					 (double const *)BASE,		\
-					 (__v4di)(__m256i)INDEX,	\
-					 (__v4df)_mm256_set1_pd(	\
-					   (double)(long long int) -1), \
-					 (int)SCALE)
-
-#define _mm256_mask_i64gather_pd(SRC, BASE, INDEX, MASK, SCALE)	 \
-  (__m256d) __builtin_ia32_gatherdiv4df ((__v4df)(__m256d)SRC,	 \
-					 (double const *)BASE,	 \
-					 (__v4di)(__m256i)INDEX, \
-					 (__v4df)(__m256d)MASK,	 \
-					 (int)SCALE)
+					 (double const *) (BASE),	\
+					 (__v4di)(__m256i) (INDEX),	\
+					 (__v4df)			\
+					 _mm256_cmp_pd (_mm256_setzero_pd (),\
+							_mm256_setzero_pd (),\
+							_CMP_EQ_OQ),	\
+					 (int) (SCALE))
+
+#define _mm256_mask_i64gather_pd(SRC, BASE, INDEX, MASK, SCALE)	 	\
+  (__m256d) __builtin_ia32_gatherdiv4df ((__v4df)(__m256d) (SRC),	\
+					 (double const *) (BASE),	\
+					 (__v4di)(__m256i) (INDEX),	\
+					 (__v4df)(__m256d) (MASK),	\
+					 (int) (SCALE))
 
 #define _mm_i32gather_ps(BASE, INDEX, SCALE)				\
   (__m128) __builtin_ia32_gathersiv4sf ((__v4sf) _mm_setzero_ps (),	\
-					(float const *)BASE,		\
-					(__v4si)(__m128i)INDEX,		\
-					_mm_set1_ps ((float)(int) -1),	\
-					(int)SCALE)
-
-#define _mm_mask_i32gather_ps(SRC, BASE, INDEX, MASK, SCALE)	 \
-  (__m128) __builtin_ia32_gathersiv4sf ((__v4sf)(__m128)SRC,	 \
-					(float const *)BASE,	 \
-					(__v4si)(__m128i)INDEX,	 \
-					(__v4sf)(__m128)MASK,	 \
-					(int)SCALE)
-
-#define _mm256_i32gather_ps(BASE, INDEX, SCALE)			       \
-  (__m256) __builtin_ia32_gathersiv8sf ((__v8sf) _mm256_setzero_ps (), \
-					(float const *)BASE,	       \
-					(__v8si)(__m256i)INDEX,	       \
-					(__v8sf)_mm256_set1_ps (       \
-					  (float)(int) -1),	       \
-					(int)SCALE)
-
-#define _mm256_mask_i32gather_ps(SRC, BASE, INDEX, MASK, SCALE) \
-  (__m256) __builtin_ia32_gathersiv8sf ((__v8sf)(__m256)SRC,	\
-					(float const *)BASE,	\
-					(__v8si)(__m256i)INDEX, \
-					(__v8sf)(__m256)MASK,	\
-					(int)SCALE)
+					(float const *) (BASE),		\
+					(__v4si)(__m128i) (INDEX),	\
+					(__v4sf)			\
+					_mm_cmpeq_ps (_mm_setzero_ps (),\
+						      _mm_setzero_ps ()),\
+					(int) (SCALE))
+
+#define _mm_mask_i32gather_ps(SRC, BASE, INDEX, MASK, SCALE)	 	\
+  (__m128) __builtin_ia32_gathersiv4sf ((__v4sf)(__m128) (SRC),		\
+					(float const *) (BASE),		\
+					(__v4si)(__m128i) (INDEX),	\
+					(__v4sf)(__m128) (MASK),	\
+					(int) (SCALE))
+
+#define _mm256_i32gather_ps(BASE, INDEX, SCALE)				\
+  (__m256) __builtin_ia32_gathersiv8sf ((__v8sf) _mm256_setzero_ps (),	\
+					(float const *) (BASE),		\
+					(__v8si)(__m256i) (INDEX),	\
+					(__v8sf)			\
+					_mm256_cmp_ps (_mm256_setzero_ps (),\
+						       _mm256_setzero_ps (),\
+						       _CMP_EQ_OQ),	\
+					(int) (SCALE))
+
+#define _mm256_mask_i32gather_ps(SRC, BASE, INDEX, MASK, SCALE)		\
+  (__m256) __builtin_ia32_gathersiv8sf ((__v8sf)(__m256) (SRC),		\
+					(float const *) (BASE),		\
+					(__v8si)(__m256i) (INDEX),	\
+					(__v8sf)(__m256) (MASK),	\
+					(int) (SCALE))
 
 #define _mm_i64gather_ps(BASE, INDEX, SCALE)				\
   (__m128) __builtin_ia32_gatherdiv4sf ((__v4sf) _mm_setzero_pd (),	\
-					(float const *)BASE,		\
-					(__v2di)(__m128i)INDEX,		\
-					(__v4sf)_mm_set1_ps (		\
-					  (float)(int) -1),		\
-					(int)SCALE)
-
-#define _mm_mask_i64gather_ps(SRC, BASE, INDEX, MASK, SCALE)	 \
-  (__m128) __builtin_ia32_gatherdiv4sf ((__v4sf)(__m128)SRC,	 \
-					(float const *)BASE,	 \
-					(__v2di)(__m128i)INDEX,	 \
-					(__v4sf)(__m128)MASK,	 \
-					(int)SCALE)
+					(float const *) (BASE),		\
+					(__v2di)(__m128i) (INDEX),	\
+					(__v4sf)			\
+					_mm_cmpeq_ps (_mm_setzero_ps (),\
+						      _mm_setzero_ps ()),\
+					(int) (SCALE))
+
+#define _mm_mask_i64gather_ps(SRC, BASE, INDEX, MASK, SCALE)		\
+  (__m128) __builtin_ia32_gatherdiv4sf ((__v4sf)(__m128) (SRC),		\
+					(float const *) (BASE),		\
+					(__v2di)(__m128i) (INDEX),	\
+					(__v4sf)(__m128) (MASK),	\
+					(int) (SCALE))
 
 #define _mm256_i64gather_ps(BASE, INDEX, SCALE)				\
   (__m128) __builtin_ia32_gatherdiv4sf256 ((__v4sf) _mm_setzero_ps (),	\
-					   (float const *)BASE,		\
-					   (__v4di)(__m256i)INDEX,	\
-					   (__v4sf)_mm_set1_ps(		\
-					     (float)(int) -1),		\
-					   (int)SCALE)
-
-#define _mm256_mask_i64gather_ps(SRC, BASE, INDEX, MASK, SCALE)	   \
-  (__m128) __builtin_ia32_gatherdiv4sf256 ((__v4sf)(__m128)SRC,	   \
-					   (float const *)BASE,	   \
-					   (__v4di)(__m256i)INDEX, \
-					   (__v4sf)(__m128)MASK,   \
-					   (int)SCALE)
+					   (float const *) (BASE),	\
+					   (__v4di)(__m256i) (INDEX),	\
+					   (__v4sf)			\
+					   _mm_cmpeq_ps (_mm_setzero_ps (),\
+							 _mm_setzero_ps ()),\
+					   (int) (SCALE))
+
+#define _mm256_mask_i64gather_ps(SRC, BASE, INDEX, MASK, SCALE)	   	\
+  (__m128) __builtin_ia32_gatherdiv4sf256 ((__v4sf)(__m128) (SRC),	\
+					   (float const *) (BASE),	\
+					   (__v4di)(__m256i) (INDEX),	\
+					   (__v4sf)(__m128) (MASK),	\
+					   (int) (SCALE))
 
 #define _mm_i32gather_epi64(BASE, INDEX, SCALE)				\
   (__m128i) __builtin_ia32_gathersiv2di ((__v2di) _mm_setzero_si128 (), \
-					 (long long const *)BASE,	\
-					 (__v4si)(__m128i)INDEX,	\
+					 (long long const *) (BASE),	\
+					 (__v4si)(__m128i) (INDEX),	\
 					 (__v2di)_mm_set1_epi64x (-1),	\
-					 (int)SCALE)
+					 (int) (SCALE))
 
-#define _mm_mask_i32gather_epi64(SRC, BASE, INDEX, MASK, SCALE)	  \
-  (__m128i) __builtin_ia32_gathersiv2di ((__v2di)(__m128i)SRC,	  \
-					 (long long const *)BASE, \
-					 (__v4si)(__m128i)INDEX,  \
-					 (__v2di)(__m128i)MASK,	  \
-					 (int)SCALE)
+#define _mm_mask_i32gather_epi64(SRC, BASE, INDEX, MASK, SCALE)	  	\
+  (__m128i) __builtin_ia32_gathersiv2di ((__v2di)(__m128i) (SRC),	\
+					 (long long const *) (BASE),	\
+					 (__v4si)(__m128i) (INDEX),	\
+					 (__v2di)(__m128i) (MASK),	\
+					 (int) (SCALE))
 
 #define _mm256_i32gather_epi64(BASE, INDEX, SCALE)			   \
   (__m256i) __builtin_ia32_gathersiv4di ((__v4di) _mm256_setzero_si256 (), \
-					 (long long const *)BASE,	   \
-					 (__v4si)(__m128i)INDEX,	   \
+					 (long long const *) (BASE),	   \
+					 (__v4si)(__m128i) (INDEX),	   \
 					 (__v4di)_mm256_set1_epi64x (-1),  \
-					 (int)SCALE)
+					 (int) (SCALE))
 
-#define _mm256_mask_i32gather_epi64(SRC, BASE, INDEX, MASK, SCALE) \
-  (__m256i) __builtin_ia32_gathersiv4di ((__v4di)(__m256i)SRC,	   \
-					 (long long const *)BASE,  \
-					 (__v4si)(__m128i)INDEX,   \
-					 (__v4di)(__m256i)MASK,	   \
-					 (int)SCALE)
+#define _mm256_mask_i32gather_epi64(SRC, BASE, INDEX, MASK, SCALE)	\
+  (__m256i) __builtin_ia32_gathersiv4di ((__v4di)(__m256i) (SRC),	\
+					 (long long const *) (BASE),	\
+					 (__v4si)(__m128i) (INDEX),	\
+					 (__v4di)(__m256i) (MASK),	\
+					 (int) (SCALE))
 
 #define _mm_i64gather_epi64(BASE, INDEX, SCALE)				\
   (__m128i) __builtin_ia32_gatherdiv2di ((__v2di) _mm_setzero_si128 (), \
-					 (long long const *)BASE,	\
-					 (__v2di)(__m128i)INDEX,	\
+					 (long long const *) (BASE),	\
+					 (__v2di)(__m128i) (INDEX),	\
 					 (__v2di)_mm_set1_epi64x (-1),	\
-					 (int)SCALE)
+					 (int) (SCALE))
 
-#define _mm_mask_i64gather_epi64(SRC, BASE, INDEX, MASK, SCALE)	  \
-  (__m128i) __builtin_ia32_gatherdiv2di ((__v2di)(__m128i)SRC,	  \
-					 (long long const *)BASE, \
-					 (__v2di)(__m128i)INDEX,  \
-					 (__v2di)(__m128i)MASK,	  \
-					 (int)SCALE)
+#define _mm_mask_i64gather_epi64(SRC, BASE, INDEX, MASK, SCALE)		\
+  (__m128i) __builtin_ia32_gatherdiv2di ((__v2di)(__m128i) (SRC),	\
+					 (long long const *) (BASE),	\
+					 (__v2di)(__m128i) (INDEX),	\
+					 (__v2di)(__m128i) (MASK),	\
+					 (int) (SCALE))
 
 #define _mm256_i64gather_epi64(BASE, INDEX, SCALE)			   \
   (__m256i) __builtin_ia32_gatherdiv4di ((__v4di) _mm256_setzero_si256 (), \
-					 (long long const *)BASE,	   \
-					 (__v4di)(__m256i)INDEX,	   \
+					 (long long const *) (BASE),	   \
+					 (__v4di)(__m256i) (INDEX),	   \
 					 (__v4di)_mm256_set1_epi64x (-1),  \
-					 (int)SCALE)
+					 (int) (SCALE))
 
-#define _mm256_mask_i64gather_epi64(SRC, BASE, INDEX, MASK, SCALE) \
-  (__m256i) __builtin_ia32_gatherdiv4di ((__v4di)(__m256i)SRC,	   \
-					 (long long const *)BASE,  \
-					 (__v4di)(__m256i)INDEX,   \
-					 (__v4di)(__m256i)MASK,	   \
-					 (int)SCALE)
+#define _mm256_mask_i64gather_epi64(SRC, BASE, INDEX, MASK, SCALE) 	\
+  (__m256i) __builtin_ia32_gatherdiv4di ((__v4di)(__m256i) (SRC),	\
+					 (long long const *) (BASE),	\
+					 (__v4di)(__m256i) (INDEX),	\
+					 (__v4di)(__m256i) (MASK),	\
+					 (int) (SCALE))
 
 #define _mm_i32gather_epi32(BASE, INDEX, SCALE)				\
   (__m128i) __builtin_ia32_gathersiv4si ((__v4si) _mm_setzero_si128 (),	\
-					 (int const *)BASE,		\
-					 (__v4si)(__m128i)INDEX,	\
+					 (int const *) (BASE),		\
+					 (__v4si)(__m128i) (INDEX),	\
 					 (__v4si)_mm_set1_epi32 (-1),	\
-					 (int)SCALE)
+					 (int) (SCALE))
 
-#define _mm_mask_i32gather_epi32(SRC, BASE, INDEX, MASK, SCALE) \
-  (__m128i) __builtin_ia32_gathersiv4si ((__v4si)(__m128i)SRC,	\
-					(int const *)BASE,	\
-					(__v4si)(__m128i)INDEX, \
-					(__v4si)(__m128i)MASK,	\
-					(int)SCALE)
+#define _mm_mask_i32gather_epi32(SRC, BASE, INDEX, MASK, SCALE)		\
+  (__m128i) __builtin_ia32_gathersiv4si ((__v4si)(__m128i) (SRC),	\
+					(int const *) (BASE),		\
+					(__v4si)(__m128i) (INDEX),	\
+					(__v4si)(__m128i) (MASK),	\
+					(int) (SCALE))
 
 #define _mm256_i32gather_epi32(BASE, INDEX, SCALE)			   \
   (__m256i) __builtin_ia32_gathersiv8si ((__v8si) _mm256_setzero_si256 (), \
-					 (int const *)BASE,		   \
-					 (__v8si)(__m256i)INDEX,	   \
+					 (int const *) (BASE),		   \
+					 (__v8si)(__m256i) (INDEX),	   \
 					 (__v8si)_mm256_set1_epi32 (-1),   \
-					 (int)SCALE)
+					 (int) (SCALE))
 
-#define _mm256_mask_i32gather_epi32(SRC, BASE, INDEX, MASK, SCALE) \
-  (__m256i) __builtin_ia32_gathersiv8si ((__v8si)(__m256i)SRC,	   \
-					(int const *)BASE,	   \
-					(__v8si)(__m256i)INDEX,	   \
-					(__v8si)(__m256i)MASK,	   \
-					(int)SCALE)
+#define _mm256_mask_i32gather_epi32(SRC, BASE, INDEX, MASK, SCALE)	\
+  (__m256i) __builtin_ia32_gathersiv8si ((__v8si)(__m256i) (SRC),	\
+					(int const *) (BASE),	   	\
+					(__v8si)(__m256i) (INDEX),	\
+					(__v8si)(__m256i) (MASK),	\
+					(int) (SCALE))
 
 #define _mm_i64gather_epi32(BASE, INDEX, SCALE)				\
   (__m128i) __builtin_ia32_gatherdiv4si ((__v4si) _mm_setzero_si128 (),	\
-					 (int const *)BASE,		\
-					 (__v2di)(__m128i)INDEX,	\
+					 (int const *) (BASE),		\
+					 (__v2di)(__m128i) (INDEX),	\
 					 (__v4si)_mm_set1_epi32 (-1),	\
-					 (int)SCALE)
+					 (int) (SCALE))
 
-#define _mm_mask_i64gather_epi32(SRC, BASE, INDEX, MASK, SCALE) \
-  (__m128i) __builtin_ia32_gatherdiv4si ((__v4si)(__m128i)SRC,	\
-					(int const *)BASE,	\
-					(__v2di)(__m128i)INDEX, \
-					(__v4si)(__m128i)MASK,	\
-					(int)SCALE)
+#define _mm_mask_i64gather_epi32(SRC, BASE, INDEX, MASK, SCALE)		\
+  (__m128i) __builtin_ia32_gatherdiv4si ((__v4si)(__m128i) (SRC),	\
+					(int const *) (BASE),		\
+					(__v2di)(__m128i) (INDEX),	\
+					(__v4si)(__m128i) (MASK),	\
+					(int) (SCALE))
 
 #define _mm256_i64gather_epi32(BASE, INDEX, SCALE)			   \
   (__m128i) __builtin_ia32_gatherdiv4si256 ((__v4si) _mm_setzero_si128 (), \
-					    (int const *)BASE,		   \
-					    (__v4di)(__m256i)INDEX,	   \
+					    (int const *) (BASE),	   \
+					    (__v4di)(__m256i) (INDEX),	   \
 					    (__v4si)_mm_set1_epi32(-1),	   \
-					    (int)SCALE)
-
-#define _mm256_mask_i64gather_epi32(SRC, BASE, INDEX, MASK, SCALE) \
-  (__m128i) __builtin_ia32_gatherdiv4si256 ((__v4si)(__m128i)SRC,  \
-					   (int const *)BASE,	   \
-					   (__v4di)(__m256i)INDEX, \
-					   (__v4si)(__m128i)MASK,  \
-					   (int)SCALE)
+					    (int) (SCALE))
+
+#define _mm256_mask_i64gather_epi32(SRC, BASE, INDEX, MASK, SCALE)	\
+  (__m128i) __builtin_ia32_gatherdiv4si256 ((__v4si)(__m128i) (SRC),	\
+					   (int const *) (BASE),	\
+					   (__v4di)(__m256i) (INDEX),	\
+					   (__v4si)(__m128i) (MASK),	\
+					   (int) (SCALE))
 #endif  /* __OPTIMIZE__ */
 
 #ifdef __DISABLE_AVX2__
diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h
index 74184ff8a17..f739c1795cc 100644
--- a/gcc/config/i386/avx512fintrin.h
+++ b/gcc/config/i386/avx512fintrin.h
@@ -10185,179 +10185,189 @@ _mm512_mask_i64scatter_epi64 (void *__addr, __mmask8 __mask,
 #else
 #define _mm512_i32gather_ps(INDEX, ADDR, SCALE)				\
   (__m512) __builtin_ia32_gathersiv16sf ((__v16sf)_mm512_undefined_ps(),\
-					 (void const *)ADDR,		\
-					 (__v16si)(__m512i)INDEX,	\
-					 (__mmask16)0xFFFF, (int)SCALE)
+					 (void const *) (ADDR),		\
+					 (__v16si)(__m512i) (INDEX),	\
+					 (__mmask16)0xFFFF,		\
+					 (int) (SCALE))
 
 #define _mm512_mask_i32gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m512) __builtin_ia32_gathersiv16sf ((__v16sf)(__m512)V1OLD,	\
-					 (void const *)ADDR,		\
-					 (__v16si)(__m512i)INDEX,	\
-					 (__mmask16)MASK, (int)SCALE)
+  (__m512) __builtin_ia32_gathersiv16sf ((__v16sf)(__m512) (V1OLD),	\
+					 (void const *) (ADDR),		\
+					 (__v16si)(__m512i) (INDEX),	\
+					 (__mmask16) (MASK),		\
+					 (int) (SCALE))
 
 #define _mm512_i32gather_pd(INDEX, ADDR, SCALE)				\
   (__m512d) __builtin_ia32_gathersiv8df ((__v8df)_mm512_undefined_pd(),	\
-					 (void const *)ADDR,		\
-					 (__v8si)(__m256i)INDEX,	\
-					 (__mmask8)0xFF, (int)SCALE)
+					 (void const *) (ADDR),		\
+					 (__v8si)(__m256i) (INDEX),	\
+					 (__mmask8)0xFF, (int) (SCALE))
 
 #define _mm512_mask_i32gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m512d) __builtin_ia32_gathersiv8df ((__v8df)(__m512d)V1OLD,	\
-					 (void const *)ADDR,		\
-					 (__v8si)(__m256i)INDEX,	\
-					 (__mmask8)MASK, (int)SCALE)
+  (__m512d) __builtin_ia32_gathersiv8df ((__v8df)(__m512d) (V1OLD),	\
+					 (void const *) (ADDR),		\
+					 (__v8si)(__m256i) (INDEX),	\
+					 (__mmask8) (MASK),		\
+					 (int) (SCALE))
 
 #define _mm512_i64gather_ps(INDEX, ADDR, SCALE)				\
   (__m256) __builtin_ia32_gatherdiv16sf ((__v8sf)_mm256_undefined_ps(),	\
-					 (void const *)ADDR,		\
-					 (__v8di)(__m512i)INDEX,	\
-					 (__mmask8)0xFF, (int)SCALE)
+					 (void const *) (ADDR),		\
+					 (__v8di)(__m512i) (INDEX),	\
+					 (__mmask8)0xFF, (int) (SCALE))
 
 #define _mm512_mask_i64gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m256) __builtin_ia32_gatherdiv16sf ((__v8sf)(__m256)V1OLD,		\
-					 (void const *)ADDR,		\
-					 (__v8di)(__m512i)INDEX,	\
-					 (__mmask8)MASK, (int)SCALE)
+  (__m256) __builtin_ia32_gatherdiv16sf ((__v8sf)(__m256) (V1OLD),	\
+					 (void const *) (ADDR),		\
+					 (__v8di)(__m512i) (INDEX),	\
+					 (__mmask8) (MASK),		\
+					 (int) (SCALE))
 
 #define _mm512_i64gather_pd(INDEX, ADDR, SCALE)				\
   (__m512d) __builtin_ia32_gatherdiv8df ((__v8df)_mm512_undefined_pd(),	\
-					 (void const *)ADDR,		\
-					 (__v8di)(__m512i)INDEX,	\
-					 (__mmask8)0xFF, (int)SCALE)
+					 (void const *) (ADDR),		\
+					 (__v8di)(__m512i) (INDEX),	\
+					 (__mmask8)0xFF, (int) (SCALE))
 
 #define _mm512_mask_i64gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m512d) __builtin_ia32_gatherdiv8df ((__v8df)(__m512d)V1OLD,	\
-					 (void const *)ADDR,		\
-					 (__v8di)(__m512i)INDEX,	\
-					 (__mmask8)MASK, (int)SCALE)
+  (__m512d) __builtin_ia32_gatherdiv8df ((__v8df)(__m512d) (V1OLD),	\
+					 (void const *) (ADDR),		\
+					 (__v8di)(__m512i) (INDEX),	\
+					 (__mmask8) (MASK),		\
+					 (int) (SCALE))
 
 #define _mm512_i32gather_epi32(INDEX, ADDR, SCALE)			\
-  (__m512i) __builtin_ia32_gathersiv16si ((__v16si)_mm512_undefined_epi32 (),	\
-					  (void const *)ADDR,		\
-					  (__v16si)(__m512i)INDEX,	\
-					  (__mmask16)0xFFFF, (int)SCALE)
+  (__m512i) __builtin_ia32_gathersiv16si ((__v16si)_mm512_undefined_epi32 (),\
+					  (void const *) (ADDR),	\
+					  (__v16si)(__m512i) (INDEX),	\
+					  (__mmask16)0xFFFF,		\
+					  (int) (SCALE))
 
 #define _mm512_mask_i32gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m512i) __builtin_ia32_gathersiv16si ((__v16si)(__m512i)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v16si)(__m512i)INDEX,	\
-					  (__mmask16)MASK, (int)SCALE)
+  (__m512i) __builtin_ia32_gathersiv16si ((__v16si)(__m512i) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v16si)(__m512i) (INDEX),	\
+					  (__mmask16) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm512_i32gather_epi64(INDEX, ADDR, SCALE)			\
-  (__m512i) __builtin_ia32_gathersiv8di ((__v8di)_mm512_undefined_epi32 (),	\
-					 (void const *)ADDR,		\
-					 (__v8si)(__m256i)INDEX,	\
-					 (__mmask8)0xFF, (int)SCALE)
+  (__m512i) __builtin_ia32_gathersiv8di ((__v8di)_mm512_undefined_epi32 (),\
+					 (void const *) (ADDR),		\
+					 (__v8si)(__m256i) (INDEX),	\
+					 (__mmask8)0xFF, (int) (SCALE))
 
 #define _mm512_mask_i32gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m512i) __builtin_ia32_gathersiv8di ((__v8di)(__m512i)V1OLD,	\
-					 (void const *)ADDR,		\
-					 (__v8si)(__m256i)INDEX,	\
-					 (__mmask8)MASK, (int)SCALE)
-
-#define _mm512_i64gather_epi32(INDEX, ADDR, SCALE)			  \
-  (__m256i) __builtin_ia32_gatherdiv16si ((__v8si)_mm256_undefined_si256(), \
-					  (void const *)ADDR,		  \
-					  (__v8di)(__m512i)INDEX,	  \
-					  (__mmask8)0xFF, (int)SCALE)
+  (__m512i) __builtin_ia32_gathersiv8di ((__v8di)(__m512i) (V1OLD),	\
+					 (void const *) (ADDR),		\
+					 (__v8si)(__m256i) (INDEX),	\
+					 (__mmask8) (MASK),		\
+					 (int) (SCALE))
+
+#define _mm512_i64gather_epi32(INDEX, ADDR, SCALE)			   \
+  (__m256i) __builtin_ia32_gatherdiv16si ((__v8si)_mm256_undefined_si256(),\
+					  (void const *) (ADDR),	   \
+					  (__v8di)(__m512i) (INDEX),	   \
+					  (__mmask8)0xFF, (int) (SCALE))
 
 #define _mm512_mask_i64gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m256i) __builtin_ia32_gatherdiv16si ((__v8si)(__m256i)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v8di)(__m512i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m256i) __builtin_ia32_gatherdiv16si ((__v8si)(__m256i) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v8di)(__m512i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm512_i64gather_epi64(INDEX, ADDR, SCALE)			\
-  (__m512i) __builtin_ia32_gatherdiv8di ((__v8di)_mm512_undefined_epi32 (),	\
-					 (void const *)ADDR,		\
-					 (__v8di)(__m512i)INDEX,	\
-					 (__mmask8)0xFF, (int)SCALE)
+  (__m512i) __builtin_ia32_gatherdiv8di ((__v8di)_mm512_undefined_epi32 (),\
+					 (void const *) (ADDR),		\
+					 (__v8di)(__m512i) (INDEX),	\
+					 (__mmask8)0xFF, (int) (SCALE))
 
 #define _mm512_mask_i64gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m512i) __builtin_ia32_gatherdiv8di ((__v8di)(__m512i)V1OLD,	\
-					 (void const *)ADDR,		\
-					 (__v8di)(__m512i)INDEX,	\
-					 (__mmask8)MASK, (int)SCALE)
+  (__m512i) __builtin_ia32_gatherdiv8di ((__v8di)(__m512i) (V1OLD),	\
+					 (void const *) (ADDR),		\
+					 (__v8di)(__m512i) (INDEX),	\
+					 (__mmask8) (MASK),		\
+					 (int) (SCALE))
 
 #define _mm512_i32scatter_ps(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv16sf ((void *)ADDR, (__mmask16)0xFFFF,	\
-				 (__v16si)(__m512i)INDEX,		\
-				 (__v16sf)(__m512)V1, (int)SCALE)
+  __builtin_ia32_scattersiv16sf ((void *) (ADDR), (__mmask16)0xFFFF,	\
+				 (__v16si)(__m512i) (INDEX),		\
+				 (__v16sf)(__m512) (V1), (int) (SCALE))
 
 #define _mm512_mask_i32scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scattersiv16sf ((void *)ADDR, (__mmask16)MASK,		\
-				 (__v16si)(__m512i)INDEX,		\
-				 (__v16sf)(__m512)V1, (int)SCALE)
+  __builtin_ia32_scattersiv16sf ((void *) (ADDR), (__mmask16) (MASK),	\
+				 (__v16si)(__m512i) (INDEX),		\
+				 (__v16sf)(__m512) (V1), (int) (SCALE))
 
 #define _mm512_i32scatter_pd(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv8df ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v8si)(__m256i)INDEX,			\
-				(__v8df)(__m512d)V1, (int)SCALE)
+  __builtin_ia32_scattersiv8df ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v8si)(__m256i) (INDEX),		\
+				(__v8df)(__m512d) (V1), (int) (SCALE))
 
 #define _mm512_mask_i32scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scattersiv8df ((void *)ADDR, (__mmask8)MASK,		\
-				(__v8si)(__m256i)INDEX,			\
-				(__v8df)(__m512d)V1, (int)SCALE)
+  __builtin_ia32_scattersiv8df ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v8si)(__m256i) (INDEX),		\
+				(__v8df)(__m512d) (V1), (int) (SCALE))
 
 #define _mm512_i64scatter_ps(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv16sf ((void *)ADDR, (__mmask8)0xFF,		\
-				 (__v8di)(__m512i)INDEX,		\
-				 (__v8sf)(__m256)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv16sf ((void *) (ADDR), (__mmask8)0xFF,	\
+				 (__v8di)(__m512i) (INDEX),		\
+				 (__v8sf)(__m256) (V1), (int) (SCALE))
 
 #define _mm512_mask_i64scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scatterdiv16sf ((void *)ADDR, (__mmask16)MASK,		\
-				 (__v8di)(__m512i)INDEX,		\
-				 (__v8sf)(__m256)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv16sf ((void *) (ADDR), (__mmask16) (MASK),	\
+				 (__v8di)(__m512i) (INDEX),		\
+				 (__v8sf)(__m256) (V1), (int) (SCALE))
 
 #define _mm512_i64scatter_pd(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv8df ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v8di)(__m512i)INDEX,			\
-				(__v8df)(__m512d)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv8df ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v8di)(__m512i) (INDEX),		\
+				(__v8df)(__m512d) (V1), (int) (SCALE))
 
 #define _mm512_mask_i64scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scatterdiv8df ((void *)ADDR, (__mmask8)MASK,		\
-				(__v8di)(__m512i)INDEX,			\
-				(__v8df)(__m512d)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv8df ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v8di)(__m512i) (INDEX),		\
+				(__v8df)(__m512d) (V1), (int) (SCALE))
 
 #define _mm512_i32scatter_epi32(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv16si ((void *)ADDR, (__mmask16)0xFFFF,	\
-				 (__v16si)(__m512i)INDEX,		\
-				 (__v16si)(__m512i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv16si ((void *) (ADDR), (__mmask16)0xFFFF,	\
+				 (__v16si)(__m512i) (INDEX),		\
+				 (__v16si)(__m512i) (V1), (int) (SCALE))
 
 #define _mm512_mask_i32scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)	\
-  __builtin_ia32_scattersiv16si ((void *)ADDR, (__mmask16)MASK,		\
-				 (__v16si)(__m512i)INDEX,		\
-				 (__v16si)(__m512i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv16si ((void *) (ADDR), (__mmask16) (MASK),	\
+				 (__v16si)(__m512i) (INDEX),		\
+				 (__v16si)(__m512i) (V1), (int) (SCALE))
 
 #define _mm512_i32scatter_epi64(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv8di ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v8si)(__m256i)INDEX,			\
-				(__v8di)(__m512i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv8di ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v8si)(__m256i) (INDEX),		\
+				(__v8di)(__m512i) (V1), (int) (SCALE))
 
 #define _mm512_mask_i32scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)	\
-  __builtin_ia32_scattersiv8di ((void *)ADDR, (__mmask8)MASK,		\
-				(__v8si)(__m256i)INDEX,			\
-				(__v8di)(__m512i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv8di ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v8si)(__m256i) (INDEX),		\
+				(__v8di)(__m512i) (V1), (int) (SCALE))
 
 #define _mm512_i64scatter_epi32(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv16si ((void *)ADDR, (__mmask8)0xFF,		\
-				 (__v8di)(__m512i)INDEX,		\
-				 (__v8si)(__m256i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv16si ((void *) (ADDR), (__mmask8)0xFF,	\
+				 (__v8di)(__m512i) (INDEX),		\
+				 (__v8si)(__m256i) (V1), (int) (SCALE))
 
 #define _mm512_mask_i64scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)	\
-  __builtin_ia32_scatterdiv16si ((void *)ADDR, (__mmask8)MASK,		\
-				 (__v8di)(__m512i)INDEX,		\
-				 (__v8si)(__m256i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv16si ((void *) (ADDR), (__mmask8) (MASK),	\
+				 (__v8di)(__m512i) (INDEX),		\
+				 (__v8si)(__m256i) (V1), (int) (SCALE))
 
 #define _mm512_i64scatter_epi64(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv8di ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v8di)(__m512i)INDEX,			\
-				(__v8di)(__m512i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv8di ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v8di)(__m512i) (INDEX),		\
+				(__v8di)(__m512i) (V1), (int) (SCALE))
 
 #define _mm512_mask_i64scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)	\
-  __builtin_ia32_scatterdiv8di ((void *)ADDR, (__mmask8)MASK,		\
-				(__v8di)(__m512i)INDEX,			\
-				(__v8di)(__m512i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv8di ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v8di)(__m512i) (INDEX),		\
+				(__v8di)(__m512i) (V1), (int) (SCALE))
 #endif
 
 extern __inline __m512d
diff --git a/gcc/config/i386/avx512pfintrin.h b/gcc/config/i386/avx512pfintrin.h
index 05dacd881ad..67c7f336752 100644
--- a/gcc/config/i386/avx512pfintrin.h
+++ b/gcc/config/i386/avx512pfintrin.h
@@ -192,68 +192,73 @@ _mm512_mask_prefetch_i64scatter_ps (void *__addr, __mmask16 __mask,
 
 #else
 #define _mm512_prefetch_i32gather_pd(INDEX, ADDR, SCALE, HINT)		     \
-  __builtin_ia32_gatherpfdpd ((__mmask8)0xFF, (__v8si)(__m256i)INDEX,	     \
-			      (void const *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_gatherpfdpd ((__mmask8)0xFF, (__v8si)(__m256i) (INDEX),     \
+			      (void const *) (ADDR), (int) (SCALE),	     \
+			      (int) (HINT))
 
 #define _mm512_prefetch_i32gather_ps(INDEX, ADDR, SCALE, HINT)		     \
-  __builtin_ia32_gatherpfdps ((__mmask16)0xFFFF, (__v16si)(__m512i)INDEX,    \
-			      (void const *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_gatherpfdps ((__mmask16)0xFFFF, (__v16si)(__m512i) (INDEX), \
+			      (void const *) (ADDR), (int) (SCALE),	     \
+			      (int) (HINT))
 
 #define _mm512_mask_prefetch_i32gather_pd(INDEX, MASK, ADDR, SCALE, HINT)    \
-  __builtin_ia32_gatherpfdpd ((__mmask8)MASK, (__v8si)(__m256i)INDEX,	     \
-			      (void const *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_gatherpfdpd ((__mmask8) (MASK), (__v8si)(__m256i) (INDEX),  \
+			      (void const *) (ADDR), (int) (SCALE),	     \
+			      (int) (HINT))
 
 #define _mm512_mask_prefetch_i32gather_ps(INDEX, MASK, ADDR, SCALE, HINT)    \
-  __builtin_ia32_gatherpfdps ((__mmask16)MASK, (__v16si)(__m512i)INDEX,      \
-			      (void const *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_gatherpfdps ((__mmask16) (MASK), (__v16si)(__m512i) (INDEX),\
+			      (void const *) (ADDR), (int) (SCALE),	     \
+			      (int) (HINT))
 
 #define _mm512_prefetch_i64gather_pd(INDEX, ADDR, SCALE, HINT)		     \
-  __builtin_ia32_gatherpfqpd ((__mmask8)0xFF, (__v8di)(__m512i)INDEX,	     \
-			      (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_gatherpfqpd ((__mmask8)0xFF, (__v8di)(__m512i) (INDEX),     \
+			      (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_prefetch_i64gather_ps(INDEX, ADDR, SCALE, HINT)		     \
-  __builtin_ia32_gatherpfqps ((__mmask8)0xFF, (__v8di)(__m512i)INDEX,	     \
-			      (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_gatherpfqps ((__mmask8)0xFF, (__v8di)(__m512i) (INDEX),     \
+			      (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_mask_prefetch_i64gather_pd(INDEX, MASK, ADDR, SCALE, HINT)    \
-  __builtin_ia32_gatherpfqpd ((__mmask8)MASK, (__v8di)(__m512i)INDEX,	     \
-			      (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_gatherpfqpd ((__mmask8) (MASK), (__v8di)(__m512i) (INDEX),  \
+			      (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_mask_prefetch_i64gather_ps(INDEX, MASK, ADDR, SCALE, HINT)    \
-  __builtin_ia32_gatherpfqps ((__mmask8)MASK, (__v8di)(__m512i)INDEX,	     \
-			      (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_gatherpfqps ((__mmask8) (MASK), (__v8di)(__m512i) (INDEX),  \
+			      (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_prefetch_i32scatter_pd(ADDR, INDEX, SCALE, HINT)              \
-  __builtin_ia32_scatterpfdpd ((__mmask8)0xFF, (__v8si)(__m256i)INDEX,       \
-			       (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_scatterpfdpd ((__mmask8)0xFF, (__v8si)(__m256i) (INDEX),    \
+			       (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_prefetch_i32scatter_ps(ADDR, INDEX, SCALE, HINT)              \
-  __builtin_ia32_scatterpfdps ((__mmask16)0xFFFF, (__v16si)(__m512i)INDEX,   \
-			       (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_scatterpfdps ((__mmask16)0xFFFF, (__v16si)(__m512i) (INDEX),\
+			       (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_mask_prefetch_i32scatter_pd(ADDR, MASK, INDEX, SCALE, HINT)   \
-  __builtin_ia32_scatterpfdpd ((__mmask8)MASK, (__v8si)(__m256i)INDEX,       \
-			       (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_scatterpfdpd ((__mmask8) (MASK), (__v8si)(__m256i) (INDEX), \
+			       (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_mask_prefetch_i32scatter_ps(ADDR, MASK, INDEX, SCALE, HINT)   \
-  __builtin_ia32_scatterpfdps ((__mmask16)MASK, (__v16si)(__m512i)INDEX,     \
-			       (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_scatterpfdps ((__mmask16) (MASK),			     \
+			       (__v16si)(__m512i) (INDEX),		     \
+			       (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_prefetch_i64scatter_pd(ADDR, INDEX, SCALE, HINT)              \
-  __builtin_ia32_scatterpfqpd ((__mmask8)0xFF, (__v8di)(__m512i)INDEX,	     \
-			       (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_scatterpfqpd ((__mmask8)0xFF, (__v8di)(__m512i) (INDEX),    \
+			       (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_prefetch_i64scatter_ps(ADDR, INDEX, SCALE, HINT)              \
-  __builtin_ia32_scatterpfqps ((__mmask8)0xFF, (__v8di)(__m512i)INDEX,	     \
-			       (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_scatterpfqps ((__mmask8)0xFF, (__v8di)(__m512i) (INDEX),    \
+			       (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_mask_prefetch_i64scatter_pd(ADDR, MASK, INDEX, SCALE, HINT)   \
-  __builtin_ia32_scatterpfqpd ((__mmask8)MASK, (__v8di)(__m512i)INDEX,	     \
-			       (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_scatterpfqpd ((__mmask8) (MASK), (__v8di)(__m512i) (INDEX), \
+			       (void *) (ADDR), (int) (SCALE), (int) (HINT))
 
 #define _mm512_mask_prefetch_i64scatter_ps(ADDR, MASK, INDEX, SCALE, HINT)   \
-  __builtin_ia32_scatterpfqps ((__mmask8)MASK, (__v8di)(__m512i)INDEX,	     \
-			       (void *)ADDR, (int)SCALE, (int)HINT)
+  __builtin_ia32_scatterpfqps ((__mmask8) (MASK), (__v8di)(__m512i) (INDEX), \
+			       (void *) (ADDR), (int) (SCALE), (int) (HINT))
 #endif
 
 #ifdef __DISABLE_AVX512PF__
diff --git a/gcc/config/i386/avx512vlintrin.h b/gcc/config/i386/avx512vlintrin.h
index 68b5537845b..58ac1f9d9bd 100644
--- a/gcc/config/i386/avx512vlintrin.h
+++ b/gcc/config/i386/avx512vlintrin.h
@@ -12924,260 +12924,276 @@ _mm256_permutex_pd (__m256d __X, const int __M)
                                           (__mmask8)(U)))
 
 #define _mm256_mmask_i32gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m256) __builtin_ia32_gather3siv8sf ((__v8sf)(__m256)V1OLD,		\
-					 (void const *)ADDR,		\
-					 (__v8si)(__m256i)INDEX,	\
-					 (__mmask8)MASK, (int)SCALE)
+  (__m256) __builtin_ia32_gather3siv8sf ((__v8sf)(__m256) (V1OLD),	\
+					 (void const *) (ADDR),		\
+					 (__v8si)(__m256i) (INDEX),	\
+					 (__mmask8) (MASK),		\
+					 (int) (SCALE))
 
 #define _mm_mmask_i32gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)		\
-  (__m128) __builtin_ia32_gather3siv4sf ((__v4sf)(__m128)V1OLD,		\
-					 (void const *)ADDR,		\
-					 (__v4si)(__m128i)INDEX,	\
-					 (__mmask8)MASK, (int)SCALE)
+  (__m128) __builtin_ia32_gather3siv4sf ((__v4sf)(__m128) (V1OLD),	\
+					 (void const *) (ADDR),		\
+					 (__v4si)(__m128i) (INDEX),	\
+					 (__mmask8) (MASK),		\
+					 (int) (SCALE))
 
 #define _mm256_mmask_i32gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m256d) __builtin_ia32_gather3siv4df ((__v4df)(__m256d)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v4si)(__m128i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m256d) __builtin_ia32_gather3siv4df ((__v4df)(__m256d) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v4si)(__m128i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm_mmask_i32gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)		\
-  (__m128d) __builtin_ia32_gather3siv2df ((__v2df)(__m128d)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v4si)(__m128i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m128d) __builtin_ia32_gather3siv2df ((__v2df)(__m128d) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v4si)(__m128i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm256_mmask_i64gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m128) __builtin_ia32_gather3div8sf ((__v4sf)(__m128)V1OLD,		\
-					 (void const *)ADDR,		\
-					 (__v4di)(__m256i)INDEX,	\
-					 (__mmask8)MASK, (int)SCALE)
+  (__m128) __builtin_ia32_gather3div8sf ((__v4sf)(__m128) (V1OLD),	\
+					 (void const *) (ADDR),		\
+					 (__v4di)(__m256i) (INDEX),	\
+					 (__mmask8) (MASK),		\
+					 (int) (SCALE))
 
 #define _mm_mmask_i64gather_ps(V1OLD, MASK, INDEX, ADDR, SCALE)		\
-  (__m128) __builtin_ia32_gather3div4sf ((__v4sf)(__m128)V1OLD,		\
-					 (void const *)ADDR,		\
-					 (__v2di)(__m128i)INDEX,	\
-					 (__mmask8)MASK, (int)SCALE)
+  (__m128) __builtin_ia32_gather3div4sf ((__v4sf)(__m128) (V1OLD),	\
+					 (void const *) (ADDR),		\
+					 (__v2di)(__m128i) (INDEX),	\
+					 (__mmask8) (MASK),		\
+					 (int) (SCALE))
 
 #define _mm256_mmask_i64gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m256d) __builtin_ia32_gather3div4df ((__v4df)(__m256d)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v4di)(__m256i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m256d) __builtin_ia32_gather3div4df ((__v4df)(__m256d) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v4di)(__m256i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm_mmask_i64gather_pd(V1OLD, MASK, INDEX, ADDR, SCALE)		\
-  (__m128d) __builtin_ia32_gather3div2df ((__v2df)(__m128d)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v2di)(__m128i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m128d) __builtin_ia32_gather3div2df ((__v2df)(__m128d) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v2di)(__m128i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm256_mmask_i32gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m256i) __builtin_ia32_gather3siv8si ((__v8si)(__m256i)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v8si)(__m256i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m256i) __builtin_ia32_gather3siv8si ((__v8si)(__m256i) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v8si)(__m256i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm_mmask_i32gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m128i) __builtin_ia32_gather3siv4si ((__v4si)(__m128i)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v4si)(__m128i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m128i) __builtin_ia32_gather3siv4si ((__v4si)(__m128i) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v4si)(__m128i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm256_mmask_i32gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m256i) __builtin_ia32_gather3siv4di ((__v4di)(__m256i)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v4si)(__m128i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m256i) __builtin_ia32_gather3siv4di ((__v4di)(__m256i) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v4si)(__m128i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm_mmask_i32gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m128i) __builtin_ia32_gather3siv2di ((__v2di)(__m128i)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v4si)(__m128i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m128i) __builtin_ia32_gather3siv2di ((__v2di)(__m128i) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v4si)(__m128i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm256_mmask_i64gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m128i) __builtin_ia32_gather3div8si ((__v4si)(__m128i)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v4di)(__m256i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m128i) __builtin_ia32_gather3div8si ((__v4si)(__m128i) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v4di)(__m256i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm_mmask_i64gather_epi32(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m128i) __builtin_ia32_gather3div4si ((__v4si)(__m128i)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v2di)(__m128i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m128i) __builtin_ia32_gather3div4si ((__v4si)(__m128i) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v2di)(__m128i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm256_mmask_i64gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m256i) __builtin_ia32_gather3div4di ((__v4di)(__m256i)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v4di)(__m256i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m256i) __builtin_ia32_gather3div4di ((__v4di)(__m256i) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v4di)(__m256i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm_mmask_i64gather_epi64(V1OLD, MASK, INDEX, ADDR, SCALE)	\
-  (__m128i) __builtin_ia32_gather3div2di ((__v2di)(__m128i)V1OLD,	\
-					  (void const *)ADDR,		\
-					  (__v2di)(__m128i)INDEX,	\
-					  (__mmask8)MASK, (int)SCALE)
+  (__m128i) __builtin_ia32_gather3div2di ((__v2di)(__m128i) (V1OLD),	\
+					  (void const *) (ADDR),	\
+					  (__v2di)(__m128i) (INDEX),	\
+					  (__mmask8) (MASK),		\
+					  (int) (SCALE))
 
 #define _mm256_i32scatter_ps(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv8sf ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v8si)(__m256i)INDEX,			\
-				(__v8sf)(__m256)V1, (int)SCALE)
+  __builtin_ia32_scattersiv8sf ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v8si)(__m256i) (INDEX),		\
+				(__v8sf)(__m256) (V1), (int) (SCALE))
 
 #define _mm256_mask_i32scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scattersiv8sf ((void *)ADDR, (__mmask8)MASK,		\
-				(__v8si)(__m256i)INDEX,			\
-				(__v8sf)(__m256)V1, (int)SCALE)
+  __builtin_ia32_scattersiv8sf ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v8si)(__m256i) (INDEX),		\
+				(__v8sf)(__m256) (V1), (int) (SCALE))
 
 #define _mm_i32scatter_ps(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv4sf ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v4sf)(__m128)V1, (int)SCALE)
+  __builtin_ia32_scattersiv4sf ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v4sf)(__m128) (V1), (int) (SCALE))
 
 #define _mm_mask_i32scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scattersiv4sf ((void *)ADDR, (__mmask8)MASK,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v4sf)(__m128)V1, (int)SCALE)
+  __builtin_ia32_scattersiv4sf ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v4sf)(__m128) (V1), (int) (SCALE))
 
 #define _mm256_i32scatter_pd(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv4df ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v4df)(__m256d)V1, (int)SCALE)
+  __builtin_ia32_scattersiv4df ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v4df)(__m256d) (V1), (int) (SCALE))
 
 #define _mm256_mask_i32scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scattersiv4df ((void *)ADDR, (__mmask8)MASK,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v4df)(__m256d)V1, (int)SCALE)
+  __builtin_ia32_scattersiv4df ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v4df)(__m256d) (V1), (int) (SCALE))
 
 #define _mm_i32scatter_pd(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv2df ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v2df)(__m128d)V1, (int)SCALE)
+  __builtin_ia32_scattersiv2df ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v2df)(__m128d) (V1), (int) (SCALE))
 
 #define _mm_mask_i32scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scattersiv2df ((void *)ADDR, (__mmask8)MASK,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v2df)(__m128d)V1, (int)SCALE)
+  __builtin_ia32_scattersiv2df ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v2df)(__m128d) (V1), (int) (SCALE))
 
 #define _mm256_i64scatter_ps(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv8sf ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v4di)(__m256i)INDEX,			\
-				(__v4sf)(__m128)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv8sf ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v4di)(__m256i) (INDEX),		\
+				(__v4sf)(__m128) (V1), (int) (SCALE))
 
 #define _mm256_mask_i64scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scatterdiv8sf ((void *)ADDR, (__mmask8)MASK,		\
-				(__v4di)(__m256i)INDEX,			\
-				(__v4sf)(__m128)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv8sf ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v4di)(__m256i) (INDEX),		\
+				(__v4sf)(__m128) (V1), (int) (SCALE))
 
 #define _mm_i64scatter_ps(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv4sf ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v2di)(__m128i)INDEX,			\
-				(__v4sf)(__m128)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv4sf ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v2di)(__m128i) (INDEX),		\
+				(__v4sf)(__m128) (V1), (int) (SCALE))
 
 #define _mm_mask_i64scatter_ps(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scatterdiv4sf ((void *)ADDR, (__mmask8)MASK,		\
-				(__v2di)(__m128i)INDEX,			\
-				(__v4sf)(__m128)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv4sf ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v2di)(__m128i) (INDEX),		\
+				(__v4sf)(__m128) (V1), (int) (SCALE))
 
 #define _mm256_i64scatter_pd(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv4df ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v4di)(__m256i)INDEX,			\
-				(__v4df)(__m256d)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv4df ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v4di)(__m256i) (INDEX),		\
+				(__v4df)(__m256d) (V1), (int) (SCALE))
 
 #define _mm256_mask_i64scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scatterdiv4df ((void *)ADDR, (__mmask8)MASK,		\
-				(__v4di)(__m256i)INDEX,			\
-				(__v4df)(__m256d)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv4df ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v4di)(__m256i) (INDEX),		\
+				(__v4df)(__m256d) (V1), (int) (SCALE))
 
 #define _mm_i64scatter_pd(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv2df ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v2di)(__m128i)INDEX,			\
-				(__v2df)(__m128d)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv2df ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v2di)(__m128i) (INDEX),		\
+				(__v2df)(__m128d) (V1), (int) (SCALE))
 
 #define _mm_mask_i64scatter_pd(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scatterdiv2df ((void *)ADDR, (__mmask8)MASK,		\
-				(__v2di)(__m128i)INDEX,			\
-				(__v2df)(__m128d)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv2df ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v2di)(__m128i) (INDEX),		\
+				(__v2df)(__m128d) (V1), (int) (SCALE))
 
 #define _mm256_i32scatter_epi32(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv8si ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v8si)(__m256i)INDEX,			\
-				(__v8si)(__m256i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv8si ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v8si)(__m256i) (INDEX),		\
+				(__v8si)(__m256i) (V1), (int) (SCALE))
 
 #define _mm256_mask_i32scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)	\
-  __builtin_ia32_scattersiv8si ((void *)ADDR, (__mmask8)MASK,		\
-				(__v8si)(__m256i)INDEX,			\
-				(__v8si)(__m256i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv8si ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v8si)(__m256i) (INDEX),		\
+				(__v8si)(__m256i) (V1), (int) (SCALE))
 
 #define _mm_i32scatter_epi32(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv4si ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v4si)(__m128i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv4si ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v4si)(__m128i) (V1), (int) (SCALE))
 
 #define _mm_mask_i32scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scattersiv4si ((void *)ADDR, (__mmask8)MASK,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v4si)(__m128i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv4si ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v4si)(__m128i) (V1), (int) (SCALE))
 
 #define _mm256_i32scatter_epi64(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv4di ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v4di)(__m256i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv4di ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v4di)(__m256i) (V1), (int) (SCALE))
 
 #define _mm256_mask_i32scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)	\
-  __builtin_ia32_scattersiv4di ((void *)ADDR, (__mmask8)MASK,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v4di)(__m256i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv4di ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v4di)(__m256i) (V1), (int) (SCALE))
 
 #define _mm_i32scatter_epi64(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scattersiv2di ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v2di)(__m128i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv2di ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v2di)(__m128i) (V1), (int) (SCALE))
 
 #define _mm_mask_i32scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scattersiv2di ((void *)ADDR, (__mmask8)MASK,		\
-				(__v4si)(__m128i)INDEX,			\
-				(__v2di)(__m128i)V1, (int)SCALE)
+  __builtin_ia32_scattersiv2di ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v4si)(__m128i) (INDEX),		\
+				(__v2di)(__m128i) (V1), (int) (SCALE))
 
 #define _mm256_i64scatter_epi32(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv8si ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v4di)(__m256i)INDEX,			\
-				(__v4si)(__m128i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv8si ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v4di)(__m256i) (INDEX),		\
+				(__v4si)(__m128i) (V1), (int) (SCALE))
 
 #define _mm256_mask_i64scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)	\
-  __builtin_ia32_scatterdiv8si ((void *)ADDR, (__mmask8)MASK,		\
-				(__v4di)(__m256i)INDEX,			\
-				(__v4si)(__m128i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv8si ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v4di)(__m256i) (INDEX),		\
+				(__v4si)(__m128i) (V1), (int) (SCALE))
 
 #define _mm_i64scatter_epi32(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv4si ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v2di)(__m128i)INDEX,			\
-				(__v4si)(__m128i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv4si ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v2di)(__m128i) (INDEX),		\
+				(__v4si)(__m128i) (V1), (int) (SCALE))
 
 #define _mm_mask_i64scatter_epi32(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scatterdiv4si ((void *)ADDR, (__mmask8)MASK,		\
-				(__v2di)(__m128i)INDEX,			\
-				(__v4si)(__m128i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv4si ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v2di)(__m128i) (INDEX),		\
+				(__v4si)(__m128i) (V1), (int) (SCALE))
 
 #define _mm256_i64scatter_epi64(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv4di ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v4di)(__m256i)INDEX,			\
-				(__v4di)(__m256i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv4di ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v4di)(__m256i) (INDEX),		\
+				(__v4di)(__m256i) (V1), (int) (SCALE))
 
 #define _mm256_mask_i64scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)	\
-  __builtin_ia32_scatterdiv4di ((void *)ADDR, (__mmask8)MASK,		\
-				(__v4di)(__m256i)INDEX,			\
-				(__v4di)(__m256i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv4di ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v4di)(__m256i) (INDEX),		\
+				(__v4di)(__m256i) (V1), (int) (SCALE))
 
 #define _mm_i64scatter_epi64(ADDR, INDEX, V1, SCALE)			\
-  __builtin_ia32_scatterdiv2di ((void *)ADDR, (__mmask8)0xFF,		\
-				(__v2di)(__m128i)INDEX,			\
-				(__v2di)(__m128i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv2di ((void *) (ADDR), (__mmask8)0xFF,	\
+				(__v2di)(__m128i) (INDEX),		\
+				(__v2di)(__m128i) (V1), (int) (SCALE))
 
 #define _mm_mask_i64scatter_epi64(ADDR, MASK, INDEX, V1, SCALE)		\
-  __builtin_ia32_scatterdiv2di ((void *)ADDR, (__mmask8)MASK,		\
-				(__v2di)(__m128i)INDEX,			\
-				(__v2di)(__m128i)V1, (int)SCALE)
+  __builtin_ia32_scatterdiv2di ((void *) (ADDR), (__mmask8) (MASK),	\
+				(__v2di)(__m128i) (INDEX),		\
+				(__v2di)(__m128i) (V1), (int) (SCALE))
 
 #define _mm256_mask_shuffle_epi32(W, U, X, C)                                       \
   ((__m256i)  __builtin_ia32_pshufd256_mask ((__v8si)(__m256i)(X), (int)(C),        \

commit a0159c30c19a1271f6b6ba6bc489c2c1c59954a3
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Apr 29 17:31:26 2020 +0200

    x86: Fix -O0 remaining intrinsic macros [PR94832]
    
    A few other macros seem to suffer from the same issue.  What I've done was:
    cat gcc/config/i386/*intrin.h | sed -e ':x /\\$/ { N; s/\\\n//g ; bx }' \
    | grep '^[[:blank:]]*#[[:blank:]]*define[[:blank:]].*(' | sed 's/[      ]\+/ /g' \
    > /tmp/macros
    and then looking for regexps:
    )[a-zA-Z]
    ) [a-zA-Z]
    [a-zA-Z][-+*/%]
    [a-zA-Z] [-+*/%]
    [-+*/%][a-zA-Z]
    [-+*/%] [a-zA-Z]
    in the resulting file.
    
    2020-04-29  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94832
            * config/i386/avx512bwintrin.h (_mm512_alignr_epi8,
            _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands
            used in casts into parens.
            * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph,
            _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph,
            _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph,
            _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask,
            _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask,
            _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask,
            _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise.
            * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8,
            _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8,
            _mm256_mask_cmp_epu8_mask): Likewise.
            * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph,
            _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise.
            * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise.
            * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise.
    
    (cherry picked from commit 0c8217b16f307c3eedce8f22354714938613f701)

diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h
index 24ad5f1e2af..d168ee5c921 100644
--- a/gcc/config/i386/avx512bwintrin.h
+++ b/gcc/config/i386/avx512bwintrin.h
@@ -3128,16 +3128,16 @@ _mm512_bsrli_epi128 (__m512i __A, const int __N)
 #define _mm512_alignr_epi8(X, Y, N)						    \
   ((__m512i) __builtin_ia32_palignr512 ((__v8di)(__m512i)(X),			    \
 					(__v8di)(__m512i)(Y),			    \
-					(int)(N * 8)))
+					(int)((N) * 8)))
 
 #define _mm512_mask_alignr_epi8(W, U, X, Y, N)					    \
   ((__m512i) __builtin_ia32_palignr512_mask ((__v8di)(__m512i)(X),		    \
-					    (__v8di)(__m512i)(Y), (int)(N * 8),	    \
+					    (__v8di)(__m512i)(Y), (int)((N) * 8),   \
 					    (__v8di)(__m512i)(W), (__mmask64)(U)))
 
 #define _mm512_maskz_alignr_epi8(U, X, Y, N)					    \
   ((__m512i) __builtin_ia32_palignr512_mask ((__v8di)(__m512i)(X),		    \
-					     (__v8di)(__m512i)(Y), (int)(N * 8),    \
+					     (__v8di)(__m512i)(Y), (int)((N) * 8),  \
 					     (__v8di)(__m512i)			    \
 					     _mm512_setzero_si512 (),		    \
 					     (__mmask64)(U)))
diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h
index f739c1795cc..142c0ee2350 100644
--- a/gcc/config/i386/avx512fintrin.h
+++ b/gcc/config/i386/avx512fintrin.h
@@ -8394,22 +8394,22 @@ _mm512_maskz_cvtps_ph (__mmask16 __W, __m512 __A, const int __I)
     (__m512)__builtin_ia32_vcvtph2ps512_mask((__v16hi)(A), (__v16sf)_mm512_setzero_ps(), U, B)
 
 #define _mm512_cvt_roundps_ph(A, I)						 \
-  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) A, (int) (I),\
+  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) (A), (int) (I),\
     (__v16hi)_mm256_undefined_si256 (), -1))
 #define _mm512_cvtps_ph(A, I)						 \
-  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) A, (int) (I),\
+  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) (A), (int) (I),\
     (__v16hi)_mm256_undefined_si256 (), -1))
 #define _mm512_mask_cvt_roundps_ph(U, W, A, I)				 \
-  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) A, (int) (I),\
+  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) (A), (int) (I),\
     (__v16hi)(__m256i)(U), (__mmask16) (W)))
 #define _mm512_mask_cvtps_ph(U, W, A, I)				 \
-  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) A, (int) (I),\
+  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) (A), (int) (I),\
     (__v16hi)(__m256i)(U), (__mmask16) (W)))
 #define _mm512_maskz_cvt_roundps_ph(W, A, I)					 \
-  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) A, (int) (I),\
+  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) (A), (int) (I),\
     (__v16hi)_mm256_setzero_si256 (), (__mmask16) (W)))
 #define _mm512_maskz_cvtps_ph(W, A, I)					 \
-  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) A, (int) (I),\
+  ((__m256i) __builtin_ia32_vcvtps2ph512_mask ((__v16sf)(__m512) (A), (int) (I),\
     (__v16hi)_mm256_setzero_si256 (), (__mmask16) (W)))
 #endif
 
@@ -9798,32 +9798,32 @@ _mm_mask_cmp_round_ss_mask (__mmask8 __M, __m128 __X, __m128 __Y,
 #define _mm512_mask_cmp_epi64_mask(M, X, Y, P)				\
   ((__mmask8) __builtin_ia32_cmpq512_mask ((__v8di)(__m512i)(X),	\
 					   (__v8di)(__m512i)(Y), (int)(P),\
-					   (__mmask8)M))
+					   (__mmask8)(M)))
 
 #define _mm512_mask_cmp_epi32_mask(M, X, Y, P)				\
   ((__mmask16) __builtin_ia32_cmpd512_mask ((__v16si)(__m512i)(X),	\
 					    (__v16si)(__m512i)(Y), (int)(P), \
-					    (__mmask16)M))
+					    (__mmask16)(M)))
 
 #define _mm512_mask_cmp_epu64_mask(M, X, Y, P)				\
   ((__mmask8) __builtin_ia32_ucmpq512_mask ((__v8di)(__m512i)(X),	\
 					    (__v8di)(__m512i)(Y), (int)(P),\
-					    (__mmask8)M))
+					    (__mmask8)(M)))
 
 #define _mm512_mask_cmp_epu32_mask(M, X, Y, P)				\
   ((__mmask16) __builtin_ia32_ucmpd512_mask ((__v16si)(__m512i)(X),	\
 					     (__v16si)(__m512i)(Y), (int)(P), \
-					     (__mmask16)M))
+					     (__mmask16)(M)))
 
 #define _mm512_mask_cmp_round_pd_mask(M, X, Y, P, R)			\
   ((__mmask8) __builtin_ia32_cmppd512_mask ((__v8df)(__m512d)(X),	\
 					    (__v8df)(__m512d)(Y), (int)(P),\
-					    (__mmask8)M, R))
+					    (__mmask8)(M), R))
 
 #define _mm512_mask_cmp_round_ps_mask(M, X, Y, P, R)			\
   ((__mmask16) __builtin_ia32_cmpps512_mask ((__v16sf)(__m512)(X),	\
 					     (__v16sf)(__m512)(Y), (int)(P),\
-					     (__mmask16)M, R))
+					     (__mmask16)(M), R))
 
 #define _mm_cmp_round_sd_mask(X, Y, P, R)				\
   ((__mmask8) __builtin_ia32_cmpsd_mask ((__v2df)(__m128d)(X),		\
@@ -14508,12 +14508,12 @@ _mm_mask_cmp_ss_mask (__mmask8 __M, __m128 __X, __m128 __Y, const int __P)
 #define _mm512_mask_cmp_pd_mask(M, X, Y, P)					\
   ((__mmask8) __builtin_ia32_cmppd512_mask ((__v8df)(__m512d)(X),	\
 					    (__v8df)(__m512d)(Y), (int)(P),\
-					    (__mmask8)M, _MM_FROUND_CUR_DIRECTION))
+					    (__mmask8)(M), _MM_FROUND_CUR_DIRECTION))
 
 #define _mm512_mask_cmp_ps_mask(M, X, Y, P)					\
   ((__mmask16) __builtin_ia32_cmpps512_mask ((__v16sf)(__m512)(X),	\
 					     (__v16sf)(__m512)(Y), (int)(P),\
-					     (__mmask16)M,_MM_FROUND_CUR_DIRECTION))
+					     (__mmask16)(M),_MM_FROUND_CUR_DIRECTION))
 
 #define _mm_cmp_sd_mask(X, Y, P)					\
   ((__mmask8) __builtin_ia32_cmpsd_mask ((__v2df)(__m128d)(X),		\
diff --git a/gcc/config/i386/avx512vlbwintrin.h b/gcc/config/i386/avx512vlbwintrin.h
index 02afce15686..0b2767f25a1 100644
--- a/gcc/config/i386/avx512vlbwintrin.h
+++ b/gcc/config/i386/avx512vlbwintrin.h
@@ -1787,7 +1787,7 @@ _mm_maskz_slli_epi16 (__mmask8 __U, __m128i __A, int __B)
 #else
 #define _mm256_mask_alignr_epi8(W, U, X, Y, N)					    \
   ((__m256i) __builtin_ia32_palignr256_mask ((__v4di)(__m256i)(X),		    \
-					    (__v4di)(__m256i)(Y), (int)(N * 8),	    \
+					    (__v4di)(__m256i)(Y), (int)((N) * 8),   \
 					    (__v4di)(__m256i)(X), (__mmask32)(U)))
 
 #define _mm256_mask_srli_epi16(W, U, A, B)                              \
@@ -1864,18 +1864,18 @@ _mm_maskz_slli_epi16 (__mmask8 __U, __m128i __A, int __B)
 
 #define _mm256_maskz_alignr_epi8(U, X, Y, N)					    \
   ((__m256i) __builtin_ia32_palignr256_mask ((__v4di)(__m256i)(X),		    \
-					    (__v4di)(__m256i)(Y), (int)(N * 8),	    \
+					    (__v4di)(__m256i)(Y), (int)((N) * 8),   \
 					    (__v4di)(__m256i)_mm256_setzero_si256 (),   \
 					    (__mmask32)(U)))
 
 #define _mm_mask_alignr_epi8(W, U, X, Y, N)					    \
   ((__m128i) __builtin_ia32_palignr128_mask ((__v2di)(__m128i)(X),		    \
-					    (__v2di)(__m128i)(Y), (int)(N * 8),	    \
+					    (__v2di)(__m128i)(Y), (int)((N) * 8),   \
 					    (__v2di)(__m128i)(X), (__mmask16)(U)))
 
 #define _mm_maskz_alignr_epi8(U, X, Y, N)					    \
   ((__m128i) __builtin_ia32_palignr128_mask ((__v2di)(__m128i)(X),		    \
-					    (__v2di)(__m128i)(Y), (int)(N * 8),	    \
+					    (__v2di)(__m128i)(Y), (int)((N) * 8),   \
 					    (__v2di)(__m128i)_mm_setzero_si128 (),  \
 					    (__mmask16)(U)))
 
@@ -2033,7 +2033,7 @@ _mm_maskz_slli_epi16 (__mmask8 __U, __m128i __A, int __B)
 #define _mm256_mask_cmp_epu8_mask(M, X, Y, P)				\
   ((__mmask32) __builtin_ia32_ucmpb256_mask ((__v32qi)(__m256i)(X),	\
 					    (__v32qi)(__m256i)(Y), (int)(P),\
-					    (__mmask32)M))
+					    (__mmask32)(M)))
 #endif
 
 extern __inline __mmask32
diff --git a/gcc/config/i386/avx512vlintrin.h b/gcc/config/i386/avx512vlintrin.h
index 58ac1f9d9bd..008e077f5e5 100644
--- a/gcc/config/i386/avx512vlintrin.h
+++ b/gcc/config/i386/avx512vlintrin.h
@@ -13390,19 +13390,19 @@ _mm256_permutex_pd (__m256d __X, const int __M)
         (__mmask8)(U)))
 
 #define _mm_mask_cvtps_ph(W, U, A, I)						\
-  ((__m128i) __builtin_ia32_vcvtps2ph_mask ((__v4sf)(__m128) A, (int) (I),      \
+  ((__m128i) __builtin_ia32_vcvtps2ph_mask ((__v4sf)(__m128) (A), (int) (I),	\
       (__v8hi)(__m128i) (W), (__mmask8) (U)))
 
 #define _mm_maskz_cvtps_ph(U, A, I)						\
-  ((__m128i) __builtin_ia32_vcvtps2ph_mask ((__v4sf)(__m128) A, (int) (I),      \
+  ((__m128i) __builtin_ia32_vcvtps2ph_mask ((__v4sf)(__m128) (A), (int) (I),	\
       (__v8hi)(__m128i) _mm_setzero_si128 (), (__mmask8) (U)))
 
 #define _mm256_mask_cvtps_ph(W, U, A, I)					\
-  ((__m128i) __builtin_ia32_vcvtps2ph256_mask ((__v8sf)(__m256) A, (int) (I),	\
+  ((__m128i) __builtin_ia32_vcvtps2ph256_mask ((__v8sf)(__m256) (A), (int) (I),	\
       (__v8hi)(__m128i) (W), (__mmask8) (U)))
 
 #define _mm256_maskz_cvtps_ph(U, A, I)						\
-  ((__m128i) __builtin_ia32_vcvtps2ph256_mask ((__v8sf)(__m256) A, (int) (I),   \
+  ((__m128i) __builtin_ia32_vcvtps2ph256_mask ((__v8sf)(__m256) (A), (int) (I),	\
       (__v8hi)(__m128i) _mm_setzero_si128 (), (__mmask8) (U)))
 
 #define _mm256_mask_srai_epi32(W, U, A, B)				\
diff --git a/gcc/config/i386/f16cintrin.h b/gcc/config/i386/f16cintrin.h
index 5c0490ccc09..c14be108dc3 100644
--- a/gcc/config/i386/f16cintrin.h
+++ b/gcc/config/i386/f16cintrin.h
@@ -84,10 +84,10 @@ _mm256_cvtps_ph (__m256 __A, const int __I)
     }))
 
 #define _mm_cvtps_ph(A, I) \
-  ((__m128i) __builtin_ia32_vcvtps2ph ((__v4sf)(__m128) A, (int) (I)))
+  ((__m128i) __builtin_ia32_vcvtps2ph ((__v4sf)(__m128) (A), (int) (I)))
 
 #define _mm256_cvtps_ph(A, I) \
-  ((__m128i) __builtin_ia32_vcvtps2ph256 ((__v8sf)(__m256) A, (int) (I)))
+  ((__m128i) __builtin_ia32_vcvtps2ph256 ((__v8sf)(__m256) (A), (int) (I)))
 #endif /* __OPTIMIZE */
 
 #ifdef __DISABLE_F16C__
diff --git a/gcc/config/i386/shaintrin.h b/gcc/config/i386/shaintrin.h
index 970d5b598ed..eda9f0130ae 100644
--- a/gcc/config/i386/shaintrin.h
+++ b/gcc/config/i386/shaintrin.h
@@ -64,8 +64,8 @@ _mm_sha1rnds4_epu32 (__m128i __A, __m128i __B, const int __I)
 }
 #else
 #define _mm_sha1rnds4_epu32(A, B, I)				    \
-  ((__m128i) __builtin_ia32_sha1rnds4 ((__v4si)(__m128i)A,	    \
-				       (__v4si)(__m128i)B, (int)I))
+  ((__m128i) __builtin_ia32_sha1rnds4 ((__v4si)(__m128i)(A),	    \
+				       (__v4si)(__m128i)(B), (int)(I)))
 #endif
 
 extern __inline __m128i

commit e5f9acf964cd7956359d1cbbbd3670545ebfd714
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat May 2 12:09:04 2020 +0200

    tilegx: Unbreak build
    
    ../../gcc/config/tilegx/tilegx.md:4109:1: ambiguous attribute 'n'; could be '1' (via 'I124MODE:n') or '4' (via 'I48MODE:n')
    ../../gcc/config/tilegx/tilegx.md:4109:1: ambiguous attribute 'n'; could be '1' (via 'I124MODE:n') or '' (via 'I48MODE:n')
    ../../gcc/config/tilegx/tilegx.md:4109:1: ambiguous attribute 'n'; could be '2' (via 'I124MODE:n') or '4' (via 'I48MODE:n')
    ../../gcc/config/tilegx/tilegx.md:4109:1: ambiguous attribute 'n'; could be '2' (via 'I124MODE:n') or '' (via 'I48MODE:n')
    ../../gcc/config/tilegx/tilegx.md:4109:1: ambiguous attribute 'n'; could be '4' (via 'I124MODE:n') or '' (via 'I48MODE:n')
    
    The insn name already uses <I124MODE:n> explicitly, just the preparation
    stmts don't, and as it creates a I124MODE lowpart subreg of a word mode
    register, <I124MODE:n> seems obviously correct.
    
    2020-05-02  Jakub Jelinek  <jakub@redhat.com>
    
            * config/tilegx/tilegx.md
            (insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>): Use <I124MODE:n>
            rather than just <n>.
    
    (cherry picked from commit 0118d0397f94c307b76aa14abec99347a93da621)

diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md
index 17af2e76929..3de5d7bb363 100644
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -4110,7 +4110,7 @@
   operands[1] = simplify_gen_subreg (<I124MODE:MODE>mode, operands[1],
 				     DImode,
 				     BYTES_BIG_ENDIAN
-				     ? UNITS_PER_WORD - <n> : 0);
+				     ? UNITS_PER_WORD - <I124MODE:n> : 0);
 })
 
 (define_insn "*insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>"

commit b79f3e1e67ca0c5e14b677e3fc847a3c79881b5f
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Apr 30 21:48:30 2020 +0200

    c: Fix ICE with _Atomic side-effect in nested fn param decls [PR94842]
    
    If there are _Atomic side-effects in the parameter declarations
    of non-nested function, when they are parsed, current_function_decl is
    NULL, the create_artificial_label created labels during build_atomic* are
    then adjusted by store_parm_decls through set_labels_context_r callback.
    Unfortunately, if such thing happens in nested function parameter
    declarations, while those decls are parsed current_function_decl is the
    parent function (and am not sure it is a good idea to temporarily clear it,
    some code perhaps should be aware it is in a nested function, or it can
    refer to variables from the parent function etc.) and that means
    store_param_decls through set_labels_context_r doesn't adjust anything.
    As those labels are emitted in the nested function body rather than in the
    parent, I think it is ok to override the context in those cases.
    
    2020-04-30  Jakub Jelinek  <jakub@redhat.com>
    
            PR c/94842
            * c-decl.c (set_labels_context_r): In addition to context-less
            LABEL_DECLs adjust also LABEL_DECLs with context equal to
            parent function if any.
            (store_parm_decls): Adjust comment.
    
            * gcc.dg/pr94842.c: New test.
    
    (cherry picked from commit 61fb8963c22d91152a9c46a3512307bef3b3d7f7)

diff --git a/gcc/c/c-decl.c b/gcc/c/c-decl.c
index 2cdbff1a960..6d417cb4274 100644
--- a/gcc/c/c-decl.c
+++ b/gcc/c/c-decl.c
@@ -9320,15 +9320,18 @@ store_parm_decls_from (struct c_arg_info *arg_info)
   store_parm_decls ();
 }
 
-/* Called by walk_tree to look for and update context-less labels.  */
+/* Called by walk_tree to look for and update context-less labels
+   or labels with context in the parent function.  */
 
 static tree
 set_labels_context_r (tree *tp, int *walk_subtrees, void *data)
 {
+  tree ctx = static_cast<tree>(data);
   if (TREE_CODE (*tp) == LABEL_EXPR
-      && DECL_CONTEXT (LABEL_EXPR_LABEL (*tp)) == NULL_TREE)
+      && (DECL_CONTEXT (LABEL_EXPR_LABEL (*tp)) == NULL_TREE
+	  || DECL_CONTEXT (LABEL_EXPR_LABEL (*tp)) == DECL_CONTEXT (ctx)))
     {
-      DECL_CONTEXT (LABEL_EXPR_LABEL (*tp)) = static_cast<tree>(data);
+      DECL_CONTEXT (LABEL_EXPR_LABEL (*tp)) = ctx;
       *walk_subtrees = 0;
     }
 
@@ -9399,7 +9402,11 @@ store_parm_decls (void)
 	 gotos, labels, etc.  Because at that time the function decl
 	 for F has not been created yet, those labels do not have any
 	 function context.  But we have the fndecl now, so update the
-	 labels accordingly.  gimplify_expr would crash otherwise.  */
+	 labels accordingly.  gimplify_expr would crash otherwise.
+	 Or with nested functions the labels could be created with parent
+	 function's context, while when the statement is emitted at the
+	 start of the nested function, it needs the nested function's
+	 context.  */
       walk_tree_without_duplicates (&arg_info->pending_sizes,
 				    set_labels_context_r, fndecl);
       add_stmt (arg_info->pending_sizes);
diff --git a/gcc/testsuite/gcc.dg/pr94842.c b/gcc/testsuite/gcc.dg/pr94842.c
new file mode 100644
index 00000000000..33d9d42644c
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94842.c
@@ -0,0 +1,11 @@
+/* PR c/94842 */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+_Atomic float x = 5;
+
+void
+foo (void)
+{
+  void bar (float y[(int) (x += 2)]) {}
+}

commit 10f44fe62fc461d4333290bfdadee4d2ea1f79d4
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed May 6 09:31:19 2020 +0200

    combine: Don't replace SET_SRC with REG_EQUAL note content if SET_SRC has side-effects [PR94873]
    
    There were some discussions about whether REG_EQUAL notes are valid on insns with a single
    set which contains auto-inc-dec side-effects in the SET_SRC and the majority thinks that
    it should be valid.  So, this patch fixes the combiner to punt in that case, because otherwise
    the auto-inc-dec side-effects from the SET_SRC are lost.
    
    2020-05-06  Jakub Jelinek  <jakub@redhat.com>
    
            PR rtl-optimization/94873
            * combine.c (combine_instructions): Don't optimize using REG_EQUAL
            note if SET_SRC (set) has side-effects.
    
            * gcc.dg/pr94873.c: New test.
    
    (cherry picked from commit 8982e39b46b1e4a4b09022ddebd758b77ab73bac)

diff --git a/gcc/combine.c b/gcc/combine.c
index 1ba66c154a5..60d54f1893f 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -1486,6 +1486,7 @@ combine_instructions (rtx_insn *f, unsigned int nregs)
 	      if ((set = single_set (temp)) != 0
 		  && (note = find_reg_equal_equiv_note (temp)) != 0
 		  && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
+		  && ! side_effects_p (SET_SRC (set))
 		  /* Avoid using a register that may already been marked
 		     dead by an earlier instruction.  */
 		  && ! unmentioned_reg_p (note, SET_SRC (set))
diff --git a/gcc/testsuite/gcc.dg/pr94873.c b/gcc/testsuite/gcc.dg/pr94873.c
new file mode 100644
index 00000000000..36152176fbf
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94873.c
@@ -0,0 +1,27 @@
+/* PR rtl-optimization/94873 */
+/* { dg-do run { target int128 } } */
+/* { dg-options "-O -fno-merge-constants -fno-split-wide-types -fno-tree-fre" } */
+
+__attribute__((noipa)) void
+foo (const char *p, int q)
+{
+  if (p[0] != '%' || p[1] != '0' || p[2] != '2' || p[3] != 'x' || p[4] != '\0')
+    __builtin_abort ();
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+  if ((unsigned char) q != 0x95)
+    __builtin_abort ();
+#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+  if ((unsigned char) q != 0)
+    __builtin_abort ();
+#endif
+}
+
+int
+main ()
+{
+  union U { __int128 a; char b[sizeof (__int128)]; };
+  char x = ((union U){ .a = 0xF4409395252B9560ULL}).b[1];
+  for (unsigned i = 0; i < sizeof (x); i++)
+    foo ("%02x", i[(volatile unsigned char *) &x]);
+  return 0;
+}

commit 102c275fde47f913bb081e76fe4ca3388940aaa1
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed May 6 09:40:33 2020 +0200

    riscv: Fix up riscv_atomic_assign_expand_fenv [PR94950]
    
    Similarly to the fixes on many other targets, riscv needs to use TARGET_EXPR
    to avoid having the create_tmp_var_raw temporaries without proper DECL_CONTEXT
    and not mentioned in local decls.
    
    2020-05-06  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94950
            * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use
            TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags.
    
    (cherry picked from commit 5454a13add37fa6a8eedbf9d2f6bdc63a7825e2c)

diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
index b1d89fc8719..7607ebad6b9 100644
--- a/gcc/config/riscv/riscv-builtins.c
+++ b/gcc/config/riscv/riscv-builtins.c
@@ -283,8 +283,8 @@ riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
   tree fsflags = GET_BUILTIN_DECL (CODE_FOR_riscv_fsflags);
   tree old_flags = create_tmp_var_raw (RISCV_ATYPE_USI);
 
-  *hold = build2 (MODIFY_EXPR, RISCV_ATYPE_USI, old_flags,
-		  build_call_expr (frflags, 0));
+  *hold = build4 (TARGET_EXPR, RISCV_ATYPE_USI, old_flags,
+		  build_call_expr (frflags, 0), NULL_TREE, NULL_TREE);
   *clear = build_call_expr (fsflags, 1, old_flags);
   *update = NULL_TREE;
 }

commit 79a11b9833baa91cef7c881532e01470fa25047f
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed May 6 23:38:13 2020 +0200

    c++: Avoid strict_aliasing_warning on dependent types or expressions [PR94951]
    
    The following testcase gets a bogus warning during build_base_path,
    when cp_build_indirect_ref* calls strict_aliasing_warning with a dependent
    expression.  IMHO calling get_alias_set etc. on dependent types feels wrong
    to me, we should just defer the warnings in those cases until instantiation
    and only handle the cases where neither type nor expr are dependent.
    
    2020-05-06  Jakub Jelinek  <jakub@redhat.com>
    
            PR c++/94951
            * typeck.c (cp_strict_aliasing_warning): New function.
            (cp_build_indirect_ref_1, build_reinterpret_cast_1): Use
            it instead of strict_aliasing_warning.
    
            * g++.dg/warn/Wstrict-aliasing-bogus-tmpl.C: New test.
    
    (cherry picked from commit d82414ebcf7716ea24688510594a2c464a105908)

diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c
index 5c064086e90..c099892b2bc 100644
--- a/gcc/cp/typeck.c
+++ b/gcc/cp/typeck.c
@@ -3134,6 +3134,22 @@ build_x_indirect_ref (location_t loc, tree expr, ref_operator errorstring,
     return rval;
 }
 
+/* Like c-family strict_aliasing_warning, but don't warn for dependent
+   types or expressions.  */
+
+static bool
+cp_strict_aliasing_warning (location_t loc, tree type, tree expr)
+{
+  if (processing_template_decl)
+    {
+      tree e = expr;
+      STRIP_NOPS (e);
+      if (dependent_type_p (type) || type_dependent_expression_p (e))
+	return false;
+    }
+  return strict_aliasing_warning (loc, type, expr);
+}
+
 /* The implementation of the above, and of indirection implied by other
    constructs.  If DO_FOLD is true, fold away INDIRECT_REF of ADDR_EXPR.  */
 
@@ -3176,10 +3192,10 @@ cp_build_indirect_ref_1 (tree ptr, ref_operator errorstring,
 	  /* If a warning is issued, mark it to avoid duplicates from
 	     the backend.  This only needs to be done at
 	     warn_strict_aliasing > 2.  */
-	  if (warn_strict_aliasing > 2)
-	    if (strict_aliasing_warning (EXPR_LOCATION (ptr),
-					 type, TREE_OPERAND (ptr, 0)))
-	      TREE_NO_WARNING (ptr) = 1;
+	  if (warn_strict_aliasing > 2
+	      && cp_strict_aliasing_warning (EXPR_LOCATION (ptr),
+					     type, TREE_OPERAND (ptr, 0)))
+	    TREE_NO_WARNING (ptr) = 1;
 	}
 
       if (VOID_TYPE_P (t))
@@ -7384,7 +7400,7 @@ build_reinterpret_cast_1 (tree type, tree expr, bool c_cast_p,
       expr = cp_build_addr_expr (expr, complain);
 
       if (warn_strict_aliasing > 2)
-	strict_aliasing_warning (EXPR_LOCATION (expr), type, expr);
+	cp_strict_aliasing_warning (EXPR_LOCATION (expr), type, expr);
 
       if (expr != error_mark_node)
 	expr = build_reinterpret_cast_1
@@ -7497,7 +7513,7 @@ build_reinterpret_cast_1 (tree type, tree expr, bool c_cast_p,
 
       if (warn_strict_aliasing <= 2)
 	/* strict_aliasing_warning STRIP_NOPs its expr.  */
-	strict_aliasing_warning (EXPR_LOCATION (expr), type, expr);
+	cp_strict_aliasing_warning (EXPR_LOCATION (expr), type, expr);
 
       return build_nop_reinterpret (type, expr);
     }
diff --git a/gcc/testsuite/g++.dg/warn/Wstrict-aliasing-bogus-tmpl.C b/gcc/testsuite/g++.dg/warn/Wstrict-aliasing-bogus-tmpl.C
new file mode 100644
index 00000000000..d0375042e42
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Wstrict-aliasing-bogus-tmpl.C
@@ -0,0 +1,12 @@
+// PR c++/94951
+// { dg-do compile }
+// { dg-options "-O2 -Wall" }
+
+struct A { int a; };
+template <int N>
+struct B : public A
+{
+  static B<N> foo () { B<N> t; t.a = 4; return t; }	// { dg-bogus "dereferencing type-punned pointer will break strict-aliasing rules" }
+};
+
+B<0> b = B<0>::foo ();

commit 819a383e5952dad6613791adba16c44d81da749b
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed May 13 11:22:37 2020 +0200

    Fix -fcompare-debug issue in purge_dead_edges [PR95080]
    
    The following testcase fails with -fcompare-debug, the bug used to be latent
    since introduction of -fcompare-debug.
    The loop at the start of purge_dead_edges behaves differently between -g0
    and -g - if the last insn is a DEBUG_INSN, then it skips not just
    DEBUG_INSNs but also NOTEs until it finds some other real insn (or bb head),
    while with -g0 it will not skip any NOTEs, so if we have
    real_insn
    note
    debug_insn // not present with -g0
    then with -g it might remove useless REG_EH_REGION from real_insn, while
    with -g0 it will not.
    
    Yet another option would be not skipping NOTE_P in the loop; I couldn't find
    in history rationale for why it is done.
    
    2020-05-13  Jakub Jelinek  <jakub@redhat.com>
    
            PR debug/95080
            * cfgrtl.c (purge_dead_edges): Skip over debug and note insns even
            if the last insn is a note.
    
            * g++.dg/opt/pr95080.C: New test.
    
    (cherry picked from commit 18edc195442291525e04f0fa4d5ef972155117da)

diff --git a/gcc/cfgrtl.c b/gcc/cfgrtl.c
index d15f94ec6dc..261aa5078e7 100644
--- a/gcc/cfgrtl.c
+++ b/gcc/cfgrtl.c
@@ -3051,7 +3051,7 @@ purge_dead_edges (basic_block bb)
   bool found;
   edge_iterator ei;
 
-  if (DEBUG_INSN_P (insn) && insn != BB_HEAD (bb))
+  if ((DEBUG_INSN_P (insn) || NOTE_P (insn)) && insn != BB_HEAD (bb))
     do
       insn = PREV_INSN (insn);
     while ((DEBUG_INSN_P (insn) || NOTE_P (insn)) && insn != BB_HEAD (bb));
diff --git a/gcc/testsuite/g++.dg/opt/pr95080.C b/gcc/testsuite/g++.dg/opt/pr95080.C
new file mode 100644
index 00000000000..2da7df73b72
--- /dev/null
+++ b/gcc/testsuite/g++.dg/opt/pr95080.C
@@ -0,0 +1,41 @@
+// PR debug/95080
+// { dg-do compile }
+// { dg-options "-Og -fcse-follow-jumps -fnon-call-exceptions -fcompare-debug" }
+
+char *a;
+
+void baz ();
+
+static inline bool
+bar ()
+{
+  int j = a[0] - 1;
+  switch (j)
+    {
+    case 0:
+    case 2:
+      return true;
+    default:
+      return false;
+    }
+}
+
+static inline bool
+foo ()
+{
+  if (bar ())
+    baz ();
+  return 0;
+}
+
+struct S
+{
+  int h;
+   ~S ();
+};
+
+S::~S ()
+{
+  if (a[0] == 0)
+    foo () != h;
+}

commit 38484dac88b157151db984790be0582bf66adcfb
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu May 14 09:51:05 2020 +0200

    openmp: Fix placement of 2nd+ preparation statement for PHIs in simd clone lowering [PR95108]
    
    For normal stmts, preparation statements are inserted before the stmt, so if we need multiple,
    they are in the correct order, but for PHIs we emit them after labels in the entry successor
    bb, and we used to emit them in the reverse order that way.
    
    2020-05-14  Jakub Jelinek  <jakub@redhat.com>
    
            PR middle-end/95108
            * omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member.
            (ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in
            entry block if info->after_stmt is NULL, otherwise add after that stmt
            and update it after adding each stmt.
            (ipa_simd_modify_function_body): Initialize info.after_stmt.
    
            * gcc.dg/gomp/pr95108.c: New test.
    
    (cherry picked from commit d0fb9ffc1b8f3b86bbdf0e915cec2136141b329b)

diff --git a/gcc/omp-simd-clone.c b/gcc/omp-simd-clone.c
index 03d6b58d8b2..ec6a2004943 100644
--- a/gcc/omp-simd-clone.c
+++ b/gcc/omp-simd-clone.c
@@ -816,6 +816,7 @@ simd_clone_init_simd_arrays (struct cgraph_node *node,
 struct modify_stmt_info {
   ipa_parm_adjustment_vec adjustments;
   gimple *stmt;
+  gimple *after_stmt;
   /* True if the parent statement was modified by
      ipa_simd_modify_stmt_ops.  */
   bool modified;
@@ -899,7 +900,10 @@ ipa_simd_modify_stmt_ops (tree *tp, int *walk_subtrees, void *data)
       gimple_stmt_iterator gsi;
       if (gimple_code (info->stmt) == GIMPLE_PHI)
 	{
-	  gsi = gsi_after_labels (single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun)));
+	  if (info->after_stmt)
+	    gsi = gsi_for_stmt (info->after_stmt);
+	  else
+	    gsi = gsi_after_labels (single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun)));
 	  /* Cache SSA_NAME for next time.  */
 	  if (cand
 	      && TREE_CODE (*orig_tp) == ADDR_EXPR
@@ -908,7 +912,12 @@ ipa_simd_modify_stmt_ops (tree *tp, int *walk_subtrees, void *data)
 	}
       else
 	gsi = gsi_for_stmt (info->stmt);
-      gsi_insert_before (&gsi, stmt, GSI_SAME_STMT);
+      if (info->after_stmt)
+	gsi_insert_after (&gsi, stmt, GSI_SAME_STMT);
+      else
+	gsi_insert_before (&gsi, stmt, GSI_SAME_STMT);
+      if (gimple_code (info->stmt) == GIMPLE_PHI)
+	info->after_stmt = stmt;
       *orig_tp = repl;
     }
   else if (!useless_type_conversion_p (TREE_TYPE (*tp), TREE_TYPE (repl)))
@@ -1013,6 +1022,7 @@ ipa_simd_modify_function_body (struct cgraph_node *node,
 	  gphi *phi = as_a <gphi *> (gsi_stmt (gsi));
 	  int i, n = gimple_phi_num_args (phi);
 	  info.stmt = phi;
+	  info.after_stmt = NULL;
 	  struct walk_stmt_info wi;
 	  memset (&wi, 0, sizeof (wi));
 	  info.modified = false;
@@ -1038,6 +1048,7 @@ ipa_simd_modify_function_body (struct cgraph_node *node,
 	{
 	  gimple *stmt = gsi_stmt (gsi);
 	  info.stmt = stmt;
+	  info.after_stmt = NULL;
 	  struct walk_stmt_info wi;
 
 	  memset (&wi, 0, sizeof (wi));
diff --git a/gcc/testsuite/gcc.dg/gomp/pr95108.c b/gcc/testsuite/gcc.dg/gomp/pr95108.c
new file mode 100644
index 00000000000..b492333686b
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/gomp/pr95108.c
@@ -0,0 +1,18 @@
+/* PR middle-end/95108 */
+/* { dg-do compile { target vect_simd_clones } } */
+/* { dg-options "-O2 -fopenmp-simd -w" } */
+
+int *v;
+
+#pragma omp declare simd
+void
+foo (int x)
+{
+  int *a = &x + 1;
+
+  for (;;)
+    {
+      *v = *a;
+      a = v;
+    }
+}

commit 4163fd72a0606199c4ab867fde0efdff6346d6f3
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu May 28 23:40:54 2020 +0200

    c++: Try to complete decomp types [PR95328]
    
    Two years ago Paolo has added the
      else if (processing_template_decl && !COMPLETE_TYPE_P (type))
        pedwarn (...);
    lines into cp_finish_decomp.  For type dependent decl we punt much earlier,
    but even for types which aren't type dependent COMPLETE_TYPE_P might be
    false as this testcase shows, so this patch tries to complete_type first
    (the reason for writing it that way is that it is then followed by another
    else if and if complete_type returns error_mark_node, we shouldn't report
    anything, as a bug should have been reported already.
    
    2020-05-28  Jakub Jelinek  <jakub@redhat.com>
    
            PR c++/95328
            * decl.c (cp_finish_decomp): Call complete_type before checking
            COMPLETE_TYPE_P.
    
            * g++.dg/cpp1z/decomp53.C: New test.
    
    (cherry picked from commit 3d8d5ddb539a5254c7ef83414377f4c74c7701d4)

diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c
index 9f1444ccff6..07a6de62e22 100644
--- a/gcc/cp/decl.c
+++ b/gcc/cp/decl.c
@@ -7813,6 +7813,8 @@ cp_finish_decomp (tree decl, tree first, unsigned int count)
       error_at (loc, "cannot decompose lambda closure type %qT", type);
       goto error_out;
     }
+  else if (processing_template_decl && complete_type (type) == error_mark_node)
+    goto error_out;
   else if (processing_template_decl && !COMPLETE_TYPE_P (type))
     pedwarn (loc, 0, "structured binding refers to incomplete class type %qT",
 	     type);
diff --git a/gcc/testsuite/g++.dg/cpp1z/decomp53.C b/gcc/testsuite/g++.dg/cpp1z/decomp53.C
new file mode 100644
index 00000000000..b34e6ac7250
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1z/decomp53.C
@@ -0,0 +1,22 @@
+// PR c++/95328
+// { dg-do compile { target c++11 } }
+// { dg-options "" }
+
+template <typename T>
+struct S
+{
+  int a, b;
+};
+
+template <typename T>
+void
+foo ()
+{
+  auto [a, b] = S<int>();	// { dg-warning "structured bindings only available with" "" { target c++14_down } }
+}
+
+int
+main ()
+{
+  foo<int> ();
+}

commit 111d3ebb356dd9f08bb0f9d0ad1044dd67a8c16c
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Jun 27 12:38:23 2020 +0200

    c-family: Use TYPE_OVERFLOW_UNDEFINED instead of !TYPE_UNSIGNED in pointer_sum [PR95903]
    
    For lp64 targets and int off ... ptr[off + 1]
    is lowered in pointer_sum to *(ptr + ((sizetype) off + (sizetype) 1)).
    That is fine when signed integer wrapping is undefined (and is not done
    already if off has unsigned type), but changes behavior for -fwrapv, where
    overflow is well defined.  Runtime test could be:
    int
    main ()
    {
      char *p = __builtin_malloc (0x100000000UL);
      if (!p) return 0;
      char *q = p + 0x80000000UL;
      int o = __INT_MAX__;
      q[o + 1] = 1;
      if (q[-__INT_MAX__ - 1] != 1) __builtin_abort ();
      return 0;
    }
    with -fwrapv or so, not included in the testsuite because it requires 4GB
    allocation (with some other test it would be enough to have something
    slightly above 2GB, but still...).
    
    2020-06-27  Jakub Jelinek  <jakub@redhat.com>
    
            PR middle-end/95903
    gcc/c-family/
            * c-common.c (pointer_int_sum): Use TYPE_OVERFLOW_UNDEFINED instead of
            !TYPE_UNSIGNED check to see if we can apply distributive law and handle
            smaller precision intop operands separately.
    gcc/testsuite/
            * c-c++-common/pr95903.c: New test.
    
    (cherry picked from commit 37995960984ea2222346dd9d168d332cd6f7adf0)

diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c
index 655c3bf10a7..c890299996b 100644
--- a/gcc/c-family/c-common.c
+++ b/gcc/c-family/c-common.c
@@ -3120,7 +3120,7 @@ pointer_int_sum (location_t loc, enum tree_code resultcode,
       /* If the constant is unsigned, and smaller than the pointer size,
 	 then we must skip this optimization.  This is because it could cause
 	 an overflow error if the constant is negative but INTOP is not.  */
-      && (!TYPE_UNSIGNED (TREE_TYPE (intop))
+      && (TYPE_OVERFLOW_UNDEFINED (TREE_TYPE (intop))
 	  || (TYPE_PRECISION (TREE_TYPE (intop))
 	      == TYPE_PRECISION (TREE_TYPE (ptrop)))))
     {
diff --git a/gcc/testsuite/c-c++-common/pr95903.c b/gcc/testsuite/c-c++-common/pr95903.c
new file mode 100644
index 00000000000..6e9f68e200f
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/pr95903.c
@@ -0,0 +1,19 @@
+/* PR middle-end/95903 */
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -fwrapv -fdump-tree-optimized" } */
+/* Verify that for -fwrapv the + 1 addition is performed in the parameter's
+   type before sign extending it.  */
+/* { dg-final { scan-tree-dump-times "off_\[0-9]+\\\(D\\\) \\+ 1" 2 "optimized" } } */
+
+char
+foo (const char *ptr, int off)
+{
+  off += 1;
+  return ptr[off];
+}
+
+char
+bar (const char *ptr, int off)
+{
+  return ptr[off + 1];
+}

commit cac9ff3a809f90236dc737a51eb8ff0e9088783c
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Jul 2 11:38:20 2020 +0200

    tree-cfg: Fix ICE with switch stmt to unreachable opt and forced labels [PR95857]
    
    The following testcase ICEs, because during the cfg cleanup, we see:
      switch (i$e_11) <default: <L12> [33.33%], case -3: <lab2> [33.33%], case 0: <L10> [33.33%], case 2: <lab2> [33.33%]>
    ...
    lab2:
      __builtin_unreachable ();
    where lab2 is FORCED_LABEL.  The way it works, we go through the case labels
    and when we reach the first one that points to gimple_seq_unreachable*
    basic block, we remove the edge (if any) from the switch bb to the bb
    containing the label and bbs reachable only through that edge we've just
    removed.  Once we do that, we must throw away all other cases that use
    the same label (or some other labels from the same bb we've removed the edge
    to and the bb).  To avoid quadratic behavior, this is not done by walking
    all remaining cases immediately before removing, but only when processing
    them later.
    For normal labels this works, fine, if the label is in a deleted bb, it will
    have NULL label_to_block and we handle that case, or, if the unreachable bb
    has some other edge to it, only the edge will be removed and not the bb,
    and again, find_edge will not find the edge and we only remove the case.
    And if a label would be to some other block, that other block wouldn't have
    been removed earlier because there would be still an edge from the switch
    block.
    Now, FORCED_LABEL (and I think DECL_NONLOCAL too) break this, because
    those labels aren't removed, but instead moved to some surrounding basic
    block.  So, when we later process those, when their gimple_seq_unreachable*
    basic block is removed, label_to_block will return some unrelated block
    (in the testcase the switch bb), so we decide to keep the case which doesn't
    seem to be unreachable, but we don't really have an edge from the switch
    block to the block the label got moved to.
    
    I thought first about punting in gimple_seq_unreachable* on
    FORCED_LABEL/DECL_NONLOCAL labels, but that might penalize even code that
    doesn't care, so this instead just makes sure that for
    FORCED_LABEL/DECL_NONLOCAL labels that are being removed (and thus moved
    randomly) we remember in a hash_set the fact that those labels should be
    treated as removed for the purpose of the optimization, and later on
    handle those labels that way.
    
    2020-07-02  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/95857
            * tree-cfg.c (group_case_labels_stmt): When removing an unreachable
            base_bb, remember all forced and non-local labels on it and later
            treat those as if they have NULL label_to_block.  Formatting fix.
            Fix a comment typo.
    
            * gcc.dg/pr95857.c: New test.
    
    (cherry picked from commit 00f24f56732861d09a9716fa5b6b8a96c2289143)

diff --git a/gcc/testsuite/gcc.dg/pr95857.c b/gcc/testsuite/gcc.dg/pr95857.c
new file mode 100644
index 00000000000..41506ea6893
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr95857.c
@@ -0,0 +1,37 @@
+/* PR tree-optimization/95857 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct E { int e; };
+int bar (void), baz (void);
+void qux (void *);
+
+void
+foo (int x)
+{
+  struct E a = { 0 };
+  struct E i = { 0 };
+  qux (&&lab2);
+  if (baz ())
+    i.e = 1;
+  else
+    a.e = -2;
+  switch (a.e)
+    {
+    case -2:
+    lab1:
+      switch (i.e)
+	{
+	case -3:
+	case 2:
+	  if (i.e-- != 2)
+	    __builtin_unreachable ();
+	lab2:
+	  baz ();
+	  goto lab1;
+	case 0:
+	  bar ();
+	}
+      break;
+    }
+}
diff --git a/gcc/tree-cfg.c b/gcc/tree-cfg.c
index baaf0b0eece..8cb3c18b41f 100644
--- a/gcc/tree-cfg.c
+++ b/gcc/tree-cfg.c
@@ -1768,6 +1768,7 @@ group_case_labels_stmt (gswitch *stmt)
   int old_size = gimple_switch_num_labels (stmt);
   int i, next_index, new_size;
   basic_block default_bb = NULL;
+  hash_set<tree> *removed_labels = NULL;
 
   default_bb = label_to_block (CASE_LABEL (gimple_switch_default_label (stmt)));
 
@@ -1784,8 +1785,11 @@ group_case_labels_stmt (gswitch *stmt)
       base_bb = label_to_block (CASE_LABEL (base_case));
 
       /* Discard cases that have the same destination as the default case or
-	 whose destiniation blocks have already been removed as unreachable.  */
-      if (base_bb == NULL || base_bb == default_bb)
+	 whose destination blocks have already been removed as unreachable.  */
+      if (base_bb == NULL
+	  || base_bb == default_bb
+	  || (removed_labels
+	      && removed_labels->contains (CASE_LABEL (base_case))))
 	{
 	  i++;
 	  continue;
@@ -1808,10 +1812,13 @@ group_case_labels_stmt (gswitch *stmt)
 	  /* Merge the cases if they jump to the same place,
 	     and their ranges are consecutive.  */
 	  if (merge_bb == base_bb
+	      && (removed_labels == NULL
+		  || !removed_labels->contains (CASE_LABEL (merge_case)))
 	      && wi::to_wide (CASE_LOW (merge_case)) == bhp1)
 	    {
-	      base_high = CASE_HIGH (merge_case) ?
-		  CASE_HIGH (merge_case) : CASE_LOW (merge_case);
+	      base_high
+		= (CASE_HIGH (merge_case)
+		   ? CASE_HIGH (merge_case) : CASE_LOW (merge_case));
 	      CASE_HIGH (base_case) = base_high;
 	      next_index++;
 	    }
@@ -1832,7 +1839,29 @@ group_case_labels_stmt (gswitch *stmt)
 	{
 	  edge base_edge = find_edge (gimple_bb (stmt), base_bb);
 	  if (base_edge != NULL)
-	    remove_edge_and_dominated_blocks (base_edge);
+	    {
+	      for (gimple_stmt_iterator gsi = gsi_start_bb (base_bb);
+		   !gsi_end_p (gsi); gsi_next (&gsi))
+		if (glabel *stmt = dyn_cast <glabel *> (gsi_stmt (gsi)))
+		  {
+		    if (FORCED_LABEL (gimple_label_label (stmt))
+			|| DECL_NONLOCAL (gimple_label_label (stmt)))
+		      {
+			/* Forced/non-local labels aren't going to be removed,
+			   but they will be moved to some neighbouring basic
+			   block. If some later case label refers to one of
+			   those labels, we should throw that case away rather
+			   than keeping it around and refering to some random
+			   other basic block without an edge to it.  */
+			if (removed_labels == NULL)
+			  removed_labels = new hash_set<tree>;
+			removed_labels->add (gimple_label_label (stmt));
+		      }
+		  }
+		else
+		  break;
+	      remove_edge_and_dominated_blocks (base_edge);
+	    }
 	  i = next_index;
 	  continue;
 	}
@@ -1849,6 +1878,7 @@ group_case_labels_stmt (gswitch *stmt)
   if (new_size < old_size)
     gimple_switch_set_num_labels (stmt, new_size);
 
+  delete removed_labels;
   return new_size < old_size;
 }
 

commit d7cd4f2de0393cde7ec091fdbbb7875733d4a059
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Jul 15 11:34:44 2020 +0200

    fix _mm512_{,mask_}cmp*_p[ds]_mask at -O0 [PR96174]
    
    The _mm512_{,mask_}cmp_p[ds]_mask and also _mm_{,mask_}cmp_s[ds]_mask
    intrinsics have an argument which must have a constant passed to it
    and so use an inline version only for ifdef __OPTIMIZE__ and have
    a #define for -O0.  But the _mm512_{,mask_}cmp*_p[ds]_mask intrinsics
    don't need a constant argument, they are essentially the first
    set with the constant added to them implicitly based on the comparison
    name, and so there is no #define version for them (correctly).
    But their inline versions are defined in between the first and s[ds]
    set and so inside of ifdef __OPTIMIZE__, which means that with -O0
    they aren't defined at all.
    
    This patch fixes that by moving those after the #ifdef __OPTIMIZE #else
    use #define #endif block.
    
    2020-07-15  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/96174
            * config/i386/avx512fintrin.h (_mm512_cmpeq_pd_mask,
            _mm512_mask_cmpeq_pd_mask, _mm512_cmplt_pd_mask,
            _mm512_mask_cmplt_pd_mask, _mm512_cmple_pd_mask,
            _mm512_mask_cmple_pd_mask, _mm512_cmpunord_pd_mask,
            _mm512_mask_cmpunord_pd_mask, _mm512_cmpneq_pd_mask,
            _mm512_mask_cmpneq_pd_mask, _mm512_cmpnlt_pd_mask,
            _mm512_mask_cmpnlt_pd_mask, _mm512_cmpnle_pd_mask,
            _mm512_mask_cmpnle_pd_mask, _mm512_cmpord_pd_mask,
            _mm512_mask_cmpord_pd_mask, _mm512_cmpeq_ps_mask,
            _mm512_mask_cmpeq_ps_mask, _mm512_cmplt_ps_mask,
            _mm512_mask_cmplt_ps_mask, _mm512_cmple_ps_mask,
            _mm512_mask_cmple_ps_mask, _mm512_cmpunord_ps_mask,
            _mm512_mask_cmpunord_ps_mask, _mm512_cmpneq_ps_mask,
            _mm512_mask_cmpneq_ps_mask, _mm512_cmpnlt_ps_mask,
            _mm512_mask_cmpnlt_ps_mask, _mm512_cmpnle_ps_mask,
            _mm512_mask_cmpnle_ps_mask, _mm512_cmpord_ps_mask,
            _mm512_mask_cmpord_ps_mask): Move outside of __OPTIMIZE__ guarded
            section.
    
            * gcc.target/i386/avx512f-vcmppd-3.c: New test.
            * gcc.target/i386/avx512f-vcmpps-3.c: New test.
    
    (cherry picked from commit 12d69dbfff9dd5ad4a30b20d1636f5cab6425e8c)

diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h
index 142c0ee2350..88771a39126 100644
--- a/gcc/config/i386/avx512fintrin.h
+++ b/gcc/config/i386/avx512fintrin.h
@@ -14134,6 +14134,88 @@ _mm512_mask_cmp_pd_mask (__mmask8 __U, __m512d __X, __m512d __Y, const int __P)
 						  _MM_FROUND_CUR_DIRECTION);
 }
 
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cmp_sd_mask (__m128d __X, __m128d __Y, const int __P)
+{
+  return (__mmask8) __builtin_ia32_cmpsd_mask ((__v2df) __X,
+					       (__v2df) __Y, __P,
+					       (__mmask8) -1,
+					       _MM_FROUND_CUR_DIRECTION);
+}
+
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cmp_sd_mask (__mmask8 __M, __m128d __X, __m128d __Y, const int __P)
+{
+  return (__mmask8) __builtin_ia32_cmpsd_mask ((__v2df) __X,
+					       (__v2df) __Y, __P,
+					       (__mmask8) __M,
+					       _MM_FROUND_CUR_DIRECTION);
+}
+
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cmp_ss_mask (__m128 __X, __m128 __Y, const int __P)
+{
+  return (__mmask8) __builtin_ia32_cmpss_mask ((__v4sf) __X,
+					       (__v4sf) __Y, __P,
+					       (__mmask8) -1,
+					       _MM_FROUND_CUR_DIRECTION);
+}
+
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cmp_ss_mask (__mmask8 __M, __m128 __X, __m128 __Y, const int __P)
+{
+  return (__mmask8) __builtin_ia32_cmpss_mask ((__v4sf) __X,
+					       (__v4sf) __Y, __P,
+					       (__mmask8) __M,
+					       _MM_FROUND_CUR_DIRECTION);
+}
+
+#else
+#define _mm512_cmp_pd_mask(X, Y, P)					\
+  ((__mmask8) __builtin_ia32_cmppd512_mask ((__v8df)(__m512d)(X),	\
+					    (__v8df)(__m512d)(Y), (int)(P),\
+					    (__mmask8)-1,_MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_cmp_ps_mask(X, Y, P)					\
+  ((__mmask16) __builtin_ia32_cmpps512_mask ((__v16sf)(__m512)(X),	\
+					     (__v16sf)(__m512)(Y), (int)(P),\
+					     (__mmask16)-1,_MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_mask_cmp_pd_mask(M, X, Y, P)					\
+  ((__mmask8) __builtin_ia32_cmppd512_mask ((__v8df)(__m512d)(X),	\
+					    (__v8df)(__m512d)(Y), (int)(P),\
+					    (__mmask8)(M), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_mask_cmp_ps_mask(M, X, Y, P)					\
+  ((__mmask16) __builtin_ia32_cmpps512_mask ((__v16sf)(__m512)(X),	\
+					     (__v16sf)(__m512)(Y), (int)(P),\
+					     (__mmask16)(M),_MM_FROUND_CUR_DIRECTION))
+
+#define _mm_cmp_sd_mask(X, Y, P)					\
+  ((__mmask8) __builtin_ia32_cmpsd_mask ((__v2df)(__m128d)(X),		\
+					 (__v2df)(__m128d)(Y), (int)(P),\
+					 (__mmask8)-1,_MM_FROUND_CUR_DIRECTION))
+
+#define _mm_mask_cmp_sd_mask(M, X, Y, P)					\
+  ((__mmask8) __builtin_ia32_cmpsd_mask ((__v2df)(__m128d)(X),		\
+					 (__v2df)(__m128d)(Y), (int)(P),\
+					 M,_MM_FROUND_CUR_DIRECTION))
+
+#define _mm_cmp_ss_mask(X, Y, P)					\
+  ((__mmask8) __builtin_ia32_cmpss_mask ((__v4sf)(__m128)(X),		\
+					 (__v4sf)(__m128)(Y), (int)(P), \
+					 (__mmask8)-1,_MM_FROUND_CUR_DIRECTION))
+
+#define _mm_mask_cmp_ss_mask(M, X, Y, P)					\
+  ((__mmask8) __builtin_ia32_cmpss_mask ((__v4sf)(__m128)(X),		\
+					 (__v4sf)(__m128)(Y), (int)(P), \
+					 M,_MM_FROUND_CUR_DIRECTION))
+#endif
+
 extern __inline __mmask8
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm512_cmpeq_pd_mask (__m512d __X, __m512d __Y)
@@ -14454,88 +14536,6 @@ _mm512_mask_cmpord_ps_mask (__mmask16 __U, __m512 __X, __m512 __Y)
 						   _MM_FROUND_CUR_DIRECTION);
 }
 
-extern __inline __mmask8
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_cmp_sd_mask (__m128d __X, __m128d __Y, const int __P)
-{
-  return (__mmask8) __builtin_ia32_cmpsd_mask ((__v2df) __X,
-					       (__v2df) __Y, __P,
-					       (__mmask8) -1,
-					       _MM_FROUND_CUR_DIRECTION);
-}
-
-extern __inline __mmask8
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_mask_cmp_sd_mask (__mmask8 __M, __m128d __X, __m128d __Y, const int __P)
-{
-  return (__mmask8) __builtin_ia32_cmpsd_mask ((__v2df) __X,
-					       (__v2df) __Y, __P,
-					       (__mmask8) __M,
-					       _MM_FROUND_CUR_DIRECTION);
-}
-
-extern __inline __mmask8
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_cmp_ss_mask (__m128 __X, __m128 __Y, const int __P)
-{
-  return (__mmask8) __builtin_ia32_cmpss_mask ((__v4sf) __X,
-					       (__v4sf) __Y, __P,
-					       (__mmask8) -1,
-					       _MM_FROUND_CUR_DIRECTION);
-}
-
-extern __inline __mmask8
-__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_mask_cmp_ss_mask (__mmask8 __M, __m128 __X, __m128 __Y, const int __P)
-{
-  return (__mmask8) __builtin_ia32_cmpss_mask ((__v4sf) __X,
-					       (__v4sf) __Y, __P,
-					       (__mmask8) __M,
-					       _MM_FROUND_CUR_DIRECTION);
-}
-
-#else
-#define _mm512_cmp_pd_mask(X, Y, P)					\
-  ((__mmask8) __builtin_ia32_cmppd512_mask ((__v8df)(__m512d)(X),	\
-					    (__v8df)(__m512d)(Y), (int)(P),\
-					    (__mmask8)-1,_MM_FROUND_CUR_DIRECTION))
-
-#define _mm512_cmp_ps_mask(X, Y, P)					\
-  ((__mmask16) __builtin_ia32_cmpps512_mask ((__v16sf)(__m512)(X),	\
-					     (__v16sf)(__m512)(Y), (int)(P),\
-					     (__mmask16)-1,_MM_FROUND_CUR_DIRECTION))
-
-#define _mm512_mask_cmp_pd_mask(M, X, Y, P)					\
-  ((__mmask8) __builtin_ia32_cmppd512_mask ((__v8df)(__m512d)(X),	\
-					    (__v8df)(__m512d)(Y), (int)(P),\
-					    (__mmask8)(M), _MM_FROUND_CUR_DIRECTION))
-
-#define _mm512_mask_cmp_ps_mask(M, X, Y, P)					\
-  ((__mmask16) __builtin_ia32_cmpps512_mask ((__v16sf)(__m512)(X),	\
-					     (__v16sf)(__m512)(Y), (int)(P),\
-					     (__mmask16)(M),_MM_FROUND_CUR_DIRECTION))
-
-#define _mm_cmp_sd_mask(X, Y, P)					\
-  ((__mmask8) __builtin_ia32_cmpsd_mask ((__v2df)(__m128d)(X),		\
-					 (__v2df)(__m128d)(Y), (int)(P),\
-					 (__mmask8)-1,_MM_FROUND_CUR_DIRECTION))
-
-#define _mm_mask_cmp_sd_mask(M, X, Y, P)					\
-  ((__mmask8) __builtin_ia32_cmpsd_mask ((__v2df)(__m128d)(X),		\
-					 (__v2df)(__m128d)(Y), (int)(P),\
-					 M,_MM_FROUND_CUR_DIRECTION))
-
-#define _mm_cmp_ss_mask(X, Y, P)					\
-  ((__mmask8) __builtin_ia32_cmpss_mask ((__v4sf)(__m128)(X),		\
-					 (__v4sf)(__m128)(Y), (int)(P), \
-					 (__mmask8)-1,_MM_FROUND_CUR_DIRECTION))
-
-#define _mm_mask_cmp_ss_mask(M, X, Y, P)					\
-  ((__mmask8) __builtin_ia32_cmpss_mask ((__v4sf)(__m128)(X),		\
-					 (__v4sf)(__m128)(Y), (int)(P), \
-					 M,_MM_FROUND_CUR_DIRECTION))
-#endif
-
 extern __inline __mmask16
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm512_kmov (__mmask16 __A)
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcmppd-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vcmppd-3.c
new file mode 100644
index 00000000000..3d36eca78fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcmppd-3.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx512f" } */
+
+#include "avx512f-vcmppd-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcmpps-3.c b/gcc/testsuite/gcc.target/i386/avx512f-vcmpps-3.c
new file mode 100644
index 00000000000..af797aad2de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcmpps-3.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx512f" } */
+
+#include "avx512f-vcmpps-1.c"

commit 6b326d90d2195f00eb37dbf1be963ee3880af3b9
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Aug 8 11:10:30 2020 +0200

    openmp: Handle clauses with gimple sequences in convert_nonlocal_omp_clauses properly
    
    If the walk_body on the various sequences of reduction, lastprivate and/or linear
    clauses needs to create a temporary variable, we should declare that variable
    in that sequence rather than outside, where it would need to be privatized inside of
    the construct.
    
    2020-08-08  Jakub Jelinek  <jakub@redhat.com>
    
            PR fortran/93553
            * tree-nested.c (convert_nonlocal_omp_clauses): For
            OMP_CLAUSE_REDUCTION, OMP_CLAUSE_LASTPRIVATE and OMP_CLAUSE_LINEAR
            save info->new_local_var_chain around walks of the clause gimple
            sequences and declare_vars if needed into the sequence.
    
    2020-08-08  Tobias Burnus  <tobias@codesourcery.com>
    
            PR fortran/93553
            * testsuite/libgomp.fortran/pr93553.f90: New test.
    
    (cherry picked from commit 676b5525e8333005bdc1c596ed086f1da27a450f)

diff --git a/gcc/tree-nested.c b/gcc/tree-nested.c
index e7ea290065b..d63b4101b67 100644
--- a/gcc/tree-nested.c
+++ b/gcc/tree-nested.c
@@ -1346,12 +1346,22 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi)
 	      if (OMP_CLAUSE_REDUCTION_DECL_PLACEHOLDER (clause))
 		DECL_CONTEXT (OMP_CLAUSE_REDUCTION_DECL_PLACEHOLDER (clause))
 		  = info->context;
+	      tree save_local_var_chain = info->new_local_var_chain;
+	      info->new_local_var_chain = NULL;
+	      gimple_seq *seq = &OMP_CLAUSE_REDUCTION_GIMPLE_INIT (clause);
 	      walk_body (convert_nonlocal_reference_stmt,
-			 convert_nonlocal_reference_op, info,
-			 &OMP_CLAUSE_REDUCTION_GIMPLE_INIT (clause));
+			 convert_nonlocal_reference_op, info, seq);
+	      if (info->new_local_var_chain)
+		declare_vars (info->new_local_var_chain,
+			      gimple_seq_first_stmt (*seq), false);
+	      info->new_local_var_chain = NULL;
+	      seq = &OMP_CLAUSE_REDUCTION_GIMPLE_MERGE (clause);
 	      walk_body (convert_nonlocal_reference_stmt,
-			 convert_nonlocal_reference_op, info,
-			 &OMP_CLAUSE_REDUCTION_GIMPLE_MERGE (clause));
+			 convert_nonlocal_reference_op, info, seq);
+	      if (info->new_local_var_chain)
+		declare_vars (info->new_local_var_chain,
+			      gimple_seq_first_stmt (*seq), false);
+	      info->new_local_var_chain = save_local_var_chain;
 	      DECL_CONTEXT (OMP_CLAUSE_REDUCTION_PLACEHOLDER (clause))
 		= old_context;
 	      if (OMP_CLAUSE_REDUCTION_DECL_PLACEHOLDER (clause))
@@ -1361,15 +1371,31 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi)
 	  break;
 
 	case OMP_CLAUSE_LASTPRIVATE:
-	  walk_body (convert_nonlocal_reference_stmt,
-		     convert_nonlocal_reference_op, info,
-		     &OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (clause));
+	  {
+	    tree save_local_var_chain = info->new_local_var_chain;
+	    info->new_local_var_chain = NULL;
+	    gimple_seq *seq = &OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (clause);
+	    walk_body (convert_nonlocal_reference_stmt,
+		       convert_nonlocal_reference_op, info, seq);
+	    if (info->new_local_var_chain)
+	      declare_vars (info->new_local_var_chain,
+			    gimple_seq_first_stmt (*seq), false);
+	    info->new_local_var_chain = save_local_var_chain;
+	  }
 	  break;
 
 	case OMP_CLAUSE_LINEAR:
-	  walk_body (convert_nonlocal_reference_stmt,
-		     convert_nonlocal_reference_op, info,
-		     &OMP_CLAUSE_LINEAR_GIMPLE_SEQ (clause));
+	  {
+	    tree save_local_var_chain = info->new_local_var_chain;
+	    info->new_local_var_chain = NULL;
+	    gimple_seq *seq = &OMP_CLAUSE_LINEAR_GIMPLE_SEQ (clause);
+	    walk_body (convert_nonlocal_reference_stmt,
+		       convert_nonlocal_reference_op, info, seq);
+	    if (info->new_local_var_chain)
+	      declare_vars (info->new_local_var_chain,
+			    gimple_seq_first_stmt (*seq), false);
+	    info->new_local_var_chain = save_local_var_chain;
+	  }
 	  break;
 
 	default:
diff --git a/libgomp/testsuite/libgomp.fortran/pr93553.f90 b/libgomp/testsuite/libgomp.fortran/pr93553.f90
new file mode 100644
index 00000000000..5d6f10febed
--- /dev/null
+++ b/libgomp/testsuite/libgomp.fortran/pr93553.f90
@@ -0,0 +1,21 @@
+program p
+   implicit none
+   integer :: x(8) = 0
+   call sub(x)
+end
+subroutine sub(x)
+   implicit none
+   integer i
+   integer :: x(8)
+   integer :: c(8) = [(11*i, i=1,8)]
+   call s
+   if (any (x /= c)) stop 1
+contains
+   subroutine s
+      integer :: i
+      !$omp parallel do reduction(+:x)
+      do i = 1, 8
+         x(i) = c(i)
+      end do
+   end
+end

commit 4ae2e2b9405aff8c242769c8139ce33115df568e
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Aug 11 16:46:49 2020 +0200

    c-family: Fix ICE in get_atomic_generic_size [PR96545]
    
    As the testcase shows, we would ICE if the type of the first argument of
    various atomic builtins was pointer to (non-void) incomplete type, we would
    assume that TYPE_SIZE_UNIT must be non-NULL.  This patch diagnoses it
    instead.  And also changes the TREE_CODE != INTEGER_CST check to
    !tree_fits_uhwi_p, as we use tree_to_uhwi after this and at least in theory
    the int could be too large and not fit.
    
    2020-08-11  Jakub Jelinek  <jakub@redhat.com>
    
            PR c/96545
            * c-common.c (get_atomic_generic_size): Require that first argument's
            type points to a complete type and use tree_fits_uhwi_p instead of
            just INTEGER_CST TREE_CODE check for the TYPE_SIZE_UNIT.
    
            * c-c++-common/pr96545.c: New test.
    
    (cherry picked from commit 7840b4dc05539cf5575b3e9ff57ff5f6c3da2cae)

diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c
index c890299996b..6ce5744a373 100644
--- a/gcc/c-family/c-common.c
+++ b/gcc/c-family/c-common.c
@@ -6661,8 +6661,15 @@ get_atomic_generic_size (location_t loc, tree function,
       return 0;
     }
 
+  if (!COMPLETE_TYPE_P (TREE_TYPE (type_0)))
+    {
+      error_at (loc, "argument 1 of %qE must be a pointer to a complete type",
+		function);
+      return 0;
+    }
+
   /* Types must be compile time constant sizes. */
-  if (TREE_CODE ((TYPE_SIZE_UNIT (TREE_TYPE (type_0)))) != INTEGER_CST)
+  if (!tree_fits_uhwi_p ((TYPE_SIZE_UNIT (TREE_TYPE (type_0)))))
     {
       error_at (loc, 
 		"argument 1 of %qE must be a pointer to a constant size type",
diff --git a/gcc/testsuite/c-c++-common/pr96545.c b/gcc/testsuite/c-c++-common/pr96545.c
new file mode 100644
index 00000000000..bc6b0cf345c
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/pr96545.c
@@ -0,0 +1,31 @@
+/* PR c/96545 */
+/* { dg-do compile } */
+
+extern char x[], y[], z[];
+struct S;
+extern struct S s, t, u;
+int v, w;
+
+void
+foo (void)
+{
+  __atomic_exchange (&x, &y, &z, 0);	/* { dg-error "must be a pointer to a complete type" } */
+}
+
+void
+bar (void)
+{
+  __atomic_exchange (&s, &t, &u, 0);	/* { dg-error "must be a pointer to a complete type" } */
+}
+
+void
+baz (void)
+{
+  __atomic_exchange (&v, &t, &w, 0);	/* { dg-error "size mismatch in argument 2 of" } */
+}
+
+void
+qux (void)
+{
+  __atomic_exchange (&v, &w, &t, 0);	/* { dg-error "size mismatch in argument 3 of" } */
+}

commit 2346f2b89780790210816eeea12b817e61652b26
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Aug 18 07:51:58 2020 +0200

    c: Fix -Wunused-but-set-* warning with _Generic [PR96571]
    
    The following testcase shows various problems with -Wunused-but-set*
    warnings and _Generic construct.  I think it is best to treat the selector
    and the ignored expressions as (potentially) read, because when they are
    parsed, the vars in there are already marked as TREE_USED.
    
    2020-08-18  Jakub Jelinek  <jakub@redhat.com>
    
            PR c/96571
            * c-parser.c (c_parser_generic_selection): Change match_found from bool
            to int, holding index of the match.  Call mark_exp_read on the selector
            expression and on expressions other than the selected one.
    
            * gcc.dg/Wunused-var-4.c: New test.
    
    (cherry picked from commit 6d42cbe5ad7a7b46437f2576c9920e44dc14b386)

diff --git a/gcc/c/c-parser.c b/gcc/c/c-parser.c
index 75ef0a437a7..bea4dd2a779 100644
--- a/gcc/c/c-parser.c
+++ b/gcc/c/c-parser.c
@@ -7585,7 +7585,7 @@ c_parser_generic_selection (c_parser *parser)
   struct c_expr selector, error_expr;
   tree selector_type;
   struct c_generic_association matched_assoc;
-  bool match_found = false;
+  int match_found = -1;
   location_t generic_loc, selector_loc;
 
   error_expr.original_code = ERROR_MARK;
@@ -7620,6 +7620,7 @@ c_parser_generic_selection (c_parser *parser)
       c_parser_skip_until_found (parser, CPP_CLOSE_PAREN, NULL);
       return selector;
     }
+  mark_exp_read (selector.value);
   selector_type = TREE_TYPE (selector.value);
   /* In ISO C terms, rvalues (including the controlling expression of
      _Generic) do not have qualified types.  */
@@ -7719,18 +7720,18 @@ c_parser_generic_selection (c_parser *parser)
 
       if (assoc.type == NULL_TREE)
 	{
-	  if (!match_found)
+	  if (match_found < 0)
 	    {
 	      matched_assoc = assoc;
-	      match_found = true;
+	      match_found = associations.length ();
 	    }
 	}
       else if (comptypes (assoc.type, selector_type))
 	{
-	  if (!match_found || matched_assoc.type == NULL_TREE)
+	  if (match_found < 0 || matched_assoc.type == NULL_TREE)
 	    {
 	      matched_assoc = assoc;
-	      match_found = true;
+	      match_found = associations.length ();
 	    }
 	  else
 	    {
@@ -7748,13 +7749,19 @@ c_parser_generic_selection (c_parser *parser)
       c_parser_consume_token (parser);
     }
 
+  unsigned int ix;
+  struct c_generic_association *iter;
+  FOR_EACH_VEC_ELT (associations, ix, iter)
+    if (ix != (unsigned) match_found)
+      mark_exp_read (iter->expression.value);
+
   if (!parens.require_close (parser))
     {
       c_parser_skip_until_found (parser, CPP_CLOSE_PAREN, NULL);
       return error_expr;
     }
 
-  if (!match_found)
+  if (match_found < 0)
     {
       error_at (selector_loc, "%<_Generic%> selector of type %qT is not "
 		"compatible with any association",
diff --git a/gcc/testsuite/gcc.dg/Wunused-var-4.c b/gcc/testsuite/gcc.dg/Wunused-var-4.c
new file mode 100644
index 00000000000..08ddcf4407e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/Wunused-var-4.c
@@ -0,0 +1,33 @@
+/* PR c/96571 */
+/* { dg-do compile } */
+/* { dg-options "-std=c99 -O2 -Wunused-but-set-variable" } */
+
+enum E { V };
+
+int
+foo (void)
+{
+  enum E v;				/* { dg-bogus "set but not used" } */
+  return _Generic (v, enum E : 0);
+}
+
+int
+bar (void)
+{
+  int a = 0;				/* { dg-bogus "set but not used" } */
+  return _Generic (0, int : a);
+}
+
+int
+baz (void)
+{
+  int a;				/* { dg-bogus "set but not used" } */
+  return _Generic (0, long long : a, int : 0);
+}
+
+int
+qux (void)
+{
+  int a;				/* { dg-bogus "set but not used" } */
+  return _Generic (0, long long : a, default: 0);
+}

commit 5378a7496db299c06f3be72a2db2eab280f29dbb
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Aug 25 13:49:40 2020 +0200

    gimple: Ignore *0 = {CLOBBER} in path isolation [PR96722]
    
    Clobbers of MEM_REF with NULL address are just fancy nops, something we just
    ignore and don't emit any code for it (ditto for other clobbers), they just
    mark end of life on something, so we shouldn't infer from those that there
    is some UB.
    
    2020-08-25  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/96722
            * gimple.c (infer_nonnull_range): Formatting fix.
            (infer_nonnull_range_by_dereference): Return false for clobber stmts.
    
            * g++.dg/opt/pr96722.C: New test.
    
    (cherry picked from commit a5b15fcb954ba63d58f0daa700281aba33b5f24a)

diff --git a/gcc/gimple.c b/gcc/gimple.c
index 9dc4911a36e..18fc2f86a69 100644
--- a/gcc/gimple.c
+++ b/gcc/gimple.c
@@ -2782,8 +2782,8 @@ check_loadstore (gimple *, tree op, tree, void *data)
 bool
 infer_nonnull_range (gimple *stmt, tree op)
 {
-  return infer_nonnull_range_by_dereference (stmt, op)
-    || infer_nonnull_range_by_attribute (stmt, op);
+  return (infer_nonnull_range_by_dereference (stmt, op)
+	  || infer_nonnull_range_by_attribute (stmt, op));
 }
 
 /* Return true if OP can be inferred to be non-NULL after STMT
@@ -2795,7 +2795,8 @@ infer_nonnull_range_by_dereference (gimple *stmt, tree op)
      non-NULL if -fdelete-null-pointer-checks is enabled.  */
   if (!flag_delete_null_pointer_checks
       || !POINTER_TYPE_P (TREE_TYPE (op))
-      || gimple_code (stmt) == GIMPLE_ASM)
+      || gimple_code (stmt) == GIMPLE_ASM
+      || gimple_clobber_p (stmt))
     return false;
 
   if (walk_stmt_load_store_ops (stmt, (void *)op,
diff --git a/gcc/testsuite/g++.dg/opt/pr96722.C b/gcc/testsuite/g++.dg/opt/pr96722.C
new file mode 100644
index 00000000000..408dfeea8a0
--- /dev/null
+++ b/gcc/testsuite/g++.dg/opt/pr96722.C
@@ -0,0 +1,20 @@
+// PR tree-optimization/96722
+// { dg-do run }
+// { dg-options "-O2" }
+
+struct S { int s; ~S () {} };
+
+void
+foo (S *a)
+{
+  if (a)
+    return;
+  a->~S ();
+}
+
+int
+main ()
+{
+  S s;
+  foo (&s);
+}

commit 36290fcee3b6f1bb71dad0aaba7a68e71d825b74
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Aug 26 10:30:15 2020 +0200

    dwarf2out: Fix up dwarf2out_next_real_insn caching [PR96729]
    
    The addition of NOTE_INSN_BEGIN_STMT and NOTE_INSN_INLINE_ENTRY notes
    reintroduced quadratic behavior into dwarf2out_var_location.
    This function needs to know the next real instruction to which the var
    location note applies, but the way final_scan_insn is called outside of
    final.c main loop doesn't make it easy to look up the next real insn in
    there (and for non-dwarf it is even useless).  Usually next real insn is
    only a few notes away, but we can have hundreds of thousands of consecutive
    notes only followed by a real insn.  dwarf2out_var_location to avoid the
    quadratic behavior contains a cache, it remembers the next note and when it
    is called again on that loc_note, it can use the previously computed
    dwarf2out_next_real_insn result, rather than walking the insn chain once
    again.  But, for NOTE_INSN_{BEGIN_STMT,INLINE_ENTRY} dwarf2out_var_location
    is not called while the code puts into the cache those notes, which means if
    we have e.g. in the worst case NOTE_INSN_VAR_LOCATION and
    NOTE_INSN_BEGIN_STMT notes alternating, the cache is not really used.
    
    The following patch fixes it by looking up the next NOTE_INSN_VAR_LOCATION
    if any.  While the lookup could be perhaps done together with looking for
    the next real insn once (e.g. in dwarf2out_next_real_insn or its copy),
    there are other dwarf2out_next_real_insn callers which don't need/want that
    behavior and if there are more than two NOTE_INSN_VAR_LOCATION notes
    followed by the same real insn, we need to do that "find next
    NOTE_INSN_VAR_LOCATION" walk anyway.
    
    On the testcase from the PR this patch speeds it 2.8times, from 0m0.674s
    to 0m0.236s (why it takes for the reporter more than 60s is unknown).
    
    2020-08-26  Jakub Jelinek  <jakub@redhat.com>
    
            PR debug/96729
            * dwarf2out.c (dwarf2out_next_real_insn): Adjust function comment.
            (dwarf2out_var_location): Look for next_note only if next_real is
            non-NULL, in that case look for the first non-deleted
            NOTE_INSN_VAR_LOCATION between loc_note and next_real, if any.
    
    (cherry picked from commit ca1afa261d03c9343dff1208325f87d9ba69ec7a)

diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index 63a56609cef..467de650394 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -27204,7 +27204,7 @@ static bool maybe_at_text_label_p = true;
 /* One above highest N where .LVLN label might be equal to .Ltext0 label.  */
 static unsigned int first_loclabel_num_not_at_text_label;
 
-/* Look ahead for a real insn, or for a begin stmt marker.  */
+/* Look ahead for a real insn.  */
 
 static rtx_insn *
 dwarf2out_next_real_insn (rtx_insn *loc_note)
@@ -27229,7 +27229,7 @@ dwarf2out_var_location (rtx_insn *loc_note)
 {
   char loclabel[MAX_ARTIFICIAL_LABEL_BYTES + 2];
   struct var_loc_node *newloc;
-  rtx_insn *next_real, *next_note;
+  rtx_insn *next_real;
   rtx_insn *call_insn = NULL;
   static const char *last_label;
   static const char *last_postcall_label;
@@ -27254,7 +27254,6 @@ dwarf2out_var_location (rtx_insn *loc_note)
 	      var_loc_p = false;
 
 	      next_real = dwarf2out_next_real_insn (call_insn);
-	      next_note = NULL;
 	      cached_next_real_insn = NULL;
 	      goto create_label;
 	    }
@@ -27282,7 +27281,6 @@ dwarf2out_var_location (rtx_insn *loc_note)
 		  var_loc_p = false;
 
 		  next_real = dwarf2out_next_real_insn (call_insn);
-		  next_note = NULL;
 		  cached_next_real_insn = NULL;
 		  goto create_label;
 		}
@@ -27311,22 +27309,28 @@ dwarf2out_var_location (rtx_insn *loc_note)
 	next_real = NULL;
     }
 
-  next_note = NEXT_INSN (loc_note);
-  if (! next_note
-      || next_note->deleted ()
-      || ! NOTE_P (next_note)
-      || (NOTE_KIND (next_note) != NOTE_INSN_VAR_LOCATION
-	  && NOTE_KIND (next_note) != NOTE_INSN_BEGIN_STMT
-	  && NOTE_KIND (next_note) != NOTE_INSN_INLINE_ENTRY))
-    next_note = NULL;
-
   if (! next_real)
     next_real = dwarf2out_next_real_insn (loc_note);
 
-  if (next_note)
+  if (next_real)
     {
-      expected_next_loc_note = next_note;
-      cached_next_real_insn = next_real;
+      rtx_insn *next_note = NEXT_INSN (loc_note);
+      while (next_note != next_real)
+	{
+	  if (! next_note->deleted ()
+	      && NOTE_P (next_note)
+	      && NOTE_KIND (next_note) == NOTE_INSN_VAR_LOCATION)
+	    break;
+	  next_note = NEXT_INSN (next_note);
+	}
+
+      if (next_note == next_real)
+	cached_next_real_insn = NULL;
+      else
+	{
+	  expected_next_loc_note = next_note;
+	  cached_next_real_insn = next_real;
+	}
     }
   else
     cached_next_real_insn = NULL;

commit 550a13d7163a480aa6158bae54dfd080995884d9
Author: Segher Boessenkool <segher@kernel.crashing.org>
Date:   Fri Apr 24 13:33:14 2020 +0000

    rs6000: Properly handle LE index munging in vec_shr (PR94710)
    
    The PR shows the compiler crashing with -mvsx -mlittle -O0.  This turns
    out to be caused by a failure to make of the higher bits in an index
    endian conversion.
    
    2020-04-24  Segher Boessenkool  <segher@kernel.crashing.org>
    
            PR target/94710
            * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little
            endian byteshift_val calculation.
    
    (cherry picked from commit 9c725245beed2f056b67f5dc218fef6cb869c5f2)

diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 21743c6be26..fa9c1616634 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -1227,7 +1227,8 @@
   emit_move_insn (zero_reg, CONST0_RTX (<MODE>mode));
   if (!BYTES_BIG_ENDIAN)
     {
-      byteshift_val = 16 - byteshift_val;
+      /* Note, byteshift_val can be 0!  */
+      byteshift_val = -byteshift_val & 15;
       op1 = zero_reg;
       op2 = operands[1];
     }

commit e991bd1ecd85b421ce6fc9364e66068e293e3f00
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Sep 18 00:17:58 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7275a7d4567..8a21aac9b0e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,598 @@
+2020-09-17  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	Backported from master:
+	2020-04-24  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/94710
+	* config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little
+	endian byteshift_val calculation.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-26  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/96729
+	* dwarf2out.c (dwarf2out_next_real_insn): Adjust function comment.
+	(dwarf2out_var_location): Look for next_note only if next_real is
+	non-NULL, in that case look for the first non-deleted
+	NOTE_INSN_VAR_LOCATION between loc_note and next_real, if any.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-25  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/96722
+	* gimple.c (infer_nonnull_range): Formatting fix.
+	(infer_nonnull_range_by_dereference): Return false for clobber stmts.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-08  Jakub Jelinek  <jakub@redhat.com>
+
+	PR fortran/93553
+	* tree-nested.c (convert_nonlocal_omp_clauses): For
+	OMP_CLAUSE_REDUCTION, OMP_CLAUSE_LASTPRIVATE and OMP_CLAUSE_LINEAR
+	save info->new_local_var_chain around walks of the clause gimple
+	sequences and declare_vars if needed into the sequence.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-07-15  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/96174
+	* config/i386/avx512fintrin.h (_mm512_cmpeq_pd_mask,
+	_mm512_mask_cmpeq_pd_mask, _mm512_cmplt_pd_mask,
+	_mm512_mask_cmplt_pd_mask, _mm512_cmple_pd_mask,
+	_mm512_mask_cmple_pd_mask, _mm512_cmpunord_pd_mask,
+	_mm512_mask_cmpunord_pd_mask, _mm512_cmpneq_pd_mask,
+	_mm512_mask_cmpneq_pd_mask, _mm512_cmpnlt_pd_mask,
+	_mm512_mask_cmpnlt_pd_mask, _mm512_cmpnle_pd_mask,
+	_mm512_mask_cmpnle_pd_mask, _mm512_cmpord_pd_mask,
+	_mm512_mask_cmpord_pd_mask, _mm512_cmpeq_ps_mask,
+	_mm512_mask_cmpeq_ps_mask, _mm512_cmplt_ps_mask,
+	_mm512_mask_cmplt_ps_mask, _mm512_cmple_ps_mask,
+	_mm512_mask_cmple_ps_mask, _mm512_cmpunord_ps_mask,
+	_mm512_mask_cmpunord_ps_mask, _mm512_cmpneq_ps_mask,
+	_mm512_mask_cmpneq_ps_mask, _mm512_cmpnlt_ps_mask,
+	_mm512_mask_cmpnlt_ps_mask, _mm512_cmpnle_ps_mask,
+	_mm512_mask_cmpnle_ps_mask, _mm512_cmpord_ps_mask,
+	_mm512_mask_cmpord_ps_mask): Move outside of __OPTIMIZE__ guarded
+	section.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-07-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/95857
+	* tree-cfg.c (group_case_labels_stmt): When removing an unreachable
+	base_bb, remember all forced and non-local labels on it and later
+	treat those as if they have NULL label_to_block.  Formatting fix.
+	Fix a comment typo.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-14  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/95108
+	* omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member.
+	(ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in
+	entry block if info->after_stmt is NULL, otherwise add after that stmt
+	and update it after adding each stmt.
+	(ipa_simd_modify_function_body): Initialize info.after_stmt.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-13  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/95080
+	* cfgrtl.c (purge_dead_edges): Skip over debug and note insns even
+	if the last insn is a note.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94950
+	* config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use
+	TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/94873
+	* combine.c (combine_instructions): Don't optimize using REG_EQUAL
+	note if SET_SRC (set) has side-effects.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-02  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/tilegx/tilegx.md
+	(insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>): Use <I124MODE:n>
+	rather than just <n>.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-29  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94832
+	* config/i386/avx512bwintrin.h (_mm512_alignr_epi8,
+	_mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands
+	used in casts into parens.
+	* config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph,
+	_mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph,
+	_mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph,
+	_mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask,
+	_mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask,
+	_mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask,
+	_mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise.
+	* config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8,
+	_mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8,
+	_mm256_mask_cmp_epu8_mask): Likewise.
+	* config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph,
+	_mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise.
+	* config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise.
+	* config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-29  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94832
+	* config/i386/avx2intrin.h (_mm_mask_i32gather_pd,
+	_mm256_mask_i32gather_pd, _mm_mask_i64gather_pd,
+	_mm256_mask_i64gather_pd, _mm_mask_i32gather_ps,
+	_mm256_mask_i32gather_ps, _mm_mask_i64gather_ps,
+	_mm256_mask_i64gather_ps, _mm_i32gather_epi64,
+	_mm_mask_i32gather_epi64, _mm256_i32gather_epi64,
+	_mm256_mask_i32gather_epi64, _mm_i64gather_epi64,
+	_mm_mask_i64gather_epi64, _mm256_i64gather_epi64,
+	_mm256_mask_i64gather_epi64, _mm_i32gather_epi32,
+	_mm_mask_i32gather_epi32, _mm256_i32gather_epi32,
+	_mm256_mask_i32gather_epi32, _mm_i64gather_epi32,
+	_mm_mask_i64gather_epi32, _mm256_i64gather_epi32,
+	_mm256_mask_i64gather_epi32): Surround macro parameter uses with
+	parens.
+	(_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd,
+	_mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps,
+	_mm_i64gather_ps, _mm256_i64gather_ps): Likewise.  Don't use
+	as mask vector containing -1.0 or -1.0f elts, but instead vector
+	with all bits set using _mm*_cmpeq_p? with zero operands.
+	* config/i386/avx512fintrin.h (_mm512_i32gather_ps,
+	_mm512_mask_i32gather_ps, _mm512_i32gather_pd,
+	_mm512_mask_i32gather_pd, _mm512_i64gather_ps,
+	_mm512_mask_i64gather_ps, _mm512_i64gather_pd,
+	_mm512_mask_i64gather_pd, _mm512_i32gather_epi32,
+	_mm512_mask_i32gather_epi32, _mm512_i32gather_epi64,
+	_mm512_mask_i32gather_epi64, _mm512_i64gather_epi32,
+	_mm512_mask_i64gather_epi32, _mm512_i64gather_epi64,
+	_mm512_mask_i64gather_epi64, _mm512_i32scatter_ps,
+	_mm512_mask_i32scatter_ps, _mm512_i32scatter_pd,
+	_mm512_mask_i32scatter_pd, _mm512_i64scatter_ps,
+	_mm512_mask_i64scatter_ps, _mm512_i64scatter_pd,
+	_mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32,
+	_mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64,
+	_mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32,
+	_mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64,
+	_mm512_mask_i64scatter_epi64): Surround macro parameter uses with
+	parens.
+	* config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd,
+	_mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd,
+	_mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd,
+	_mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd,
+	_mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd,
+	_mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd,
+	_mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd,
+	_mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd,
+	_mm512_mask_prefetch_i64scatter_ps): Likewise.
+	* config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps,
+	_mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd,
+	_mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps,
+	_mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd,
+	_mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32,
+	_mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64,
+	_mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32,
+	_mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64,
+	_mm_mmask_i64gather_epi64, _mm256_i32scatter_ps,
+	_mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps,
+	_mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd,
+	_mm_mask_i32scatter_pd, _mm256_i64scatter_ps,
+	_mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps,
+	_mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd,
+	_mm_mask_i64scatter_pd, _mm256_i32scatter_epi32,
+	_mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32,
+	_mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64,
+	_mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64,
+	_mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32,
+	_mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32,
+	_mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64,
+	_mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64,
+	_mm_mask_i64scatter_epi64): Likewise.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-29  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94826
+	* config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use
+	TARGET_EXPR instead of MODIFY_EXPR for first assignment to
+	fenv_var, fenv_clear and old_fenv variables.  For fenv_addr
+	take address of TARGET_EXPR of fenv_var with void_node initializer.
+	Formatting fixes.
+
+2020-09-17  Haijian Zhang  <z.zhanghaijian@huawei.com>
+
+	Backported from master:
+	2020-04-29  Haijian Zhang  <z.zhanghaijian@huawei.com>
+
+	PR target/94820
+	* config/aarch64/aarch64-builtins.c
+	(aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of
+	MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and
+	new_fenv_var.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-28  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94809
+	* tree.c (build_call_expr_internal_loc_array): Call
+	process_call_operands.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-27  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94780
+	* config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use
+	TARGET_EXPR instead of MODIFY_EXPR for first assignment to
+	sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-23  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94710
+	* optabs.c (expand_vec_perm_const): For shift_amt const0_rtx
+	just return v2.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-23  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/94705
+	* attribs.c (decl_attribute): Don't diagnose attribute exclusions
+	if last_decl is error_mark_node or has such a TREE_TYPE.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-21  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/94641
+	* stor-layout.c (place_field, finalize_record_size): Don't emit
+	-Wpadded warning on TYPE_ARTIFICIAL rli->t.
+	* ubsan.c (ubsan_get_type_descriptor_type,
+	ubsan_get_source_location_type, ubsan_create_data): Set
+	TYPE_ARTIFICIAL.
+	* asan.c (asan_global_struct): Likewise.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/94618
+	* cfgrtl.c (delete_insn_and_edges): Set purge not just when
+	insn is the BB_END of its block, but also when it is only followed
+	by DEBUG_INSNs in its block.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-08  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94524
+	* tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
+	negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
+	op1 rather than op1 itself at the end.  Punt for signed modulo by
+	most negative constant.
+	* tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
+	modulo by most negative constant.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-08  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94438
+	* config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
+	1, 2, 4 and 8.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94509
+	* config/i386/i386.c (expand_vec_perm_pshufb): Fix the check
+	for inter-lane permutation for 64-byte modes.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94488
+	* config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
+	ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
+	Assume it is a REG after that instead of testing it and doing FAIL
+	otherwise.  Formatting fix.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Hannes Domani  <ssbssa@yahoo.de>
+		    Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/94459
+	* dwarf2out.c (gen_subprogram_die): Look through references, pointers,
+	arrays, pointer-to-members, function types and qualifiers when
+	checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
+	to emit type again on definition.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94460
+	* config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
+	avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
+	second half of first lane from first lane of second operand and
+	first half of second lane from second lane of first operand.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/94423
+	* tree-object-size.c (pass_object_sizes::execute): Don't call
+	replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
+	call replace_call_with_value.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Marc Glisse  <marc.glisse@inria.fr>
+		    Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/94412
+	* fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
+	ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/93069
+	* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
+	<store_mask_constraint> instead of m in output operand constraint.
+	(vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
+	%{%3%}.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94329
+	* tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
+	on the last stmt in a bb, make sure gsi_prev isn't done immediately
+	after gsi_last_bb.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/94303
+	* varasm.c (output_constructor_array_range): If local->index
+	RANGE_EXPR doesn't start at the current location in the constructor,
+	skip needed number of bytes using assemble_zeros or assert we don't
+	go backwards.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Richard Biener  <rguenther@suse.de>
+		    Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/94283
+	* tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/94283
+	* tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
+	GF_PLF_2, but don't add them to worklist.  Don't add an assigment to
+	worklist or set GF_PLF_2 just because it is used in a debug stmt in
+	another bb.  Formatting improvements.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94211
+	* tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
+	instead of estimate_num_insns for bb_seq (middle_bb).  Rename
+	emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
+	all uses.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/94167
+	* tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
+	DEBUG_STMTs.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/93566
+	* tree-nested.c (convert_nonlocal_omp_clauses,
+	convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
+	with C/C++ array sections.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94121
+	* config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
+	instead of GEN_INT.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	* doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
+	ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
+	and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
+	* doc/tm.texi: Regenerated.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94130
+	* tree-ssa-dse.c: Include gimplify.h.
+	(increment_start_addr): If stmt has lhs, drop the lhs from call and
+	set it after the call to the original value of the first argument.
+	Formatting fixes.
+	(decrement_count): Formatting fix.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94134
+	* config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
+	at the start to switch to data section.  Don't print extra newline if
+	.globl directive has not been emitted.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94121
+	* config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
+	instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/94111
+	* dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
+	is rvc_normal, otherwise use real_to_decimal to print the number to
+	string.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94114
+	* tree-loop-distribution.c (generate_memset_builtin): Call
+	rewrite_to_non_trapping_overflow even on mem.
+	(generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
+	on dest and src.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/93399
+	* tree-pretty-print.h (pretty_print_string): Declare.
+	* tree-pretty-print.c (pretty_print_string): Remove forward
+	declaration, no longer static.  Change nbytes parameter type
+	from unsigned to size_t.
+	* print-rtl.c (print_value) <case CONST_STRING>: Use
+	pretty_print_string and for shrink way too long strings.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/93888
+	* tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-05  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94046
+	* config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
+	SRC and MASK arguments to __m128 from __m128d.
+	(_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
+	from __m256d.
+	(_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
+	from __m128d.
+	* config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
+	argument to __m128i from __m128d.
+	(_mm256_permute2_pd): Fix first cast of C argument to __m256i from
+	__m256d.
+	(_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
+	(_mm256_permute2_ps): Fix first cast of C argument to __m256i from
+	__m256.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-03  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/94002
+	* explow.c (plus_constant): Punt if cst has VOIDmode and
+	get_pool_mode is different from mode.
+
 2020-09-16  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	PR target/96139
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index fae3fa1fac6..1900f8394ad 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200917
+20200918
diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index dbe7441d7a0..7eb77fb06d3 100644
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,23 @@
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-11  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/96545
+	* c-common.c (get_atomic_generic_size): Require that first argument's
+	type points to a complete type and use tree_fits_uhwi_p instead of
+	just INTEGER_CST TREE_CODE check for the TYPE_SIZE_UNIT.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-06-27  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/95903
+	* c-common.c (pointer_int_sum): Use TYPE_OVERFLOW_UNDEFINED instead of
+	!TYPE_UNSIGNED check to see if we can apply distributive law and handle
+	smaller precision intop operands separately.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index 0fc2d97f1d8..453582ed75a 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,44 @@
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-18  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/96571
+	* c-parser.c (c_parser_generic_selection): Change match_found from bool
+	to int, holding index of the match.  Call mark_exp_read on the selector
+	expression and on expressions other than the selected one.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/94842
+	* c-decl.c (set_labels_context_r): In addition to context-less
+	LABEL_DECLs adjust also LABEL_DECLs with context equal to
+	parent function if any.
+	(store_parm_decls): Adjust comment.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/94172
+	* c-tree.h (C_TYPE_INCOMPLETE_VARS): Define to TYPE_LANG_SLOT_1
+	instead of TYPE_VFIELD, and support it on {RECORD,UNION,ENUMERAL}_TYPE.
+	(TYPE_ACTUAL_ARG_TYPES): Check that it is only used on FUNCTION_TYPEs.
+	* c-decl.c (pushdecl): Push C_TYPE_INCOMPLETE_VARS also to
+	ENUMERAL_TYPEs.
+	(finish_incomplete_vars): New function, moved from finish_struct.  Use
+	relayout_decl instead of layout_decl.
+	(finish_struct): Remove obsolete comment about C_TYPE_INCOMPLETE_VARS
+	being TYPE_VFIELD.  Use finish_incomplete_vars.
+	(finish_enum): Clear C_TYPE_INCOMPLETE_VARS.  Call
+	finish_incomplete_vars.
+	* c-typeck.c (c_build_qualified_type): Clear C_TYPE_INCOMPLETE_VARS
+	also on ENUMERAL_TYPEs.
+
 2020-03-04  Release Manager
 
 	* GCC 8.4.0 released.
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 311cc43936d..d2396105afa 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,75 @@
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-28  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/95328
+	* decl.c (cp_finish_decomp): Call complete_type before checking
+	COMPLETE_TYPE_P.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/94951
+	* typeck.c (cp_strict_aliasing_warning): New function.
+	(cp_build_indirect_ref_1, build_reinterpret_cast_1): Use
+	it instead of strict_aliasing_warning.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-24  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/94742
+	* semantics.c (finish_call_expr): When looking if all overloads
+	are noreturn, use STRIP_TEMPLATE to look through TEMPLATE_DECLs.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/94571
+	* parser.c (cp_parser_simple_declaration): Fix up a pasto in
+	diagnostics.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-08  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/94325
+	* decl.c (begin_destructor_body): For CLASSTYPE_VBASECLASSES class
+	dtors, if CLASSTYPE_PRIMARY_BINFO is non-NULL, but not BINFO_VIRTUAL_P,
+	look at CLASSTYPE_PRIMARY_BINFO of its BINFO_TYPE if it is not
+	BINFO_VIRTUAL_P, and so on.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/93931
+	* parser.c (cp_parser_omp_var_list_no_open): Call process_outer_var_ref
+	on outer_automatic_var_p decls.
+	* cp-gimplify.c (cxx_omp_disregard_value_expr): Return true also for
+	capture proxy decls.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/90995
+	* parser.c (cp_parser_enum_specifier): Use temp_override for
+	parser->colon_corrects_to_scope_p, replace goto out with return.
+	If scoped enum or enum with underlying type is not followed by
+	{ or ;, call cp_parser_commit_to_tentative_parse before calling
+	cp_parser_error and make sure to return error_mark_node instead of
+	NULL_TREE.  Formatting fixes.
+
 2020-05-25  Jason Merrill  <jason@redhat.com>
 
 	PR c++/90749
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 1e3dbccdb25..406351bee17 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,381 @@
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-25  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/96722
+	* g++.dg/opt/pr96722.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-18  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/96571
+	* gcc.dg/Wunused-var-4.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-11  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/96545
+	* c-c++-common/pr96545.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-07-15  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/96174
+	* gcc.target/i386/avx512f-vcmppd-3.c: New test.
+	* gcc.target/i386/avx512f-vcmpps-3.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-07-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/95857
+	* gcc.dg/pr95857.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-06-27  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/95903
+	* c-c++-common/pr95903.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-28  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/95328
+	* g++.dg/cpp1z/decomp53.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-14  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/95108
+	* gcc.dg/gomp/pr95108.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-13  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/95080
+	* g++.dg/opt/pr95080.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/94951
+	* g++.dg/warn/Wstrict-aliasing-bogus-tmpl.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/94873
+	* gcc.dg/pr94873.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-05-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/94842
+	* gcc.dg/pr94842.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-28  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94809
+	* gcc.c-torture/execute/pr94809.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-27  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94780
+	* gcc.dg/pr94780.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-24  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/94742
+	* g++.dg/warn/Wreturn-type-12.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-23  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/94705
+	* gcc.dg/pr94705.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-21  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/94641
+	* c-c++-common/ubsan/pr94641.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/94618
+	* g++.dg/opt/pr94618.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/94571
+	* g++.dg/cpp1z/decomp51.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-08  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94524
+	* gcc.c-torture/execute/pr94524-1.c: New test.
+	* gcc.c-torture/execute/pr94524-2.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-08  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94438
+	* gcc.target/i386/avx512bw-pr94438.c: New test.
+	* gcc.target/i386/avx512vlbw-pr94438.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-08  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/94325
+	* g++.dg/ubsan/vptr-15.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94509
+	* gcc.target/i386/avx512bw-pr94509-1.c: New test.
+	* gcc.target/i386/avx512bw-pr94509-2.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94488
+	* gcc.c-torture/compile/pr94488.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Hannes Domani  <ssbssa@yahoo.de>
+		    Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/94459
+	* g++.dg/debug/pr94459.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94460
+	* gcc.target/i386/avx2-pr94460.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/94423
+	* gcc.dg/ubsan/pr94423.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Marc Glisse  <marc.glisse@inria.fr>
+		    Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/94412
+	* gcc.c-torture/execute/pr94412.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/93069
+	* gcc.target/i386/avx512vl-pr93069.c: New test.
+	* gcc.dg/vect/pr93069.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94329
+	* gfortran.dg/pr94329.f90: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/94303
+	* g++.dg/torture/pr94303.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Richard Biener  <rguenther@suse.de>
+		    Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/94283
+	* gcc.dg/pr94283.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/94283
+	* gcc.target/i386/pr94283.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94211
+	* gcc.dg/pr94211.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/94172
+	* gcc.dg/pr94172-1.c: New test.
+	* gcc.dg/pr94172-2.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/90995
+	* g++.dg/cpp0x/enum40.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/94167
+	* gcc.dg/pr94167.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94130
+	* gcc.c-torture/execute/pr94130.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94134
+	* gcc.c-torture/execute/pr94134.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94121
+	* gcc.dg/pr94121.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/94111
+	* gcc.dg/dfp/pr94111.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/94114
+	* gcc.dg/pr94114.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/93399
+	* gcc.dg/pr93399.c: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/93888
+	* g++.dg/guality/pr93888.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-05  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94046
+	* g++.dg/ext/pr94046-1.C: New test.
+	* g++.dg/ext/pr94046-2.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-03  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/94002
+	* gcc.dg/pr94002.c: New test.
+
 2020-09-16  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	PR target/96139
diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 1490061187f..9bc4ac32fdd 100644
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,28 @@
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-08-08  Jakub Jelinek  <jakub@redhat.com>
+		    Tobias Burnus  <tobias@codesourcery.com>
+
+	PR fortran/93553
+	* testsuite/libgomp.fortran/pr93553.f90: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-04-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/93931
+	* testsuite/libgomp.c++/pr93931.C: New test.
+
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/93566
+	* testsuite/libgomp.c/pr93566.c: New test.
+
 2020-06-04  Thomas Schwinge  <thomas@codesourcery.com>
 
 	* testsuite/libgomp.oacc-fortran/error_stop-1.f: Initialize before
diff --git a/maintainer-scripts/ChangeLog b/maintainer-scripts/ChangeLog
index 229b644a9d7..7af39391960 100644
--- a/maintainer-scripts/ChangeLog
+++ b/maintainer-scripts/ChangeLog
@@ -1,3 +1,11 @@
+2020-09-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-03-17  Jakub Jelinek  <jakub@redhat.com>
+
+	* gcc_release (upload_files): Without -l, pass -m 755 to the mkdir
+	command invoked through ssh.
+
 2020-03-04  Jakub Jelinek  <jakub@redhat.com>
 
 	* gcc_release: Add support for -b local-git-repo argument.

commit bbb72c2ccc271541e0d1feb25d2256d47041df59
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Wed Apr 29 11:51:38 2020 +0100

    arm: Extend the PR94780 fix to arm
    
    Essentially the same fix as for x86.
    
    2020-04-29  Richard Sandiford  <richard.sandiford@arm.com>
    
    gcc/
            * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
            TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
            fenv_var and new_fenv_var.
    
    (cherry picked from commit 1d7ead9cba91533291e0048d22b711ca124e19de)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8a21aac9b0e..9d11b8a47e6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-29  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
+	TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
+	fenv_var and new_fenv_var.
+
 2020-09-17  Segher Boessenkool  <segher@kernel.crashing.org>
 
 	Backported from master:
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 183a7b907f6..48500bca825 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -3260,8 +3260,9 @@ arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
   mask = build_int_cst (unsigned_type_node,
 			~((ARM_FE_ALL_EXCEPT << ARM_FE_EXCEPT_SHIFT)
 			  | ARM_FE_ALL_EXCEPT));
-  ld_fenv = build2 (MODIFY_EXPR, unsigned_type_node,
-		    fenv_var, build_call_expr (get_fpscr, 0));
+  ld_fenv = build4 (TARGET_EXPR, unsigned_type_node,
+		    fenv_var, build_call_expr (get_fpscr, 0),
+		    NULL_TREE, NULL_TREE);
   masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask);
   hold_fnclex = build_call_expr (set_fpscr, 1, masked_fenv);
   *hold = build2 (COMPOUND_EXPR, void_type_node,
@@ -3282,8 +3283,8 @@ arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
        __atomic_feraiseexcept (new_fenv_var);  */
 
   new_fenv_var = create_tmp_var_raw (unsigned_type_node);
-  reload_fenv = build2 (MODIFY_EXPR, unsigned_type_node, new_fenv_var,
-			build_call_expr (get_fpscr, 0));
+  reload_fenv = build4 (TARGET_EXPR, unsigned_type_node, new_fenv_var,
+			build_call_expr (get_fpscr, 0), NULL_TREE, NULL_TREE);
   restore_fnenv = build_call_expr (set_fpscr, 1, fenv_var);
   atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
   update_call = build_call_expr (atomic_feraiseexcept, 1,

commit 87ae45cdbd7b70a4c92d5137552228ed9ad9e9e7
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Sep 16 09:42:33 2020 +0200

    store-merging: Consider also overlapping stores earlier in the by bitpos sorting [PR97053]
    
    As the testcases show, if we have something like:
      MEM <char[12]> [&b + 8B] = {};
      MEM[(short *) &b] = 5;
      _5 = *x_4(D);
      MEM <long long unsigned int> [&b + 2B] = _5;
      MEM[(char *)&b + 16B] = 88;
      MEM[(int *)&b + 20B] = 1;
    then in sort_by_bitpos the stores are almost like in the given order,
    except the first store is after the = _5; store.
    We can't coalesce the = 5; store with = _5;, because the latter is MEM_REF,
    while the former INTEGER_CST, and we can't coalesce the = _5 store with
    the = {} store because the former is MEM_REF, the latter INTEGER_CST.
    But we happily coalesce the remaining 3 stores, which is wrong, because the
    = _5; store overlaps those and is in between them in the program order.
    We already have code to deal with similar cases in check_no_overlap, but we
    deal only with the following stores in sort_by_bitpos order, not the earlier
    ones.
    
    The following patch checks also the earlier ones.  In coalesce_immediate_stores
    it computes the first one that needs to be checked (all the ones whose
    bitpos + bitsize is smaller or equal to merged_store->start don't need to be
    checked and don't need to be checked even for any following attempts because
    of the sort_by_bitpos sorting) and the end of that (that is the first store
    in the merged_store).
    
    2020-09-16  Jakub Jelinek  <jakub@redhat.com>
    
            PR tree-optimization/97053
            * gimple-ssa-store-merging.c (check_no_overlap): Add FIRST_ORDER,
            START, FIRST_EARLIER and LAST_EARLIER arguments.  Return false if
            any stores between FIRST_EARLIER inclusive and LAST_EARLIER exclusive
            has order in between FIRST_ORDER and LAST_ORDER and overlaps the to
            be merged store.
            (imm_store_chain_info::try_coalesce_bswap): Add FIRST_EARLIER argument.
            Adjust check_no_overlap caller.
            (imm_store_chain_info::coalesce_immediate_stores): Add first_earlier
            and last_earlier variables, adjust them during iterations.  Adjust
            check_no_overlap callers, call check_no_overlap even when extending
            overlapping stores by extra INTEGER_CST stores.
    
            * gcc.dg/store_merging_31.c: New test.
            * gcc.dg/store_merging_32.c: New test.
    
    (cherry picked from commit bd909071ac04e94f4b6f0baab64d0687ec55681d)

diff --git a/gcc/gimple-ssa-store-merging.c b/gcc/gimple-ssa-store-merging.c
index 52aef607ab4..dd075c98620 100644
--- a/gcc/gimple-ssa-store-merging.c
+++ b/gcc/gimple-ssa-store-merging.c
@@ -2014,7 +2014,8 @@ struct imm_store_chain_info
       }
   }
   bool terminate_and_process_chain ();
-  bool try_coalesce_bswap (merged_store_group *, unsigned int, unsigned int);
+  bool try_coalesce_bswap (merged_store_group *, unsigned int, unsigned int,
+			   unsigned int);
   bool coalesce_immediate_stores ();
   bool output_merged_store (merged_store_group *);
   bool output_merged_stores ();
@@ -2335,14 +2336,39 @@ gather_bswap_load_refs (vec<tree> *refs, tree val)
    into the group.  That way it will be its own store group and will
    not be touched.  If ALL_INTEGER_CST_P and there are overlapping
    INTEGER_CST stores, those are mergeable using merge_overlapping,
-   so don't return false for those.  */
+   so don't return false for those.
+
+   Similarly, check stores from FIRST_EARLIER (inclusive) to END_EARLIER
+   (exclusive), whether they don't overlap the bitrange START to END
+   and have order in between FIRST_ORDER and LAST_ORDER.  This is to
+   prevent merging in cases like:
+     MEM <char[12]> [&b + 8B] = {};
+     MEM[(short *) &b] = 5;
+     _5 = *x_4(D);
+     MEM <long long unsigned int> [&b + 2B] = _5;
+     MEM[(char *)&b + 16B] = 88;
+     MEM[(int *)&b + 20B] = 1;
+   The = {} store comes in sort_by_bitpos before the = 88 store, and can't
+   be merged with it, because the = _5 store overlaps these and is in between
+   them in sort_by_order ordering.  If it was merged, the merged store would
+   go after the = _5 store and thus change behavior.  */
 
 static bool
 check_no_overlap (vec<store_immediate_info *> m_store_info, unsigned int i,
-		  bool all_integer_cst_p, unsigned int last_order,
-		  unsigned HOST_WIDE_INT end)
+		  bool all_integer_cst_p, unsigned int first_order,
+		  unsigned int last_order, unsigned HOST_WIDE_INT start,
+		  unsigned HOST_WIDE_INT end, unsigned int first_earlier,
+		  unsigned end_earlier)
 {
   unsigned int len = m_store_info.length ();
+  for (unsigned int j = first_earlier; j < end_earlier; j++)
+    {
+      store_immediate_info *info = m_store_info[j];
+      if (info->order > first_order
+	  && info->order < last_order
+	  && info->bitpos + info->bitsize > start)
+	return false;
+    }
   for (++i; i < len; ++i)
     {
       store_immediate_info *info = m_store_info[i];
@@ -2363,7 +2389,8 @@ check_no_overlap (vec<store_immediate_info *> m_store_info, unsigned int i,
 bool
 imm_store_chain_info::try_coalesce_bswap (merged_store_group *merged_store,
 					  unsigned int first,
-					  unsigned int try_size)
+					  unsigned int try_size,
+					  unsigned int first_earlier)
 {
   unsigned int len = m_store_info.length (), last = first;
   unsigned HOST_WIDE_INT width = m_store_info[first]->bitsize;
@@ -2502,7 +2529,8 @@ imm_store_chain_info::try_coalesce_bswap (merged_store_group *merged_store,
   if (n.base_addr == NULL_TREE && !is_gimple_val (n.src))
     return false;
 
-  if (!check_no_overlap (m_store_info, last, false, last_order, end))
+  if (!check_no_overlap (m_store_info, last, false, first_order, last_order,
+			 merged_store->start, end, first_earlier, first))
     return false;
 
   /* Don't handle memory copy this way if normal non-bswap processing
@@ -2594,6 +2622,8 @@ imm_store_chain_info::coalesce_immediate_stores ()
 
   store_immediate_info *info;
   unsigned int i, ignore = 0;
+  unsigned int first_earlier = 0;
+  unsigned int end_earlier = 0;
 
   /* Order the stores by the bitposition they write to.  */
   m_store_info.qsort (sort_by_bitpos);
@@ -2615,6 +2645,12 @@ imm_store_chain_info::coalesce_immediate_stores ()
       if (i <= ignore)
 	continue;
 
+      while (first_earlier < end_earlier
+	     && (m_store_info[first_earlier]->bitpos
+		 + m_store_info[first_earlier]->bitsize
+		 <= merged_store->start))
+	first_earlier++;
+
       /* First try to handle group of stores like:
 	 p[0] = data >> 24;
 	 p[1] = data >> 16;
@@ -2628,7 +2664,8 @@ imm_store_chain_info::coalesce_immediate_stores ()
 	{
 	  unsigned int try_size;
 	  for (try_size = 64; try_size >= 16; try_size >>= 1)
-	    if (try_coalesce_bswap (merged_store, i - 1, try_size))
+	    if (try_coalesce_bswap (merged_store, i - 1, try_size,
+				    first_earlier))
 	      break;
 
 	  if (try_size >= 16)
@@ -2636,7 +2673,10 @@ imm_store_chain_info::coalesce_immediate_stores ()
 	      ignore = i + merged_store->stores.length () - 1;
 	      m_merged_store_groups.safe_push (merged_store);
 	      if (ignore < m_store_info.length ())
-		merged_store = new merged_store_group (m_store_info[ignore]);
+		{
+		  merged_store = new merged_store_group (m_store_info[ignore]);
+		  end_earlier = ignore;
+		}
 	      else
 		merged_store = NULL;
 	      continue;
@@ -2662,12 +2702,16 @@ imm_store_chain_info::coalesce_immediate_stores ()
 	  if (info->rhs_code == INTEGER_CST
 	      && merged_store->stores[0]->rhs_code == INTEGER_CST)
 	    {
+	      unsigned int first_order
+		= MIN (merged_store->first_order, info->order);
 	      unsigned int last_order
 		= MAX (merged_store->last_order, info->order);
 	      unsigned HOST_WIDE_INT end
 		= MAX (merged_store->start + merged_store->width,
 		       info->bitpos + info->bitsize);
-	      if (check_no_overlap (m_store_info, i, true, last_order, end))
+	      if (check_no_overlap (m_store_info, i, true, first_order,
+				    last_order, merged_store->start, end,
+				    first_earlier, end_earlier))
 		{
 		  /* check_no_overlap call above made sure there are no
 		     overlapping stores with non-INTEGER_CST rhs_code
@@ -2696,6 +2740,7 @@ imm_store_chain_info::coalesce_immediate_stores ()
 		  do
 		    {
 		      unsigned int max_order = 0;
+		      unsigned int min_order = first_order;
 		      unsigned first_nonmergeable_int_order = ~0U;
 		      unsigned HOST_WIDE_INT this_end = end;
 		      k = i;
@@ -2721,6 +2766,7 @@ imm_store_chain_info::coalesce_immediate_stores ()
 				  break;
 				}
 			      k = j;
+			      min_order = MIN (min_order, info2->order);
 			      this_end = MAX (this_end,
 					      info2->bitpos + info2->bitsize);
 			    }
@@ -2736,6 +2782,12 @@ imm_store_chain_info::coalesce_immediate_stores ()
 			    first_nonmergeable_order
 			      = MIN (first_nonmergeable_order, info2->order);
 			}
+		      if (k > i
+			  && !check_no_overlap (m_store_info, len - 1, true,
+						min_order, try_order,
+						merged_store->start, this_end,
+						first_earlier, end_earlier))
+			k = 0;
 		      if (k == 0)
 			{
 			  if (last_order == try_order)
@@ -2828,11 +2880,14 @@ imm_store_chain_info::coalesce_immediate_stores ()
 		  ? compatible_load_p (merged_store, info, base_addr, 1)
 		  : !info->ops[1].base_addr)
 	      && check_no_overlap (m_store_info, i, false,
-				   MAX (merged_store->last_order,
+				   MIN (merged_store->first_order,
 					info->order),
+				   MAX (merged_store->last_order,
+					info->order), merged_store->start,
 				   MAX (merged_store->start
 					+ merged_store->width,
-					info->bitpos + info->bitsize)))
+					info->bitpos + info->bitsize),
+				   first_earlier, end_earlier))
 	    {
 	      merged_store->merge_into (info);
 	      continue;
@@ -2851,6 +2906,7 @@ imm_store_chain_info::coalesce_immediate_stores ()
 	m_merged_store_groups.safe_push (merged_store);
 
       merged_store = new merged_store_group (info);
+      end_earlier = i;
     }
 
   /* Record or discard the last store group.  */
diff --git a/gcc/testsuite/gcc.dg/store_merging_31.c b/gcc/testsuite/gcc.dg/store_merging_31.c
new file mode 100644
index 00000000000..32c21eb053c
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/store_merging_31.c
@@ -0,0 +1,27 @@
+/* PR tree-optimization/97053 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+struct S { short a; char b[9]; int c; char d; int e; };
+
+__attribute__((noipa)) void
+foo (char *x, char *y)
+{
+  if (__builtin_strcmp (x, "ABCDXXXX") != 0
+      || __builtin_strcmp (y, "ABCDXXXX") != 0)
+    __builtin_abort ();
+}
+
+int
+main ()
+{
+  char a[9] = "XXXXXXXX";
+  struct S b = {};
+  __builtin_memcpy (a, "ABCD", 4);
+  b.a = 5;
+  __builtin_memcpy (b.b, a, 8); 
+  b.d = 'X';
+  b.e = 1;
+  foo (a, b.b);
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/store_merging_32.c b/gcc/testsuite/gcc.dg/store_merging_32.c
new file mode 100644
index 00000000000..8c90489bdeb
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/store_merging_32.c
@@ -0,0 +1,129 @@
+/* PR tree-optimization/97053 */
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-tree-dse" } */
+
+struct __attribute__((packed, may_alias)) S { long long s; };
+struct __attribute__((packed, may_alias)) T { short t; };
+
+__attribute__((noipa)) void
+test (char *p, char *q, int s)
+{
+  if ((s & 1) == 0)
+    {
+      if (*(short __attribute__((may_alias)) *) &p[sizeof (short)]
+	  != *(short __attribute__((may_alias)) *) &q[sizeof (short)]
+	  || (((struct S __attribute__((may_alias)) *) &p[1])->s
+	      != ((struct S __attribute__((may_alias)) *) &q[1])->s)
+	  || (*(short __attribute__((may_alias)) *) &p[2 * sizeof (short)]
+	      != *(short __attribute__((may_alias)) *) &q[2 * sizeof (short)]))
+	__builtin_abort ();
+    }
+  else
+    {
+      if (*(short __attribute__((may_alias)) *) &p[sizeof (short)]
+	  != *(short __attribute__((may_alias)) *) &q[sizeof (short)]
+	  || (((struct S __attribute__((may_alias)) *) &p[1])->s
+	      != ((struct S __attribute__((may_alias)) *) &q[1])->s)
+	  || (((struct T __attribute__((may_alias)) *) &p[2 * sizeof (short) - 1])->t
+	      != ((struct T __attribute__((may_alias)) *) &q[2 * sizeof (short) - 1])->t)
+	  || p[3 * sizeof (short) - 2] != q[3 * sizeof (short) - 2])
+	__builtin_abort ();
+    }
+}
+
+__attribute__((noipa)) void
+foo (long long *p, char *q, char *r, char *s)
+{
+  char a[64] __attribute__((aligned (__alignof (short))));
+  *(short __attribute__((may_alias)) *) &a[sizeof (short)] = 1;
+  ((struct S __attribute__((may_alias)) *) &a[1])->s = p[0];
+  *(short __attribute__((may_alias)) *) &a[2 * sizeof (short)] = 2;
+  *(short __attribute__((may_alias)) *) &q[sizeof (short)] = 1;
+  ((struct S __attribute__((may_alias)) *) &r[1])->s = p[0];
+  *(short __attribute__((may_alias)) *) &s[2 * sizeof (short)] = 2;
+  test (a, q, 0);
+}
+
+__attribute__((noipa)) void
+bar (long long *p, char *q, char *r, char *s, char *t)
+{
+  char a[64] __attribute__((aligned (__alignof (short))));
+  *(short __attribute__((may_alias)) *) &a[sizeof (short)] = 1;
+  ((struct S __attribute__((may_alias)) *) &a[1])->s = p[0];
+  ((struct T __attribute__((may_alias)) *) &a[2 * sizeof (short) - 1])->t = 2;
+  a[3 * sizeof (short) - 2] = 3;
+  *(short __attribute__((may_alias)) *) &q[sizeof (short)] = 1;
+  ((struct S __attribute__((may_alias)) *) &r[1])->s = p[0];
+  ((struct T __attribute__((may_alias)) *) &s[2 * sizeof (short) - 1])->t = 2;
+  t[3 * sizeof (short) - 2] = 3;
+  test (a, q, 1);
+}
+
+__attribute__((noipa)) void
+baz (long long *p, char *q, char *r, char *s)
+{
+  char a[64] __attribute__((aligned (__alignof (short))));
+  *(short __attribute__((may_alias)) *) &a[2 * sizeof (short)] = 2;
+  ((struct S __attribute__((may_alias)) *) &a[1])->s = p[0];
+  *(short __attribute__((may_alias)) *) &a[sizeof (short)] = 1;
+  *(short __attribute__((may_alias)) *) &q[2 * sizeof (short)] = 2;
+  ((struct S __attribute__((may_alias)) *) &r[1])->s = p[0];
+  *(short __attribute__((may_alias)) *) &s[sizeof (short)] = 1;
+  test (a, q, 2);
+}
+
+__attribute__((noipa)) void
+qux (long long *p, char *q, char *r, char *s, char *t)
+{
+  char a[64] __attribute__((aligned (__alignof (short))));
+  *(short __attribute__((may_alias)) *) &a[2 * sizeof (short) - 1] = 2;
+  ((struct S __attribute__((may_alias)) *) &a[1])->s = p[0];
+  a[3 * sizeof (short) - 2] = 3;
+  *(short __attribute__((may_alias)) *) &a[sizeof (short)] = 1;
+  ((struct T __attribute__((may_alias)) *) &q[2 * sizeof (short) - 1])->t = 2;
+  ((struct S __attribute__((may_alias)) *) &r[1])->s = p[0];
+  s[3 * sizeof (short) - 2] = 3;
+  ((struct T __attribute__((may_alias)) *) &t[sizeof (short)])->t = 1;
+  test (a, q, 3);
+}
+
+__attribute__((noipa)) void
+corge (long long *p, char *q, char *r, char *s, short u[3])
+{
+  char a[64] __attribute__((aligned (__alignof (short))));
+  *(short __attribute__((may_alias)) *) &a[2 * sizeof (short)] = u[2];
+  ((struct S __attribute__((may_alias)) *) &a[1])->s = p[0];
+  *(short __attribute__((may_alias)) *) &a[sizeof (short)] = u[1];
+  *(short __attribute__((may_alias)) *) &q[2 * sizeof (short)] = u[2];
+  ((struct S __attribute__((may_alias)) *) &r[1])->s = p[0];
+  *(short __attribute__((may_alias)) *) &s[sizeof (short)] = u[1];
+  test (a, q, 4);
+}
+
+__attribute__((noipa)) void
+garply (long long *p, char *q, char *r, char *s, short u[3])
+{
+  char a[64] __attribute__((aligned (__alignof (short))));
+  *(short __attribute__((may_alias)) *) &a[sizeof (short)] = u[1];
+  ((struct S __attribute__((may_alias)) *) &a[1])->s = p[0];
+  *(short __attribute__((may_alias)) *) &a[2 * sizeof (short)] = u[2];
+  *(short __attribute__((may_alias)) *) &s[sizeof (short)] = u[1];
+  ((struct S __attribute__((may_alias)) *) &r[1])->s = p[0];
+  *(short __attribute__((may_alias)) *) &q[2 * sizeof (short)] = u[2];
+  test (a, q, 6);
+}
+
+int
+main ()
+{
+  char a[64] __attribute__((aligned (__alignof (short))));
+  long long p = -1LL;
+  short u[] = { 1, 2, 3 };
+  foo (&p, &a[0], &a[0], &a[0]);
+  bar (&p, &a[0], &a[0], &a[0], &a[0]);
+  baz (&p, &a[0], &a[0], &a[0]);
+  qux (&p, &a[0], &a[0], &a[0], &a[0]);
+  corge (&p, &a[0], &a[0], &a[0], u);
+  garply (&p, &a[0], &a[0], &a[0], u);
+  return 0;
+}

commit 766493676bd8068367167f0a8de2511305d6c9a0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Sep 19 00:17:45 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9d11b8a47e6..960c3852933 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,30 @@
+2020-09-18  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-09-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/97053
+	* gimple-ssa-store-merging.c (check_no_overlap): Add FIRST_ORDER,
+	START, FIRST_EARLIER and LAST_EARLIER arguments.  Return false if
+	any stores between FIRST_EARLIER inclusive and LAST_EARLIER exclusive
+	has order in between FIRST_ORDER and LAST_ORDER and overlaps the to
+	be merged store.
+	(imm_store_chain_info::try_coalesce_bswap): Add FIRST_EARLIER argument.
+	Adjust check_no_overlap caller.
+	(imm_store_chain_info::coalesce_immediate_stores): Add first_earlier
+	and last_earlier variables, adjust them during iterations.  Adjust
+	check_no_overlap callers, call check_no_overlap even when extending
+	overlapping stores by extra INTEGER_CST stores.
+
+2020-09-18  Richard Sandiford  <richard.sandiford@arm.com>
+
+	Backported from master:
+	2020-04-29  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
+	TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
+	fenv_var and new_fenv_var.
+
 2020-04-29  Richard Sandiford  <richard.sandiford@arm.com>
 
 	* config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1900f8394ad..795f43e0fdb 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200918
+20200919
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 406351bee17..23af1fe515a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2020-09-18  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-09-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/97053
+	* gcc.dg/store_merging_31.c: New test.
+	* gcc.dg/store_merging_32.c: New test.
+
 2020-09-17  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:

commit aef149efb6d3fc97a38c74f7022124a6ba247746
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Thu Jul 2 20:48:16 2020 +0200

    PR fortran/93423 - ICE on invalid with argument list for module procedure
    
    When recovering from an error, a NULL pointer dereference could occur.
    Check for that situation and punt.
    
    gcc/fortran/
            PR fortran/93423
            * resolve.c (resolve_symbol): Avoid NULL pointer dereference.
    
    (cherry picked from commit b88744905a46be44ffa3c57d46080f601ae832b8)

diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
index 462d07351ad..be63ce50bf2 100644
--- a/gcc/fortran/resolve.c
+++ b/gcc/fortran/resolve.c
@@ -15348,7 +15348,7 @@ resolve_symbol (gfc_symbol *sym)
       if (formal)
 	{
 	  sym->formal_ns = formal->sym->ns;
-          if (sym->ns != formal->sym->ns)
+	  if (sym->formal_ns && sym->ns != formal->sym->ns)
 	    sym->formal_ns->refs++;
 	}
     }
diff --git a/gcc/testsuite/gfortran.dg/pr93423.f90 b/gcc/testsuite/gfortran.dg/pr93423.f90
new file mode 100644
index 00000000000..fed5914daba
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr93423.f90
@@ -0,0 +1,21 @@
+! { dg-do compile }
+! PR fortran/93423 - ICE on invalid with argument list for module procedure
+
+module t
+  type :: b
+   contains
+     procedure :: p => bp
+  end type b
+  interface
+     module function bp(s)
+       class(b), intent(inout) :: s
+       integer, pointer :: bp
+     end function
+  end interface
+end module t
+
+submodule (t) ts
+contains
+  module procedure bp(s) ! { dg-error "must be in a generic module interface" }
+  end procedure bp       ! { dg-error "Expecting END SUBMODULE statement" }
+end submodule ts

commit e0c7ff6237c78d99b40869afbdcdbe27fe98b698
Author: Tobias Burnus <tobias@codesourcery.com>
Date:   Thu Sep 17 14:01:09 2020 +0200

    Fortran: Avoid double-free with parse error (PR96041, PR93423)
    
    gcc/fortran/
    
            PR fortran/96041
            PR fortran/93423
            * decl.c (gfc_match_submod_proc): Avoid later double-free
            in the error case.
    
    (cherry picked from commit c12facd22881517127ebbe213d7ecc7fc1fcea4e)

diff --git a/gcc/fortran/decl.c b/gcc/fortran/decl.c
index 3d04e65015d..6249562de29 100644
--- a/gcc/fortran/decl.c
+++ b/gcc/fortran/decl.c
@@ -9460,6 +9460,15 @@ gfc_match_submod_proc (void)
 
   if (gfc_match_eos () != MATCH_YES)
     {
+      /* Unset st->n.sym. Note: in reject_statement (), the symbol changes are
+	 undone, such that the st->n.sym->formal points to the original symbol;
+	 if now this namespace is finalized, the formal namespace is freed,
+	 but it might be still needed in the parent namespace.  */
+      gfc_symtree *st = gfc_find_symtree (gfc_current_ns->sym_root, sym->name);
+      st->n.sym = NULL;
+      gfc_free_symbol (sym->tlink);
+      sym->tlink = NULL;
+      sym->refs--;
       gfc_syntax_error (ST_MODULE_PROC);
       return MATCH_ERROR;
     }

commit ec4b95d001a8fe1ff7c2aa1d560b295ea8e3edd1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Sep 20 00:17:36 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 795f43e0fdb..2225e4604f0 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200919
+20200920
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 3dac343f4d8..27d7dce2710 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,21 @@
+2020-09-19  Tobias Burnus  <tobias@codesourcery.com>
+
+	Backported from master:
+	2020-09-17  Tobias Burnus  <tobias@codesourcery.com>
+
+	PR fortran/96041
+	PR fortran/93423
+	* decl.c (gfc_match_submod_proc): Avoid later double-free
+	in the error case.
+
+2020-09-19  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-07-02  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/93423
+	* resolve.c (resolve_symbol): Avoid NULL pointer dereference.
+
 2020-07-23  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 23af1fe515a..eb5bb3cf008 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-09-19  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-07-02  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/93423
+	* gfortran.dg/pr93423.f90: New file.
+
 2020-09-18  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:

commit 4c78dccc580d475d7204ea21d19e84d4d31194ce
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Sep 21 00:17:41 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2225e4604f0..fb22edf35a9 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200920
+20200921

commit 8340a89f38932d1a8980ad9a4cb34f3bd0183b3a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Sep 22 00:17:41 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index fb22edf35a9..ca3ee10cb82 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200921
+20200922

commit 6e86f0926f8de014cb0b0218442812e9f3ea8e95
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Tue Sep 22 09:39:33 2020 +0100

    libstdc++: Use correct argument type for __use_alloc [PR 96803]
    
    The _Tuple_impl constructor for allocator-extended construction from a
    different tuple type uses the _Tuple_impl's own _Head type in the
    __use_alloc test. That is incorrect, because the argument tuple could
    have a different type. Using the wrong type might select the
    leading-allocator convention when it should use the trailing-allocator
    convention, or vice versa.
    
    This backport includes the value category fix from r11-3348.
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/96803
            * include/std/tuple
            (_Tuple_impl(allocator_arg_t, Alloc, const _Tuple_impl<U...>&)):
            Replace parameter pack with a type parameter and a pack and pass
            the first type to __use_alloc.
            * testsuite/20_util/tuple/cons/96803.cc: New test.
    
    (cherry picked from commit 5494edae83ad33c769bd1ebc98f0c492453a6417)

diff --git a/libstdc++-v3/include/std/tuple b/libstdc++-v3/include/std/tuple
index 1d0074129b1..f2d553f7035 100644
--- a/libstdc++-v3/include/std/tuple
+++ b/libstdc++-v3/include/std/tuple
@@ -271,13 +271,13 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 	  _Base(__use_alloc<_Head, _Alloc, _Head>(__a),
 	        std::forward<_Head>(_M_head(__in))) { }
 
-      template<typename _Alloc, typename... _UElements>
+      template<typename _Alloc, typename _UHead, typename... _UTails>
 	_Tuple_impl(allocator_arg_t __tag, const _Alloc& __a,
-	            const _Tuple_impl<_Idx, _UElements...>& __in)
+		    const _Tuple_impl<_Idx, _UHead, _UTails...>& __in)
 	: _Inherited(__tag, __a,
-		     _Tuple_impl<_Idx, _UElements...>::_M_tail(__in)),
-	  _Base(__use_alloc<_Head, _Alloc, _Head>(__a),
-		_Tuple_impl<_Idx, _UElements...>::_M_head(__in)) { }
+		     _Tuple_impl<_Idx, _UHead, _UTails...>::_M_tail(__in)),
+	  _Base(__use_alloc<_Head, _Alloc, const _UHead&>(__a),
+		_Tuple_impl<_Idx, _UHead, _UTails...>::_M_head(__in)) { }
 
       template<typename _Alloc, typename _UHead, typename... _UTails>
 	_Tuple_impl(allocator_arg_t __tag, const _Alloc& __a,
@@ -410,7 +410,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
       template<typename _Alloc, typename _UHead>
 	_Tuple_impl(allocator_arg_t __tag, const _Alloc& __a,
 	            const _Tuple_impl<_Idx, _UHead>& __in)
-	: _Base(__use_alloc<_Head, _Alloc, _Head>(__a),
+	: _Base(__use_alloc<_Head, _Alloc, const _UHead&>(__a),
 		_Tuple_impl<_Idx, _UHead>::_M_head(__in)) { }
 
       template<typename _Alloc, typename _UHead>
diff --git a/libstdc++-v3/testsuite/20_util/tuple/cons/96803.cc b/libstdc++-v3/testsuite/20_util/tuple/cons/96803.cc
new file mode 100644
index 00000000000..867a42150e0
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/tuple/cons/96803.cc
@@ -0,0 +1,62 @@
+// Copyright (C) 2020 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-do compile { target c++11 } }
+
+#include <tuple>
+#include <memory>
+
+struct X
+{
+  using allocator_type = std::allocator<int>;
+
+  X(X&&) { }
+  X(std::allocator_arg_t, const allocator_type&, X&&) { }
+
+  explicit X(int) { }
+  explicit X(int, allocator_type) { }
+};
+
+void
+test01()
+{
+  // PR libstdc++/96803
+  // std::tuple chooses wrong constructor for uses-allocator construction
+  std::tuple<int> o;
+  std::tuple<X> nok(std::allocator_arg, std::allocator<int>(), o);
+
+  std::tuple<int, int> oo;
+  std::tuple<X, X> nn(std::allocator_arg, std::allocator<int>(), oo);
+}
+
+struct Y
+{
+  using allocator_type = std::allocator<int>;
+
+  Y(const X&) { }
+  Y(const X&, const allocator_type&) { }
+
+  Y(X&&) { }
+  Y(std::allocator_arg_t, const allocator_type&, X&&) { }
+};
+
+void
+test02()
+{
+  std::tuple<X, X> o{1, 1};
+  std::tuple<Y, Y> oo(std::allocator_arg, std::allocator<int>(), o);
+}

commit 874bdcd54b53283a82418649ea7457c1d6804562
Author: Vlad Lazar <vlad.lazar@arm.com>
Date:   Fri Aug 31 15:00:54 2018 +0000

    [AArch64] Implement new intrinsics vabsd_s64 and vnegd_s64.
    
    gcc/
    2018-08-31  Vlad Lazar  <vlad.lazar@arm.com>
    
            PR target/71233
            * config/aarch64/arm_neon.h (vabsd_s64): New.
            (vnegd_s64): Likewise.
    
    gcc/testsuite/
    2018-08-31  Vlad Lazar  <vlad.lazar@arm.com>
    
            PR target/71233
            * gcc.target/aarch64/scalar_intrinsics.c (test_vnegd_s64): New.
            * gcc.target/aarch64/vneg_s.c (RUN_TEST_SCALAR): New.
            (test_vnegd_s64): Likewise.
            * gcc.target/aarch64/vnegd_s64.c: New.
            * gcc.target/aarch64/vabsd_s64.c: New.
    
    (cherry picked from commit 66da5b53107962a1c115a9686f2220de27f276f7)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index dd53e243b52..7bcd1e1c844 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -11822,6 +11822,18 @@ vabsq_s64 (int64x2_t __a)
   return __builtin_aarch64_absv2di (__a);
 }
 
+/* Try to avoid moving between integer and vector registers.
+   For why the cast to unsigned is needed check the vnegd_s64 intrinsic.
+   There is a testcase related to this issue:
+   gcc.target/aarch64/vabsd_s64.c.  */
+
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vabsd_s64 (int64_t __a)
+{
+  return __a < 0 ? - (uint64_t) __a : __a;
+}
+
 /* vadd */
 
 __extension__ extern __inline int64_t
@@ -23189,6 +23201,25 @@ vneg_s64 (int64x1_t __a)
   return -__a;
 }
 
+/* According to the ACLE, the negative of the minimum (signed)
+   value is itself.  This leads to a semantics mismatch, as this is
+   undefined behaviour in C.  The value range predictor is not
+   aware that the negation of a negative number can still be negative
+   and it may try to fold the expression.  See the test in
+   gcc.target/aarch64/vnegd_s64.c for an example.
+
+   The cast below tricks the value range predictor to include
+   INT64_MIN in the range it computes.  So for x in the range
+   [INT64_MIN, y] the range prediction after vnegd_s64 (x) will
+   be ~[INT64_MIN + 1, y].  */
+
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vnegd_s64 (int64_t __a)
+{
+  return - (uint64_t) __a;
+}
+
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vnegq_f32 (float32x4_t __a)
diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
index ea29066e369..d943989768d 100644
--- a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
+++ b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -627,6 +627,14 @@ test_vqabss_s32 (int32_t a)
   return vqabss_s32 (a);
 }
 
+/* { dg-final { scan-assembler-times "\\tneg\\tx\[0-9\]+" 1 } } */
+
+int64_t
+test_vnegd_s64 (int64_t a)
+{
+  return vnegd_s64 (a);
+}
+
 /* { dg-final { scan-assembler-times "\\tsqneg\\tb\[0-9\]+" 1 } } */
 
 int8_t
diff --git a/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_3.c b/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_3.c
new file mode 100644
index 00000000000..cf4e7ae4679
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_3.c
@@ -0,0 +1,39 @@
+/* Test the vabsd_s64 intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "--save-temps -O2" } */
+
+#include <arm_neon.h>
+#include <limits.h>
+
+extern void abort (void);
+
+#define force_simd(V1)   asm volatile ("mov %d0, %1.d[0]"       \
+           : "=w"(V1)                                           \
+           : "w"(V1)                                            \
+           : /* No clobbers */);
+
+#define RUN_TEST(test, answ)   \
+{                                      \
+  force_simd (test);                   \
+  force_simd (answ);                   \
+  int64_t res = vabsd_s64 (test);      \
+  force_simd (res);                    \
+  if (res != answ)                     \
+    abort ();                          \
+}
+
+int64_t input[] = {INT64_MAX, 10, 0, -10, INT64_MIN + 1, INT64_MIN};
+int64_t expected[] = {INT64_MAX, 10, 0, 10, INT64_MAX, INT64_MIN};
+
+int main (void)
+{
+  RUN_TEST (input[0], expected[0]);
+  RUN_TEST (input[1], expected[1]);
+  RUN_TEST (input[2], expected[2]);
+  RUN_TEST (input[3], expected[3]);
+  RUN_TEST (input[4], expected[4]);
+  RUN_TEST (input[5], expected[5]);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/vabsd_s64.c b/gcc/testsuite/gcc.target/aarch64/vabsd_s64.c
new file mode 100644
index 00000000000..a0f88ee12c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vabsd_s64.c
@@ -0,0 +1,34 @@
+/* Check that the compiler does not optimise the vabsd_s64 call out.
+   We need to check for this because there is a mismatch in semantics
+   between the ACLE, which states that he absolute value of the minimum
+   (signed) value is itself, and C, where this is undefined behaviour.  */
+
+/* { dg-do run } */
+/* { dg-options "--save-temps -fno-inline -O2" } */
+
+#include <arm_neon.h>
+#include <limits.h>
+
+extern void abort (void);
+
+int
+bar (int64_t x)
+{
+  if (x < (int64_t) 0)
+    return vabsd_s64 (x) < (int64_t) 0;
+  else
+	return -1;
+}
+
+int
+main (void)
+{
+  int ans = 1;
+  int res_abs = bar (INT64_MIN);
+
+  if (res_abs != ans)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/vneg_s.c b/gcc/testsuite/gcc.target/aarch64/vneg_s.c
index 911054053ea..e7f20f2831f 100644
--- a/gcc/testsuite/gcc.target/aarch64/vneg_s.c
+++ b/gcc/testsuite/gcc.target/aarch64/vneg_s.c
@@ -75,6 +75,18 @@ extern void abort (void);
       }									\
   }
 
+#define RUN_TEST_SCALAR(test_val, answ_val, a, b)     \
+  {                                                   \
+    int64_t res;                                      \
+    INHIB_OPTIMIZATION;                               \
+    a = test_val;                                     \
+    b = answ_val;                                     \
+    force_simd (b);                                   \
+    force_simd (a);                                   \
+    res = vnegd_s64 (a);                              \
+    force_simd (res);                                 \
+  }
+
 int
 test_vneg_s8 ()
 {
@@ -177,7 +189,24 @@ test_vneg_s64 ()
   return 0;
 }
 
-/* { dg-final { scan-assembler-times "neg\\td\[0-9\]+, d\[0-9\]+" 8 } } */
+int
+test_vnegd_s64 ()
+{
+  int64_t a, b;
+
+  RUN_TEST_SCALAR (TEST0, ANSW0, a, b);
+  RUN_TEST_SCALAR (TEST1, ANSW1, a, b);
+  RUN_TEST_SCALAR (TEST2, ANSW2, a, b);
+  RUN_TEST_SCALAR (TEST3, ANSW3, a, b);
+  RUN_TEST_SCALAR (TEST4, ANSW4, a, b);
+  RUN_TEST_SCALAR (TEST5, ANSW5, a, b);
+  RUN_TEST_SCALAR (LLONG_MAX, LLONG_MIN + 1, a, b);
+  RUN_TEST_SCALAR (LLONG_MIN, LLONG_MIN, a, b);
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "neg\\td\[0-9\]+, d\[0-9\]+" 16 } } */
 
 int
 test_vnegq_s8 ()
@@ -283,6 +312,9 @@ main (int argc, char **argv)
   if (test_vneg_s64 ())
     abort ();
 
+  if (test_vnegd_s64 ())
+    abort ();
+
   if (test_vnegq_s8 ())
     abort ();
 
diff --git a/gcc/testsuite/gcc.target/aarch64/vnegd_s64.c b/gcc/testsuite/gcc.target/aarch64/vnegd_s64.c
new file mode 100644
index 00000000000..73d478ff49d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vnegd_s64.c
@@ -0,0 +1,36 @@
+/* Check that the compiler does not optimise the negation out.
+   We need to check for this because there is a mismatch in semantics
+   between the ACLE, which states that he negative of the minimum
+   (signed) value is itself and C, where this is undefined behaviour.  */
+
+/* { dg-do run } */
+/* { dg-options "--save-temps -O2" } */
+
+#include <arm_neon.h>
+#include <limits.h>
+
+extern void abort (void);
+
+int
+foo (int64_t x)
+{
+  if (x < (int64_t) 0)
+    return vnegd_s64 (x) < (int64_t) 0;
+  else
+    return -1;
+}
+
+/* { dg-final { scan-assembler-times {neg\tx[0-9]+, x[0-9]+} 1 } } */
+
+int
+main (void)
+{
+  int ans = 1;
+  int res = foo (INT64_MIN);
+
+  if (res != ans)
+    abort ();
+
+  return 0;
+}
+

commit 04b5e64e6440bfccaee60921e9df1cfa653dad04
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Sep 23 00:17:39 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 960c3852933..5697b44a10e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-09-22  Vlad Lazar  <vlad.lazar@arm.com>
+
+	Backported from master:
+	2018-08-31  Vlad Lazar  <vlad.lazar@arm.com>
+
+	PR target/71233
+	* config/aarch64/arm_neon.h (vabsd_s64): New.
+	(vnegd_s64): Likewise.
+
 2020-09-18  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ca3ee10cb82..1a983d8f051 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200922
+20200923
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index eb5bb3cf008..d35366fb1ef 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,16 @@
+2020-09-22  Vlad Lazar  <vlad.lazar@arm.com>
+
+	Backported from master:
+	2018-08-31  Vlad Lazar  <vlad.lazar@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/scalar_intrinsics.c (test_vnegd_s64): New.
+	* gcc.target/aarch64/vneg_s.c (RUN_TEST_SCALAR): New.
+	(test_vnegd_s64): Likewise.
+	* gcc.target/aarch64/vnegd_s64.c: New.
+	* gcc.target/aarch64/vabsd_s64.c: New.
+	* gcc.target/aarch64/vabs_intrinsic_3.c: New file.
+
 2020-09-19  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index f477a26c38c..69f60a3ba85 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,15 @@
+2020-09-22  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-08-26  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/96803
+	* include/std/tuple
+	(_Tuple_impl(allocator_arg_t, Alloc, const _Tuple_impl<U...>&)):
+	Replace parameter pack with a type parameter and a pack and pass
+	the first type to __use_alloc.
+	* testsuite/20_util/tuple/cons/96803.cc: New test.
+
 2020-09-11  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit bbc1763ca663d8093f99f8b12b172eeb0814c72e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Sep 24 00:17:45 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1a983d8f051..52a894dd654 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200923
+20200924

commit 1540e95f2c4bb49b1ce31d840ca29bec56d08167
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Thu Sep 24 10:22:58 2020 +0100

    aarch64: Add support for Neoverse V1 CPU
    
    This patch backports the AArch64 support for Arm's Neoverse V1 CPU to
    GCC 8.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64-cores.def: Add Neoverse V1.
            * config/aarch64/aarch64-tune.md: Regenerate.
            * doc/invoke.texi: Document support for Neoverse V1.

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index eb01390c262..35ce68ad077 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -98,6 +98,7 @@ AARCH64_CORE("saphira",     saphira,    falkor,    8_3A,  AARCH64_FL_FOR_ARCH8_3
 
 /* ARM ('A') cores. */
 AARCH64_CORE("zeus", zeus, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE, cortexa72, 0x41, 0xd40, -1)
+AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE, cortexa72, 0x41, 0xd40, -1)
 
 /* ARMv8-A big.LITTLE implementations.  */
 
diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index c2de5e873a7..e8894ee4a9d 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr "tune"
-	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,saphira,zeus,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55"
+	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,saphira,zeus,neoversev1,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55"
 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 47126319e72..a46a9cb31f7 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14771,8 +14771,8 @@ Specify the name of the target processor for which GCC should tune the
 performance of the code.  Permissible values for this option are:
 @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
 @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
-@samp{cortex-a76}, @samp{ares}, @samp{neoverse-n1}, @samp{zeus},
-@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{saphira},
+@samp{cortex-a76}, @samp{ares}, @samp{neoverse-n1}, @samp{neoverse-v1},
+@samp{zeus}, @samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{saphira},
 @samp{xgene1}, @samp{vulcan}, @samp{thunderx},
 @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
 @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},

commit 11e0e5fa724f9f6f979abe537d6485850abfe4d9
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Mon May 21 10:33:30 2018 +0000

    Add missing AArch64 NEON instrinctics for Armv8.2-a to Armv8.4-a
    
    This patch adds the missing neon intrinsics for all 128 bit vector Integer modes for the
    three-way XOR and negate and xor instructions for Arm8.2-a to Armv8.4-a.
    
    gcc/
            PR target/71233
            * config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to
            eor3q<mode>4.
            (aarch64_bcaxqv8hi): Change to bcaxq<mode>4.
            * config/aarch64/aarch64-simd-builtins.def (veor3q_u8, veor3q_u32,
            veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
            vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
            vbcaxq_s64): New.
            * config/aarch64/arm_neon.h: Likewise.
            * config/aarch64/iterators.md (VQ_I): New.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/sha3.h (veor3q_u8, veor3q_u32,
            veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
            vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
            vbcaxq_s64): New.
            * gcc.target/aarch64/sha3_1.c: Likewise.
            * gcc.target/aarch64/sha3_2.c: Likewise.
            * gcc.target/aarch64/sha3_3.c: Likewise.
    
    (cherry picked from commit d21052ebd7ac9d545a26dde3229c57f872c1d5f3)

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index f71a40ef118..fe3e392cfb9 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -614,14 +614,16 @@
   VAR1 (BINOPU, crypto_sha512su0q, 0, v2di)
   /* Implemented by aarch64_crypto_sha512su1qv2di.  */
   VAR1 (TERNOPU, crypto_sha512su1q, 0, v2di)
-  /* Implemented by aarch64_eor3qv8hi.  */
-  VAR1 (TERNOPU, eor3q, 0, v8hi)
+  /* Implemented by eor3q<mode>4.  */
+  BUILTIN_VQ_I (TERNOPU, eor3q, 4)
+  BUILTIN_VQ_I (TERNOP, eor3q, 4)
   /* Implemented by aarch64_rax1qv2di.  */
   VAR1 (BINOPU, rax1q, 0, v2di)
   /* Implemented by aarch64_xarqv2di.  */
   VAR1 (TERNOPUI, xarq, 0, v2di)
-  /* Implemented by aarch64_bcaxqv8hi.  */
-  VAR1 (TERNOPU, bcaxq, 0, v8hi)
+  /* Implemented by bcaxq<mode>4.  */
+  BUILTIN_VQ_I (TERNOPU, bcaxq, 4)
+  BUILTIN_VQ_I (TERNOP, bcaxq, 4)
 
   /* Implemented by aarch64_fml<f16mac1>l<f16quad>_low<mode>.  */
   VAR1 (TERNOP, fmlal_low, 0, v2sf)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 816d627ce9e..8cec46d30ca 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -6045,13 +6045,13 @@
 
 ;; sha3
 
-(define_insn "aarch64_eor3qv8hi"
-  [(set (match_operand:V8HI 0 "register_operand" "=w")
-	(xor:V8HI
-	 (xor:V8HI
-	  (match_operand:V8HI 2 "register_operand" "%w")
-	  (match_operand:V8HI 3 "register_operand" "w"))
-	 (match_operand:V8HI 1 "register_operand" "w")))]
+(define_insn "eor3q<mode>4"
+  [(set (match_operand:VQ_I 0 "register_operand" "=w")
+	(xor:VQ_I
+	 (xor:VQ_I
+	  (match_operand:VQ_I 2 "register_operand" "w")
+	  (match_operand:VQ_I 3 "register_operand" "w"))
+	 (match_operand:VQ_I 1 "register_operand" "w")))]
   "TARGET_SIMD && TARGET_SHA3"
   "eor3\\t%0.16b, %1.16b, %2.16b, %3.16b"
   [(set_attr "type" "crypto_sha3")]
@@ -6081,13 +6081,13 @@
   [(set_attr "type" "crypto_sha3")]
 )
 
-(define_insn "aarch64_bcaxqv8hi"
-  [(set (match_operand:V8HI 0 "register_operand" "=w")
-	(xor:V8HI
-	 (and:V8HI
-	  (not:V8HI (match_operand:V8HI 3 "register_operand" "w"))
-	  (match_operand:V8HI 2 "register_operand" "w"))
-	 (match_operand:V8HI 1 "register_operand" "w")))]
+(define_insn "bcaxq<mode>4"
+  [(set (match_operand:VQ_I 0 "register_operand" "=w")
+	(xor:VQ_I
+	 (and:VQ_I
+	  (not:VQ_I (match_operand:VQ_I 3 "register_operand" "w"))
+	  (match_operand:VQ_I 2 "register_operand" "w"))
+	 (match_operand:VQ_I 1 "register_operand" "w")))]
   "TARGET_SIMD && TARGET_SHA3"
   "bcax\\t%0.16b, %1.16b, %2.16b, %3.16b"
   [(set_attr "type" "crypto_sha3")]
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 7bcd1e1c844..8932a7b0e67 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -33675,6 +33675,13 @@ vsha512su1q_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
   return __builtin_aarch64_crypto_sha512su1qv2di_uuuu (__a, __b, __c);
 }
 
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+veor3q_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
+{
+  return __builtin_aarch64_eor3qv16qi_uuuu (__a, __b, __c);
+}
+
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 veor3q_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
@@ -33682,6 +33689,49 @@ veor3q_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
   return __builtin_aarch64_eor3qv8hi_uuuu (__a, __b, __c);
 }
 
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+veor3q_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+{
+  return __builtin_aarch64_eor3qv4si_uuuu (__a, __b, __c);
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+veor3q_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
+{
+  return __builtin_aarch64_eor3qv2di_uuuu (__a, __b, __c);
+}
+
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+veor3q_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
+{
+  return __builtin_aarch64_eor3qv16qi (__a, __b, __c);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+veor3q_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+{
+  return __builtin_aarch64_eor3qv8hi (__a, __b, __c);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+veor3q_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return __builtin_aarch64_eor3qv4si (__a, __b, __c);
+}
+
+__extension__ extern __inline int64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+veor3q_s64 (int64x2_t __a, int64x2_t __b, int64x2_t __c)
+{
+  return __builtin_aarch64_eor3qv2di (__a, __b, __c);
+}
+
 __extension__ extern __inline uint64x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vrax1q_u64 (uint64x2_t __a, uint64x2_t __b)
@@ -33696,12 +33746,63 @@ vxarq_u64 (uint64x2_t __a, uint64x2_t __b, const int imm6)
   return __builtin_aarch64_xarqv2di_uuus (__a, __b,imm6);
 }
 
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vbcaxq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c)
+{
+  return __builtin_aarch64_bcaxqv16qi_uuuu (__a, __b, __c);
+}
+
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vbcaxq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c)
 {
   return __builtin_aarch64_bcaxqv8hi_uuuu (__a, __b, __c);
 }
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vbcaxq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c)
+{
+  return __builtin_aarch64_bcaxqv4si_uuuu (__a, __b, __c);
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vbcaxq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
+{
+  return __builtin_aarch64_bcaxqv2di_uuuu (__a, __b, __c);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vbcaxq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
+{
+  return __builtin_aarch64_bcaxqv16qi (__a, __b, __c);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vbcaxq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+{
+  return __builtin_aarch64_bcaxqv8hi (__a, __b, __c);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vbcaxq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return __builtin_aarch64_bcaxqv4si (__a, __b, __c);
+}
+
+__extension__ extern __inline int64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vbcaxq_s64 (int64x2_t __a, int64x2_t __b, int64x2_t __c)
+{
+  return __builtin_aarch64_bcaxqv2di (__a, __b, __c);
+}
+
+
 #pragma GCC pop_options
 
 #pragma GCC push_options
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 914a30aa77c..88176a1ed97 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -81,6 +81,9 @@
 ;; Quad vector modes.
 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
 
+;; Quad integer vector modes.
+(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
+
 ;; VQ without 2 element modes.
 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sha3.h b/gcc/testsuite/gcc.target/aarch64/sha3.h
index 76dd1931dff..c8537c25196 100644
--- a/gcc/testsuite/gcc.target/aarch64/sha3.h
+++ b/gcc/testsuite/gcc.target/aarch64/sha3.h
@@ -1,10 +1,26 @@
 #include "arm_neon.h"
 
-uint16x8_t
-test_veor3q_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
-{
-  return veor3q_u16 (a, b, c);
-}
+#define TEST_VEOR3(T, S) T \
+test_veor3q_ ## S (T a, T b, T c) \
+{ \
+  return veor3q_ ## S (a, b, c); \
+} \
+
+#define TEST_VBCAX(T, S) T \
+test_vbcaxq_ ## S (T a, T b, T c) \
+{ \
+  return vbcaxq_ ## S (a, b, c); \
+} \
+
+
+TEST_VEOR3 (uint8x16_t, u8)
+TEST_VEOR3 (uint16x8_t, u16)
+TEST_VEOR3 (uint32x4_t, u32)
+TEST_VEOR3 (uint64x2_t, u64)
+TEST_VEOR3 (int8x16_t, s8)
+TEST_VEOR3 (int16x8_t, s16)
+TEST_VEOR3 (int32x4_t, s32)
+TEST_VEOR3 (int64x2_t, s64)
 
 uint64x2_t
 test_vrax1q_u64 (uint64x2_t a, uint64x2_t b)
@@ -18,8 +34,12 @@ test_vxarq_u64 (uint64x2_t a, uint64x2_t b)
   return vxarq_u64 (a, b, 15);
 }
 
-uint16x8_t
-test_vbcaxq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
-{
-  return vbcaxq_u16 (a, b, c);
-}
+TEST_VBCAX (uint8x16_t, u8)
+TEST_VBCAX (uint16x8_t, u16)
+TEST_VBCAX (uint32x4_t, u32)
+TEST_VBCAX (uint64x2_t, u64)
+TEST_VBCAX (int8x16_t, s8)
+TEST_VBCAX (int16x8_t, s16)
+TEST_VBCAX (int32x4_t, s32)
+TEST_VBCAX (int64x2_t, s64)
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sha3_1.c b/gcc/testsuite/gcc.target/aarch64/sha3_1.c
index 879eadd875e..0727ce77028 100644
--- a/gcc/testsuite/gcc.target/aarch64/sha3_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sha3_1.c
@@ -4,7 +4,7 @@
 #include "sha3.h"
 
 
-/* { dg-final { scan-assembler-times "eor3\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "eor3\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 8 } } */
 /* { dg-final { scan-assembler-times "rax1\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
 /* { dg-final { scan-assembler-times "xar\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d, 15" 1 } } */
-/* { dg-final { scan-assembler-times "bcax\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "bcax\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 8 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sha3_2.c b/gcc/testsuite/gcc.target/aarch64/sha3_2.c
index 2afe28c4744..2d051161133 100644
--- a/gcc/testsuite/gcc.target/aarch64/sha3_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sha3_2.c
@@ -3,7 +3,7 @@
 
 #include "sha3.h"
 
-/* { dg-final { scan-assembler-times "eor3\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "eor3\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 8 } } */
 /* { dg-final { scan-assembler-times "rax1\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
 /* { dg-final { scan-assembler-times "xar\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d, 15" 1 } } */
-/* { dg-final { scan-assembler-times "bcax\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "bcax\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 8 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sha3_3.c b/gcc/testsuite/gcc.target/aarch64/sha3_3.c
index 8915c805c3e..8d8ee77c293 100644
--- a/gcc/testsuite/gcc.target/aarch64/sha3_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sha3_3.c
@@ -3,7 +3,7 @@
 
 #include "sha3.h"
 
-/* { dg-final { scan-assembler-times "eor3\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "eor3\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 8 } } */
 /* { dg-final { scan-assembler-times "rax1\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
 /* { dg-final { scan-assembler-times "xar\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d, 15" 1 } } */
-/* { dg-final { scan-assembler-times "bcax\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "bcax\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 8 } } */

commit 7409639ab568d0d4babcc17370816a2ddd112b72
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Mon Feb 25 17:46:16 2019 +0000

    AArch64: Update Armv8.4-a's FP16 FML intrinsics
    
    This patch updates the Armv8.4-a FP16 FML intrinsics's suffixes from u32 to f16
    to be more consistent with the naming convention for intrinsics.
    
    The specifications for these intrinsics have not been published yet so we do
    not need to maintain the old names.
    
    The patch was created with the following script:
    
    grep -lIE "(vfml[as].+)_u32" -r gcc/ | grep -iEv ".+Changelog.*" \
      | xargs sed -i -E -e "s/(vfml[as].+)_u32/\1_f16/g"
    
    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32,
            vfmlalq_low_u32, vfmlslq_low_u32, vfmlal_high_u32, vfmlsl_high_u32,
            vfmlalq_high_u32, vfmlslq_high_u32, vfmlal_lane_low_u32,
            vfmlsl_lane_low_u32, vfmlal_laneq_low_u32, vfmlsl_laneq_low_u32,
            vfmlalq_lane_low_u32, vfmlslq_lane_low_u32, vfmlalq_laneq_low_u32,
            vfmlslq_laneq_low_u32, vfmlal_lane_high_u32, vfmlsl_lane_high_u32,
            vfmlal_laneq_high_u32, vfmlsl_laneq_high_u32, vfmlalq_lane_high_u32,
            vfmlslq_lane_high_u32, vfmlalq_laneq_high_u32, vfmlslq_laneq_high_u32):
            Rename ...
            (vfmlal_low_f16, vfmlsl_low_f16, vfmlalq_low_f16, vfmlslq_low_f16,
            vfmlal_high_f16, vfmlsl_high_f16, vfmlalq_high_f16, vfmlslq_high_f16,
            vfmlal_lane_low_f16, vfmlsl_lane_low_f16, vfmlal_laneq_low_f16,
            vfmlsl_laneq_low_f16, vfmlalq_lane_low_f16, vfmlslq_lane_low_f16,
            vfmlalq_laneq_low_f16, vfmlslq_laneq_low_f16, vfmlal_lane_high_f16,
            vfmlsl_lane_high_f16, vfmlal_laneq_high_f16, vfmlsl_laneq_high_f16,
            vfmlalq_lane_high_f16, vfmlslq_lane_high_f16, vfmlalq_laneq_high_f16,
            vfmlslq_laneq_high_f16): ... To this.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/fp16_fmul_high.h (test_vfmlal_high_u32,
            test_vfmlalq_high_u32, test_vfmlsl_high_u32, test_vfmlslq_high_u32):
            Rename ...
            (test_vfmlal_high_f16, test_vfmlalq_high_f16, test_vfmlsl_high_f16,
            test_vfmlslq_high_f16): ... To this.
            * gcc.target/aarch64/fp16_fmul_lane_high.h (test_vfmlal_lane_high_u32,
            tets_vfmlsl_lane_high_u32, test_vfmlal_laneq_high_u32,
            test_vfmlsl_laneq_high_u32, test_vfmlalq_lane_high_u32,
            test_vfmlslq_lane_high_u32, test_vfmlalq_laneq_high_u32,
            test_vfmlslq_laneq_high_u32): Rename ...
            (test_vfmlal_lane_high_f16, tets_vfmlsl_lane_high_f16,
            test_vfmlal_laneq_high_f16, test_vfmlsl_laneq_high_f16,
            test_vfmlalq_lane_high_f16, test_vfmlslq_lane_high_f16,
            test_vfmlalq_laneq_high_f16, test_vfmlslq_laneq_high_f16): ... To this.
            * gcc.target/aarch64/fp16_fmul_lane_low.h (test_vfmlal_lane_low_u32,
            test_vfmlsl_lane_low_u32, test_vfmlal_laneq_low_u32,
            test_vfmlsl_laneq_low_u32, test_vfmlalq_lane_low_u32,
            test_vfmlslq_lane_low_u32, test_vfmlalq_laneq_low_u32,
            test_vfmlslq_laneq_low_u32): Rename ...
            (test_vfmlal_lane_low_f16, test_vfmlsl_lane_low_f16,
            test_vfmlal_laneq_low_f16, test_vfmlsl_laneq_low_f16,
            test_vfmlalq_lane_low_f16, test_vfmlslq_lane_low_f16,
            test_vfmlalq_laneq_low_f16, test_vfmlslq_laneq_low_f16): ... To this.
            * gcc.target/aarch64/fp16_fmul_low.h (test_vfmlal_low_u32,
            test_vfmlalq_low_u32, test_vfmlsl_low_u32, test_vfmlslq_low_u32):
            Rename ...
            (test_vfmlal_low_f16, test_vfmlalq_low_f16, test_vfmlsl_low_f16,
            test_vfmlslq_low_f16): ... To This.
            * lib/target-supports.exp
            (check_effective_target_arm_fp16fml_neon_ok_nocache): Update test.
    
    (cherry picked from commit 9d04c986b6faed878dbcc86d2f9392a721a3936e)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 8932a7b0e67..e34deec729c 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -33810,63 +33810,63 @@ vbcaxq_s64 (int64x2_t __a, int64x2_t __b, int64x2_t __c)
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlal_low_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b)
+vfmlal_low_f16 (float32x2_t __r, float16x4_t __a, float16x4_t __b)
 {
   return __builtin_aarch64_fmlal_lowv2sf (__r, __a, __b);
 }
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlsl_low_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b)
+vfmlsl_low_f16 (float32x2_t __r, float16x4_t __a, float16x4_t __b)
 {
   return __builtin_aarch64_fmlsl_lowv2sf (__r, __a, __b);
 }
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlalq_low_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b)
+vfmlalq_low_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b)
 {
   return __builtin_aarch64_fmlalq_lowv4sf (__r, __a, __b);
 }
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlslq_low_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b)
+vfmlslq_low_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b)
 {
   return __builtin_aarch64_fmlslq_lowv4sf (__r, __a, __b);
 }
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlal_high_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b)
+vfmlal_high_f16 (float32x2_t __r, float16x4_t __a, float16x4_t __b)
 {
   return __builtin_aarch64_fmlal_highv2sf (__r, __a, __b);
 }
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlsl_high_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b)
+vfmlsl_high_f16 (float32x2_t __r, float16x4_t __a, float16x4_t __b)
 {
   return __builtin_aarch64_fmlsl_highv2sf (__r, __a, __b);
 }
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlalq_high_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b)
+vfmlalq_high_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b)
 {
   return __builtin_aarch64_fmlalq_highv4sf (__r, __a, __b);
 }
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlslq_high_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b)
+vfmlslq_high_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b)
 {
   return __builtin_aarch64_fmlslq_highv4sf (__r, __a, __b);
 }
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlal_lane_low_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
+vfmlal_lane_low_f16 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
 		     const int __lane)
 {
   return __builtin_aarch64_fmlal_lane_lowv2sf (__r, __a, __b, __lane);
@@ -33874,7 +33874,7 @@ vfmlal_lane_low_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlsl_lane_low_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
+vfmlsl_lane_low_f16 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
 		     const int __lane)
 {
   return __builtin_aarch64_fmlsl_lane_lowv2sf (__r, __a, __b, __lane);
@@ -33882,7 +33882,7 @@ vfmlsl_lane_low_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlal_laneq_low_u32 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
+vfmlal_laneq_low_f16 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
 		      const int __lane)
 {
   return __builtin_aarch64_fmlal_laneq_lowv2sf (__r, __a, __b, __lane);
@@ -33890,7 +33890,7 @@ vfmlal_laneq_low_u32 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlsl_laneq_low_u32 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
+vfmlsl_laneq_low_f16 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
 		      const int __lane)
 {
   return __builtin_aarch64_fmlsl_laneq_lowv2sf (__r, __a, __b, __lane);
@@ -33898,7 +33898,7 @@ vfmlsl_laneq_low_u32 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlalq_lane_low_u32 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
+vfmlalq_lane_low_f16 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
 		      const int __lane)
 {
   return __builtin_aarch64_fmlalq_lane_lowv4sf (__r, __a, __b, __lane);
@@ -33906,7 +33906,7 @@ vfmlalq_lane_low_u32 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlslq_lane_low_u32 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
+vfmlslq_lane_low_f16 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
 		      const int __lane)
 {
   return __builtin_aarch64_fmlslq_lane_lowv4sf (__r, __a, __b, __lane);
@@ -33914,7 +33914,7 @@ vfmlslq_lane_low_u32 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlalq_laneq_low_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
+vfmlalq_laneq_low_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
 		       const int __lane)
 {
   return __builtin_aarch64_fmlalq_laneq_lowv4sf (__r, __a, __b, __lane);
@@ -33922,7 +33922,7 @@ vfmlalq_laneq_low_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlslq_laneq_low_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
+vfmlslq_laneq_low_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
 		      const int __lane)
 {
   return __builtin_aarch64_fmlslq_laneq_lowv4sf (__r, __a, __b, __lane);
@@ -33930,7 +33930,7 @@ vfmlslq_laneq_low_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlal_lane_high_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
+vfmlal_lane_high_f16 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
 		     const int __lane)
 {
   return __builtin_aarch64_fmlal_lane_highv2sf (__r, __a, __b, __lane);
@@ -33938,7 +33938,7 @@ vfmlal_lane_high_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlsl_lane_high_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
+vfmlsl_lane_high_f16 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
 		     const int __lane)
 {
   return __builtin_aarch64_fmlsl_lane_highv2sf (__r, __a, __b, __lane);
@@ -33946,7 +33946,7 @@ vfmlsl_lane_high_u32 (float32x2_t __r, float16x4_t __a, float16x4_t __b,
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlal_laneq_high_u32 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
+vfmlal_laneq_high_f16 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
 		      const int __lane)
 {
   return __builtin_aarch64_fmlal_laneq_highv2sf (__r, __a, __b, __lane);
@@ -33954,7 +33954,7 @@ vfmlal_laneq_high_u32 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
 
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlsl_laneq_high_u32 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
+vfmlsl_laneq_high_f16 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
 		      const int __lane)
 {
   return __builtin_aarch64_fmlsl_laneq_highv2sf (__r, __a, __b, __lane);
@@ -33962,7 +33962,7 @@ vfmlsl_laneq_high_u32 (float32x2_t __r, float16x4_t __a, float16x8_t __b,
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlalq_lane_high_u32 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
+vfmlalq_lane_high_f16 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
 		      const int __lane)
 {
   return __builtin_aarch64_fmlalq_lane_highv4sf (__r, __a, __b, __lane);
@@ -33970,7 +33970,7 @@ vfmlalq_lane_high_u32 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlslq_lane_high_u32 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
+vfmlslq_lane_high_f16 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
 		      const int __lane)
 {
   return __builtin_aarch64_fmlslq_lane_highv4sf (__r, __a, __b, __lane);
@@ -33978,7 +33978,7 @@ vfmlslq_lane_high_u32 (float32x4_t __r, float16x8_t __a, float16x4_t __b,
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlalq_laneq_high_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
+vfmlalq_laneq_high_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
 		       const int __lane)
 {
   return __builtin_aarch64_fmlalq_laneq_highv4sf (__r, __a, __b, __lane);
@@ -33986,7 +33986,7 @@ vfmlalq_laneq_high_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
 
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vfmlslq_laneq_high_u32 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
+vfmlslq_laneq_high_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
 		      const int __lane)
 {
   return __builtin_aarch64_fmlslq_laneq_highv4sf (__r, __a, __b, __lane);
diff --git a/gcc/testsuite/gcc.target/aarch64/fp16_fmul_high.h b/gcc/testsuite/gcc.target/aarch64/fp16_fmul_high.h
index 9c86bd19153..def85038a72 100644
--- a/gcc/testsuite/gcc.target/aarch64/fp16_fmul_high.h
+++ b/gcc/testsuite/gcc.target/aarch64/fp16_fmul_high.h
@@ -1,25 +1,25 @@
 #include "arm_neon.h"
 
 float32x2_t
-test_vfmlal_high_u32 (float32x2_t r, float16x4_t a, float16x4_t b)
+test_vfmlal_high_f16 (float32x2_t r, float16x4_t a, float16x4_t b)
 {
-  return vfmlal_high_u32 (r, a, b);
+  return vfmlal_high_f16 (r, a, b);
 }
 
 float32x4_t
-test_vfmlalq_high_u32 (float32x4_t r, float16x8_t a, float16x8_t b)
+test_vfmlalq_high_f16 (float32x4_t r, float16x8_t a, float16x8_t b)
 {
-  return vfmlalq_high_u32 (r, a, b);
+  return vfmlalq_high_f16 (r, a, b);
 }
 
 float32x2_t
-test_vfmlsl_high_u32 (float32x2_t r, float16x4_t a, float16x4_t b)
+test_vfmlsl_high_f16 (float32x2_t r, float16x4_t a, float16x4_t b)
 {
-  return vfmlsl_high_u32 (r, a, b);
+  return vfmlsl_high_f16 (r, a, b);
 }
 
 float32x4_t
-test_vfmlslq_high_u32 (float32x4_t r, float16x8_t a, float16x8_t b)
+test_vfmlslq_high_f16 (float32x4_t r, float16x8_t a, float16x8_t b)
 {
-  return vfmlslq_high_u32 (r, a, b);
+  return vfmlslq_high_f16 (r, a, b);
 }
diff --git a/gcc/testsuite/gcc.target/aarch64/fp16_fmul_lane_high.h b/gcc/testsuite/gcc.target/aarch64/fp16_fmul_lane_high.h
index 1039347865e..a0b95f8b81e 100644
--- a/gcc/testsuite/gcc.target/aarch64/fp16_fmul_lane_high.h
+++ b/gcc/testsuite/gcc.target/aarch64/fp16_fmul_lane_high.h
@@ -1,49 +1,49 @@
 #include "arm_neon.h"
 
 float32x2_t
-test_vfmlal_lane_high_u32 (float32x2_t r, float16x4_t a, float16x4_t b)
+test_vfmlal_lane_high_f16 (float32x2_t r, float16x4_t a, float16x4_t b)
 {
-  return vfmlal_lane_high_u32 (r, a, b, 0);
+  return vfmlal_lane_high_f16 (r, a, b, 0);
 }
 
 float32x2_t
-tets_vfmlsl_lane_high_u32  (float32x2_t r, float16x4_t a, float16x4_t b)
+tets_vfmlsl_lane_high_f16  (float32x2_t r, float16x4_t a, float16x4_t b)
 {
-  return vfmlsl_lane_high_u32 (r, a, b, 0);
+  return vfmlsl_lane_high_f16 (r, a, b, 0);
 }
 
 float32x2_t
-test_vfmlal_laneq_high_u32 (float32x2_t r, float16x4_t a, float16x8_t b)
+test_vfmlal_laneq_high_f16 (float32x2_t r, float16x4_t a, float16x8_t b)
 {
-  return vfmlal_laneq_high_u32 (r, a, b, 6);
+  return vfmlal_laneq_high_f16 (r, a, b, 6);
 }
 
 float32x2_t
-test_vfmlsl_laneq_high_u32 (float32x2_t r, float16x4_t a, float16x8_t b)
+test_vfmlsl_laneq_high_f16 (float32x2_t r, float16x4_t a, float16x8_t b)
 {
-  return vfmlsl_laneq_high_u32 (r, a, b, 6);
+  return vfmlsl_laneq_high_f16 (r, a, b, 6);
 }
 
 float32x4_t
-test_vfmlalq_lane_high_u32 (float32x4_t r, float16x8_t a, float16x4_t b)
+test_vfmlalq_lane_high_f16 (float32x4_t r, float16x8_t a, float16x4_t b)
 {
-  return vfmlalq_lane_high_u32 (r, a, b, 1);
+  return vfmlalq_lane_high_f16 (r, a, b, 1);
 }
 
 float32x4_t
-test_vfmlslq_lane_high_u32 (float32x4_t r, float16x8_t a, float16x4_t b)
+test_vfmlslq_lane_high_f16 (float32x4_t r, float16x8_t a, float16x4_t b)
 {
-  return vfmlslq_lane_high_u32 (r, a, b, 1);
+  return vfmlslq_lane_high_f16 (r, a, b, 1);
 }
 
 float32x4_t
-test_vfmlalq_laneq_high_u32  (float32x4_t r, float16x8_t a, float16x8_t b)
+test_vfmlalq_laneq_high_f16  (float32x4_t r, float16x8_t a, float16x8_t b)
 {
-  return vfmlalq_laneq_high_u32 (r, a, b, 7);
+  return vfmlalq_laneq_high_f16 (r, a, b, 7);
 }
 
 float32x4_t
-test_vfmlslq_laneq_high_u32 (float32x4_t r, float16x8_t a, float16x8_t b)
+test_vfmlslq_laneq_high_f16 (float32x4_t r, float16x8_t a, float16x8_t b)
 {
-  return vfmlslq_laneq_high_u32 (r, a, b, 7);
+  return vfmlslq_laneq_high_f16 (r, a, b, 7);
 }
diff --git a/gcc/testsuite/gcc.target/aarch64/fp16_fmul_lane_low.h b/gcc/testsuite/gcc.target/aarch64/fp16_fmul_lane_low.h
index b689741bdb0..bf49829c4be 100644
--- a/gcc/testsuite/gcc.target/aarch64/fp16_fmul_lane_low.h
+++ b/gcc/testsuite/gcc.target/aarch64/fp16_fmul_lane_low.h
@@ -1,49 +1,49 @@
 #include "arm_neon.h"
 
 float32x2_t
-test_vfmlal_lane_low_u32 (float32x2_t r, float16x4_t a, float16x4_t b)
+test_vfmlal_lane_low_f16 (float32x2_t r, float16x4_t a, float16x4_t b)
 {
-  return vfmlal_lane_low_u32 (r, a, b, 0);
+  return vfmlal_lane_low_f16 (r, a, b, 0);
 }
 
 float32x2_t
-test_vfmlsl_lane_low_u32 (float32x2_t r, float16x4_t a, float16x4_t b)
+test_vfmlsl_lane_low_f16 (float32x2_t r, float16x4_t a, float16x4_t b)
 {
-  return vfmlsl_lane_low_u32 (r, a, b, 0);
+  return vfmlsl_lane_low_f16 (r, a, b, 0);
 }
 
 float32x2_t
-test_vfmlal_laneq_low_u32 (float32x2_t r, float16x4_t a, float16x8_t b)
+test_vfmlal_laneq_low_f16 (float32x2_t r, float16x4_t a, float16x8_t b)
 {
-  return vfmlal_laneq_low_u32 (r, a, b, 6);
+  return vfmlal_laneq_low_f16 (r, a, b, 6);
 }
 
 float32x2_t
-test_vfmlsl_laneq_low_u32 (float32x2_t r, float16x4_t a, float16x8_t b)
+test_vfmlsl_laneq_low_f16 (float32x2_t r, float16x4_t a, float16x8_t b)
 {
-  return vfmlsl_laneq_low_u32 (r, a, b, 6);
+  return vfmlsl_laneq_low_f16 (r, a, b, 6);
 }
 
 float32x4_t
-test_vfmlalq_lane_low_u32 (float32x4_t r, float16x8_t a, float16x4_t b)
+test_vfmlalq_lane_low_f16 (float32x4_t r, float16x8_t a, float16x4_t b)
 {
-  return vfmlalq_lane_low_u32 (r, a, b, 1);
+  return vfmlalq_lane_low_f16 (r, a, b, 1);
 }
 
 float32x4_t
-test_vfmlslq_lane_low_u32 (float32x4_t r, float16x8_t a, float16x4_t b)
+test_vfmlslq_lane_low_f16 (float32x4_t r, float16x8_t a, float16x4_t b)
 {
-  return vfmlslq_lane_low_u32 (r, a, b, 1);
+  return vfmlslq_lane_low_f16 (r, a, b, 1);
 }
 
 float32x4_t
-test_vfmlalq_laneq_low_u32 (float32x4_t r, float16x8_t a, float16x8_t b)
+test_vfmlalq_laneq_low_f16 (float32x4_t r, float16x8_t a, float16x8_t b)
 {
-  return vfmlalq_laneq_low_u32 (r, a, b, 7);
+  return vfmlalq_laneq_low_f16 (r, a, b, 7);
 }
 
 float32x4_t
-test_vfmlslq_laneq_low_u32 (float32x4_t r, float16x8_t a, float16x8_t b)
+test_vfmlslq_laneq_low_f16 (float32x4_t r, float16x8_t a, float16x8_t b)
 {
-  return vfmlslq_laneq_low_u32 (r, a, b, 7);
+  return vfmlslq_laneq_low_f16 (r, a, b, 7);
 }
diff --git a/gcc/testsuite/gcc.target/aarch64/fp16_fmul_low.h b/gcc/testsuite/gcc.target/aarch64/fp16_fmul_low.h
index 778ca1c245c..b039b548b58 100644
--- a/gcc/testsuite/gcc.target/aarch64/fp16_fmul_low.h
+++ b/gcc/testsuite/gcc.target/aarch64/fp16_fmul_low.h
@@ -1,25 +1,25 @@
 #include "arm_neon.h"
 
 float32x2_t
-test_vfmlal_low_u32 (float32x2_t r, float16x4_t a, float16x4_t b)
+test_vfmlal_low_f16 (float32x2_t r, float16x4_t a, float16x4_t b)
 {
-  return vfmlal_low_u32 (r, a, b);
+  return vfmlal_low_f16 (r, a, b);
 }
 
 float32x4_t
-test_vfmlalq_low_u32 (float32x4_t r, float16x8_t a, float16x8_t b)
+test_vfmlalq_low_f16 (float32x4_t r, float16x8_t a, float16x8_t b)
 {
-  return vfmlalq_low_u32 (r, a, b);
+  return vfmlalq_low_f16 (r, a, b);
 }
 
 float32x2_t
-test_vfmlsl_low_u32 (float32x2_t r, float16x4_t a, float16x4_t b)
+test_vfmlsl_low_f16 (float32x2_t r, float16x4_t a, float16x4_t b)
 {
-  return vfmlsl_low_u32 (r, a, b);
+  return vfmlsl_low_f16 (r, a, b);
 }
 
 float32x4_t
-test_vfmlslq_low_u32 (float32x4_t r, float16x8_t a, float16x8_t b)
+test_vfmlslq_low_f16 (float32x4_t r, float16x8_t a, float16x8_t b)
 {
-  return vfmlslq_low_u32 (r, a, b);
+  return vfmlslq_low_f16 (r, a, b);
 }
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index e6b84041fc5..3d85e17b74f 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4556,7 +4556,7 @@ proc check_effective_target_arm_fp16fml_neon_ok_nocache { } {
 		float32x2_t
 		foo (float32x2_t r, float16x4_t a, float16x4_t b)
 		{
-		  return vfmlal_high_u32 (r, a, b);
+		  return vfmlal_high_f16 (r, a, b);
 		}
         } "$flags -march=armv8.2-a+fp16fml"] } {
             set et_arm_fp16fml_neon_flags "$flags -march=armv8.2-a+fp16fml"

commit a8ec9cc2241f4e0c387e78f23bae0100c74de6a8
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 3 08:40:30 2019 +0000

    Add support for __jcvt intrinsic
    
    This patch implements the __jcvt ACLE intrinsic [1] that maps down to the FJCVTZS [2] instruction from Armv8.3-a.
    No fancy mode iterators or nothing. Just a single builtin, UNSPEC and define_insn and the associate plumbing.
    This patch also defines __ARM_FEATURE_JCVT to indicate when the intrinsic is available.
    
    [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics
    [2] https://developer.arm.com/docs/ddi0596/latest/simd-and-floating-point-instructions-alphabetic-order/fjcvtzs-floating-point-javascript-convert-to-signed-fixed-point-rounding-toward-zero
    
    gcc/
            PR target/71233
            * config/aarch64/aarch64.md (UNSPEC_FJCVTZS): Define.
            (aarch64_fjcvtzs): New define_insn.
            * config/aarch64/aarch64.h (TARGET_JSCVT): Define.
            * config/aarch64/aarch64-builtins.c (aarch64_builtins):
            Add AARCH64_JSCVT.
            (aarch64_init_builtins): Initialize __builtin_aarch64_jcvtzs.
            (aarch64_expand_builtin): Handle AARCH64_JSCVT.
            * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
            __ARM_FEATURE_JCVT where appropriate.
            * config/aarch64/arm_acle.h (__jcvt): Define.
            * doc/sourcebuild.texi (aarch64_fjcvtzs_hw) Document new
            target supports option.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/acle/jcvt_1.c: New test.
            * gcc.target/aarch64/acle/jcvt_2.c: New testcase.
            * lib/target-supports.exp
            (check_effective_target_aarch64_fjcvtzs_hw): Add new check for
            FJCVTZS hw.
    
    Co-Authored-By: Andrea Corallo  <andrea.corallo@arm.com>
    
    (cherry picked from commit e1d5d19ec4f84b67ac693fef5b2add7dc9cf056d)
    (cherry picked from commit 2c62952f8160bdc8d4111edb34a4bc75096c1e05)
    (cherry picked from commit d2b86e14c14020f3e119ab8f462e2a91bd7d46e5)
    (cherry picked from commit 58ae77d3ba70a2b9ccc90a90f3f82cf46239d5f1)

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index ced3aa6c100..9a542e829a4 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -399,6 +399,8 @@ enum aarch64_builtins
   AARCH64_PAUTH_BUILTIN_AUTIA1716,
   AARCH64_PAUTH_BUILTIN_PACIA1716,
   AARCH64_PAUTH_BUILTIN_XPACLRI,
+  /* Builtin for Arm8.3-a Javascript conversion instruction.  */
+  AARCH64_JSCVT,
   AARCH64_BUILTIN_MAX
 };
 
@@ -1002,6 +1004,12 @@ aarch64_init_builtins (void)
   aarch64_init_crc32_builtins ();
   aarch64_init_builtin_rsqrt ();
 
+  tree ftype_jcvt
+    = build_function_type_list (intSI_type_node, double_type_node, NULL);
+  aarch64_builtin_decls[AARCH64_JSCVT]
+    = add_builtin_function ("__builtin_aarch64_jcvtzs", ftype_jcvt,
+			    AARCH64_JSCVT, BUILT_IN_MD, NULL, NULL_TREE);
+
   /* Initialize pointer authentication builtins which are backed by instructions
      in NOP encoding space.
 
@@ -1391,6 +1399,16 @@ aarch64_expand_builtin (tree exp,
 	}
 
       return target;
+
+    case AARCH64_JSCVT:
+      {
+	expand_operand ops[2];
+	create_output_operand (&ops[0], target, SImode);
+	op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
+	create_input_operand (&ops[1], op0, DFmode);
+	expand_insn (CODE_FOR_aarch64_fjcvtzs, 2, ops);
+	return ops[0].value;
+      }
     }
 
   if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX)
diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index 108c0120394..fcce3d672b6 100644
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -109,6 +109,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
 
   aarch64_def_or_undef (TARGET_CRC32, "__ARM_FEATURE_CRC32", pfile);
   aarch64_def_or_undef (TARGET_DOTPROD, "__ARM_FEATURE_DOTPROD", pfile);
+  aarch64_def_or_undef (TARGET_JSCVT, "__ARM_FEATURE_JCVT", pfile);
 
   cpp_undef (pfile, "__AARCH64_CMODEL_TINY__");
   cpp_undef (pfile, "__AARCH64_CMODEL_SMALL__");
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 976f9afae54..8c63733c699 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -234,6 +234,9 @@ extern unsigned aarch64_architecture_version;
 /* ARMv8.3-A features.  */
 #define TARGET_ARMV8_3	(AARCH64_ISA_V8_3)
 
+/* Javascript conversion instruction from Armv8.3-a.  */
+#define TARGET_JSCVT	(TARGET_FLOAT && AARCH64_ISA_V8_3)
+
 /* Make sure this is always defined so we don't have to check for ifdefs
    but rather use normal ifs.  */
 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 82db038c77a..2b492b53391 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -105,6 +105,7 @@
     UNSPEC_CRC32X
     UNSPEC_FCVTZS
     UNSPEC_FCVTZU
+    UNSPEC_FJCVTZS
     UNSPEC_URECPE
     UNSPEC_FRECPE
     UNSPEC_FRECPS
@@ -5885,6 +5886,16 @@
   [(set_attr "length" "0")]
 )
 
+(define_insn "aarch64_fjcvtzs"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec:SI [(match_operand:DF 1 "register_operand" "w")]
+		   UNSPEC_FJCVTZS))
+   (clobber (reg:CC CC_REGNUM))]
+  "TARGET_JSCVT"
+  "fjcvtzs\\t%w0, %d1"
+  [(set_attr "type" "f_cvtf2i")]
+)
+
 ;; Pointer authentication patterns are always provided.  In architecture
 ;; revisions prior to ARMv8.3-A these HINT instructions operate as NOPs.
 ;; This lets the user write portable software which authenticates pointers
diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index 8504c3f1d76..7bae393c33d 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -29,6 +29,16 @@
 
 #include <stdint.h>
 
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.3-a")
+__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+__jcvt (double __a)
+{
+  return __builtin_aarch64_jcvtzs (__a);
+}
+
+#pragma GCC pop_options
+
 #pragma GCC push_options
 
 #pragma GCC target ("+nothing+crc")
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index ad7dea3744c..eb85aca5042 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1898,6 +1898,9 @@ AArch64 target which generates instruction sequences for big endian.
 Binutils installed on test system supports relocation types required by -fpic
 for AArch64 small memory model.
 
+@item aarch64_fjcvtzs_hw
+AArch64 target that is able to generate and execute armv8.3-a FJCVTZS
+instruction.
 @end table
 
 @subsubsection MIPS-specific attributes
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/jcvt_1.c b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_1.c
new file mode 100644
index 00000000000..0c900b1b57c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_1.c
@@ -0,0 +1,15 @@
+/* Test the __jcvt ACLE intrinsic.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.3-a" } */
+
+#include <arm_acle.h>
+
+#ifdef __ARM_FEATURE_JCVT
+int32_t
+test_jcvt (double a)
+{
+  return __jcvt (a);
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fjcvtzs\tw\[0-9\]+, d\[0-9\]+\n" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c
new file mode 100644
index 00000000000..ea2dfd14cf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c
@@ -0,0 +1,33 @@
+/* Test the __jcvt ACLE intrinsic.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -march=armv8.3-a -save-temps" } */
+/* { dg-require-effective-target aarch64_fjcvtzs_hw } */
+
+#include <arm_acle.h>
+
+extern void abort (void);
+
+#ifdef __ARM_FEATURE_JCVT
+volatile int32_t x;
+
+int __attribute__((noinline))
+foo (double a, int b, int c)
+{
+  b = b > c;
+  x = __jcvt (a);
+  return b;
+}
+
+int
+main (void)
+{
+  int x = foo (1.1, 2, 3);
+  if (x)
+    abort ();
+
+  return 0;
+}
+
+#endif
+
+/* { dg-final { scan-assembler-times "fjcvtzs\tw\[0-9\]+, d\[0-9\]+\n" 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 3d85e17b74f..fde6cf45274 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4386,6 +4386,27 @@ proc check_effective_target_arm_neonv2_hw { } {
     } [add_options_for_arm_neonv2 ""]]
 }
 
+# Return 1 if the target supports executing the armv8.3-a FJCVTZS
+# instruction.
+proc check_effective_target_aarch64_fjcvtzs_hw { } {
+    if { ![istarget aarch64*-*-*] } {
+	return 0
+    }
+    return [check_runtime aarch64_fjcvtzs_hw_available {
+	int
+	main (void)
+	{
+	  double in = 25.1;
+	  int out;
+	  asm volatile ("fjcvtzs %w0, %d1"
+			: "=r" (out)
+			: "w" (in)
+			: /* No clobbers.  */);
+	  return out != 25;
+	}
+    } "-march=armv8.3-a" ]
+}
+
 # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
 # otherwise.  The test is valid for AArch64 and ARM.  Record the command
 # line options needed.

commit 97c34eb5f57bb1d37f3feddefefa5f553bcea9fc
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Mon Sep 14 08:52:27 2020 -0700

    rtl_data: Add sp_is_clobbered_by_asm
    
    Add sp_is_clobbered_by_asm to rtl_data to inform backends that the stack
    pointer is clobbered by asm statement.
    
    gcc/
    
            PR target/97032
            * cfgexpand.c (expand_asm_stmt): Set sp_is_clobbered_by_asm to
            true if the stack pointer is clobbered by asm statement.
            * emit-rtl.h (rtl_data): Add sp_is_clobbered_by_asm.
            * config/i386/i386.c (ix86_get_drap_rtx): Set need_drap to true
            if the stack pointer is clobbered by asm statement.
    
    gcc/testsuite/
    
            PR target/97032
            * gcc.target/i386/pr97032.c: New test.
    
    (cherry picked from commit 453a20c65722719b9e2d84339f215e7ec87692dc)

diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index 18565bf1dab..dcf491954f1 100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -2972,6 +2972,9 @@ expand_asm_stmt (gasm *stmt)
 			   regname);
 		    return;
 		  }
+		/* Clobbering the stack pointer register.  */
+		else if (reg == (int) STACK_POINTER_REGNUM)
+		  crtl->sp_is_clobbered_by_asm = true;
 
 	        SET_HARD_REG_BIT (clobbered_regs, reg);
 	        rtx x = gen_rtx_REG (reg_raw_mode[reg], reg);
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index f3c722b51e9..ce20bc2ab4e 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -12528,10 +12528,12 @@ ix86_update_stack_boundary (void)
 static rtx
 ix86_get_drap_rtx (void)
 {
-  /* We must use DRAP if there are outgoing arguments on stack and
+  /* We must use DRAP if there are outgoing arguments on stack or
+     the stack pointer register is clobbered by asm statment and
      ACCUMULATE_OUTGOING_ARGS is false.  */
   if (ix86_force_drap
-      || (cfun->machine->outgoing_args_on_stack
+      || ((cfun->machine->outgoing_args_on_stack
+	   || crtl->sp_is_clobbered_by_asm)
 	  && !ACCUMULATE_OUTGOING_ARGS))
     crtl->need_drap = true;
 
diff --git a/gcc/emit-rtl.h b/gcc/emit-rtl.h
index 4e7bd1ec26d..55dc3e84e9c 100644
--- a/gcc/emit-rtl.h
+++ b/gcc/emit-rtl.h
@@ -265,6 +265,9 @@ struct GTY(()) rtl_data {
      pass_stack_ptr_mod has run.  */
   bool sp_is_unchanging;
 
+  /* True if the stack pointer is clobbered by asm statement.  */
+  bool sp_is_clobbered_by_asm;
+
   /* Nonzero if function being compiled doesn't contain any calls
      (ignoring the prologue and epilogue).  This is set prior to
      register allocation in IRA and is valid for the remaining
diff --git a/gcc/testsuite/gcc.target/i386/pr97032.c b/gcc/testsuite/gcc.target/i386/pr97032.c
new file mode 100644
index 00000000000..b9ef2ad0c05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr97032.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target { ia32 && fstack_protector } } } */
+/* { dg-options "-O2 -mincoming-stack-boundary=2 -fstack-protector-all" } */
+
+#include <stdarg.h>
+
+extern int *__errno_location (void);
+
+long
+sys_socketcall (int op, ...)
+{
+  long int res;
+  va_list ap;
+  va_start (ap, op);
+  asm volatile ("push %%ebx; movl %2, %%ebx; int $0x80; pop %%ebx"
+		: "=a" (res) : "0" (102), "ri" (16), "c" (ap) : "memory", "esp");
+  if (__builtin_expect (res > 4294963200UL, 0))
+    *__errno_location () = -res;
+  va_end (ap);
+  return res;
+}
+
+/* { dg-final { scan-assembler "call\[ \t\]*_?__errno_location" } } */

commit 5a2283440668f96a537f8a9e3cd5fc659d0643e2
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Sep 25 00:17:47 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5697b44a10e..e596b0d7780 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,81 @@
+2020-09-24  H.J. Lu  <hjl.tools@gmail.com>
+
+	Backported from master:
+	2020-09-16  H.J. Lu  <hjl.tools@gmail.com>
+
+	PR target/97032
+	* cfgexpand.c (expand_asm_stmt): Set sp_is_clobbered_by_asm to
+	true if the stack pointer is clobbered by asm statement.
+	* emit-rtl.h (rtl_data): Add sp_is_clobbered_by_asm.
+	* config/i386/i386.c (ix86_get_drap_rtx): Set need_drap to true
+	if the stack pointer is clobbered by asm statement.
+
+2020-09-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+		    Andrea Corallo   <andrea.corallo@arm.com>
+
+	PR target/71233
+	* config/aarch64/aarch64.md (UNSPEC_FJCVTZS): Define.
+	(aarch64_fjcvtzs): New define_insn.
+	* config/aarch64/aarch64.h (TARGET_JSCVT): Define.
+	* config/aarch64/aarch64-builtins.c (aarch64_builtins):
+	Add AARCH64_JSCVT.
+	(aarch64_init_builtins): Initialize __builtin_aarch64_jcvtzs.
+	(aarch64_expand_builtin): Handle AARCH64_JSCVT.
+	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
+	__ARM_FEATURE_JCVT where appropriate.
+	* config/aarch64/arm_acle.h (__jcvt): Define.
+	* doc/sourcebuild.texi (aarch64_fjcvtzs_hw) Document new
+	target supports option.
+
+2020-09-24  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2019-02-25  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/71233
+	* config/aarch64/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32,
+	vfmlalq_low_u32, vfmlslq_low_u32, vfmlal_high_u32, vfmlsl_high_u32,
+	vfmlalq_high_u32, vfmlslq_high_u32, vfmlal_lane_low_u32,
+	vfmlsl_lane_low_u32, vfmlal_laneq_low_u32, vfmlsl_laneq_low_u32,
+	vfmlalq_lane_low_u32, vfmlslq_lane_low_u32, vfmlalq_laneq_low_u32,
+	vfmlslq_laneq_low_u32, vfmlal_lane_high_u32, vfmlsl_lane_high_u32,
+	vfmlal_laneq_high_u32, vfmlsl_laneq_high_u32, vfmlalq_lane_high_u32,
+	vfmlslq_lane_high_u32, vfmlalq_laneq_high_u32, vfmlslq_laneq_high_u32):
+	Rename ...
+	(vfmlal_low_f16, vfmlsl_low_f16, vfmlalq_low_f16, vfmlslq_low_f16,
+	vfmlal_high_f16, vfmlsl_high_f16, vfmlalq_high_f16, vfmlslq_high_f16,
+	vfmlal_lane_low_f16, vfmlsl_lane_low_f16, vfmlal_laneq_low_f16,
+	vfmlsl_laneq_low_f16, vfmlalq_lane_low_f16, vfmlslq_lane_low_f16,
+	vfmlalq_laneq_low_f16, vfmlslq_laneq_low_f16, vfmlal_lane_high_f16,
+	vfmlsl_lane_high_f16, vfmlal_laneq_high_f16, vfmlsl_laneq_high_f16,
+	vfmlalq_lane_high_f16, vfmlslq_lane_high_f16, vfmlalq_laneq_high_f16,
+	vfmlslq_laneq_high_f16): ... To this.
+
+2020-09-24  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2018-05-21  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/71233
+	* config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to
+	eor3q<mode>4.
+	(aarch64_bcaxqv8hi): Change to bcaxq<mode>4.
+	* config/aarch64/aarch64-simd-builtins.def (veor3q_u8, veor3q_u32,
+	veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
+	vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
+	vbcaxq_s64): New.
+	* config/aarch64/arm_neon.h: Likewise.
+	* config/aarch64/iterators.md (VQ_I): New.
+
+2020-09-24  Alex Coplan  <alex.coplan@arm.com>
+
+	* config/aarch64/aarch64-cores.def: Add Neoverse V1.
+	* config/aarch64/aarch64-tune.md: Regenerate.
+	* doc/invoke.texi: Document support for Neoverse V1.
+
 2020-09-22  Vlad Lazar  <vlad.lazar@arm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 52a894dd654..cfe4a2ef954 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200924
+20200925
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d35366fb1ef..b2e821ad7b0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,75 @@
+2020-09-24  H.J. Lu  <hjl.tools@gmail.com>
+
+	Backported from master:
+	2020-09-16  H.J. Lu  <hjl.tools@gmail.com>
+
+	PR target/97032
+	* gcc.target/i386/pr97032.c: New test.
+
+2020-09-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+		    Andrea Corallo   <andrea.corallo@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/acle/jcvt_1.c: New test.
+	* gcc.target/aarch64/acle/jcvt_2.c: New testcase.
+	* lib/target-supports.exp
+	(check_effective_target_aarch64_fjcvtzs_hw): Add new check for
+	FJCVTZS hw.
+
+2020-09-24  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2019-02-25  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/fp16_fmul_high.h (test_vfmlal_high_u32,
+	test_vfmlalq_high_u32, test_vfmlsl_high_u32, test_vfmlslq_high_u32):
+	Rename ...
+	(test_vfmlal_high_f16, test_vfmlalq_high_f16, test_vfmlsl_high_f16,
+	test_vfmlslq_high_f16): ... To this.
+	* gcc.target/aarch64/fp16_fmul_lane_high.h (test_vfmlal_lane_high_u32,
+	tets_vfmlsl_lane_high_u32, test_vfmlal_laneq_high_u32,
+	test_vfmlsl_laneq_high_u32, test_vfmlalq_lane_high_u32,
+	test_vfmlslq_lane_high_u32, test_vfmlalq_laneq_high_u32,
+	test_vfmlslq_laneq_high_u32): Rename ...
+	(test_vfmlal_lane_high_f16, tets_vfmlsl_lane_high_f16,
+	test_vfmlal_laneq_high_f16, test_vfmlsl_laneq_high_f16,
+	test_vfmlalq_lane_high_f16, test_vfmlslq_lane_high_f16,
+	test_vfmlalq_laneq_high_f16, test_vfmlslq_laneq_high_f16): ... To this.
+	* gcc.target/aarch64/fp16_fmul_lane_low.h (test_vfmlal_lane_low_u32,
+	test_vfmlsl_lane_low_u32, test_vfmlal_laneq_low_u32,
+	test_vfmlsl_laneq_low_u32, test_vfmlalq_lane_low_u32,
+	test_vfmlslq_lane_low_u32, test_vfmlalq_laneq_low_u32,
+	test_vfmlslq_laneq_low_u32): Rename ...
+	(test_vfmlal_lane_low_f16, test_vfmlsl_lane_low_f16,
+	test_vfmlal_laneq_low_f16, test_vfmlsl_laneq_low_f16,
+	test_vfmlalq_lane_low_f16, test_vfmlslq_lane_low_f16,
+	test_vfmlalq_laneq_low_f16, test_vfmlslq_laneq_low_f16): ... To this.
+	* gcc.target/aarch64/fp16_fmul_low.h (test_vfmlal_low_u32,
+	test_vfmlalq_low_u32, test_vfmlsl_low_u32, test_vfmlslq_low_u32):
+	Rename ...
+	(test_vfmlal_low_f16, test_vfmlalq_low_f16, test_vfmlsl_low_f16,
+	test_vfmlslq_low_f16): ... To This.
+	* lib/target-supports.exp
+	(check_effective_target_arm_fp16fml_neon_ok_nocache): Update test.
+
+2020-09-24  Tamar Christina  <tamar.christina@arm.com>
+
+	Backported from master:
+	2018-05-21  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/sha3.h (veor3q_u8, veor3q_u32,
+	veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
+	vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
+	vbcaxq_s64): New.
+	* gcc.target/aarch64/sha3_1.c: Likewise.
+	* gcc.target/aarch64/sha3_2.c: Likewise.
+	* gcc.target/aarch64/sha3_3.c: Likewise.
+
 2020-09-22  Vlad Lazar  <vlad.lazar@arm.com>
 
 	Backported from master:

commit 26020c849802a03f7a0634636d752ffbc7729096
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Mon Oct 21 10:52:05 2019 +0000

    AArch64: Implement __rndr, __rndrrs intrinsics
    
    This patch implements the recently published[1] __rndr and __rndrrs
    intrinsics used to access the RNG in Armv8.5-A.
    The __rndrrs intrinsics can be used to reseed the generator too.
    They are guarded by the __ARM_FEATURE_RNG feature macro.
    A quirk with these intrinsics is that they store the random number in
    their pointer argument and return a status
    code if the generation succeeded.
    
    The instructions themselves write the CC flags indicating the success of
    the operation that we can then read with a CSET.
    Therefore this implementation makes use of the IGNORE indicator to the
    builtin expand machinery to avoid generating
    the CSET if its result is unused (the CC reg clobbering effect is still
    reflected in the pattern).
    I've checked that using unspec_volatile prevents undesirable CSEing of
    the instructions.
    
    [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics
    
    gcc/
            PR target/71233
            * config/aarch64/aarch64.md (UNSPEC_RNDR, UNSPEC_RNDRRS):
            Define.
            (aarch64_rndr): New define_insn.
            (aarch64_rndrrs): Likewise.
            * config/aarch64/aarch64.h (AARCH64_ISA_RNG): Define.
            (TARGET_RNG): Likewise.
            (AARCH64_FL_RNG): Likewise.
            * config/aarch64/aarch64-option-extensions.def (rng): Define.
            * config/aarch64/aarch64-builtins.c (enum aarch64_builtins):
            Add AARCH64_BUILTIN_RNG_RNDR, AARCH64_BUILTIN_RNG_RNDRRS.
            (aarch64_init_rng_builtins): Define.
            (aarch64_init_builtins): Call aarch64_init_rng_builtins.
            (aarch64_expand_rng_builtin): Define.
            (aarch64_expand_builtin): Use IGNORE argument, handle
            RNG builtins.
            * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins):
            Define __ARM_FEATURE_RNG when TARGET_RNG.
            * config/aarch64/arm_acle.h (__rndr, __rndrrs): Define.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/acle/rng_1.c: New test.

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 9a542e829a4..e6815900c90 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -401,6 +401,9 @@ enum aarch64_builtins
   AARCH64_PAUTH_BUILTIN_XPACLRI,
   /* Builtin for Arm8.3-a Javascript conversion instruction.  */
   AARCH64_JSCVT,
+  /* Armv8.5-a RNG instruction builtins.  */
+  AARCH64_BUILTIN_RNG_RNDR,
+  AARCH64_BUILTIN_RNG_RNDRRS,
   AARCH64_BUILTIN_MAX
 };
 
@@ -975,6 +978,24 @@ aarch64_init_pauth_hint_builtins (void)
 			    NULL_TREE);
 }
 
+/* Add builtins for Random Number instructions.  */
+
+static void
+aarch64_init_rng_builtins (void)
+{
+  tree unsigned_ptr_type = build_pointer_type (unsigned_intDI_type_node);
+  tree ftype
+    = build_function_type_list (integer_type_node, unsigned_ptr_type, NULL);
+  aarch64_builtin_decls[AARCH64_BUILTIN_RNG_RNDR]
+    = add_builtin_function ("__builtin_aarch64_rndr", ftype,
+			    AARCH64_BUILTIN_RNG_RNDR, BUILT_IN_MD, NULL,
+			    NULL_TREE);
+  aarch64_builtin_decls[AARCH64_BUILTIN_RNG_RNDRRS]
+    = add_builtin_function ("__builtin_aarch64_rndrrs", ftype,
+			    AARCH64_BUILTIN_RNG_RNDRRS, BUILT_IN_MD, NULL,
+			    NULL_TREE);
+}
+
 void
 aarch64_init_builtins (void)
 {
@@ -1003,6 +1024,7 @@ aarch64_init_builtins (void)
 
   aarch64_init_crc32_builtins ();
   aarch64_init_builtin_rsqrt ();
+  aarch64_init_rng_builtins ();
 
   tree ftype_jcvt
     = build_function_type_list (intSI_type_node, double_type_node, NULL);
@@ -1321,6 +1343,42 @@ aarch64_expand_builtin_rsqrt (int fcode, tree exp, rtx target)
   return target;
 }
 
+/* Expand a random number builtin EXP with code FCODE, putting the result
+   int TARGET.  If IGNORE is true the return value is ignored.  */
+
+rtx
+aarch64_expand_rng_builtin (tree exp, rtx target, int fcode, int ignore)
+{
+  rtx pat;
+  enum insn_code icode;
+  if (fcode == AARCH64_BUILTIN_RNG_RNDR)
+    icode = CODE_FOR_aarch64_rndr;
+  else if (fcode == AARCH64_BUILTIN_RNG_RNDRRS)
+    icode = CODE_FOR_aarch64_rndrrs;
+  else
+    gcc_unreachable ();
+
+  rtx rand = gen_reg_rtx (DImode);
+  pat = GEN_FCN (icode) (rand);
+  if (!pat)
+    return NULL_RTX;
+
+  tree arg0 = CALL_EXPR_ARG (exp, 0);
+  rtx res_addr = expand_normal (arg0);
+  res_addr = convert_memory_address (Pmode, res_addr);
+  rtx res_mem = gen_rtx_MEM (DImode, res_addr);
+  emit_insn (pat);
+  emit_move_insn (res_mem, rand);
+  /* If the status result is unused don't generate the CSET code.  */
+  if (ignore)
+    return target;
+
+  rtx cc_reg = gen_rtx_REG (CC_Zmode, CC_REGNUM);
+  rtx cmp_rtx = gen_rtx_fmt_ee (NE, SImode, cc_reg, const0_rtx);
+  emit_insn (gen_aarch64_cstoresi (target, cmp_rtx, cc_reg));
+  return target;
+}
+
 /* Expand an expression EXP that calls a built-in function,
    with result going to TARGET if that's convenient.  */
 rtx
@@ -1409,6 +1467,9 @@ aarch64_expand_builtin (tree exp,
 	expand_insn (CODE_FOR_aarch64_fjcvtzs, 2, ops);
 	return ops[0].value;
       }
+    case AARCH64_BUILTIN_RNG_RNDR:
+    case AARCH64_BUILTIN_RNG_RNDRRS:
+      return aarch64_expand_rng_builtin (exp, target, fcode, ignore);
     }
 
   if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX)
diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index fcce3d672b6..4ad96f5e4af 100644
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -156,6 +156,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
   aarch64_def_or_undef (TARGET_SM4, "__ARM_FEATURE_SM4", pfile);
   aarch64_def_or_undef (TARGET_F16FML, "__ARM_FEATURE_FP16_FML", pfile);
 
+  aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile);
+
   /* Not for ACLE, but required to keep "float.h" correct if we switch
      target between implementations that do or do not support ARMv8.2-A
      16-bit floating-point extensions.  */
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index a575448e406..bfd9245c595 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -114,4 +114,7 @@ AARCH64_OPT_EXTENSION("fp16fml", AARCH64_FL_F16FML, AARCH64_FL_FP | AARCH64_FL_F
    Disabling "sve" just disables "sve".  */
 AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, 0, false, "sve")
 
+/* Enabling/Disabling "rng" only changes "rng".  */
+AARCH64_OPT_EXTENSION("rng", AARCH64_FL_RNG, 0, 0, false, "")
+
 #undef AARCH64_OPT_EXTENSION
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 8c63733c699..feda16e80a0 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -157,6 +157,7 @@ extern unsigned aarch64_architecture_version;
 #define AARCH64_FL_SM4	      (1 << 17)  /* Has ARMv8.4-A SM3 and SM4.  */
 #define AARCH64_FL_SHA3	      (1 << 18)  /* Has ARMv8.4-a SHA3 and SHA512.  */
 #define AARCH64_FL_F16FML     (1 << 19)  /* Has ARMv8.4-a FP16 extensions.  */
+#define AARCH64_FL_RNG        (1 << 23)  /* ARMv8.5-A Random Number Insns.  */
 
 /* Has FP and SIMD.  */
 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
@@ -196,6 +197,7 @@ extern unsigned aarch64_architecture_version;
 #define AARCH64_ISA_SM4	           (aarch64_isa_flags & AARCH64_FL_SM4)
 #define AARCH64_ISA_SHA3	   (aarch64_isa_flags & AARCH64_FL_SHA3)
 #define AARCH64_ISA_F16FML	   (aarch64_isa_flags & AARCH64_FL_F16FML)
+#define AARCH64_ISA_RNG		   (aarch64_isa_flags & AARCH64_FL_RNG)
 
 /* Crypto is an optional extension to AdvSIMD.  */
 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
@@ -237,6 +239,9 @@ extern unsigned aarch64_architecture_version;
 /* Javascript conversion instruction from Armv8.3-a.  */
 #define TARGET_JSCVT	(TARGET_FLOAT && AARCH64_ISA_V8_3)
 
+/* Random number instructions from Armv8.5-a.  */
+#define TARGET_RNG (AARCH64_ISA_RNG)
+
 /* Make sure this is always defined so we don't have to check for ifdefs
    but rather use normal ifs.  */
 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 2b492b53391..9fc555c4006 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -201,6 +201,8 @@
     UNSPECV_SET_FPSR		; Represent assign of FPSR content.
     UNSPECV_BLOCKAGE		; Represent a blockage
     UNSPECV_PROBE_STACK_RANGE	; Represent stack range probing.
+    UNSPEC_RNDR			; Represent RNDR
+    UNSPEC_RNDRRS		; Represent RNDRRS
   ]
 )
 
@@ -6098,6 +6100,26 @@
 		   (match_operand 1))
 	      (clobber (reg:CC CC_REGNUM))])])
 
+(define_insn "aarch64_rndr"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec_volatile:DI [(const_int 0)] UNSPEC_RNDR))
+   (set (reg:CC_Z CC_REGNUM)
+	(unspec_volatile:CC_Z [(const_int 0)] UNSPEC_RNDR))]
+  "TARGET_RNG"
+  "mrs\t%0, RNDR"
+  [(set_attr "type" "mrs")]
+)
+
+(define_insn "aarch64_rndrrs"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec_volatile:DI [(const_int 0)] UNSPEC_RNDRRS))
+   (set (reg:CC_Z CC_REGNUM)
+	(unspec_volatile:CC_Z [(const_int 0)] UNSPEC_RNDRRS))]
+  "TARGET_RNG"
+  "mrs\t%0, RNDRRS"
+  [(set_attr "type" "mrs")]
+)
+
 ;; AdvSIMD Stuff
 (include "aarch64-simd.md")
 
diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index 7bae393c33d..8d16c8763ff 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -95,6 +95,24 @@ __crc32d (uint32_t __a, uint64_t __b)
   return __builtin_aarch64_crc32x (__a, __b);
 }
 
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("+nothing+rng")
+__extension__ static __inline int __attribute__ ((__always_inline__))
+__rndr (uint64_t *__res)
+{
+  return __builtin_aarch64_rndr (__res);
+}
+
+__extension__ static __inline int __attribute__ ((__always_inline__))
+__rndrrs (uint64_t *__res)
+{
+  return __builtin_aarch64_rndrrs (__res);
+}
+
+#pragma GCC pop_options
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rng_1.c b/gcc/testsuite/gcc.target/aarch64/acle/rng_1.c
new file mode 100644
index 00000000000..90be6939ed9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/rng_1.c
@@ -0,0 +1,53 @@
+/* Test the __rndr ACLE intrinsic.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.3-a+rng" } */
+
+#include <arm_acle.h>
+
+#ifdef __ARM_FEATURE_RNG
+/* Check that instruction is generated when status result is unused.  */
+uint64_t
+test_rndr_no_stat (void)
+{
+  uint64_t res;
+  __rndr (&res);
+  return res;
+}
+
+/* Check that instruction is generated when random number result
+   is unused.  */
+int
+test_rndr_error_check (void)
+{
+  uint64_t res;
+  int fail = __rndr (&res);
+  if (fail)
+    return 0;
+  return -1;
+}
+
+/* { dg-final { scan-assembler-times "mrs\tx..?, RNDR\n" 2 } } */
+
+/* Check that instruction is generated when status result is unused.  */
+uint64_t
+test_rndrrs_no_stat (void)
+{
+  uint64_t res;
+  __rndrrs (&res);
+  return res;
+}
+
+/* Check that instruction is generated when random number result
+   is unused.  */
+int
+test_rndrrs_error_check (void)
+{
+  uint64_t res;
+  int fail = __rndrrs (&res);
+  if (fail)
+    return 0;
+  return -1;
+}
+
+/* { dg-final { scan-assembler-times "mrs\tx..?, RNDRRS\n" 2 } } */
+#endif

commit 1788d74b05b7936e9e8dd01a8f66701ad2bc2951
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Thu Jan 10 03:30:59 2019 +0000

    AArch64: Implement Armv8.3-a complex arithmetic intrinsics
    
    I'd like to backport some patches from Tamar in GCC 9 to GCC 8 that implement the complex arithmetic intrinsics for Advanced SIMD.
    These should have been present in GCC 8 that gained support for Armv8.3-a.
    
    There were 4 follow-up fixes that I've rolled into the one commit.
    
    Bootstrapped and tested on aarch64-none-linux-gnu and arm-none-linux-gnueabihf on the GCC 8 branch.
    
    gcc/
            PR target/71233
            * config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
            Add qualifier_lane_pair_index.
            (emit-rtl.h): Include.
            (TYPES_QUADOP_LANE_PAIR): New.
            (aarch64_simd_expand_args): Use it.
            (aarch64_simd_expand_builtin): Likewise.
            (AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
            (FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
            AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
            aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
            (aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
            (aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
            AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
            AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
            AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
            AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
            * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
            * config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
            fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
            fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
            fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
            * config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
            aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
            aarch64_fcmla<rot><mode>): New.
            * config/aarch64/arm_neon.h:
            (vcadd_rot90_f16): New.
            (vcaddq_rot90_f16): New.
            (vcadd_rot270_f16): New.
            (vcaddq_rot270_f16): New.
            (vcmla_f16): New.
            (vcmlaq_f16): New.
            (vcmla_lane_f16): New.
            (vcmla_laneq_f16): New.
            (vcmlaq_lane_f16): New.
            (vcmlaq_rot90_lane_f16): New.
            (vcmla_rot90_laneq_f16): New.
            (vcmla_rot90_lane_f16): New.
            (vcmlaq_rot90_f16): New.
            (vcmla_rot90_f16): New.
            (vcmlaq_laneq_f16): New.
            (vcmla_rot180_laneq_f16): New.
            (vcmla_rot180_lane_f16): New.
            (vcmlaq_rot180_f16): New.
            (vcmla_rot180_f16): New.
            (vcmlaq_rot90_laneq_f16): New.
            (vcmlaq_rot270_laneq_f16): New.
            (vcmlaq_rot270_lane_f16): New.
            (vcmla_rot270_laneq_f16): New.
            (vcmlaq_rot270_f16): New.
            (vcmla_rot270_f16): New.
            (vcmlaq_rot180_laneq_f16): New.
            (vcmlaq_rot180_lane_f16): New.
            (vcmla_rot270_lane_f16): New.
            (vcadd_rot90_f32): New.
            (vcaddq_rot90_f32): New.
            (vcaddq_rot90_f64): New.
            (vcadd_rot270_f32): New.
            (vcaddq_rot270_f32): New.
            (vcaddq_rot270_f64): New.
            (vcmla_f32): New.
            (vcmlaq_f32): New.
            (vcmlaq_f64): New.
            (vcmla_lane_f32): New.
            (vcmla_laneq_f32): New.
            (vcmlaq_lane_f32): New.
            (vcmlaq_laneq_f32): New.
            (vcmla_rot90_f32): New.
            (vcmlaq_rot90_f32): New.
            (vcmlaq_rot90_f64): New.
            (vcmla_rot90_lane_f32): New.
            (vcmla_rot90_laneq_f32): New.
            (vcmlaq_rot90_lane_f32): New.
            (vcmlaq_rot90_laneq_f32): New.
            (vcmla_rot180_f32): New.
            (vcmlaq_rot180_f32): New.
            (vcmlaq_rot180_f64): New.
            (vcmla_rot180_lane_f32): New.
            (vcmla_rot180_laneq_f32): New.
            (vcmlaq_rot180_lane_f32): New.
            (vcmlaq_rot180_laneq_f32): New.
            (vcmla_rot270_f32): New.
            (vcmlaq_rot270_f32): New.
            (vcmlaq_rot270_f64): New.
            (vcmla_rot270_lane_f32): New.
            (vcmla_rot270_laneq_f32): New.
            (vcmlaq_rot270_lane_f32): New.
            (vcmlaq_rot270_laneq_f32): New.
            * config/aarch64/aarch64.h (TARGET_COMPLEX): New.
            * config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
            UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
            (FCADD, FCMLA): New.
            (rot): New.
            (FCMLA_maybe_lane): New.
            * config/arm/types.md (neon_fcadd, neon_fcmla): New.
    
    gcc/testsuite/
            PR target/71233
            * lib/target-supports.exp
            (check_effective_target_arm_v8_3a_complex_neon_ok_nocache,
            check_effective_target_arm_v8_3a_complex_neon_ok,
            add_options_for_arm_v8_3a_complex_neon,
            check_effective_target_arm_v8_3a_complex_neon_hw,
            check_effective_target_vect_complex_rot_N): New.
            * gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
            * gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index e6815900c90..234ceeff6fc 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -42,6 +42,7 @@
 #include "langhooks.h"
 #include "gimple-iterator.h"
 #include "case-cfn-macros.h"
+#include "emit-rtl.h"
 
 #define v8qi_UP  E_V8QImode
 #define v4hi_UP  E_V4HImode
@@ -102,7 +103,10 @@ enum aarch64_type_qualifiers
   /* Lane indices - must be in range, and flipped for bigendian.  */
   qualifier_lane_index = 0x200,
   /* Lane indices for single lane structure loads and stores.  */
-  qualifier_struct_load_store_lane_index = 0x400
+  qualifier_struct_load_store_lane_index = 0x400,
+  /* Lane indices selected in pairs. - must be in range, and flipped for
+     bigendian.  */
+  qualifier_lane_pair_index = 0x800,
 };
 
 typedef struct
@@ -171,6 +175,11 @@ aarch64_types_ternopu_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
 #define TYPES_TERNOPUI (aarch64_types_ternopu_imm_qualifiers)
 
 
+static enum aarch64_type_qualifiers
+aarch64_types_quadop_lane_pair_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_none, qualifier_none, qualifier_none,
+      qualifier_none, qualifier_lane_pair_index };
+#define TYPES_QUADOP_LANE_PAIR (aarch64_types_quadop_lane_pair_qualifiers)
 static enum aarch64_type_qualifiers
 aarch64_types_quadop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_none,
@@ -356,6 +365,18 @@ static aarch64_simd_builtin_datum aarch64_simd_builtin_data[] = {
   CRC32_BUILTIN (crc32cw, SI) \
   CRC32_BUILTIN (crc32cx, DI)
 
+/* The next 8 FCMLA instrinsics require some special handling compared the
+   normal simd intrinsics.  */
+#define AARCH64_SIMD_FCMLA_LANEQ_BUILTINS \
+  FCMLA_LANEQ_BUILTIN (0, v2sf, fcmla, V2SF, false) \
+  FCMLA_LANEQ_BUILTIN (90, v2sf, fcmla, V2SF, false) \
+  FCMLA_LANEQ_BUILTIN (180, v2sf, fcmla, V2SF, false) \
+  FCMLA_LANEQ_BUILTIN (270, v2sf, fcmla, V2SF, false) \
+  FCMLA_LANEQ_BUILTIN (0, v4hf, fcmla_laneq, V4HF, true) \
+  FCMLA_LANEQ_BUILTIN (90, v4hf, fcmla_laneq, V4HF, true) \
+  FCMLA_LANEQ_BUILTIN (180, v4hf, fcmla_laneq, V4HF, true) \
+  FCMLA_LANEQ_BUILTIN (270, v4hf, fcmla_laneq, V4HF, true) \
+
 typedef struct
 {
   const char *name;
@@ -364,9 +385,22 @@ typedef struct
   unsigned int fcode;
 } aarch64_crc_builtin_datum;
 
+/* Hold information about how to expand the FCMLA_LANEQ builtins.  */
+typedef struct
+{
+  const char *name;
+  machine_mode mode;
+  const enum insn_code icode;
+  unsigned int fcode;
+  bool lane;
+} aarch64_fcmla_laneq_builtin_datum;
+
 #define CRC32_BUILTIN(N, M) \
   AARCH64_BUILTIN_##N,
 
+#define FCMLA_LANEQ_BUILTIN(I, N, X, M, T) \
+  AARCH64_SIMD_BUILTIN_FCMLA_LANEQ##I##_##M,
+
 #undef VAR1
 #define VAR1(T, N, MAP, A) \
   AARCH64_SIMD_BUILTIN_##T##_##N##A,
@@ -404,6 +438,9 @@ enum aarch64_builtins
   /* Armv8.5-a RNG instruction builtins.  */
   AARCH64_BUILTIN_RNG_RNDR,
   AARCH64_BUILTIN_RNG_RNDRRS,
+  /* Special cased Armv8.3-A Complex FMA by Lane quad Builtins.  */
+  AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
+  AARCH64_SIMD_FCMLA_LANEQ_BUILTINS
   AARCH64_BUILTIN_MAX
 };
 
@@ -415,6 +452,18 @@ static aarch64_crc_builtin_datum aarch64_crc_builtin_data[] = {
   AARCH64_CRC32_BUILTINS
 };
 
+
+#undef FCMLA_LANEQ_BUILTIN
+#define FCMLA_LANEQ_BUILTIN(I, N, X, M, T) \
+  {"__builtin_aarch64_fcmla_laneq"#I#N, E_##M##mode, CODE_FOR_aarch64_##X##I##N, \
+   AARCH64_SIMD_BUILTIN_FCMLA_LANEQ##I##_##M, T},
+
+/* This structure contains how to manage the mapping form the builtin to the
+   instruction to generate in the backend and how to invoke the instruction.  */
+static aarch64_fcmla_laneq_builtin_datum aarch64_fcmla_lane_builtin_data[] = {
+  AARCH64_SIMD_FCMLA_LANEQ_BUILTINS
+};
+
 #undef CRC32_BUILTIN
 
 static GTY(()) tree aarch64_builtin_decls[AARCH64_BUILTIN_MAX];
@@ -747,6 +796,34 @@ aarch64_init_simd_builtin_scalar_types (void)
 
 static bool aarch64_simd_builtins_initialized_p = false;
 
+/* Due to the architecture not providing lane variant of the lane instructions
+   for fcmla we can't use the standard simd builtin expansion code, but we
+   still want the majority of the validation that would normally be done.  */
+
+void
+aarch64_init_fcmla_laneq_builtins (void)
+{
+  unsigned int i = 0;
+
+  for (i = 0; i < ARRAY_SIZE (aarch64_fcmla_lane_builtin_data); ++i)
+    {
+      aarch64_fcmla_laneq_builtin_datum* d
+	= &aarch64_fcmla_lane_builtin_data[i];
+      tree argtype = aarch64_lookup_simd_builtin_type (d->mode, qualifier_none);
+      machine_mode quadmode = GET_MODE_2XWIDER_MODE (d->mode).require ();
+      tree quadtype
+	= aarch64_lookup_simd_builtin_type (quadmode, qualifier_none);
+      tree lanetype
+	= aarch64_simd_builtin_std_type (SImode, qualifier_lane_pair_index);
+      tree ftype = build_function_type_list (argtype, argtype, argtype,
+					     quadtype, lanetype, NULL_TREE);
+      tree fndecl = add_builtin_function (d->name, ftype, d->fcode,
+					  BUILT_IN_MD, NULL, NULL_TREE);
+
+      aarch64_builtin_decls[d->fcode] = fndecl;
+    }
+}
+
 void
 aarch64_init_simd_builtins (void)
 {
@@ -875,6 +952,9 @@ aarch64_init_simd_builtins (void)
 				     NULL, NULL_TREE);
       aarch64_builtin_decls[fcode] = fndecl;
     }
+
+   /* Initialize the remaining fcmla_laneq intrinsics.  */
+   aarch64_init_fcmla_laneq_builtins ();
 }
 
 static void
@@ -1057,6 +1137,7 @@ typedef enum
   SIMD_ARG_CONSTANT,
   SIMD_ARG_LANE_INDEX,
   SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX,
+  SIMD_ARG_LANE_PAIR_INDEX,
   SIMD_ARG_STOP
 } builtin_simd_arg;
 
@@ -1128,6 +1209,24 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
 		  /* Keep to GCC-vector-extension lane indices in the RTL.  */
 		  op[opc] = aarch64_endian_lane_rtx (vmode, INTVAL (op[opc]));
 		}
+	      /* If the lane index isn't a constant then error out.  */
+	      goto constant_arg;
+
+	    case SIMD_ARG_LANE_PAIR_INDEX:
+	      /* Must be a previous operand into which this is an index and
+		 index is restricted to nunits / 2.  */
+	      gcc_assert (opc > 0);
+	      if (CONST_INT_P (op[opc]))
+		{
+		  machine_mode vmode = insn_data[icode].operand[opc - 1].mode;
+		  unsigned int nunits
+		    = GET_MODE_NUNITS (vmode).to_constant ();
+		  aarch64_simd_lane_bounds (op[opc], 0, nunits / 2, exp);
+		  /* Keep to GCC-vector-extension lane indices in the RTL.  */
+		  int lane = INTVAL (op[opc]);
+		  op[opc] = gen_int_mode (ENDIAN_LANE_N (nunits / 2, lane),
+					  SImode);
+		}
 	      /* Fall through - if the lane index isn't a constant then
 		 the next case will error.  */
 	      /* FALLTHRU */
@@ -1241,6 +1340,8 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target)
 
       if (d->qualifiers[qualifiers_k] & qualifier_lane_index)
 	args[k] = SIMD_ARG_LANE_INDEX;
+      else if (d->qualifiers[qualifiers_k] & qualifier_lane_pair_index)
+	args[k] = SIMD_ARG_LANE_PAIR_INDEX;
       else if (d->qualifiers[qualifiers_k] & qualifier_struct_load_store_lane_index)
 	args[k] = SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX;
       else if (d->qualifiers[qualifiers_k] & qualifier_immediate)
@@ -1379,6 +1480,85 @@ aarch64_expand_rng_builtin (tree exp, rtx target, int fcode, int ignore)
   return target;
 }
 
+/* Expand a FCMLA lane expression EXP with code FCODE and
+   result going to TARGET if that is convenient.  */
+
+rtx
+aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+{
+  int bcode = fcode - AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE - 1;
+  aarch64_fcmla_laneq_builtin_datum* d
+    = &aarch64_fcmla_lane_builtin_data[bcode];
+  machine_mode quadmode = GET_MODE_2XWIDER_MODE (d->mode).require ();
+  rtx op0 = force_reg (d->mode, expand_normal (CALL_EXPR_ARG (exp, 0)));
+  rtx op1 = force_reg (d->mode, expand_normal (CALL_EXPR_ARG (exp, 1)));
+  rtx op2 = force_reg (quadmode, expand_normal (CALL_EXPR_ARG (exp, 2)));
+  tree tmp = CALL_EXPR_ARG (exp, 3);
+  rtx lane_idx = expand_expr (tmp, NULL_RTX, VOIDmode, EXPAND_INITIALIZER);
+
+  /* Validate that the lane index is a constant.  */
+  if (!CONST_INT_P (lane_idx))
+    {
+      error ("%Kargument %d must be a constant immediate", exp, 4);
+      return const0_rtx;
+    }
+
+  /* Validate that the index is within the expected range.  */
+  int nunits = GET_MODE_NUNITS (quadmode).to_constant ();
+  aarch64_simd_lane_bounds (lane_idx, 0, nunits / 2, exp);
+
+  /* Generate the correct register and mode.  */
+  int lane = INTVAL (lane_idx);
+
+  if (lane < nunits / 4)
+    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+			       subreg_lowpart_offset (d->mode, quadmode));
+  else
+    {
+      /* Select the upper 64 bits, either a V2SF or V4HF, this however
+	 is quite messy, as the operation required even though simple
+	 doesn't have a simple RTL pattern, and seems it's quite hard to
+	 define using a single RTL pattern.  The target generic version
+	 gen_highpart_mode generates code that isn't optimal.  */
+      rtx temp1 = gen_reg_rtx (d->mode);
+      rtx temp2 = gen_reg_rtx (DImode);
+      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+				   subreg_lowpart_offset (d->mode, quadmode));
+      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
+      if (BYTES_BIG_ENDIAN)
+	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+      else
+	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+
+      /* And recalculate the index.  */
+      lane -= nunits / 4;
+    }
+
+  /* Keep to GCC-vector-extension lane indices in the RTL, only nunits / 4
+     (max nunits in range check) are valid.  Which means only 0-1, so we
+     only need to know the order in a V2mode.  */
+  lane_idx = aarch64_endian_lane_rtx (V2DImode, lane);
+
+  if (!target)
+    target = gen_reg_rtx (d->mode);
+  else
+    target = force_reg (d->mode, target);
+
+  rtx pat = NULL_RTX;
+
+  if (d->lane)
+    pat = GEN_FCN (d->icode) (target, op0, op1, op2, lane_idx);
+  else
+    pat = GEN_FCN (d->icode) (target, op0, op1, op2);
+
+  if (!pat)
+    return NULL_RTX;
+
+  emit_insn (pat);
+  return target;
+}
+
 /* Expand an expression EXP that calls a built-in function,
    with result going to TARGET if that's convenient.  */
 rtx
@@ -1470,6 +1650,15 @@ aarch64_expand_builtin (tree exp,
     case AARCH64_BUILTIN_RNG_RNDR:
     case AARCH64_BUILTIN_RNG_RNDRRS:
       return aarch64_expand_rng_builtin (exp, target, fcode, ignore);
+    case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF:
+    case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF:
+    case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF:
+    case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V2SF:
+    case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF:
+    case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF:
+    case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF:
+    case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF:
+      return aarch64_expand_fcmla_builtin (exp, target, fcode);
     }
 
   if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX)
diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index 4ad96f5e4af..fbcf1d95338 100644
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -110,6 +110,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
   aarch64_def_or_undef (TARGET_CRC32, "__ARM_FEATURE_CRC32", pfile);
   aarch64_def_or_undef (TARGET_DOTPROD, "__ARM_FEATURE_DOTPROD", pfile);
   aarch64_def_or_undef (TARGET_JSCVT, "__ARM_FEATURE_JCVT", pfile);
+  aarch64_def_or_undef (TARGET_COMPLEX, "__ARM_FEATURE_COMPLEX", pfile);
 
   cpp_undef (pfile, "__AARCH64_CMODEL_TINY__");
   cpp_undef (pfile, "__AARCH64_CMODEL_SMALL__");
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index fe3e392cfb9..9566dc44d0b 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -217,6 +217,25 @@
   BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0)
   BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0)
 
+  /* Implemented by aarch64_fcadd<rot><mode>.   */
+  BUILTIN_VHSDF (BINOP, fcadd90, 0)
+  BUILTIN_VHSDF (BINOP, fcadd270, 0)
+
+  /* Implemented by aarch64_fcmla{_lane}{q}<rot><mode>.   */
+  BUILTIN_VHSDF (TERNOP, fcmla0, 0)
+  BUILTIN_VHSDF (TERNOP, fcmla90, 0)
+  BUILTIN_VHSDF (TERNOP, fcmla180, 0)
+  BUILTIN_VHSDF (TERNOP, fcmla270, 0)
+  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0)
+  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0)
+  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane180, 0)
+  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane270, 0)
+
+  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane0, 0)
+  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane90, 0)
+  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane180, 0)
+  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane270, 0)
+
   BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
   VAR1 (SHIFTIMM, ashr_simd, 0, di)
   BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 8cec46d30ca..8fe7ba9e258 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -391,6 +391,81 @@
 }
 )
 
+;; The fcadd and fcmla patterns are made UNSPEC for the explicitly due to the
+;; fact that their usage need to guarantee that the source vectors are
+;; contiguous.  It would be wrong to describe the operation without being able
+;; to describe the permute that is also required, but even if that is done
+;; the permute would have been created as a LOAD_LANES which means the values
+;; in the registers are in the wrong order.
+(define_insn "aarch64_fcadd<rot><mode>"
+  [(set (match_operand:VHSDF 0 "register_operand" "=w")
+	(unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")
+		       (match_operand:VHSDF 2 "register_operand" "w")]
+		       FCADD))]
+  "TARGET_COMPLEX"
+  "fcadd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>, #<rot>"
+  [(set_attr "type" "neon_fcadd")]
+)
+
+(define_insn "aarch64_fcmla<rot><mode>"
+  [(set (match_operand:VHSDF 0 "register_operand" "=w")
+	(plus:VHSDF (match_operand:VHSDF 1 "register_operand" "0")
+		    (unspec:VHSDF [(match_operand:VHSDF 2 "register_operand" "w")
+				   (match_operand:VHSDF 3 "register_operand" "w")]
+				   FCMLA)))]
+  "TARGET_COMPLEX"
+  "fcmla\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>, #<rot>"
+  [(set_attr "type" "neon_fcmla")]
+)
+
+
+(define_insn "aarch64_fcmla_lane<rot><mode>"
+  [(set (match_operand:VHSDF 0 "register_operand" "=w")
+	(plus:VHSDF (match_operand:VHSDF 1 "register_operand" "0")
+		    (unspec:VHSDF [(match_operand:VHSDF 2 "register_operand" "w")
+				   (match_operand:VHSDF 3 "register_operand" "w")
+				   (match_operand:SI 4 "const_int_operand" "n")]
+				   FCMLA)))]
+  "TARGET_COMPLEX"
+{
+  operands[4] = aarch64_endian_lane_rtx (<VHALF>mode, INTVAL (operands[4]));
+  return "fcmla\t%0.<Vtype>, %2.<Vtype>, %3.<FCMLA_maybe_lane>, #<rot>";
+}
+  [(set_attr "type" "neon_fcmla")]
+)
+
+(define_insn "aarch64_fcmla_laneq<rot>v4hf"
+  [(set (match_operand:V4HF 0 "register_operand" "=w")
+	(plus:V4HF (match_operand:V4HF 1 "register_operand" "0")
+		   (unspec:V4HF [(match_operand:V4HF 2 "register_operand" "w")
+				 (match_operand:V8HF 3 "register_operand" "w")
+				 (match_operand:SI 4 "const_int_operand" "n")]
+				 FCMLA)))]
+  "TARGET_COMPLEX"
+{
+  operands[4] = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));
+  return "fcmla\t%0.4h, %2.4h, %3.h[%4], #<rot>";
+}
+  [(set_attr "type" "neon_fcmla")]
+)
+
+(define_insn "aarch64_fcmlaq_lane<rot><mode>"
+  [(set (match_operand:VQ_HSF 0 "register_operand" "=w")
+	(plus:VQ_HSF (match_operand:VQ_HSF 1 "register_operand" "0")
+		     (unspec:VQ_HSF [(match_operand:VQ_HSF 2 "register_operand" "w")
+				     (match_operand:<VHALF> 3 "register_operand" "w")
+				     (match_operand:SI 4 "const_int_operand" "n")]
+				     FCMLA)))]
+  "TARGET_COMPLEX"
+{
+  int nunits = GET_MODE_NUNITS (<VHALF>mode).to_constant ();
+  operands[4]
+    = gen_int_mode (ENDIAN_LANE_N (nunits / 2, INTVAL (operands[4])), SImode);
+  return "fcmla\t%0.<Vtype>, %2.<Vtype>, %3.<FCMLA_maybe_lane>, #<rot>";
+}
+  [(set_attr "type" "neon_fcmla")]
+)
+
 ;; These instructions map to the __builtins for the Dot Product operations.
 (define_insn "aarch64_<sur>dot<vsi2qi>"
   [(set (match_operand:VS 0 "register_operand" "=w")
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index feda16e80a0..42d61b94c9c 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -242,6 +242,9 @@ extern unsigned aarch64_architecture_version;
 /* Random number instructions from Armv8.5-a.  */
 #define TARGET_RNG (AARCH64_ISA_RNG)
 
+/* Armv8.3-a Complex number extension to AdvSIMD extensions.  */
+#define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3)
+
 /* Make sure this is always defined so we don't have to check for ifdefs
    but rather use normal ifs.  */
 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index e34deec729c..e73a1e1c838 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -33802,6 +33802,481 @@ vbcaxq_s64 (int64x2_t __a, int64x2_t __b, int64x2_t __c)
   return __builtin_aarch64_bcaxqv2di (__a, __b, __c);
 }
 
+#pragma GCC pop_options
+
+/* AdvSIMD Complex numbers intrinsics.  */
+
+#pragma GCC push_options
+#pragma GCC target(("arch=armv8.3-a"))
+
+#pragma GCC push_options
+#pragma GCC target(("+fp16"))
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcadd_rot90_f16 (float16x4_t __a, float16x4_t __b)
+{
+  return __builtin_aarch64_fcadd90v4hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcaddq_rot90_f16 (float16x8_t __a, float16x8_t __b)
+{
+  return __builtin_aarch64_fcadd90v8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcadd_rot270_f16 (float16x4_t __a, float16x4_t __b)
+{
+  return __builtin_aarch64_fcadd270v4hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcaddq_rot270_f16 (float16x8_t __a, float16x8_t __b)
+{
+  return __builtin_aarch64_fcadd270v8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return __builtin_aarch64_fcmla0v4hf (__r, __a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return __builtin_aarch64_fcmla0v8hf (__r, __a, __b);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_lane_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b,
+		const int __index)
+{
+  return __builtin_aarch64_fcmla_lane0v4hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_laneq_f16 (float16x4_t __r, float16x4_t __a, float16x8_t __b,
+		 const int __index)
+{
+  return __builtin_aarch64_fcmla_laneq0v4hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_lane_f16 (float16x8_t __r, float16x8_t __a, float16x4_t __b,
+		 const int __index)
+{
+  return __builtin_aarch64_fcmlaq_lane0v8hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot90_lane_f16 (float16x8_t __r, float16x8_t __a, float16x4_t __b,
+		       const int __index)
+{
+  return __builtin_aarch64_fcmlaq_lane90v8hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot90_laneq_f16 (float16x4_t __r, float16x4_t __a, float16x8_t __b,
+		       const int __index)
+{
+  return __builtin_aarch64_fcmla_laneq90v4hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot90_lane_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b,
+		      const int __index)
+{
+  return __builtin_aarch64_fcmla_lane90v4hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot90_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return __builtin_aarch64_fcmla90v8hf (__r, __a, __b);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot90_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return __builtin_aarch64_fcmla90v4hf (__r, __a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_laneq_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b,
+		  const int __index)
+{
+  return __builtin_aarch64_fcmla_lane0v8hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot180_laneq_f16 (float16x4_t __r, float16x4_t __a, float16x8_t __b,
+			const int __index)
+{
+  return __builtin_aarch64_fcmla_laneq180v4hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot180_lane_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b,
+		       const int __index)
+{
+  return __builtin_aarch64_fcmla_lane180v4hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot180_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return __builtin_aarch64_fcmla180v8hf (__r, __a, __b);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot180_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return __builtin_aarch64_fcmla180v4hf (__r, __a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot90_laneq_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b,
+			const int __index)
+{
+  return __builtin_aarch64_fcmla_lane90v8hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot270_laneq_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b,
+			 const int __index)
+{
+  return __builtin_aarch64_fcmla_lane270v8hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot270_lane_f16 (float16x8_t __r, float16x8_t __a, float16x4_t __b,
+			const int __index)
+{
+  return __builtin_aarch64_fcmlaq_lane270v8hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot270_laneq_f16 (float16x4_t __r, float16x4_t __a, float16x8_t __b,
+			const int __index)
+{
+  return __builtin_aarch64_fcmla_laneq270v4hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot270_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return __builtin_aarch64_fcmla270v8hf (__r, __a, __b);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot270_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return __builtin_aarch64_fcmla270v4hf (__r, __a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot180_laneq_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b,
+			 const int __index)
+{
+  return __builtin_aarch64_fcmla_lane180v8hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot180_lane_f16 (float16x8_t __r, float16x8_t __a, float16x4_t __b,
+			const int __index)
+{
+  return __builtin_aarch64_fcmlaq_lane180v8hf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot270_lane_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b,
+		       const int __index)
+{
+  return __builtin_aarch64_fcmla_lane270v4hf (__r, __a, __b, __index);
+}
+#pragma GCC pop_options
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcadd_rot90_f32 (float32x2_t __a, float32x2_t __b)
+{
+  return __builtin_aarch64_fcadd90v2sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b)
+{
+  return __builtin_aarch64_fcadd90v4sf (__a, __b);
+}
+
+__extension__ extern __inline float64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcaddq_rot90_f64 (float64x2_t __a, float64x2_t __b)
+{
+  return __builtin_aarch64_fcadd90v2df (__a, __b);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcadd_rot270_f32 (float32x2_t __a, float32x2_t __b)
+{
+  return __builtin_aarch64_fcadd270v2sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b)
+{
+  return __builtin_aarch64_fcadd270v4sf (__a, __b);
+}
+
+__extension__ extern __inline float64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcaddq_rot270_f64 (float64x2_t __a, float64x2_t __b)
+{
+  return __builtin_aarch64_fcadd270v2df (__a, __b);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return __builtin_aarch64_fcmla0v2sf (__r, __a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return __builtin_aarch64_fcmla0v4sf (__r, __a, __b);
+}
+
+__extension__ extern __inline float64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
+{
+  return __builtin_aarch64_fcmla0v2df (__r, __a, __b);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b,
+		const int __index)
+{
+  return __builtin_aarch64_fcmla_lane0v2sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b,
+		 const int __index)
+{
+  return __builtin_aarch64_fcmla_laneq0v2sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b,
+		 const int __index)
+{
+  return __builtin_aarch64_fcmlaq_lane0v4sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b,
+		  const int __index)
+{
+  return __builtin_aarch64_fcmla_lane0v4sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot90_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return __builtin_aarch64_fcmla90v2sf (__r, __a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot90_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return __builtin_aarch64_fcmla90v4sf (__r, __a, __b);
+}
+
+__extension__ extern __inline float64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot90_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
+{
+  return __builtin_aarch64_fcmla90v2df (__r, __a, __b);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot90_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b,
+		      const int __index)
+{
+  return __builtin_aarch64_fcmla_lane90v2sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot90_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b,
+		       const int __index)
+{
+  return __builtin_aarch64_fcmla_laneq90v2sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot90_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b,
+		       const int __index)
+{
+  return __builtin_aarch64_fcmlaq_lane90v4sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot90_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b,
+			const int __index)
+{
+  return __builtin_aarch64_fcmla_lane90v4sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot180_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return __builtin_aarch64_fcmla180v2sf (__r, __a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot180_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return __builtin_aarch64_fcmla180v4sf (__r, __a, __b);
+}
+
+__extension__ extern __inline float64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot180_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
+{
+  return __builtin_aarch64_fcmla180v2df (__r, __a, __b);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot180_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b,
+		       const int __index)
+{
+  return __builtin_aarch64_fcmla_lane180v2sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot180_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b,
+			const int __index)
+{
+  return __builtin_aarch64_fcmla_laneq180v2sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot180_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b,
+			const int __index)
+{
+  return __builtin_aarch64_fcmlaq_lane180v4sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot180_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b,
+			 const int __index)
+{
+  return __builtin_aarch64_fcmla_lane180v4sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot270_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return __builtin_aarch64_fcmla270v2sf (__r, __a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot270_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return __builtin_aarch64_fcmla270v4sf (__r, __a, __b);
+}
+
+__extension__ extern __inline float64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot270_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
+{
+  return __builtin_aarch64_fcmla270v2df (__r, __a, __b);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot270_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b,
+		       const int __index)
+{
+  return __builtin_aarch64_fcmla_lane270v2sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmla_rot270_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b,
+			const int __index)
+{
+  return __builtin_aarch64_fcmla_laneq270v2sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot270_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b,
+			const int __index)
+{
+  return __builtin_aarch64_fcmlaq_lane270v4sf (__r, __a, __b, __index);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcmlaq_rot270_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b,
+			 const int __index)
+{
+  return __builtin_aarch64_fcmla_lane270v4sf (__r, __a, __b, __index);
+}
 
 #pragma GCC pop_options
 
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 88176a1ed97..b7c7dab3aa8 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -467,6 +467,12 @@
     UNSPEC_COND_HI	; Used in aarch64-sve.md.
     UNSPEC_COND_UO	; Used in aarch64-sve.md.
     UNSPEC_LASTB	; Used in aarch64-sve.md.
+    UNSPEC_FCADD90	; Used in aarch64-simd.md.
+    UNSPEC_FCADD270	; Used in aarch64-simd.md.
+    UNSPEC_FCMLA	; Used in aarch64-simd.md.
+    UNSPEC_FCMLA90	; Used in aarch64-simd.md.
+    UNSPEC_FCMLA180	; Used in aarch64-simd.md.
+    UNSPEC_FCMLA270	; Used in aarch64-simd.md.
 ])
 
 ;; ------------------------------------------------------------------
@@ -1115,6 +1121,13 @@
 			 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
 			 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
 
+;; On AArch64 the By element instruction doesn't have a 2S variant.
+;; However because the instruction always selects a pair of values
+;; The normal 3SAME instruction can be used here instead.
+(define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]")
+				    (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]")
+				    ])
+
 ;; -------------------------------------------------------------------
 ;; Code Iterators
 ;; -------------------------------------------------------------------
@@ -1499,6 +1512,14 @@
 				      UNSPEC_COND_EQ UNSPEC_COND_NE
 				      UNSPEC_COND_GE UNSPEC_COND_GT])
 
+(define_int_iterator FCADD [UNSPEC_FCADD90
+			    UNSPEC_FCADD270])
+
+(define_int_iterator FCMLA [UNSPEC_FCMLA
+			    UNSPEC_FCMLA90
+			    UNSPEC_FCMLA180
+			    UNSPEC_FCMLA270])
+
 ;; Iterators for atomic operations.
 
 (define_int_iterator ATOMIC_LDOP
@@ -1770,3 +1791,11 @@
 
 (define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd")
 			    (UNSPEC_COND_SUB "fsub")])
+
+(define_int_attr rot [(UNSPEC_FCADD90 "90")
+		      (UNSPEC_FCADD270 "270")
+		      (UNSPEC_FCMLA "0")
+		      (UNSPEC_FCMLA90 "90")
+		      (UNSPEC_FCMLA180 "180")
+		      (UNSPEC_FCMLA270 "270")])
+
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 055cb3e7d94..18020387998 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -763,6 +763,9 @@
   neon_sub_halve,\
   neon_sub_halve_q,\
   neon_sub_halve_narrow_q,\
+\
+  neon_fcadd,\
+  neon_fcmla,\
 \
   neon_abs,\
   neon_abs_q,\
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vector-complex.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vector-complex.c
new file mode 100644
index 00000000000..c505284b193
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vector-complex.c
@@ -0,0 +1,251 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon }  */
+/* { dg-additional-options "-O2 -save-temps" } */
+
+#include <arm_neon.h>
+
+float32x2_t
+test_vcadd_rot90_f32 (float32x2_t __a, float32x2_t __b)
+{
+  return vcadd_rot90_f32 (__a, __b);
+}
+
+float32x4_t
+test_vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b)
+{
+  return vcaddq_rot90_f32 (__a, __b);
+}
+
+#ifdef __ARM_ARCH_ISA_A64
+float64x2_t
+test_vcaddq_rot90_f64 (float64x2_t __a, float64x2_t __b)
+{
+  return vcaddq_rot90_f64 (__a, __b);
+}
+#endif
+
+float32x2_t
+test_vcadd_rot270_f32 (float32x2_t __a, float32x2_t __b)
+{
+  return vcadd_rot270_f32 (__a, __b);
+}
+
+float32x4_t
+test_vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b)
+{
+  return vcaddq_rot270_f32 (__a, __b);
+}
+
+#ifdef __ARM_ARCH_ISA_A64
+float64x2_t
+test_vcaddq_rot270_f64 (float64x2_t __a, float64x2_t __b)
+{
+  return vcaddq_rot270_f64 (__a, __b);
+}
+#endif
+
+float32x2_t
+test_vcmla_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return vcmla_f32 (__r, __a, __b);
+}
+
+float32x4_t
+test_vcmlaq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return vcmlaq_f32 (__r, __a, __b);
+}
+
+#ifdef __ARM_ARCH_ISA_A64
+float64x2_t
+test_vcmlaq_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
+{
+  return vcmlaq_f64 (__r, __a, __b);
+}
+#endif
+
+float32x2_t
+test_vcmla_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return vcmla_lane_f32 (__r, __a, __b, 0);
+}
+
+float32x2_t
+test_vcmla_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b)
+{
+  return vcmla_laneq_f32 (__r, __a, __b, 1);
+}
+
+float32x4_t
+test_vcmlaq_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b)
+{
+  return vcmlaq_lane_f32 (__r, __a, __b, 0);
+}
+
+float32x4_t
+test_vcmlaq_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return vcmlaq_laneq_f32 (__r, __a, __b, 1);
+}
+
+float32x2_t
+test_vcmla_rot90_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return vcmla_rot90_f32 (__r, __a, __b);
+}
+
+float32x4_t
+test_vcmlaq_rot90_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return vcmlaq_rot90_f32 (__r, __a, __b);
+}
+
+#ifdef __ARM_ARCH_ISA_A64
+float64x2_t
+test_vcmlaq_rot90_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
+{
+  return vcmlaq_rot90_f64 (__r, __a, __b);
+}
+#endif
+
+float32x2_t
+test_vcmla_rot90_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return vcmla_rot90_lane_f32 (__r, __a, __b, 0);
+}
+
+float32x2_t
+test_vcmla_rot90_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b)
+{
+  return vcmla_rot90_laneq_f32 (__r, __a, __b, 1);
+}
+
+float32x4_t
+test_vcmlaq_rot90_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b)
+{
+  return vcmlaq_rot90_lane_f32 (__r, __a, __b, 0);
+}
+
+float32x4_t
+test_vcmlaq_rot90_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return vcmlaq_rot90_laneq_f32 (__r, __a, __b, 1);
+}
+
+float32x2_t
+test_vcmla_rot180_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return vcmla_rot180_f32 (__r, __a, __b);
+}
+
+float32x4_t
+test_vcmlaq_rot180_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return vcmlaq_rot180_f32 (__r, __a, __b);
+}
+
+#ifdef __ARM_ARCH_ISA_A64
+float64x2_t
+test_vcmlaq_rot180_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
+{
+  return vcmlaq_rot180_f64 (__r, __a, __b);
+}
+#endif
+
+float32x2_t
+test_vcmla_rot180_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return vcmla_rot180_lane_f32 (__r, __a, __b, 0);
+}
+
+float32x2_t
+test_vcmla_rot180_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b)
+{
+  return vcmla_rot180_laneq_f32 (__r, __a, __b, 1);
+}
+
+float32x4_t
+test_vcmlaq_rot180_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b)
+{
+  return vcmlaq_rot180_lane_f32 (__r, __a, __b, 0);
+}
+
+float32x4_t
+test_vcmlaq_rot180_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return vcmlaq_rot180_laneq_f32 (__r, __a, __b, 1);
+}
+
+float32x2_t
+test_vcmla_rot270_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return vcmla_rot270_f32 (__r, __a, __b);
+}
+
+float32x4_t
+test_vcmlaq_rot270_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return vcmlaq_rot270_f32 (__r, __a, __b);
+}
+
+#ifdef __ARM_ARCH_ISA_A64
+float64x2_t
+test_vcmlaq_rot270_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
+{
+  return vcmlaq_rot270_f64 (__r, __a, __b);
+}
+#endif
+
+float32x2_t
+test_vcmla_rot270_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
+{
+  return vcmla_rot270_lane_f32 (__r, __a, __b, 0);
+}
+
+float32x2_t
+test_vcmla_rot270_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b)
+{
+  return vcmla_rot270_laneq_f32 (__r, __a, __b, 1);
+}
+
+float32x4_t
+test_vcmlaq_rot270_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b)
+{
+  return vcmlaq_rot270_lane_f32 (__r, __a, __b, 0);
+}
+
+float32x4_t
+test_vcmlaq_rot270_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
+{
+  return vcmlaq_rot270_laneq_f32 (__r, __a, __b, 1);
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #0} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #180} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #0} 3 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #180} 3 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #270} 3 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #90} 3 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #0} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #180} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[0\], #0} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[0\], #180} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[0\], #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[0\], #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[1\], #0} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[1\], #180} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[1\], #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[1\], #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {dup\td[0-9]+, v[0-9]+.d\[1\]} 4 { target { aarch64*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c
new file mode 100644
index 00000000000..86a75731489
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c
@@ -0,0 +1,307 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target arm_v8_2a_fp16_neon_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-add-options arm_v8_2a_fp16_neon } */
+/* { dg-additional-options "-O2 -march=armv8.3-a+fp16 -save-temps" } */
+
+#include <arm_neon.h>
+
+float16x4_t
+test_vcadd_rot90_f16 (float16x4_t __a, float16x4_t __b)
+{
+  return vcadd_rot90_f16 (__a, __b);
+}
+
+float16x8_t
+test_vcaddq_rot90_f16 (float16x8_t __a, float16x8_t __b)
+{
+  return vcaddq_rot90_f16 (__a, __b);
+}
+
+float16x4_t
+test_vcadd_rot270_f16 (float16x4_t __a, float16x4_t __b)
+{
+  return vcadd_rot270_f16 (__a, __b);
+}
+
+float16x8_t
+test_vcaddq_rot270_f16 (float16x8_t __a, float16x8_t __b)
+{
+  return vcaddq_rot270_f16 (__a, __b);
+}
+
+float16x4_t
+test_vcmla_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_f16 (__r, __a, __b);
+}
+
+float16x8_t
+test_vcmlaq_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_f16 (__r, __a, __b);
+}
+
+float16x4_t
+test_vcmla_lane_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_lane_f16 (__r, __a, __b, 0);
+}
+
+float16x4_t
+test_vcmla_laneq_f16 (float16x4_t __r, float16x4_t __a, float16x8_t __b)
+{
+  return vcmla_laneq_f16 (__r, __a, __b, 0);
+}
+
+float16x8_t
+test_vcmlaq_lane_f16 (float16x8_t __r, float16x8_t __a, float16x4_t __b)
+{
+  return vcmlaq_lane_f16 (__r, __a, __b, 0);
+}
+
+float16x8_t
+test_vcmlaq_laneq_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_laneq_f16 (__r, __a, __b, 0);
+}
+
+float16x4_t
+test_vcmla_lane_f16_2 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_lane_f16 (__r, __a, __b, 1);
+}
+
+float16x4_t
+test_vcmla_laneq_f16_2 (float16x4_t __r, float16x4_t __a, float16x8_t __b)
+{
+  return vcmla_laneq_f16 (__r, __a, __b, 3);
+}
+
+float16x8_t
+test_vcmlaq_lane_f16_2 (float16x8_t __r, float16x8_t __a, float16x4_t __b)
+{
+  return vcmlaq_lane_f16 (__r, __a, __b, 1);
+}
+
+float16x8_t
+test_vcmlaq_laneq_f16_2 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_laneq_f16 (__r, __a, __b, 3);
+}
+
+float16x4_t
+test_vcmla_rot90_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_rot90_f16 (__r, __a, __b);
+}
+
+float16x8_t
+test_vcmlaq_rot90_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_rot90_f16 (__r, __a, __b);
+}
+
+float16x4_t
+test_vcmla_rot90_lane_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_rot90_lane_f16 (__r, __a, __b, 0);
+}
+
+float16x4_t
+test_vcmla_rot90_laneq_f16 (float16x4_t __r, float16x4_t __a, float16x8_t __b)
+{
+  return vcmla_rot90_laneq_f16 (__r, __a, __b, 0);
+}
+
+float16x8_t
+test_vcmlaq_rot90_lane_f16 (float16x8_t __r, float16x8_t __a, float16x4_t __b)
+{
+  return vcmlaq_rot90_lane_f16 (__r, __a, __b, 0);
+}
+
+float16x8_t
+test_vcmlaq_rot90_laneq_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_rot90_laneq_f16 (__r, __a, __b, 0);
+}
+
+float16x4_t
+test_vcmla_rot90_lane_f16_2 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_rot90_lane_f16 (__r, __a, __b, 1);
+}
+
+float16x4_t
+test_vcmla_rot90_laneq_f16_2 (float16x4_t __r, float16x4_t __a, float16x8_t __b)
+{
+  return vcmla_rot90_laneq_f16 (__r, __a, __b, 3);
+}
+
+float16x8_t
+test_vcmlaq_rot90_lane_f16_2 (float16x8_t __r, float16x8_t __a, float16x4_t __b)
+{
+  return vcmlaq_rot90_lane_f16 (__r, __a, __b, 1);
+}
+
+float16x8_t
+test_vcmlaq_rot90_laneq_f16_2 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_rot90_laneq_f16 (__r, __a, __b, 3);
+}
+
+float16x4_t
+test_vcmla_rot180_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_rot180_f16 (__r, __a, __b);
+}
+
+float16x8_t
+test_vcmlaq_rot180_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_rot180_f16 (__r, __a, __b);
+}
+
+float16x4_t
+test_vcmla_rot180_lane_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_rot180_lane_f16 (__r, __a, __b, 0);
+}
+
+float16x4_t
+test_vcmla_rot180_laneq_f16 (float16x4_t __r, float16x4_t __a, float16x8_t __b)
+{
+  return vcmla_rot180_laneq_f16 (__r, __a, __b, 0);
+}
+
+float16x8_t
+test_vcmlaq_rot180_lane_f16 (float16x8_t __r, float16x8_t __a, float16x4_t __b)
+{
+  return vcmlaq_rot180_lane_f16 (__r, __a, __b, 0);
+}
+
+float16x8_t
+test_vcmlaq_rot180_laneq_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_rot180_laneq_f16 (__r, __a, __b, 0);
+}
+
+float16x4_t
+test_vcmla_rot180_lane_f16_2 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_rot180_lane_f16 (__r, __a, __b, 1);
+}
+
+float16x4_t
+test_vcmla_rot180_laneq_f16_2 (float16x4_t __r, float16x4_t __a, float16x8_t __b)
+{
+  return vcmla_rot180_laneq_f16 (__r, __a, __b, 3);
+}
+
+float16x8_t
+test_vcmlaq_rot180_lane_f16_2 (float16x8_t __r, float16x8_t __a, float16x4_t __b)
+{
+  return vcmlaq_rot180_lane_f16 (__r, __a, __b, 1);
+}
+
+float16x8_t
+test_vcmlaq_rot180_laneq_f16_2 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_rot180_laneq_f16 (__r, __a, __b, 3);
+}
+
+float16x4_t
+test_vcmla_rot270_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_rot270_f16 (__r, __a, __b);
+}
+
+float16x8_t
+test_vcmlaq_rot270_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_rot270_f16 (__r, __a, __b);
+}
+
+float16x4_t
+test_vcmla_rot270_lane_f16 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_rot270_lane_f16 (__r, __a, __b, 0);
+}
+
+float16x4_t
+test_vcmla_rot270_laneq_f16 (float16x4_t __r, float16x4_t __a, float16x8_t __b)
+{
+  return vcmla_rot270_laneq_f16 (__r, __a, __b, 0);
+}
+
+float16x8_t
+test_vcmlaq_rot270_lane_f16 (float16x8_t __r, float16x8_t __a, float16x4_t __b)
+{
+  return vcmlaq_rot270_lane_f16 (__r, __a, __b, 0);
+}
+
+float16x8_t
+test_vcmlaq_rot270_laneq_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_rot270_laneq_f16 (__r, __a, __b, 0);
+}
+
+float16x4_t
+test_vcmla_rot270_lane_f16_2 (float16x4_t __r, float16x4_t __a, float16x4_t __b)
+{
+  return vcmla_rot270_lane_f16 (__r, __a, __b, 1);
+}
+
+float16x4_t
+test_vcmla_rot270_laneq_f16_2 (float16x4_t __r, float16x4_t __a, float16x8_t __b)
+{
+  return vcmla_rot270_laneq_f16 (__r, __a, __b, 3);
+}
+
+float16x8_t
+test_vcmlaq_rot270_lane_f16_2 (float16x8_t __r, float16x8_t __a, float16x4_t __b)
+{
+  return vcmlaq_rot270_lane_f16 (__r, __a, __b, 1);
+}
+
+float16x8_t
+test_vcmlaq_rot270_laneq_f16_2 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+  return vcmlaq_rot270_laneq_f16 (__r, __a, __b, 3);
+}
+
+/* { dg-final { scan-assembler-times {dup\td[0-9]+, v[0-9]+.d\[1\]} 4 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.4h, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.4h, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.8h, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.8h, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.4h, #0} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.4h, #180} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.4h, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.4h, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.h\[0\], #0} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.h\[0\], #180} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.h\[0\], #270} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.h\[0\], #90} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.h\[1\], #0} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.h\[1\], #180} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.h\[1\], #270} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4h, v[0-9]+.4h, v[0-9]+.h\[1\], #90} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.8h, #0} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.8h, #180} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.8h, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.8h, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[0\], #0} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[0\], #180} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[0\], #270} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[0\], #90} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[1\], #0} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[1\], #180} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[1\], #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[1\], #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[3\], #0} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[3\], #180} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[3\], #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.8h, v[0-9]+.8h, v[0-9]+.h\[3\], #90} 1 { target { aarch64*-*-* } } } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index fde6cf45274..8c6db512c63 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -9356,3 +9356,111 @@ proc check_effective_target_cet { } {
 	}
     } "-O2" ]
 }
+
+# Return 1 if the target supports ARMv8.3 Adv.SIMD Complex instructions
+# instructions, 0 otherwise.  The test is valid for ARM and for AArch64.
+# Record the command line options needed.
+
+proc check_effective_target_arm_v8_3a_complex_neon_ok_nocache { } {
+    global et_arm_v8_3a_complex_neon_flags
+    set et_arm_v8_3a_complex_neon_flags ""
+
+    if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
+        return 0;
+    }
+
+    # Iterate through sets of options to find the compiler flags that
+    # need to be added to the -march option.
+    foreach flags {"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
+        if { [check_no_compiler_messages_nocache \
+                  arm_v8_3a_complex_neon_ok object {
+            #if !defined (__ARM_FEATURE_COMPLEX)
+            #error "__ARM_FEATURE_COMPLEX not defined"
+            #endif
+        } "$flags -march=armv8.3-a"] } {
+            set et_arm_v8_3a_complex_neon_flags "$flags -march=armv8.3-a"
+            return 1
+        }
+    }
+
+    return 0;
+}
+
+proc check_effective_target_arm_v8_3a_complex_neon_ok { } {
+    return [check_cached_effective_target arm_v8_3a_complex_neon_ok \
+                check_effective_target_arm_v8_3a_complex_neon_ok_nocache]
+}
+
+proc add_options_for_arm_v8_3a_complex_neon { flags } {
+    if { ! [check_effective_target_arm_v8_3a_complex_neon_ok] } {
+        return "$flags"
+    }
+    global et_arm_v8_3a_complex_neon_flags
+    return "$flags $et_arm_v8_3a_complex_neon_flags"
+}
+
+# Return 1 if the target supports executing AdvSIMD instructions from ARMv8.3
+# with the complex instruction extension, 0 otherwise.  The test is valid for
+# ARM and for AArch64.
+
+proc check_effective_target_arm_v8_3a_complex_neon_hw { } {
+    if { ![check_effective_target_arm_v8_3a_complex_neon_ok] } {
+        return 0;
+    }
+    return [check_runtime arm_v8_3a_complex_neon_hw_available {
+        #include "arm_neon.h"
+        int
+        main (void)
+        {
+
+          float32x2_t results = {-4.0,5.0};
+          float32x2_t a = {1.0,3.0};
+          float32x2_t b = {2.0,5.0};
+
+          #ifdef __ARM_ARCH_ISA_A64
+          asm ("fcadd %0.2s, %1.2s, %2.2s, #90"
+               : "=w"(results)
+               : "w"(a), "w"(b)
+               : /* No clobbers.  */);
+
+          #else
+          asm ("vcadd.f32 %P0, %P1, %P2, #90"
+               : "=w"(results)
+               : "w"(a), "w"(b)
+               : /* No clobbers.  */);
+          #endif
+
+          return (results[0] == 8 && results[1] == 24) ? 1 : 0;
+        }
+    } [add_options_for_arm_v8_3a_complex_neon ""]]
+}
+
+# Return 1 if the target plus current options supports a vector
+# complex addition with rotate of half and single float modes, 0 otherwise.
+#
+# This won't change for different subtargets so cache the result.
+
+foreach N {hf sf} {
+    eval [string map [list N $N] {
+        proc check_effective_target_vect_complex_rot_N { } {
+            return [check_cached_effective_target_indexed vect_complex_rot_N {
+            expr { [istarget aarch64*-*-*]
+                    || [istarget arm*-*-*] }}]
+        }
+    }]
+}
+
+# Return 1 if the target plus current options supports a vector
+# complex addition with rotate of double float modes, 0 otherwise.
+#
+# This won't change for different subtargets so cache the result.
+
+foreach N {df} {
+    eval [string map [list N $N] {
+        proc check_effective_target_vect_complex_rot_N { } {
+            return [check_cached_effective_target_indexed vect_complex_rot_N {
+            expr { [istarget aarch64*-*-*] }}]
+        }
+    }]
+}
+

commit bf4ce3fcedf5931f25086aaf9f778fd6c750b3af
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Sep 26 00:17:45 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e596b0d7780..40bc74fa6c5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,123 @@
+2020-09-25  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/71233
+	* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
+	Add qualifier_lane_pair_index.
+	(emit-rtl.h): Include.
+	(TYPES_QUADOP_LANE_PAIR): New.
+	(aarch64_simd_expand_args): Use it.
+	(aarch64_simd_expand_builtin): Likewise.
+	(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
+	(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
+	AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
+	aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
+	(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
+	(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
+	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
+	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
+	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
+	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
+	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
+	* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
+	fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
+	fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
+	fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
+	* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
+	aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
+	aarch64_fcmla<rot><mode>): New.
+	* config/aarch64/arm_neon.h:
+	(vcadd_rot90_f16): New.
+	(vcaddq_rot90_f16): New.
+	(vcadd_rot270_f16): New.
+	(vcaddq_rot270_f16): New.
+	(vcmla_f16): New.
+	(vcmlaq_f16): New.
+	(vcmla_lane_f16): New.
+	(vcmla_laneq_f16): New.
+	(vcmlaq_lane_f16): New.
+	(vcmlaq_rot90_lane_f16): New.
+	(vcmla_rot90_laneq_f16): New.
+	(vcmla_rot90_lane_f16): New.
+	(vcmlaq_rot90_f16): New.
+	(vcmla_rot90_f16): New.
+	(vcmlaq_laneq_f16): New.
+	(vcmla_rot180_laneq_f16): New.
+	(vcmla_rot180_lane_f16): New.
+	(vcmlaq_rot180_f16): New.
+	(vcmla_rot180_f16): New.
+	(vcmlaq_rot90_laneq_f16): New.
+	(vcmlaq_rot270_laneq_f16): New.
+	(vcmlaq_rot270_lane_f16): New.
+	(vcmla_rot270_laneq_f16): New.
+	(vcmlaq_rot270_f16): New.
+	(vcmla_rot270_f16): New.
+	(vcmlaq_rot180_laneq_f16): New.
+	(vcmlaq_rot180_lane_f16): New.
+	(vcmla_rot270_lane_f16): New.
+	(vcadd_rot90_f32): New.
+	(vcaddq_rot90_f32): New.
+	(vcaddq_rot90_f64): New.
+	(vcadd_rot270_f32): New.
+	(vcaddq_rot270_f32): New.
+	(vcaddq_rot270_f64): New.
+	(vcmla_f32): New.
+	(vcmlaq_f32): New.
+	(vcmlaq_f64): New.
+	(vcmla_lane_f32): New.
+	(vcmla_laneq_f32): New.
+	(vcmlaq_lane_f32): New.
+	(vcmlaq_laneq_f32): New.
+	(vcmla_rot90_f32): New.
+	(vcmlaq_rot90_f32): New.
+	(vcmlaq_rot90_f64): New.
+	(vcmla_rot90_lane_f32): New.
+	(vcmla_rot90_laneq_f32): New.
+	(vcmlaq_rot90_lane_f32): New.
+	(vcmlaq_rot90_laneq_f32): New.
+	(vcmla_rot180_f32): New.
+	(vcmlaq_rot180_f32): New.
+	(vcmlaq_rot180_f64): New.
+	(vcmla_rot180_lane_f32): New.
+	(vcmla_rot180_laneq_f32): New.
+	(vcmlaq_rot180_lane_f32): New.
+	(vcmlaq_rot180_laneq_f32): New.
+	(vcmla_rot270_f32): New.
+	(vcmlaq_rot270_f32): New.
+	(vcmlaq_rot270_f64): New.
+	(vcmla_rot270_lane_f32): New.
+	(vcmla_rot270_laneq_f32): New.
+	(vcmlaq_rot270_lane_f32): New.
+	(vcmlaq_rot270_laneq_f32): New.
+	* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
+	* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
+	UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
+	(FCADD, FCMLA): New.
+	(rot): New.
+	(FCMLA_maybe_lane): New.
+	* config/arm/types.md (neon_fcadd, neon_fcmla): New.
+
+2020-09-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* config/aarch64/aarch64.md (UNSPEC_RNDR, UNSPEC_RNDRRS):
+	Define.
+	(aarch64_rndr): New define_insn.
+	(aarch64_rndrrs): Likewise.
+	* config/aarch64/aarch64.h (AARCH64_ISA_RNG): Define.
+	(TARGET_RNG): Likewise.
+	(AARCH64_FL_RNG): Likewise.
+	* config/aarch64/aarch64-option-extensions.def (rng): Define.
+	* config/aarch64/aarch64-builtins.c (enum aarch64_builtins):
+	Add AARCH64_BUILTIN_RNG_RNDR, AARCH64_BUILTIN_RNG_RNDRRS.
+	(aarch64_init_rng_builtins): Define.
+	(aarch64_init_builtins): Call aarch64_init_rng_builtins.
+	(aarch64_expand_rng_builtin): Define.
+	(aarch64_expand_builtin): Use IGNORE argument, handle
+	RNG builtins.
+	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins):
+	Define __ARM_FEATURE_RNG when TARGET_RNG.
+	* config/aarch64/arm_acle.h (__rndr, __rndrrs): Define.
+
 2020-09-24  H.J. Lu  <hjl.tools@gmail.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index cfe4a2ef954..bfdd19d304c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200925
+20200926
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b2e821ad7b0..32eb0521334 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,20 @@
+2020-09-25  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/71233
+	* lib/target-supports.exp
+	(check_effective_target_arm_v8_3a_complex_neon_ok_nocache,
+	check_effective_target_arm_v8_3a_complex_neon_ok,
+	add_options_for_arm_v8_3a_complex_neon,
+	check_effective_target_arm_v8_3a_complex_neon_hw,
+	check_effective_target_vect_complex_rot_N): New.
+	* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
+	* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
+
+2020-09-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/acle/rng_1.c: New test.
+
 2020-09-24  H.J. Lu  <hjl.tools@gmail.com>
 
 	Backported from master:

commit 346276f67fb7709b0e9cf6d0f870d19524309ee8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Sep 27 00:17:36 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index bfdd19d304c..51daa72546b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200926
+20200927

commit e28cc38ac34cb4de31b983f817c6e5f7dde55e2c
Author: Mark Eggleston <markeggleston@gcc.gnu.org>
Date:   Thu Jun 11 14:33:51 2020 +0100

    Fortran  :  ICE in build_field PR95614
    
    Local identifiers can not be the same as a module name.  Original
    patch by Steve Kargl resulted in name clashes between common block
    names and local identifiers.  A local identifier can be the same as
    a global identier if that identifier represents a common.  The patch
    was modified to allow global identifiers that represent a common
    block.
    
    2020-09-27  Steven G. Kargl  <kargl@gcc.gnu.org>
                Mark Eggleston  <markeggleston@gcc.gnu.org>
    
    gcc/fortran/
    
            PR fortran/95614
            * decl.c (gfc_get_common): Use gfc_match_common_name instead
            of match_common_name.
            * decl.c (gfc_bind_idents): Use gfc_match_common_name instead
            of match_common_name.
            * match.c : Rename match_common_name to gfc_match_common_name.
            * match.c (gfc_match_common): Use gfc_match_common_name instead
            of match_common_name.
            * match.h : Rename match_common_name to gfc_match_common_name.
            * resolve.c (resolve_common_vars): Check each symbol in a
            common block has a global symbol.  If there is a global symbol
            issue an error if the symbol type is known as is not a common
            block name.
    
    2020-09-27  Mark Eggleston  <markeggleston@gcc.gnu.org>
    
    gcc/testsuite/
    
            PR fortran/95614
            * gfortran.dg/pr95614_1.f90: New test.
            * gfortran.dg/pr95614_2.f90: New test.
    
    (cherry picked from commit e5a76af3a2f3324efc60b4b2778ffb29d5c377bc)

diff --git a/gcc/fortran/decl.c b/gcc/fortran/decl.c
index 6249562de29..b3d1ca020b4 100644
--- a/gcc/fortran/decl.c
+++ b/gcc/fortran/decl.c
@@ -5789,7 +5789,7 @@ get_bind_c_idents (void)
       found_id = MATCH_YES;
       gfc_get_ha_symbol (name, &tmp_sym);
     }
-  else if (match_common_name (name) == MATCH_YES)
+  else if (gfc_match_common_name (name) == MATCH_YES)
     {
       found_id = MATCH_YES;
       com_block = gfc_get_common (name, 0);
@@ -5834,7 +5834,7 @@ get_bind_c_idents (void)
 	      found_id = MATCH_YES;
 	      gfc_get_ha_symbol (name, &tmp_sym);
 	    }
-	  else if (match_common_name (name) == MATCH_YES)
+	  else if (gfc_match_common_name (name) == MATCH_YES)
 	    {
 	      found_id = MATCH_YES;
 	      com_block = gfc_get_common (name, 0);
diff --git a/gcc/fortran/match.c b/gcc/fortran/match.c
index 9b61f1f52ec..6ed83532997 100644
--- a/gcc/fortran/match.c
+++ b/gcc/fortran/match.c
@@ -5028,7 +5028,8 @@ gfc_get_common (const char *name, int from_module)
 
 /* Match a common block name.  */
 
-match match_common_name (char *name)
+match
+gfc_match_common_name (char *name)
 {
   match m;
 
@@ -5072,7 +5073,7 @@ gfc_match_common (void)
 
   for (;;)
     {
-      m = match_common_name (name);
+      m = gfc_match_common_name (name);
       if (m == MATCH_ERROR)
 	goto cleanup;
 
diff --git a/gcc/fortran/match.h b/gcc/fortran/match.h
index 418542bd5a6..5d244c237ac 100644
--- a/gcc/fortran/match.h
+++ b/gcc/fortran/match.h
@@ -103,11 +103,9 @@ match gfc_match_call (void);
 
 /* We want to use this function to check for a common-block-name
    that can exist in a bind statement, so removed the "static"
-   declaration of the function in match.c.
+   declaration of the function in match.c. */
  
-   TODO: should probably rename this now that it'll be globally seen to
-   gfc_match_common_name.  */
-match match_common_name (char *name);
+match gfc_match_common_name (char *name);
 
 match gfc_match_common (void);
 match gfc_match_block_data (void);
diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
index be63ce50bf2..7f302522cd6 100644
--- a/gcc/fortran/resolve.c
+++ b/gcc/fortran/resolve.c
@@ -932,9 +932,16 @@ static void
 resolve_common_vars (gfc_common_head *common_block, bool named_common)
 {
   gfc_symbol *csym = common_block->head;
+  gfc_gsymbol *gsym;
 
   for (; csym; csym = csym->common_next)
     {
+      gsym = gfc_find_gsymbol (gfc_gsym_root, csym->name);
+      if (gsym && gsym->type != GSYM_UNKNOWN && gsym->type != GSYM_COMMON)
+	gfc_error_now ("Global entity %qs at %L cannot appear in a "
+			"COMMON block at %L", gsym->name,
+			&gsym->where, &csym->common_block->where);
+
       /* gfc_add_in_common may have been called before, but the reported errors
 	 have been ignored to continue parsing.
 	 We do the checks again here.  */
diff --git a/gcc/testsuite/gfortran.dg/pr95614_1.f90 b/gcc/testsuite/gfortran.dg/pr95614_1.f90
new file mode 100644
index 00000000000..f835143365a
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr95614_1.f90
@@ -0,0 +1,6 @@
+! { dg-do compile }
+
+module m   ! { dg-error ".1." }
+  common m ! { dg-error "cannot appear in a COMMON" }
+end
+
diff --git a/gcc/testsuite/gfortran.dg/pr95614_2.f90 b/gcc/testsuite/gfortran.dg/pr95614_2.f90
new file mode 100644
index 00000000000..9d69a506384
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr95614_2.f90
@@ -0,0 +1,6 @@
+! { dg-do compile }
+
+module m        ! { dg-error ".1." }
+  common /xc/ m ! { dg-error "cannot appear in a COMMON" }
+end
+

commit 0ed1ce77f876cb05cd3e403c6c28e86fe0692f93
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sun Sep 27 23:18:26 2020 +0200

    optabs: Don't reuse target for multi-word expansions if it overlaps operand(s) [PR97073]
    
    The following testcase is miscompiled on i686-linux, because
    we try to expand a double-word bitwise logic operation with op0
    being a (mem:DI u) and target (mem:DI u+4), i.e. partial overlap, and
    thus end up with:
            movl    4(%esp), %eax
            andl    u, %eax
            movl    %eax, u+4
    ! movl u+4, %eax optimized out
            andl    8(%esp), %eax
            movl    %eax, u+8
    rather than with the desired:
            movl    4(%esp), %edx
            movl    8(%esp), %eax
            andl    u, %edx
            andl    u+4, %eax
            movl    %eax, u+8
            movl    %edx, u+4
    because the store of the first word to target overwrites the second word of
    the operand.
    expand_binop for this (and several similar places) already check for target
    == op0 or target == op1, this patch just adds reg_overlap_mentioned_p calls
    next to it.
    Pedantically, at least for some of these it might be sufficient to force
    a different target if there is overlap but target is not rtx_equal_p to
    the operand (e.g. in this bitwise logical case, but e.g. not in the shift
    cases where there is reordering), though that would go against the
    preexisting target == op? checks and the rationale that REG_EQUAL notes in
    that case isn't correct.
    
    2020-09-27  Jakub Jelinek  <jakub@redhat.com>
    
            PR middle-end/97073
            * optabs.c (expand_binop, expand_absneg_bit, expand_unop,
            expand_copysign_bit): Check reg_overlap_mentioned_p between target
            and operand(s) and if it returns true, force a pseudo as target.
    
            * gcc.c-torture/execute/pr97073.c: New test.
    
    (cherry picked from commit a4b31d5807f2bc67c8999b3d53369cf2a5c6e1ec)

diff --git a/gcc/optabs.c b/gcc/optabs.c
index 51d838d4f93..9e93097fa55 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -1363,6 +1363,8 @@ expand_binop (machine_mode mode, optab binoptab, rtx op0, rtx op1,
       if (target == 0
 	  || target == op0
 	  || target == op1
+	  || reg_overlap_mentioned_p (target, op0)
+	  || reg_overlap_mentioned_p (target, op1)
 	  || !valid_multiword_target_p (target))
 	target = gen_reg_rtx (int_mode);
 
@@ -1437,6 +1439,8 @@ expand_binop (machine_mode mode, optab binoptab, rtx op0, rtx op1,
 	  if (target == 0
 	      || target == op0
 	      || target == op1
+	      || reg_overlap_mentioned_p (target, op0)
+	      || reg_overlap_mentioned_p (target, op1)
 	      || !valid_multiword_target_p (target))
 	    target = gen_reg_rtx (int_mode);
 
@@ -1495,6 +1499,8 @@ expand_binop (machine_mode mode, optab binoptab, rtx op0, rtx op1,
 	  || target == op0
 	  || target == op1
 	  || !REG_P (target)
+	  || reg_overlap_mentioned_p (target, op0)
+	  || reg_overlap_mentioned_p (target, op1)
 	  || !valid_multiword_target_p (target))
 	target = gen_reg_rtx (int_mode);
 
@@ -2632,6 +2638,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
 
   if (target == 0
       || target == op0
+      || reg_overlap_mentioned_p (target, op0)
       || (nwords > 1 && !valid_multiword_target_p (target)))
     target = gen_reg_rtx (mode);
 
@@ -2910,7 +2917,10 @@ expand_unop (machine_mode mode, optab unoptab, rtx op0, rtx target,
       int i;
       rtx_insn *insns;
 
-      if (target == 0 || target == op0 || !valid_multiword_target_p (target))
+      if (target == 0
+	  || target == op0
+	  || reg_overlap_mentioned_p (target, op0)
+	  || !valid_multiword_target_p (target))
 	target = gen_reg_rtx (int_mode);
 
       start_sequence ();
@@ -3420,6 +3430,8 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
   if (target == 0
       || target == op0
       || target == op1
+      || reg_overlap_mentioned_p (target, op0)
+      || reg_overlap_mentioned_p (target, op1)
       || (nwords > 1 && !valid_multiword_target_p (target)))
     target = gen_reg_rtx (mode);
 
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr97073.c b/gcc/testsuite/gcc.c-torture/execute/pr97073.c
new file mode 100644
index 00000000000..1955e6b8bd2
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr97073.c
@@ -0,0 +1,21 @@
+/* PR middle-end/97073 */
+/* { dg-additional-options "-mno-stv" { target i?86-*-* x86_64-*-* } } */
+
+typedef unsigned long long L;
+union U { L i; struct T { unsigned k; L l; } j; } u;
+
+__attribute__((noinline,noclone)) void
+foo (L x)
+{
+  u.j.l = u.i & x;
+}
+
+int
+main ()
+{
+  u.i = 5;
+  foo (-1ULL);
+  if (u.j.l != 5)
+    __builtin_abort ();
+  return 0;
+}

commit b0897beee417e690a31ccedd7985ebd72f65f1f0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Sep 28 00:17:33 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 40bc74fa6c5..5b46236c34d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2020-09-27  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-09-27  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/97073
+	* optabs.c (expand_binop, expand_absneg_bit, expand_unop,
+	expand_copysign_bit): Check reg_overlap_mentioned_p between target
+	and operand(s) and if it returns true, force a pseudo as target.
+
 2020-09-25  Tamar Christina  <tamar.christina@arm.com>
 
 	PR target/71233
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 51daa72546b..0c0687f326c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200927
+20200928
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 27d7dce2710..7368bdc73fd 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,23 @@
+2020-09-27  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	Backported from master:
+	2020-09-27  Steven G. Kargl  <kargl@gcc.gnu.org>
+		    Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	PR fortran/95614
+	* decl.c (gfc_get_common): Use gfc_match_common_name instead
+	of match_common_name.
+	* decl.c (gfc_bind_idents): Use gfc_match_common_name instead
+	of match_common_name.
+	* match.c : Rename match_common_name to gfc_match_common_name.
+	* match.c (gfc_match_common): Use gfc_match_common_name instead
+	of match_common_name.
+	* match.h : Rename match_common_name to gfc_match_common_name.
+	* resolve.c (resolve_common_vars): Check each symbol in a
+	common block has a global symbol.  If there is a global symbol
+	issue an error if the symbol type is known as is not a common
+	block name.
+
 2020-09-19  Tobias Burnus  <tobias@codesourcery.com>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 32eb0521334..fdf60877d36 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2020-09-27  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-09-27  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/97073
+	* gcc.c-torture/execute/pr97073.c: New test.
+
+2020-09-27  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	Backported from master:
+	2020-09-27  Steven G. Kargl  <kargl@gcc.gnu.org>
+		    Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	PR fortran/95614
+	* gfortran.dg/pr95614_1.f90: New test.
+	* gfortran.dg/pr95614_2.f90: New test.
+
 2020-09-25  Tamar Christina  <tamar.christina@arm.com>
 
 	PR target/71233

commit b65099a08e257cc9c93060c6299311faaa4b44e9
Author: Mark Eggleston <markeggleston@gcc.gnu.org>
Date:   Mon Sep 28 11:04:48 2020 +0100

    Revert "Fortran  :  ICE in build_field PR95614"
    
    This reverts commit e28cc38ac34cb4de31b983f817c6e5f7dde55e2c.

diff --git a/gcc/fortran/decl.c b/gcc/fortran/decl.c
index b3d1ca020b4..6249562de29 100644
--- a/gcc/fortran/decl.c
+++ b/gcc/fortran/decl.c
@@ -5789,7 +5789,7 @@ get_bind_c_idents (void)
       found_id = MATCH_YES;
       gfc_get_ha_symbol (name, &tmp_sym);
     }
-  else if (gfc_match_common_name (name) == MATCH_YES)
+  else if (match_common_name (name) == MATCH_YES)
     {
       found_id = MATCH_YES;
       com_block = gfc_get_common (name, 0);
@@ -5834,7 +5834,7 @@ get_bind_c_idents (void)
 	      found_id = MATCH_YES;
 	      gfc_get_ha_symbol (name, &tmp_sym);
 	    }
-	  else if (gfc_match_common_name (name) == MATCH_YES)
+	  else if (match_common_name (name) == MATCH_YES)
 	    {
 	      found_id = MATCH_YES;
 	      com_block = gfc_get_common (name, 0);
diff --git a/gcc/fortran/match.c b/gcc/fortran/match.c
index 6ed83532997..9b61f1f52ec 100644
--- a/gcc/fortran/match.c
+++ b/gcc/fortran/match.c
@@ -5028,8 +5028,7 @@ gfc_get_common (const char *name, int from_module)
 
 /* Match a common block name.  */
 
-match
-gfc_match_common_name (char *name)
+match match_common_name (char *name)
 {
   match m;
 
@@ -5073,7 +5072,7 @@ gfc_match_common (void)
 
   for (;;)
     {
-      m = gfc_match_common_name (name);
+      m = match_common_name (name);
       if (m == MATCH_ERROR)
 	goto cleanup;
 
diff --git a/gcc/fortran/match.h b/gcc/fortran/match.h
index 5d244c237ac..418542bd5a6 100644
--- a/gcc/fortran/match.h
+++ b/gcc/fortran/match.h
@@ -103,9 +103,11 @@ match gfc_match_call (void);
 
 /* We want to use this function to check for a common-block-name
    that can exist in a bind statement, so removed the "static"
-   declaration of the function in match.c. */
+   declaration of the function in match.c.
  
-match gfc_match_common_name (char *name);
+   TODO: should probably rename this now that it'll be globally seen to
+   gfc_match_common_name.  */
+match match_common_name (char *name);
 
 match gfc_match_common (void);
 match gfc_match_block_data (void);
diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
index 7f302522cd6..be63ce50bf2 100644
--- a/gcc/fortran/resolve.c
+++ b/gcc/fortran/resolve.c
@@ -932,16 +932,9 @@ static void
 resolve_common_vars (gfc_common_head *common_block, bool named_common)
 {
   gfc_symbol *csym = common_block->head;
-  gfc_gsymbol *gsym;
 
   for (; csym; csym = csym->common_next)
     {
-      gsym = gfc_find_gsymbol (gfc_gsym_root, csym->name);
-      if (gsym && gsym->type != GSYM_UNKNOWN && gsym->type != GSYM_COMMON)
-	gfc_error_now ("Global entity %qs at %L cannot appear in a "
-			"COMMON block at %L", gsym->name,
-			&gsym->where, &csym->common_block->where);
-
       /* gfc_add_in_common may have been called before, but the reported errors
 	 have been ignored to continue parsing.
 	 We do the checks again here.  */
diff --git a/gcc/testsuite/gfortran.dg/pr95614_1.f90 b/gcc/testsuite/gfortran.dg/pr95614_1.f90
deleted file mode 100644
index f835143365a..00000000000
--- a/gcc/testsuite/gfortran.dg/pr95614_1.f90
+++ /dev/null
@@ -1,6 +0,0 @@
-! { dg-do compile }
-
-module m   ! { dg-error ".1." }
-  common m ! { dg-error "cannot appear in a COMMON" }
-end
-
diff --git a/gcc/testsuite/gfortran.dg/pr95614_2.f90 b/gcc/testsuite/gfortran.dg/pr95614_2.f90
deleted file mode 100644
index 9d69a506384..00000000000
--- a/gcc/testsuite/gfortran.dg/pr95614_2.f90
+++ /dev/null
@@ -1,6 +0,0 @@
-! { dg-do compile }
-
-module m        ! { dg-error ".1." }
-  common /xc/ m ! { dg-error "cannot appear in a COMMON" }
-end
-

commit 3c21a2f28014cd3bbfaee975a466dc3488052060
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 11:58:36 2020 +0100

    AArch64: Implement poly-type vadd intrinsics
    
    This implements the vadd[p]_p* intrinsics.
    In terms of functionality they are aliases of veor operations on the relevant unsigned types.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vadd_p8, vadd_p16, vadd_p64, vaddq_p8,
            vaddq_p16, vaddq_p64, vaddq_p128): Define.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vadd_poly_1.c: New test.
    
    (cherry picked from commit fa9ad35dae03dcb20c4ccb50ba1b351a8ab77970)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index e73a1e1c838..4eefb9b6106 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -34469,6 +34469,55 @@ vfmlslq_laneq_high_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b,
 
 #pragma GCC pop_options
 
+__extension__ extern __inline poly8x8_t
+__attribute ((__always_inline__, __gnu_inline__, __artificial__))
+vadd_p8 (poly8x8_t __a, poly8x8_t __b)
+{
+  return __a ^ __b;
+}
+
+__extension__ extern __inline poly16x4_t
+__attribute ((__always_inline__, __gnu_inline__, __artificial__))
+vadd_p16 (poly16x4_t __a, poly16x4_t __b)
+{
+  return __a ^ __b;
+}
+
+__extension__ extern __inline poly64x1_t
+__attribute ((__always_inline__, __gnu_inline__, __artificial__))
+vadd_p64 (poly64x1_t __a, poly64x1_t __b)
+{
+  return __a ^ __b;
+}
+
+__extension__ extern __inline poly8x16_t
+__attribute ((__always_inline__, __gnu_inline__, __artificial__))
+vaddq_p8 (poly8x16_t __a, poly8x16_t __b)
+{
+  return __a ^ __b;
+}
+
+__extension__ extern __inline poly16x8_t
+__attribute ((__always_inline__, __gnu_inline__, __artificial__))
+vaddq_p16 (poly16x8_t __a, poly16x8_t __b)
+{
+  return __a ^__b;
+}
+
+__extension__ extern __inline poly64x2_t
+__attribute ((__always_inline__, __gnu_inline__, __artificial__))
+vaddq_p64 (poly64x2_t __a, poly64x2_t __b)
+{
+  return __a ^ __b;
+}
+
+__extension__ extern __inline poly128_t
+__attribute ((__always_inline__, __gnu_inline__, __artificial__))
+vaddq_p128 (poly128_t __a, poly128_t __b)
+{
+  return __a ^ __b;
+}
+
 #undef __aarch64_vget_lane_any
 
 #undef __aarch64_vdup_lane_any
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vadd_poly_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vadd_poly_1.c
new file mode 100644
index 00000000000..a5cdf290b0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vadd_poly_1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#include <arm_neon.h>
+
+poly8x8_t
+foo (poly8x8_t a, poly8x8_t b)
+{
+  return vadd_p8 (a, b);
+}
+
+poly16x4_t
+foo16 (poly16x4_t a, poly16x4_t b)
+{
+  return vadd_p16 (a, b);
+}
+
+poly64x1_t
+foo64 (poly64x1_t a, poly64x1_t b)
+{
+  return vadd_p64 (a, b);
+}
+
+poly8x16_t
+fooq (poly8x16_t a, poly8x16_t b)
+{
+  return vaddq_p8 (a, b);
+}
+
+poly16x8_t
+fooq16 (poly16x8_t a, poly16x8_t b)
+{
+  return vaddq_p16 (a, b);
+}
+
+poly64x2_t
+fooq64 (poly64x2_t a, poly64x2_t b)
+{
+  return vaddq_p64 (a, b);
+}
+
+poly128_t
+fooq128 (poly128_t a, poly128_t b)
+{
+  return vaddq_p128 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "eor\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */
+/* { dg-final { scan-assembler-times "eor\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+/* { dg-final { scan-assembler-times "eor\\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */

commit e9ed4afbb6778dedfb1efa0ba92429a51d4d049b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:00:38 2020 +0100

    AArch64: Implement missing vceq*_p* intrinsics
    
    This patch implements some missing vceq* intrinsics on poly types.
    The behaviour is to produce the appropriate CMEQ instruction as for the unsigned types.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vceqq_p64, vceqz_p64, vceqzq_p64): Define.
    
    gcc/testsuite/
    
            PR target/71233
            * gcc.target/aarch64/simd/vceq_poly_1.c: New test.
    
    (cherry picked from commit d4703be185b422f637deebd3bb9222a41c8023d6)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 4eefb9b6106..3b5d195fd06 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -12801,6 +12801,13 @@ vceqq_u64 (uint64x2_t __a, uint64x2_t __b)
   return (__a == __b);
 }
 
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vceqq_p64 (poly64x2_t __a, poly64x2_t __b)
+{
+  return (__a == __b);
+}
+
 /* vceq - scalar.  */
 
 __extension__ extern __inline uint32_t
@@ -12910,6 +12917,13 @@ vceqz_u64 (uint64x1_t __a)
   return (__a == __AARCH64_UINT64_C (0));
 }
 
+__extension__ extern __inline uint64x1_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vceqz_p64 (poly64x1_t __a)
+{
+  return (__a == __AARCH64_UINT64_C (0));
+}
+
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vceqzq_f32 (float32x4_t __a)
@@ -12987,6 +13001,13 @@ vceqzq_u64 (uint64x2_t __a)
   return (__a == __AARCH64_UINT64_C (0));
 }
 
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vceqzq_p64 (poly64x2_t __a)
+{
+  return (__a == __AARCH64_UINT64_C (0));
+}
+
 /* vceqz - scalar.  */
 
 __extension__ extern __inline uint32_t
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vceq_poly_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vceq_poly_1.c
new file mode 100644
index 00000000000..7d43352266c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vceq_poly_1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#include <arm_neon.h>
+
+uint64x2_t
+foo (poly64x2_t a, poly64x2_t b)
+{
+  return vceqq_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "cmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+
+uint64x1_t
+fooz (poly64x1_t a)
+{
+  return vceqz_p64 (a);
+}
+
+/* { dg-final { scan-assembler-times "cmeq\\td\[0-9\]+, d\[0-9\]+, #0" 1 } } */
+
+uint64x2_t
+fooqz (poly64x2_t a)
+{
+  return vceqzq_p64 (a);
+}
+
+/* { dg-final { scan-assembler-times "cmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, #0" 1 } } */
+

commit fd250940d0e3dd17302eb5e2653255c9189bfd70
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:03:49 2020 +0100

    AArch64: Implement missing vcls intrinsics on unsigned types
    
    This patch implements some missing intrinsics that perform a CLS on unsigned SIMD types.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vcls_u8, vcls_u16, vcls_u32,
            vclsq_u8, vclsq_u16, vclsq_u32): Define.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vcls_unsigned_1.c: New test.
    
    (cherry picked from commit 30957092db46d8798e632feefb5df634488dbb33)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 3b5d195fd06..a30682cab0d 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -14206,6 +14206,48 @@ vclsq_s32 (int32x4_t __a)
   return __builtin_aarch64_clrsbv4si (__a);
 }
 
+__extension__ extern __inline int8x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcls_u8 (uint8x8_t __a)
+{
+  return __builtin_aarch64_clrsbv8qi ((int8x8_t) __a);
+}
+
+__extension__ extern __inline int16x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcls_u16 (uint16x4_t __a)
+{
+  return __builtin_aarch64_clrsbv4hi ((int16x4_t) __a);
+}
+
+__extension__ extern __inline int32x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vcls_u32 (uint32x2_t __a)
+{
+  return __builtin_aarch64_clrsbv2si ((int32x2_t) __a);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vclsq_u8 (uint8x16_t __a)
+{
+  return __builtin_aarch64_clrsbv16qi ((int8x16_t) __a);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vclsq_u16 (uint16x8_t __a)
+{
+  return __builtin_aarch64_clrsbv8hi ((int16x8_t) __a);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vclsq_u32 (uint32x4_t __a)
+{
+  return __builtin_aarch64_clrsbv4si ((int32x4_t) __a);
+}
+
 /* vclz.  */
 
 __extension__ extern __inline int8x8_t
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcls_unsigned_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcls_unsigned_1.c
new file mode 100644
index 00000000000..f7078d1a67c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcls_unsigned_1.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#include <arm_neon.h>
+
+int16x8_t
+test_16x8 (uint16x8_t a)
+{
+  return vclsq_u16 (a);
+}
+
+/* { dg-final { scan-assembler-times "cls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+
+
+int8x16_t
+test_8x16 (uint8x16_t a)
+{
+  return vclsq_u8 (a);
+}
+
+/* { dg-final { scan-assembler-times "cls\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+int32x4_t
+test_32x4 (uint32x4_t a)
+{
+  return vclsq_u32 (a);
+}
+
+/* { dg-final { scan-assembler-times "cls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+int16x4_t
+test_16x4 (uint16x4_t a)
+{
+  return vcls_u16 (a);
+}
+
+/* { dg-final { scan-assembler-times "cls\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */
+
+int8x8_t
+test_8x8 (uint8x8_t a)
+{
+  return vcls_u8 (a);
+}
+
+/* { dg-final { scan-assembler-times "cls\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
+
+int32x2_t
+test32x2 (uint32x2_t a)
+{
+  return vcls_u32 (a);
+}
+
+/* { dg-final { scan-assembler-times "cls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+

commit c0817ceebffa0be66b39c874a5da408404330b42
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 10:29:17 2020 +0100

    AArch64: Implement vstrq_p128 intrinsic
    
    This patch implements the missing vstrq_p128 intrinsic.
    It just performs a store of the poly128_t argument to a memory location.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vstrq_p128): Define.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vstrq_p128_1.c: New test.
    
    (cherry picked from commit d23ea1e865301cd45f14ccbdb0bca49251fde9e1)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index a30682cab0d..bbae8c31f5e 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -30279,6 +30279,13 @@ vst4q_p64 (poly64_t * __a, poly64x2x4_t val)
   __builtin_aarch64_st4v2di ((__builtin_aarch64_simd_di *) __a, __o);
 }
 
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vstrq_p128 (poly128_t * __ptr, poly128_t __val)
+{
+  *__ptr = __val;
+}
+
 /* vsub */
 
 __extension__ extern __inline int64_t
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vstrq_p128_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vstrq_p128_1.c
new file mode 100644
index 00000000000..8d036fde0f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vstrq_p128_1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#include <arm_neon.h>
+
+void
+test (poly128_t *ptr, poly128_t a)
+{
+  vstrq_p128 (ptr, a);
+}
+
+/* { dg-final { scan-assembler-times {stp.*x2,.*x3,.*[x0]} 1 } } */

commit a45e419416c641b7be5d4f4eb877fa390349c004
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 10:32:42 2020 +0100

    AArch64: Implement vldrq_p128 intrinsic
    
    This patch implements the missing vldrq_p128 intrinsic that just loads from the appropriate pointer.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vldrq_p128): Define.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vldrq_p128_1.c: New test.
    
    (cherry picked from commit f2868e4bcff2c7b882d01231f039459c00e59d7b)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index bbae8c31f5e..d7dc4568d41 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -19807,6 +19807,13 @@ vld4q_p64 (const poly64_t * __a)
   return ret;
 }
 
+__extension__ extern __inline poly128_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vldrq_p128 (const poly128_t * __ptr)
+{
+  return *__ptr;
+}
+
 /* vldn_dup */
 
 __extension__ extern __inline int8x8x2_t
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vldrq_p128_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vldrq_p128_1.c
new file mode 100644
index 00000000000..9c7e01b9e10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vldrq_p128_1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#include <arm_neon.h>
+
+poly128_t
+test (poly128_t * p)
+{
+  return vldrq_p128 (p);
+}
+
+/* { dg-final { scan-assembler-times {ldp.*x0,.*x1,.*[x0]} 1 } } */
+

commit 99a8808add97c61b64a4cb979e4616731b86e58b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 11:07:50 2020 +0100

    AArch64: Implement missing _p64 intrinsics for vector permutes
    
    This patch implements some missing vector permute intrinsics operating on poly64x2_t types.
    They are implemented identically to their uint64x2_t brethren.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vtrn1q_p64, vtrn2q_p64, vuzp1q_p64,
            vuzp2q_p64, vzip1q_p64, vzip2q_p64): Define.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/trn_zip_p64_1.c: New test.
    
    (cherry picked from commit e8e818399d70c5a5a3d30a54d305c6e2b92e2c66)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index d7dc4568d41..a0080b73cf1 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -30680,6 +30680,17 @@ vtrn1q_u32 (uint32x4_t __a, uint32x4_t __b)
 #endif
 }
 
+__extension__ extern __inline poly64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vtrn1q_p64 (poly64x2_t __a, poly64x2_t __b)
+{
+#ifdef __AARCH64EB__
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {3, 1});
+#else
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {0, 2});
+#endif
+}
+
 __extension__ extern __inline uint64x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vtrn1q_u64 (uint64x2_t __a, uint64x2_t __b)
@@ -30950,6 +30961,18 @@ vtrn2q_u64 (uint64x2_t __a, uint64x2_t __b)
 #endif
 }
 
+
+__extension__ extern __inline poly64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vtrn2q_p64 (poly64x2_t __a, poly64x2_t __b)
+{
+#ifdef __AARCH64EB__
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {2, 0});
+#else
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {1, 3});
+#endif
+}
+
 __extension__ extern __inline float16x4x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vtrn_f16 (float16x4_t __a, float16x4_t __b)
@@ -31596,6 +31619,17 @@ vuzp1q_u64 (uint64x2_t __a, uint64x2_t __b)
 #endif
 }
 
+__extension__ extern __inline poly64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vuzp1q_p64 (poly64x2_t __a, poly64x2_t __b)
+{
+#ifdef __AARCH64EB__
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {3, 1});
+#else
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {0, 2});
+#endif
+}
+
 __extension__ extern __inline float16x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vuzp2_f16 (float16x4_t __a, float16x4_t __b)
@@ -31855,6 +31889,17 @@ vuzp2q_u64 (uint64x2_t __a, uint64x2_t __b)
 #endif
 }
 
+__extension__ extern __inline poly64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vuzp2q_p64 (poly64x2_t __a, poly64x2_t __b)
+{
+#ifdef __AARCH64EB__
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {2, 0});
+#else
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {1, 3});
+#endif
+}
+
 __INTERLEAVE_LIST (uzp)
 
 /* vzip */
@@ -32123,6 +32168,17 @@ vzip1q_u64 (uint64x2_t __a, uint64x2_t __b)
 #endif
 }
 
+__extension__ extern __inline poly64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vzip1q_p64 (poly64x2_t __a, poly64x2_t __b)
+{
+#ifdef __AARCH64EB__
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {3, 1});
+#else
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {0, 2});
+#endif
+}
+
 __extension__ extern __inline float16x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vzip2_f16 (float16x4_t __a, float16x4_t __b)
@@ -32387,6 +32443,17 @@ vzip2q_u64 (uint64x2_t __a, uint64x2_t __b)
 #endif
 }
 
+__extension__ extern __inline poly64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vzip2q_p64 (poly64x2_t __a, poly64x2_t __b)
+{
+#ifdef __AARCH64EB__
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {2, 0});
+#else
+  return __builtin_shuffle (__a, __b, (poly64x2_t) {1, 3});
+#endif
+}
+
 __INTERLEAVE_LIST (zip)
 
 #undef __INTERLEAVE_LIST
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/trn_zip_p64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/trn_zip_p64_1.c
new file mode 100644
index 00000000000..a47321db80b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/trn_zip_p64_1.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#include <arm_neon.h>
+
+poly64x2_t
+foo (poly64x2_t a, poly64x2_t b)
+{
+  return vtrn1q_p64 (a, b);
+}
+
+poly64x2_t
+foo1 (poly64x2_t a, poly64x2_t b)
+{
+  return vtrn2q_p64 (a, b);
+}
+
+poly64x2_t
+foo2 (poly64x2_t a, poly64x2_t b)
+{
+  return vuzp1q_p64 (a, b);
+}
+
+poly64x2_t
+foo3 (poly64x2_t a, poly64x2_t b)
+{
+  return vuzp2q_p64 (a, b);
+}
+
+poly64x2_t
+foo4 (poly64x2_t a, poly64x2_t b)
+{
+  return vzip1q_p64 (a, b);
+}
+
+poly64x2_t
+foo5 (poly64x2_t a, poly64x2_t b)
+{
+  return vzip2q_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times {zip1\tv0.2d, v0.2d, v1.2d} 3 } } */
+/* { dg-final { scan-assembler-times {zip2\tv0.2d, v0.2d, v1.2d} 3 } } */
+

commit 852423cd68b403d09a14f6436080243c609a57a8
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 12:02:29 2020 +0100

    AArch64: Implement missing vrndns_f32 intrinsic
    
    This patch implements the missing vrndns_f32 intrinsic. This operates on a scalar float32_t value.
    It can be mapped down to a __builtin_aarch64_frintnsf builtin.
    
    This patch does that.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            PR target/71233
            * config/aarch64/aarch64-simd-builtins.def (frintn): Use BUILTIN_VHSDF_HSDF
            for modes.  Remove explicit hf instantiation.
            * config/aarch64/arm_neon.h (vrndns_f32): Define.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vrndns_f32_1.c: New test.
    
    (cherry picked from commit 02b5377b3766804059b7824330d33d0e1cef2e5b)

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 9566dc44d0b..8acfc083ce1 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -314,12 +314,11 @@
   BUILTIN_VHSDF (UNOP, nearbyint, 2)
   BUILTIN_VHSDF (UNOP, rint, 2)
   BUILTIN_VHSDF (UNOP, round, 2)
-  BUILTIN_VHSDF_DF (UNOP, frintn, 2)
+  BUILTIN_VHSDF_HSDF (UNOP, frintn, 2)
 
   VAR1 (UNOP, btrunc, 2, hf)
   VAR1 (UNOP, ceil, 2, hf)
   VAR1 (UNOP, floor, 2, hf)
-  VAR1 (UNOP, frintn, 2, hf)
   VAR1 (UNOP, nearbyint, 2, hf)
   VAR1 (UNOP, rint, 2, hf)
   VAR1 (UNOP, round, 2, hf)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index a0080b73cf1..33a3457b4c3 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -26204,6 +26204,13 @@ vrndmq_f64 (float64x2_t __a)
 
 /* vrndn  */
 
+__extension__ extern __inline float32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vrndns_f32 (float32_t __a)
+{
+  return __builtin_aarch64_frintnsf (__a);
+}
+
 __extension__ extern __inline float32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vrndn_f32 (float32x2_t __a)
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vrndns_f32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vrndns_f32_1.c
new file mode 100644
index 00000000000..960e4f6f768
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vrndns_f32_1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#include <arm_neon.h>
+
+float32_t
+test (float32_t a)
+{
+  return vrndns_f32 (a);
+}
+
+/* { dg-final { scan-assembler-times "frintn\\ts\[0-9\]+, s\[0-9\]+" 1 } } */
+

commit 3489c06cccb60c1af4c66aff82b670fb39f36266
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 17:37:58 2020 +0100

    AArch64: Implement missing p128<->f64 reinterpret intrinsics
    
    This patch implements the missing reinterprets to and from poly128_t and
    float64x2_t.
    I've plugged in the appropriate testing in the advsimd-intrinsics.exp
    too.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    Tested advsimd-intrinsics.exp on arm-none-eabi too to make sure arm
    testing isn't affected.
    
    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vreinterpretq_f64_p128,
            vreinterpretq_p128_f64): Define.
    
    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
            (clean_results): Add float64x2_t cleanup.
            (DECL_VARIABLE_128BITS_VARIANTS): Add float64x2_t variable.
            * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Add
            testing of vreinterpretq_f64_p128, vreinterpretq_p128_f64.
    
    (cherry picked from commit 65c9878641cbe0ed898aa7047b7b994e9d4a5bb1)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 33a3457b4c3..4b50503c446 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -6055,6 +6055,20 @@ vreinterpretq_u32_p128 (poly128_t __a)
   return (uint32x4_t)__a;
 }
 
+__extension__ extern __inline float64x2_t
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vreinterpretq_f64_p128 (poly128_t __a)
+{
+  return (float64x2_t) __a;
+}
+
+__extension__ extern __inline poly128_t
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vreinterpretq_p128_f64 (float64x2_t __a)
+{
+  return (poly128_t) __a;
+}
+
 /* vset_lane  */
 
 __extension__ extern __inline float16x4_t
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
index fde6029b7fc..791972c737e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
@@ -460,6 +460,8 @@ static void clean_results (void)
 #endif
   CLEAN(result, float, 32, 4);
 
+  AARCH64_ONLY(CLEAN(result, float, 64, 2));
+
 #if defined(__aarch64__)
   /* On AArch64, make sure to return DefaultNaN to have the same
      results as on AArch32.  */
@@ -544,7 +546,8 @@ static void clean_results (void)
   DECL_VARIABLE(VAR, poly, 16, 8);		\
   DECL_VARIABLE_CRYPTO(VAR, poly, 64, 2);	\
   DECL_VARIABLE(VAR, float, 16, 8);		\
-  DECL_VARIABLE(VAR, float, 32, 4)
+  DECL_VARIABLE(VAR, float, 32, 4);		\
+  AARCH64_ONLY(DECL_VARIABLE(VAR, float, 64, 2))
 #else
 #define DECL_VARIABLE_128BITS_VARIANTS(VAR)	\
   DECL_VARIABLE_128BITS_SIGNED_VARIANTS(VAR);	\
@@ -552,7 +555,8 @@ static void clean_results (void)
   DECL_VARIABLE(VAR, poly, 8, 16);		\
   DECL_VARIABLE(VAR, poly, 16, 8);		\
   DECL_VARIABLE_CRYPTO(VAR, poly, 64, 2);	\
-  DECL_VARIABLE(VAR, float, 32, 4)
+  DECL_VARIABLE(VAR, float, 32, 4);		\
+  AARCH64_ONLY(DECL_VARIABLE(VAR, float, 64, 2))
 #endif
 /* Declare all variants.  */
 #define DECL_VARIABLE_ALL_VARIANTS(VAR)		\
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
index 25b348223f3..67f809c7065 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c
@@ -33,6 +33,10 @@ VECT_VAR_DECL(vreint_expected_q_p128_f32,poly,64,2) [] = { 0xc1700000c1800000,
 							   0xc1500000c1600000 };
 VECT_VAR_DECL(vreint_expected_q_p128_f16,poly,64,2) [] = { 0xca80cb00cb80cc00,
 							   0xc880c900c980ca00 };
+#ifdef __aarch64__
+VECT_VAR_DECL(vreint_expected_q_p128_f64,poly,64,2) [] = { 0xc030000000000000,
+							   0xc02e000000000000 };
+#endif
 
 /* Expected results: vreinterpretq_*_p128.  */
 VECT_VAR_DECL(vreint_expected_q_s8_p128,int,8,16) [] = { 0xf0, 0xff, 0xff, 0xff,
@@ -75,6 +79,10 @@ VECT_VAR_DECL(vreint_expected_q_f16_p128,hfloat,16,8) [] = { 0xfff0, 0xffff,
 							     0xffff, 0xffff,
 							     0xfff1, 0xffff,
 							     0xffff, 0xffff };
+#ifdef __aarch64__
+VECT_VAR_DECL(vreint_expected_q_f64_p128,hfloat,64,2) [] = { 0xfffffffffffffff0,
+							     0xfffffffffffffff1 };
+#endif
 
 int main (void)
 {
@@ -90,6 +98,10 @@ int main (void)
 #endif
   VLOAD(vreint_vector, buffer, q, float, f, 32, 4);
 
+#ifdef __aarch64__
+  VLOAD(vreint_vector, buffer, q, float, f, 64, 2);
+#endif
+
   /* vreinterpretq_p128_* tests.  */
 #undef TEST_MSG
 #define TEST_MSG "VREINTERPRETQ_P128_*"
@@ -121,6 +133,10 @@ int main (void)
 #endif
   TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 32, 4, vreint_expected_q_p128_f32);
 
+#ifdef __aarch64__
+  TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 64, 2, vreint_expected_q_p128_f64);
+#endif
+
   /* vreinterpretq_*_p128 tests.  */
 #undef TEST_MSG
 #define TEST_MSG "VREINTERPRETQ_*_P128"
@@ -161,5 +177,8 @@ int main (void)
 #endif
   TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 32, 4, poly, p, 128, 1, vreint_expected_q_f32_p128);
 
+#ifdef __aarch64__
+  TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 64, 2, poly, p, 128, 1, vreint_expected_q_f64_p128);
+#endif
   return 0;
 }

commit 768c95cc6c84d504cf95fe948d808376628d2fa8
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Sep 25 10:40:18 2020 +0000

    testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,uzp,zip}_half.c
    
    Since r11-3402 (g:65c9878641cbe0ed898aa7047b7b994e9d4a5bb1), the
    vtrn_half, vuzp_half and vzip_half started failing with
    
    vtrn_half.c:76:17: error: redeclaration of 'vector_float64x2' with no linkage
    vtrn_half.c:77:17: error: redeclaration of 'vector2_float64x2' with no linkage
    vtrn_half.c:80:17: error: redeclaration of 'vector_res_float64x2' with no linkage
    
    This is because r11-3402 now always declares float64x2 variables for
    aarch64, leading to a duplicate declaration in these testcases.
    
    The fix is simply to remove these now useless declarations.
    
    These tests are skipped on arm*, so there is no impact on that target.
    
    2020-09-25  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: Remove
            declarations of vector, vector2, vector_res for float64x2 type.
            * gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: Likewise.
            * gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: Likewise.
    
    (cherry picked from commit 8c775bf447e190024fa08c55e38db94dd013a393)

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c
index 63f820fbf5a..25a0f198518 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c
@@ -73,11 +73,8 @@ void exec_vtrn_half (void)
   /* Input vector can only have 64 bits.  */
   DECL_VARIABLE_ALL_VARIANTS(vector);
   DECL_VARIABLE_ALL_VARIANTS(vector2);
-  DECL_VARIABLE(vector, float, 64, 2);
-  DECL_VARIABLE(vector2, float, 64, 2);
 
   DECL_VARIABLE_ALL_VARIANTS(vector_res);
-  DECL_VARIABLE(vector_res, float, 64, 2);
 
   clean_results ();
   /* We don't have vtrn1_T64x1, so set expected to the clean value.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c
index 8706f248591..2e6b666b71d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c
@@ -70,11 +70,8 @@ void exec_vuzp_half (void)
   /* Input vector can only have 64 bits.  */
   DECL_VARIABLE_ALL_VARIANTS(vector);
   DECL_VARIABLE_ALL_VARIANTS(vector2);
-  DECL_VARIABLE(vector, float, 64, 2);
-  DECL_VARIABLE(vector2, float, 64, 2);
 
   DECL_VARIABLE_ALL_VARIANTS(vector_res);
-  DECL_VARIABLE(vector_res, float, 64, 2);
 
   clean_results ();
   /* We don't have vuzp1_T64x1, so set expected to the clean value.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c
index 619d6b2e6ed..ef42451c82e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c
@@ -73,11 +73,8 @@ void exec_vzip_half (void)
   /* Input vector can only have 64 bits.  */
   DECL_VARIABLE_ALL_VARIANTS(vector);
   DECL_VARIABLE_ALL_VARIANTS(vector2);
-  DECL_VARIABLE(vector, float, 64, 2);
-  DECL_VARIABLE(vector2, float, 64, 2);
 
   DECL_VARIABLE_ALL_VARIANTS(vector_res);
-  DECL_VARIABLE(vector_res, float, 64, 2);
 
   clean_results ();
   /* We don't have vzip1_T64x1, so set expected to the clean value.  */

commit 8fefe1028d314a81b2356e9e9b9e1644f2eeb0ef
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Sep 29 00:17:52 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5b46236c34d..11a080fd33c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,73 @@
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* config/aarch64/arm_neon.h (vreinterpretq_f64_p128,
+	vreinterpretq_p128_f64): Define.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* config/aarch64/aarch64-simd-builtins.def (frintn): Use BUILTIN_VHSDF_HSDF
+	for modes.  Remove explicit hf instantiation.
+	* config/aarch64/arm_neon.h (vrndns_f32): Define.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* config/aarch64/arm_neon.h (vtrn1q_p64, vtrn2q_p64, vuzp1q_p64,
+	vuzp2q_p64, vzip1q_p64, vzip2q_p64): Define.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* config/aarch64/arm_neon.h (vldrq_p128): Define.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* config/aarch64/arm_neon.h (vstrq_p128): Define.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* config/aarch64/arm_neon.h (vcls_u8, vcls_u16, vcls_u32,
+	vclsq_u8, vclsq_u16, vclsq_u32): Define.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* config/aarch64/arm_neon.h (vceqq_p64, vceqz_p64, vceqzq_p64): Define.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* config/aarch64/arm_neon.h (vadd_p8, vadd_p16, vadd_p64, vaddq_p8,
+	vaddq_p16, vaddq_p64, vaddq_p128): Define.
+
 2020-09-27  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0c0687f326c..91db4fb5929 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200928
+20200929
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 7368bdc73fd..a040e81a253 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,23 @@
+2020-09-28  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	Revert:
+	2020-09-27  Steven G. Kargl  <kargl@gcc.gnu.org>
+		    Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	PR fortran/95614
+	* decl.c (gfc_get_common): Use gfc_match_common_name instead
+	of match_common_name.
+	* decl.c (gfc_bind_idents): Use gfc_match_common_name instead
+	of match_common_name.
+	* match.c : Rename match_common_name to gfc_match_common_name.
+	* match.c (gfc_match_common): Use gfc_match_common_name instead
+	of match_common_name.
+	* match.h : Rename match_common_name to gfc_match_common_name.
+	* resolve.c (resolve_common_vars): Check each symbol in a
+	common block has a global symbol.  If there is a global symbol
+	issue an error if the symbol type is known as is not a common
+	block name.
+
 2020-09-27  Mark Eggleston  <markeggleston@gcc.gnu.org>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fdf60877d36..0a4cf7c7f4d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,92 @@
+2020-09-28  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	Backported from master:
+	2020-09-25  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	PR target/71233
+	* gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: Remove
+	declarations of vector, vector2, vector_res for float64x2 type.
+	* gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: Likewise.
+	* gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: Likewise.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+	(clean_results): Add float64x2_t cleanup.
+	(DECL_VARIABLE_128BITS_VARIANTS): Add float64x2_t variable.
+	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Add
+	testing of vreinterpretq_f64_p128, vreinterpretq_p128_f64.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/simd/vrndns_f32_1.c: New test.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/simd/trn_zip_p64_1.c: New test.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/simd/vldrq_p128_1.c: New test.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/simd/vstrq_p128_1.c: New test.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/simd/vcls_unsigned_1.c: New test.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/simd/vceq_poly_1.c: New test.
+
+2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/71233
+	* gcc.target/aarch64/simd/vadd_poly_1.c: New test.
+
+2020-09-28  Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	Revert:
+	2020-09-28  Steven G. Kargl  <kargl@gcc.gnu.org>
+		    Mark Eggleston  <markeggleston@gcc.gnu.org>
+
+	PR fortran/95614
+	* gfortran.dg/pr95614_1.f90: New test.
+	* gfortran.dg/pr95614_2.f90: New test.
+
 2020-09-27  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:

commit d41b3eac2b4a499317fce6cd392a545153c30845
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Tue Sep 29 14:56:13 2020 +0100

    arm: Add support for Neoverse V1 CPU
    
    This patch backports the AArch32 support for Arm's Neoverse V1 CPU to
    GCC 8.
    
    gcc/ChangeLog:
    
            * config/arm/arm-cpus.in (neoverse-v1): New.
            * config/arm/arm-tables.opt: Regenerate.
            * config/arm/arm-tune.md: Regenerate.
            * doc/invoke.texi: Document AArch32 support for Neoverse V1.

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index ba194a80229..edfe5b378da 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1576,6 +1576,18 @@ begin cpu cortex-a75.cortex-a55
  costs cortex_a73
 end cpu cortex-a75.cortex-a55
 
+
+# Armv8.4 A-profile Architecture Processors
+begin cpu neoverse-v1
+  cname neoversev1
+  tune for cortex-a57
+  tune flags LDSCHED
+  architecture armv8.4-a+fp16
+  option crypto add FP_ARMv8 CRYPTO
+  costs cortex_a57
+end cpu neoverse-v1
+
+
 # V8 M-profile implementations.
 begin cpu cortex-m23
  cname cortexm23
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 60e5065b398..36dba62003a 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -351,6 +351,9 @@ Enum(processor_type) String(cortex-a75) Value( TARGET_CPU_cortexa75)
 EnumValue
 Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75cortexa55)
 
+EnumValue
+Enum(processor_type) String(neoverse-v1) Value( TARGET_CPU_neoversev1)
+
 EnumValue
 Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
 
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index df43a1ccbb2..c972ce55576 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -57,6 +57,6 @@
 	cortexa73,exynosm1,xgene1,
 	cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
 	cortexa73cortexa53,cortexa55,cortexa75,
-	cortexa75cortexa55,cortexm23,cortexm33,
-	cortexr52"
+	cortexa75cortexa55,neoversev1,cortexm23,
+	cortexm33,cortexr52"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a46a9cb31f7..6b40362e412 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -16334,8 +16334,8 @@ Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
 @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
 @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
-@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7},
-@samp{cortex-r8}, @samp{cortex-r52},
+@samp{neoverse-v1}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
+@samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52},
 @samp{cortex-m33},
 @samp{cortex-m23},
 @samp{cortex-m7},

commit 528348fca9a9a29ba40a32df8f1a0dc95b101aa7
Author: Hongyu Wang <hongyu.wang@intel.com>
Date:   Mon Sep 28 22:22:28 2020 +0000

    Add missing FSF copyright notes for x86 intrinsic headers.
    
    gcc/ChangeLog:
    
            PR target/97231
            * config/i386/pconfigintrin.h: Add FSF copyright notes.
            * config/i386/wbnoinvdintrin.h: Ditto.
    
    (cherry picked from commit d68f4d2ecb8ed6781e4e535d2abc498b1674d68a)

diff --git a/gcc/config/i386/pconfigintrin.h b/gcc/config/i386/pconfigintrin.h
index 1c9c35c5e2b..7b8ed88c84e 100644
--- a/gcc/config/i386/pconfigintrin.h
+++ b/gcc/config/i386/pconfigintrin.h
@@ -1,3 +1,26 @@
+/* Copyright (C) 2018-2020 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
 #ifndef _X86INTRIN_H_INCLUDED
 #error "Never use <pconfigintrin.h> directly; include <x86intrin.h> instead."
 #endif
diff --git a/gcc/config/i386/wbnoinvdintrin.h b/gcc/config/i386/wbnoinvdintrin.h
index 9312a0082c9..fa95cd0bd22 100644
--- a/gcc/config/i386/wbnoinvdintrin.h
+++ b/gcc/config/i386/wbnoinvdintrin.h
@@ -1,3 +1,26 @@
+/* Copyright (C) 2018-2020 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
 #ifndef _X86INTRIN_H_INCLUDED
 #error "Never use <wbnoinvdintrin.h> directly; include <x86intrin.h> instead."
 #endif

commit 1b4dc1d09eda31f2a8b5238df36d270830e3e3a0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Sep 30 00:17:41 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 11a080fd33c..d64294a2a7d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2020-09-29  Hongyu Wang  <hongyu.wang@intel.com>
+
+	Backported from master:
+	2020-09-29  Hongyu Wang  <hongyu.wang@intel.com>
+
+	PR target/97231
+	* config/i386/pconfigintrin.h: Add FSF copyright notes.
+	* config/i386/wbnoinvdintrin.h: Ditto.
+
+2020-09-29  Alex Coplan  <alex.coplan@arm.com>
+
+	* config/arm/arm-cpus.in (neoverse-v1): New.
+	* config/arm/arm-tables.opt: Regenerate.
+	* config/arm/arm-tune.md: Regenerate.
+	* doc/invoke.texi: Document AArch32 support for Neoverse V1.
+
 2020-09-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 91db4fb5929..f1815d15e81 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200929
+20200930

commit b0e6f198547d423b24520c13e3c29f3712026fce
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Sep 23 12:11:45 2020 -0700

    x86: Use SET operation in MOVDIRI and MOVDIR64B
    
    Since MOVDIRI and MOVDIR64B write to memory, similar to UNSPEC_MOVNT,
    use SET operation in MOVDIRI and MOVDIR64B patterns with UNSPEC instead
    of UNSPECV.
    
    gcc/
    
            PR target/97184
            * config/i386/i386.md (UNSPECV_MOVDIRI): Renamed to ...
            (UNSPEC_MOVDIRI): This.
            (UNSPECV_MOVDIR64B): Renamed to ...
            (UNSPEC_MOVDIR64B): This.
            (movdiri<mode>): Use SET operation.
            (@movdir64b_<mode>): Likewise.
    
    gcc/testsuite/
    
            PR target/97184
            * gcc.target/i386/movdir64b.c: New test.
            * gcc.target/i386/movdiri32.c: Likewise.
            * gcc.target/i386/movdiri64.c: Likewise.
            * lib/target-supports.exp (check_effective_target_movdir): New.
    
    (cherry picked from commit 5521e8a629f8bee3a7778d69521d857496556d1f)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 11d69e997bb..c17ae94f90d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -196,6 +196,10 @@
 
   ;; IRET support
   UNSPEC_INTERRUPT_RETURN
+
+  ;; For MOVDIRI and MOVDIR64B support
+  UNSPEC_MOVDIRI
+  UNSPEC_MOVDIR64B
 ])
 
 (define_c_enum "unspecv" [
@@ -289,8 +293,6 @@
   UNSPECV_WRUSS
   UNSPECV_SETSSBSY
   UNSPECV_CLRSSBSY
-  UNSPECV_MOVDIRI
-  UNSPECV_MOVDIR64B
 ])
 
 ;; Constants to represent rounding modes in the ROUND instruction
@@ -20782,17 +20784,17 @@
   [(set_attr "type" "other")])
 
 (define_insn "movdiri<mode>"
-  [(unspec_volatile:SWI48[(match_operand:SWI48 0 "memory_operand" "m")
-	(match_operand:SWI48 1 "register_operand" "r")]
-		   UNSPECV_MOVDIRI)]
+  [(set (match_operand:SWI48 0 "memory_operand" "=m")
+	(unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")]
+		      UNSPEC_MOVDIRI))]
   "TARGET_MOVDIRI"
   "movdiri\t{%1, %0|%0, %1}"
   [(set_attr "type" "other")])
 
 (define_insn "movdir64b_<mode>"
-  [(unspec_volatile:XI[(match_operand:P 0 "register_operand" "r")
-	(match_operand:XI 1 "memory_operand")]
-		 UNSPECV_MOVDIR64B)]
+  [(set (mem:XI (match_operand:P 0 "register_operand" "r"))
+	(unspec:XI [(match_operand:XI 1 "memory_operand" "m")]
+		   UNSPEC_MOVDIR64B))]
   "TARGET_MOVDIR64B"
   "movdir64b\t{%1, %0|%0, %1}"
   [(set_attr "type" "other")])
diff --git a/gcc/testsuite/gcc.target/i386/movdir64b.c b/gcc/testsuite/gcc.target/i386/movdir64b.c
new file mode 100644
index 00000000000..01451a8eb9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/movdir64b.c
@@ -0,0 +1,29 @@
+/* { dg-do run { target movdir } } */
+/* { dg-options "-mmovdir64b -O2" } */
+
+#include <x86intrin.h>
+#include <cpuid.h>
+#include <string.h>
+
+unsigned long long int src[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+unsigned long long int dest[8] __attribute__ ((aligned (64)))
+  = {-1, -1, -1, -1, -1, -1, -1, -1};
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid_count (7, 0, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  if ((ecx & bit_MOVDIR64B) == 0)
+    return 0;
+
+  _movdir64b (dest, src);
+
+  if (memcmp (dest, src, sizeof (dest)) != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/movdiri32.c b/gcc/testsuite/gcc.target/i386/movdiri32.c
new file mode 100644
index 00000000000..04a412f9bf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/movdiri32.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target movdir } } */
+/* { dg-options "-mmovdiri -O2" } */
+
+#include <x86intrin.h>
+#include <cpuid.h>
+
+unsigned int dest = -1;
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid_count (7, 0, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  if ((ecx & bit_MOVDIRI) == 0)
+    return 0;
+
+  _directstoreu_u32 (&dest, 0xbadbeef);
+
+  if (dest != 0xbadbeef)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/movdiri64.c b/gcc/testsuite/gcc.target/i386/movdiri64.c
new file mode 100644
index 00000000000..e0cb6081496
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/movdiri64.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { movdir && { ! ia32 } } } } */
+/* { dg-options "-mmovdiri -O2" } */
+
+#include <x86intrin.h>
+#include <cpuid.h>
+
+unsigned long long int dest = -1LL;
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid_count (7, 0, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  if ((ecx & bit_MOVDIRI) == 0)
+    return 0;
+
+  _directstoreu_u64 (&dest, 0x12345678badbeef);
+
+  if (dest != 0x12345678badbeef)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 8c6db512c63..4516cfc49e4 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -9464,3 +9464,19 @@ foreach N {df} {
     }]
 }
 
+# Return 1 if we're able to assemble movdiri and movdir64b
+
+proc check_effective_target_movdir { } {
+    return [check_no_compiler_messages movdir object {
+	void
+	foo (unsigned int *d, unsigned int s)
+	{
+	  __builtin_ia32_directstoreu_u32 (d, s);
+	}
+	void
+	bar (void *d, const void *s)
+	{
+	  __builtin_ia32_movdir64b (d, s);
+	}
+    } "-mmovdiri -mmovdir64b" ]
+}

commit 292d4ff8f63f0a611958a6e37cbf6545ba86fa63
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Fri Sep 25 17:32:43 2020 +0100

    AArch64: Add Linux cpuinfo string for rng feature
    
    The Linux kernel has defined the cpuinfo string for the +rng feature, so
    this patch adds that to GCC so that -march=native can pick it up.
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            * config/aarch64/aarch64-option-extensions.def (rng): Add
            cpuinfo string.
    
    (cherry picked from commit 0d8f3f612d662ea3007c184a11ea5eb7d58760e7)
    (cherry picked from commit 05c3a208a19af25fbfd5c7cad8be12e23bf84cfa)

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index bfd9245c595..29e282b714a 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -115,6 +115,6 @@ AARCH64_OPT_EXTENSION("fp16fml", AARCH64_FL_F16FML, AARCH64_FL_FP | AARCH64_FL_F
 AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, 0, false, "sve")
 
 /* Enabling/Disabling "rng" only changes "rng".  */
-AARCH64_OPT_EXTENSION("rng", AARCH64_FL_RNG, 0, 0, false, "")
+AARCH64_OPT_EXTENSION("rng", AARCH64_FL_RNG, 0, 0, false, "rng")
 
 #undef AARCH64_OPT_EXTENSION

commit e38531c3f12100cb69691598ebd5ab985a56bc25
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Oct 1 00:17:43 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d64294a2a7d..a7ece67f7e0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+2020-09-30  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-09-30  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-option-extensions.def (rng): Add
+	cpuinfo string.
+
+2020-09-30  H.J. Lu  <hjl.tools@gmail.com>
+
+	Backported from master:
+	2020-09-30  H.J. Lu  <hjl.tools@gmail.com>
+
+	PR target/97184
+	* config/i386/i386.md (UNSPECV_MOVDIRI): Renamed to ...
+	(UNSPEC_MOVDIRI): This.
+	(UNSPECV_MOVDIR64B): Renamed to ...
+	(UNSPEC_MOVDIR64B): This.
+	(movdiri<mode>): Use SET operation.
+	(@movdir64b_<mode>): Likewise.
+
 2020-09-29  Hongyu Wang  <hongyu.wang@intel.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f1815d15e81..c5ffab19559 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20200930
+20201001
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0a4cf7c7f4d..e6a2cc50f8c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2020-09-30  H.J. Lu  <hjl.tools@gmail.com>
+
+	Backported from master:
+	2020-09-30  H.J. Lu  <hjl.tools@gmail.com>
+
+	PR target/97184
+	* gcc.target/i386/movdir64b.c: New test.
+	* gcc.target/i386/movdiri32.c: Likewise.
+	* gcc.target/i386/movdiri64.c: Likewise.
+	* lib/target-supports.exp (check_effective_target_movdir): New.
+
 2020-09-28  Christophe Lyon  <christophe.lyon@linaro.org>
 
 	Backported from master:

commit 925d3cf3e3640238b585480f100a46c428118370
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Thu Oct 1 09:53:48 2020 +0100

    aarch64: Add support for Neoverse N2 CPU
    
    This patch backports the AArch64 support for Arm's Neoverse N2 CPU to
    GCC 8.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64-cores.def: Add Neoverse N2.
            * config/aarch64/aarch64-tune.md: Regenerate.
            * doc/invoke.texi: Document AArch64 support for Neoverse N2.

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 35ce68ad077..c6c1e3739de 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -100,6 +100,9 @@ AARCH64_CORE("saphira",     saphira,    falkor,    8_3A,  AARCH64_FL_FOR_ARCH8_3
 AARCH64_CORE("zeus", zeus, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE, cortexa72, 0x41, 0xd40, -1)
 AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE, cortexa72, 0x41, 0xd40, -1)
 
+/* Armv8.5-A Architecture Processors.  */
+AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd49, -1)
+
 /* ARMv8-A big.LITTLE implementations.  */
 
 AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1)
diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index e8894ee4a9d..2d7c9aa4740 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr "tune"
-	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,saphira,zeus,neoversev1,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55"
+	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,saphira,zeus,neoversev1,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55"
 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6b40362e412..b91366daafd 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14771,9 +14771,9 @@ Specify the name of the target processor for which GCC should tune the
 performance of the code.  Permissible values for this option are:
 @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
 @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
-@samp{cortex-a76}, @samp{ares}, @samp{neoverse-n1}, @samp{neoverse-v1},
-@samp{zeus}, @samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{saphira},
-@samp{xgene1}, @samp{vulcan}, @samp{thunderx},
+@samp{cortex-a76}, @samp{ares}, @samp{neoverse-n1}, @samp{neoverse-n2},
+@samp{neoverse-v1}, @samp{zeus}, @samp{exynos-m1}, @samp{falkor},
+@samp{qdf24xx}, @samp{saphira}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx},
 @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
 @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},
 @samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},

commit 442cec79a034be1c6ac315ad70dff11974468a5b
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Oct 1 11:04:56 2020 +0200

    s390: Fix up s390_atomic_assign_expand_fenv
    
    The following patch fixes
    -FAIL: gcc.dg/pr94780.c (internal compiler error)
    -FAIL: gcc.dg/pr94780.c (test for excess errors)
    -FAIL: gcc.dg/pr94842.c (internal compiler error)
    -FAIL: gcc.dg/pr94842.c (test for excess errors)
    on s390x-linux.  The fix is essentially the same as has been applied to many
    other targets (i386, aarch64, arm, rs6000, alpha, riscv).
    
    2020-10-01  Jakub Jelinek  <jakub@redhat.com>
    
            * config/s390/s390.c (s390_atomic_assign_expand_fenv): Use
            TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
            fenv_var and old_fpc.  Formatting fixes.
    
    (cherry picked from commit 85516b71730d8f9401c34407ac3fadf5f1ebfc4e)

diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 9057154be07..20424537558 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -16225,12 +16225,13 @@ s390_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 
      fenv_var = __builtin_s390_efpc ();
      __builtin_s390_sfpc (fenv_var & mask) */
-  tree old_fpc = build2 (MODIFY_EXPR, unsigned_type_node, fenv_var, call_efpc);
-  tree new_fpc =
-    build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var,
-	    build_int_cst (unsigned_type_node,
-			   ~(FPC_DXC_MASK | FPC_FLAGS_MASK |
-			     FPC_EXCEPTION_MASK)));
+  tree old_fpc = build4 (TARGET_EXPR, unsigned_type_node, fenv_var, call_efpc,
+			 NULL_TREE, NULL_TREE);
+  tree new_fpc
+    = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var,
+	      build_int_cst (unsigned_type_node,
+			     ~(FPC_DXC_MASK | FPC_FLAGS_MASK
+			       | FPC_EXCEPTION_MASK)));
   tree set_new_fpc = build_call_expr (sfpc, 1, new_fpc);
   *hold = build2 (COMPOUND_EXPR, void_type_node, old_fpc, set_new_fpc);
 
@@ -16249,8 +16250,8 @@ s390_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
   __atomic_feraiseexcept ((old_fpc & FPC_FLAGS_MASK) >> FPC_FLAGS_SHIFT);  */
 
   old_fpc = create_tmp_var_raw (unsigned_type_node);
-  tree store_old_fpc = build2 (MODIFY_EXPR, void_type_node,
-			       old_fpc, call_efpc);
+  tree store_old_fpc = build4 (TARGET_EXPR, void_type_node, old_fpc, call_efpc,
+			       NULL_TREE, NULL_TREE);
 
   set_new_fpc = build_call_expr (sfpc, 1, fenv_var);
 

commit 8586b291c50bd1796ef98d9c29837c622a59d8d1
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu Oct 1 15:22:51 2020 +0100

    AArch64: Add rng feature to Neoverse V1
    
    This patch adds the +rng feature to the Neoverse V1 entry. It exists in
    the GCC 11 and 10 branches, but was missed out on GCC 9 and 8 as those
    didn't support the rng intrinsic then, but they do now.
    
    gcc/
            * config/aarch64/aarch64-cores.def (zeus): Add AARCH64_FL_RNG to
            features.
            (neoverse-v1): Likewise.

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index c6c1e3739de..6a766bfd7cd 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -97,8 +97,8 @@ AARCH64_CORE("saphira",     saphira,    falkor,    8_3A,  AARCH64_FL_FOR_ARCH8_3
 /* ARMv8.4-A Architecture Processors.  */
 
 /* ARM ('A') cores. */
-AARCH64_CORE("zeus", zeus, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE, cortexa72, 0x41, 0xd40, -1)
-AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE, cortexa72, 0x41, 0xd40, -1)
+AARCH64_CORE("zeus", zeus, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd40, -1)
+AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd40, -1)
 
 /* Armv8.5-A Architecture Processors.  */
 AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd49, -1)

commit 42140cb640bd8ab9362d89b8ab01f31309069710
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu Oct 1 17:36:13 2020 +0100

    AArch64: Add prefer_advsimd_autovec internal tune_flag
    
    This is the GCC 8 version of the prefer_advsimd_autovec patch.
    It's very similar to the GCC 9 version.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            * config/aarch64/aarch64-tuning-flags.def
            (PREFER_ADVSIMD_AUTOVEC): Define.
            * config/aarch64/aarch64.c (aarch64_preferred_simd_mode): Use
            it.
            (aarch64_autovectorize_vector_sizes): Likewise.

diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def
index ea9ead234cb..0f242630f46 100644
--- a/gcc/config/aarch64/aarch64-tuning-flags.def
+++ b/gcc/config/aarch64/aarch64-tuning-flags.def
@@ -41,4 +41,7 @@ AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW)
    are not considered cheap.  */
 AARCH64_EXTRA_TUNING_OPTION ("cheap_shift_extend", CHEAP_SHIFT_EXTEND)
 
+/* Prefer Advanced SIMD over SVE for auto-vectorization.  */
+AARCH64_EXTRA_TUNING_OPTION ("prefer_advsimd_autovec", PREFER_ADVSIMD_AUTOVEC)
+
 #undef AARCH64_EXTRA_TUNING_OPTION
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index e20a4ccc6dc..6c05a6686c5 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -12970,7 +12970,12 @@ aarch64_simd_container_mode (scalar_mode mode, poly_int64 width)
 static machine_mode
 aarch64_preferred_simd_mode (scalar_mode mode)
 {
-  poly_int64 bits = TARGET_SVE ? BITS_PER_SVE_VECTOR : 128;
+  /* If current tuning prefers Advanced SIMD, bypass SVE.  */
+  bool use_sve
+    = TARGET_SVE
+      && !(aarch64_tune_params.extra_tuning_flags
+	   & AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC);
+  poly_int64 bits = use_sve ? BITS_PER_SVE_VECTOR : 128;
   return aarch64_simd_container_mode (mode, bits);
 }
 
@@ -12979,7 +12984,11 @@ aarch64_preferred_simd_mode (scalar_mode mode)
 static void
 aarch64_autovectorize_vector_sizes (vector_sizes *sizes)
 {
-  if (TARGET_SVE)
+  bool use_sve
+    = TARGET_SVE
+      && !(aarch64_tune_params.extra_tuning_flags
+	   & AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC);
+  if (use_sve)
     sizes->safe_push (BYTES_PER_SVE_VECTOR);
   sizes->safe_push (16);
   sizes->safe_push (8);

commit d44721af80bba1be9493a5944ba4afa72dc47f58
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Oct 2 00:17:45 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a7ece67f7e0..5df557a8299 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,32 @@
+2020-10-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-tuning-flags.def
+	(PREFER_ADVSIMD_AUTOVEC): Define.
+	* config/aarch64/aarch64.c (aarch64_preferred_simd_mode): Use
+	it.
+	(aarch64_autovectorize_vector_sizes): Likewise.
+
+2020-10-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-cores.def (zeus): Add AARCH64_FL_RNG to
+	features.
+	(neoverse-v1): Likewise.
+
+2020-10-01  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2020-10-01  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/s390/s390.c (s390_atomic_assign_expand_fenv): Use
+	TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
+	fenv_var and old_fpc.  Formatting fixes.
+
+2020-10-01  Alex Coplan  <alex.coplan@arm.com>
+
+	* config/aarch64/aarch64-cores.def: Add Neoverse N2.
+	* config/aarch64/aarch64-tune.md: Regenerate.
+	* doc/invoke.texi: Document AArch64 support for Neoverse N2.
+
 2020-09-30  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c5ffab19559..4d58d2f285c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201001
+20201002

commit a9ba7f6cb74a6bc591d98983d37160edbc2ba06b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Fri Oct 2 15:39:11 2020 +0100

    AArch64: Add Neoverse V1 tuning struct
    
    This GCC 8 patch duplicates the Cortex-A72 tuning struct that's
    currently used for Neoverse V1 and
    AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC tune flag to prefer Advanced
    SIMD over SVE autovectorisation.
    
    gcc/
            * config/aarch64/aarch64.c (neoversev1_tunings): Define.
            * config/aarch64/aarch64-cores.def (zeus): Use it.
            (neoverse-v1): Likewise.

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 6a766bfd7cd..29727fabc2a 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -97,8 +97,8 @@ AARCH64_CORE("saphira",     saphira,    falkor,    8_3A,  AARCH64_FL_FOR_ARCH8_3
 /* ARMv8.4-A Architecture Processors.  */
 
 /* ARM ('A') cores. */
-AARCH64_CORE("zeus", zeus, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd40, -1)
-AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd40, -1)
+AARCH64_CORE("zeus", zeus, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, neoversev1, 0x41, 0xd40, -1)
+AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, neoversev1, 0x41, 0xd40, -1)
 
 /* Armv8.5-A Architecture Processors.  */
 AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd49, -1)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 6c05a6686c5..3d218b6b951 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -760,6 +760,32 @@ static const struct tune_params cortexa72_tunings =
   &generic_prefetch_tune
 };
 
+static const struct tune_params neoversev1_tunings =
+{
+  &cortexa57_extra_costs,
+  &generic_addrcost_table,
+  &cortexa57_regmove_cost,
+  &cortexa57_vector_cost,
+  &generic_branch_cost,
+  &generic_approx_modes,
+  4, /* memmov_cost  */
+  3, /* issue_rate  */
+  (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+   | AARCH64_FUSE_MOVK_MOVK), /* fusible_ops  */
+  16,	/* function_align.  */
+  4,	/* jump_align.  */
+  8,	/* loop_align.  */
+  2,	/* int_reassoc_width.  */
+  4,	/* fp_reassoc_width.  */
+  1,	/* vec_reassoc_width.  */
+  2,	/* min_div_recip_mul_sf.  */
+  2,	/* min_div_recip_mul_df.  */
+  0,	/* max_case_values.  */
+  tune_params::AUTOPREFETCHER_WEAK,	/* autoprefetcher_model.  */
+  (AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC),	/* tune_flags.  */
+  &generic_prefetch_tune
+};
+
 static const struct tune_params cortexa73_tunings =
 {
   &cortexa57_extra_costs,

commit cb79435c6832ae55857ac86cf14deb059294ad67
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Fri Oct 2 18:07:30 2020 +0100

    arm: Add support for Neoverse N2 CPU
    
    This patch backports the AArch32 support for Arm's Neoverse N2 CPU to
    GCC 8.
    
    gcc/ChangeLog:
    
            * config/arm/arm-cpus.in (neoverse-n2): New.
            * config/arm/arm-tables.opt: Regenerate.
            * config/arm/arm-tune.md: Regenerate.
            * config/arm/driver-arm.c (arm_cpu_table): Add Neoverse N2.
            * doc/invoke.texi: Document support for Neoverse N2.

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index edfe5b378da..39a9e8b76ba 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1588,6 +1588,17 @@ begin cpu neoverse-v1
 end cpu neoverse-v1
 
 
+# Armv8.5 A-profile Architecture Processors
+begin cpu neoverse-n2
+  cname neoversen2
+  tune for cortex-a57
+  tune flags LDSCHED
+  architecture armv8.4-a+fp16
+  option crypto add FP_ARMv8 CRYPTO
+  costs cortex_a57
+end cpu neoverse-n2
+
+
 # V8 M-profile implementations.
 begin cpu cortex-m23
  cname cortexm23
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 36dba62003a..a0fb8323ee3 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -354,6 +354,9 @@ Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75co
 EnumValue
 Enum(processor_type) String(neoverse-v1) Value( TARGET_CPU_neoversev1)
 
+EnumValue
+Enum(processor_type) String(neoverse-n2) Value( TARGET_CPU_neoversen2)
+
 EnumValue
 Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
 
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index c972ce55576..ea3dbcda43f 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -57,6 +57,6 @@
 	cortexa73,exynosm1,xgene1,
 	cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
 	cortexa73cortexa53,cortexa55,cortexa75,
-	cortexa75cortexa55,neoversev1,cortexm23,
-	cortexm33,cortexr52"
+	cortexa75cortexa55,neoversev1,neoversen2,
+	cortexm23,cortexm33,cortexr52"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c
index a53c2272864..45ad92ef0e0 100644
--- a/gcc/config/arm/driver-arm.c
+++ b/gcc/config/arm/driver-arm.c
@@ -56,6 +56,7 @@ static struct vendor_cpu arm_cpu_table[] = {
     {"0xd09", "armv8-a+crc", "cortex-a73"},
     {"0xd05", "armv8.2-a+fp16+dotprod", "cortex-a55"},
     {"0xd0a", "armv8.2-a+fp16+dotprod", "cortex-a75"},
+    {"0xd49", "armv8.4-a+fp16", "neoverse-n2"},
     {"0xc14", "armv7-r", "cortex-r4"},
     {"0xc15", "armv7-r", "cortex-r5"},
     {"0xc17", "armv7-r", "cortex-r7"},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b91366daafd..78ca7738df2 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -16334,8 +16334,8 @@ Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
 @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
 @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
-@samp{neoverse-v1}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
-@samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52},
+@samp{neoverse-v1}, @samp{neoverse-n2}, @samp{cortex-r4}, @samp{cortex-r4f},
+@samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52},
 @samp{cortex-m33},
 @samp{cortex-m23},
 @samp{cortex-m7},

commit a8e1fa105202bb92a483b5ff3512219427a46de9
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Oct 3 00:17:43 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5df557a8299..213c6a53cc9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2020-10-02  Alex Coplan  <alex.coplan@arm.com>
+
+	* config/arm/arm-cpus.in (neoverse-n2): New.
+	* config/arm/arm-tables.opt: Regenerate.
+	* config/arm/arm-tune.md: Regenerate.
+	* config/arm/driver-arm.c (arm_cpu_table): Add Neoverse N2.
+	* doc/invoke.texi: Document support for Neoverse N2.
+
+2020-10-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.c (neoversev1_tunings): Define.
+	* config/aarch64/aarch64-cores.def (zeus): Use it.
+	(neoverse-v1): Likewise.
+
 2020-10-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* config/aarch64/aarch64-tuning-flags.def
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4d58d2f285c..c28ca09d231 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201002
+20201003

commit f02e03b729fb2b1c58f7acb9dec82af3d24b6084
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Oct 4 00:17:37 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c28ca09d231..db901996879 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201003
+20201004

commit 46f2b419640f5f233e56f80e99d902bb1da256b3
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Oct 5 00:17:32 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index db901996879..9d81fe17340 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201004
+20201005

commit cb0a59cb7efa7d39e91ef28a692a424cc3c90fd3
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Oct 6 00:17:41 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 9d81fe17340..684bf4bc84d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201005
+20201006

commit 367e8e91d16c92834855f306eedb402c43a4589f
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Tue Oct 6 16:48:48 2020 +0100

    arm: Add missing part number for Neoverse V1
    
    This patch adds the part number for Neoverse V1 which was missing from
    the initial AArch32 support in GCC 8.
    
    gcc/ChangeLog:
    
            * config/arm/driver-arm.c (arm_cpu_table): Add neoverse-v1.

diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c
index 45ad92ef0e0..83522897d06 100644
--- a/gcc/config/arm/driver-arm.c
+++ b/gcc/config/arm/driver-arm.c
@@ -56,6 +56,7 @@ static struct vendor_cpu arm_cpu_table[] = {
     {"0xd09", "armv8-a+crc", "cortex-a73"},
     {"0xd05", "armv8.2-a+fp16+dotprod", "cortex-a55"},
     {"0xd0a", "armv8.2-a+fp16+dotprod", "cortex-a75"},
+    {"0xd40", "armv8.4-a+fp16", "neoverse-v1"},
     {"0xd49", "armv8.4-a+fp16", "neoverse-n2"},
     {"0xc14", "armv7-r", "cortex-r4"},
     {"0xc15", "armv7-r", "cortex-r5"},

commit bc3b48a1d15b0920c32bba9efd880de2120b5f48
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Oct 7 00:17:45 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 213c6a53cc9..d0ed9184227 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2020-10-06  Alex Coplan  <alex.coplan@arm.com>
+
+	* config/arm/driver-arm.c (arm_cpu_table): Add neoverse-v1.
+
 2020-10-02  Alex Coplan  <alex.coplan@arm.com>
 
 	* config/arm/arm-cpus.in (neoverse-n2): New.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 684bf4bc84d..8478d98f282 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201006
+20201007

commit 775c628e44e073df45e22a7b557f184e8966d05e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Oct 8 00:17:44 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 8478d98f282..df504552863 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201007
+20201008

commit ba597a9fad83b3721c5a4d30d9fcf27f8a29eb86
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Thu Oct 8 00:05:53 2020 +0100

    libstdc++: Fix non-reserved name in header
    
    There's a "il" parameter in a std::seed_seq constructor in <random>
    which is only reserved since C++14.
    
    libstdc++-v3/ChangeLog:
    
            * include/bits/random.h (seed_seq(initializer_list<T>)): Rename
            parameter to use reserved name.
            * testsuite/17_intro/names.cc: Check "il".
    
    (cherry picked from commit 23f75da95f5e8e09e9fcbd5b0d2885e6c44739aa)

diff --git a/libstdc++-v3/include/bits/random.h b/libstdc++-v3/include/bits/random.h
index ccd5c834db8..50da41615d5 100644
--- a/libstdc++-v3/include/bits/random.h
+++ b/libstdc++-v3/include/bits/random.h
@@ -5968,7 +5968,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
     { }
 
     template<typename _IntType>
-      seed_seq(std::initializer_list<_IntType> il);
+      seed_seq(std::initializer_list<_IntType> __il);
 
     template<typename _InputIterator>
       seed_seq(_InputIterator __begin, _InputIterator __end);
diff --git a/libstdc++-v3/testsuite/17_intro/names.cc b/libstdc++-v3/testsuite/17_intro/names.cc
index dad7ba970aa..d758138dfb1 100644
--- a/libstdc++-v3/testsuite/17_intro/names.cc
+++ b/libstdc++-v3/testsuite/17_intro/names.cc
@@ -104,6 +104,11 @@
 #define uses_allocator  (
 #endif
 
+#if __cplusplus < 201402L
+// <complex> defines operator""il
+#define il  (
+#endif
+
 #if __cplusplus < 201703L
 // <charconv> defines to_chars_result::ptr and to_chars_result::ec
 #define ec (

commit 6c343f9378c8dcd4b5f9d2b93a9568c736d00404
Author: Alan Modra <amodra@gmail.com>
Date:   Thu Oct 1 19:14:09 2020 +0930

    [RS6000] ICE in decompose, at rtl.h:2282
    
    during RTL pass: fwprop1
    gcc.dg/pr82596.c: In function 'test_cststring':
    gcc.dg/pr82596.c:27:1: internal compiler error: in decompose, at rtl.h:2282
    
    -m32 gcc/testsuite/gcc.dg/pr82596.c fails along with other tests after
    applying rtx_cost patches, which exposed a backend bug.
    legitimize_address when presented with the following address
            (plus (reg) (const_int 0x7ffffffff))
    attempts to rewrite it as a high/low sum.  The low part is 0xffff, or
    -1, making the high part 0x80000000.  But this is no longer canonical
    for SImode.
    
            * config/rs6000/rs6000.c (rs6000_legitimize_address): Use
            gen_int_mode for high part of address constant.
    
    (cherry picked from commit 4c69e61f4307865b95151006e480ae2022b30454)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index aea362cdf6e..891c4c54e5f 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -8967,7 +8967,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
 	low_int = 0;
       high_int = INTVAL (XEXP (x, 1)) - low_int;
       sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
-					 GEN_INT (high_int)), 0);
+					 gen_int_mode (high_int, Pmode)), 0);
       return plus_constant (Pmode, sum, low_int);
     }
   else if (GET_CODE (x) == PLUS

commit 7f8115b305f1a1a2ddec4f59bc08a3415359dda6
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 30 12:00:20 2020 +0100

    PR target/96313 AArch64: vqmovun* return types should be unsigned
    
    In this PR we have the wrong return type for some intrinsics. It should
    be unsigned, but we implement it as signed.
    Fix this by adjusting the type qualifiers used when creating the
    builtins and fixing the type in the arm_neon.h intrinsic.
    With the adjustment in qualifiers we now don't need to cast the result
    when returning.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            PR target/96313
            * config/aarch64/aarch64-simd-builtins.def (sqmovun): Use UNOPUS
            qualifiers.
            * config/aarch64/arm_neon.h (vqmovun_s16): Adjust builtin call.
            Remove unnecessary result cast.
            (vqmovun_s32): Likewise.
            (vqmovun_s64): Likewise.
            (vqmovunh_s16): Likewise.  Fix return type.
            (vqmovuns_s32): Likewise.
            (vqmovund_s64): Likewise.
    
    gcc/testsuite/
            PR target/96313
            * gcc.target/aarch64/pr96313.c: New test.
            * gcc.target/aarch64/scalar_intrinsics.c (test_vqmovunh_s16):
            Adjust return type.
            (test_vqmovuns_s32): Likewise.
            (test_vqmovund_s64): Likewise.
    
    (cherry picked from commit 135b043196b5575c690ef1e07bcbb49bf037c3a2)
    (cherry picked from commit 7d177b142dcbe841124fe023cb592914d4200e57)
    (cherry picked from commit 18d980d94f8d7187ce30bf23ddd365fa54189c36)

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 8acfc083ce1..81382cc095f 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -155,7 +155,7 @@
   BUILTIN_VQN (TERNOP, raddhn2, 0)
   BUILTIN_VQN (TERNOP, rsubhn2, 0)
 
-  BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
+  BUILTIN_VSQN_HSDI (UNOPUS, sqmovun, 0)
   /* Implemented by aarch64_<sur>qmovn<mode>.  */
   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 4b50503c446..856b4e5e08c 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -24177,42 +24177,42 @@ __extension__ extern __inline uint8x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqmovun_s16 (int16x8_t __a)
 {
-  return (uint8x8_t) __builtin_aarch64_sqmovunv8hi (__a);
+  return __builtin_aarch64_sqmovunv8hi_us (__a);
 }
 
 __extension__ extern __inline uint16x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqmovun_s32 (int32x4_t __a)
 {
-  return (uint16x4_t) __builtin_aarch64_sqmovunv4si (__a);
+  return __builtin_aarch64_sqmovunv4si_us (__a);
 }
 
 __extension__ extern __inline uint32x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqmovun_s64 (int64x2_t __a)
 {
-  return (uint32x2_t) __builtin_aarch64_sqmovunv2di (__a);
+  return __builtin_aarch64_sqmovunv2di_us (__a);
 }
 
-__extension__ extern __inline int8_t
+__extension__ extern __inline uint8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqmovunh_s16 (int16_t __a)
 {
-  return (int8_t) __builtin_aarch64_sqmovunhi (__a);
+  return __builtin_aarch64_sqmovunhi_us (__a);
 }
 
-__extension__ extern __inline int16_t
+__extension__ extern __inline uint16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqmovuns_s32 (int32_t __a)
 {
-  return (int16_t) __builtin_aarch64_sqmovunsi (__a);
+  return __builtin_aarch64_sqmovunsi_us (__a);
 }
 
-__extension__ extern __inline int32_t
+__extension__ extern __inline uint32_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vqmovund_s64 (int64_t __a)
 {
-  return (int32_t) __builtin_aarch64_sqmovundi (__a);
+  return __builtin_aarch64_sqmovundi_us (__a);
 }
 
 /* vqneg */
diff --git a/gcc/testsuite/gcc.target/aarch64/pr96313.c b/gcc/testsuite/gcc.target/aarch64/pr96313.c
new file mode 100644
index 00000000000..0bf7604092f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr96313.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+#include <arm_neon.h>
+
+uint32_t (*fp3)(int64_t) = vqmovund_s64;
+uint8_t (*fp4)(int16_t) = vqmovunh_s16;
+uint16_t (*fp5)(int32_t) = vqmovuns_s32;
+
diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
index d943989768d..c2e13b651e9 100644
--- a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
+++ b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -661,7 +661,7 @@ test_vqnegs_s32 (int32_t a)
 
 /* { dg-final { scan-assembler-times "\\tsqxtun\\tb\[0-9\]+" 1 } } */
 
-int8_t
+uint8_t
 test_vqmovunh_s16 (int16_t a)
 {
   return vqmovunh_s16 (a);
@@ -669,7 +669,7 @@ test_vqmovunh_s16 (int16_t a)
 
 /* { dg-final { scan-assembler-times "\\tsqxtun\\th\[0-9\]+" 1 } } */
 
-int16_t
+uint16_t
 test_vqmovuns_s32 (int32_t a)
 {
   return vqmovuns_s32 (a);
@@ -677,7 +677,7 @@ test_vqmovuns_s32 (int32_t a)
 
 /* { dg-final { scan-assembler-times "\\tsqxtun\\ts\[0-9\]+" 1 } } */
 
-int32_t
+uint32_t
 test_vqmovund_s64 (int64_t a)
 {
   return vqmovund_s64 (a);

commit 311183d74e4f3fd5a37749cfbb0960e655e715fb
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 30 12:01:23 2020 +0100

    PR target/97150 AArch64: 2nd parameter of unsigned Neon scalar shift intrinsics should be signed
    
    In this PR the second argument to the intrinsics should be signed but we
    use an unsigned one erroneously.
    The corresponding builtins are already using the correct types so it's
    just a matter of correcting the signatures in arm_neon.h
    
    gcc/
            PR target/97150
            * config/aarch64/arm_neon.h (vqrshlb_u8): Make second argument
            signed.
            (vqrshlh_u16): Likewise.
            (vqrshls_u32): Likewise.
            (vqrshld_u64): Likewise.
            (vqshlb_u8): Likewise.
            (vqshlh_u16): Likewise.
            (vqshls_u32): Likewise.
            (vqshld_u64): Likewise.
            (vshld_u64): Likewise.
    
    gcc/testsuite/
            PR target/97150
            * gcc.target/aarch64/pr97150.c: New test.
    
    (cherry picked from commit 2d8fbebdb1eaca8de557ab3052535a8e4b8f8972)
    (cherry picked from commit 11af9c329ae528abb8c69ae8fae96a0f3fc6ed87)
    (cherry picked from commit d5c6ea22fe6db1ee19a178941a8c7f8ff5d0538c)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 856b4e5e08c..2741b67b8d4 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -24468,28 +24468,28 @@ vqrshld_s64 (int64_t __a, int64_t __b)
 
 __extension__ extern __inline uint8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vqrshlb_u8 (uint8_t __a, uint8_t __b)
+vqrshlb_u8 (uint8_t __a, int8_t __b)
 {
   return __builtin_aarch64_uqrshlqi_uus (__a, __b);
 }
 
 __extension__ extern __inline uint16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vqrshlh_u16 (uint16_t __a, uint16_t __b)
+vqrshlh_u16 (uint16_t __a, int16_t __b)
 {
   return __builtin_aarch64_uqrshlhi_uus (__a, __b);
 }
 
 __extension__ extern __inline uint32_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vqrshls_u32 (uint32_t __a, uint32_t __b)
+vqrshls_u32 (uint32_t __a, int32_t __b)
 {
   return __builtin_aarch64_uqrshlsi_uus (__a, __b);
 }
 
 __extension__ extern __inline uint64_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vqrshld_u64 (uint64_t __a, uint64_t __b)
+vqrshld_u64 (uint64_t __a, int64_t __b)
 {
   return __builtin_aarch64_uqrshldi_uus (__a, __b);
 }
@@ -24768,28 +24768,28 @@ vqshld_s64 (int64_t __a, int64_t __b)
 
 __extension__ extern __inline uint8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vqshlb_u8 (uint8_t __a, uint8_t __b)
+vqshlb_u8 (uint8_t __a, int8_t __b)
 {
   return __builtin_aarch64_uqshlqi_uus (__a, __b);
 }
 
 __extension__ extern __inline uint16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vqshlh_u16 (uint16_t __a, uint16_t __b)
+vqshlh_u16 (uint16_t __a, int16_t __b)
 {
   return __builtin_aarch64_uqshlhi_uus (__a, __b);
 }
 
 __extension__ extern __inline uint32_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vqshls_u32 (uint32_t __a, uint32_t __b)
+vqshls_u32 (uint32_t __a, int32_t __b)
 {
   return __builtin_aarch64_uqshlsi_uus (__a, __b);
 }
 
 __extension__ extern __inline uint64_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vqshld_u64 (uint64_t __a, uint64_t __b)
+vqshld_u64 (uint64_t __a, int64_t __b)
 {
   return __builtin_aarch64_uqshldi_uus (__a, __b);
 }
@@ -27127,7 +27127,7 @@ vshld_s64 (int64_t __a, int64_t __b)
 
 __extension__ extern __inline uint64_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vshld_u64 (uint64_t __a, uint64_t __b)
+vshld_u64 (uint64_t __a, int64_t __b)
 {
   return __builtin_aarch64_ushldi_uus (__a, __b);
 }
diff --git a/gcc/testsuite/gcc.target/aarch64/pr97150.c b/gcc/testsuite/gcc.target/aarch64/pr97150.c
new file mode 100644
index 00000000000..7abdd8cf347
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr97150.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+
+#include <arm_neon.h>
+
+uint8_t  (*fp0)(uint8_t, int8_t)   = vqshlb_u8;
+uint16_t (*fp1)(uint16_t, int16_t) = vqshlh_u16;
+uint32_t (*fp2)(uint32_t, int32_t) = vqshls_u32;
+uint64_t (*fp3)(uint64_t, int64_t) = vqshld_u64;
+uint8_t  (*fp4)(uint8_t, int8_t)   = vqrshlb_u8;
+uint16_t (*fp5)(uint16_t, int16_t) = vqrshlh_u16;
+uint32_t (*fp6)(uint32_t, int32_t) = vqrshls_u32;
+uint64_t (*fp7)(uint64_t, int64_t) = vqrshld_u64;
+uint64_t (*fp8)(uint64_t, int64_t) = vshld_u64;
+

commit 03a38ad58202b465f90e1795ba8f52100c3dc4f4
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Oct 9 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d0ed9184227..faef3adaada 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,44 @@
+2020-10-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-10-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/97150
+	* config/aarch64/arm_neon.h (vqrshlb_u8): Make second argument
+	signed.
+	(vqrshlh_u16): Likewise.
+	(vqrshls_u32): Likewise.
+	(vqrshld_u64): Likewise.
+	(vqshlb_u8): Likewise.
+	(vqshlh_u16): Likewise.
+	(vqshls_u32): Likewise.
+	(vqshld_u64): Likewise.
+	(vshld_u64): Likewise.
+
+2020-10-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-10-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/96313
+	* config/aarch64/aarch64-simd-builtins.def (sqmovun): Use UNOPUS
+	qualifiers.
+	* config/aarch64/arm_neon.h (vqmovun_s16): Adjust builtin call.
+	Remove unnecessary result cast.
+	(vqmovun_s32): Likewise.
+	(vqmovun_s64): Likewise.
+	(vqmovunh_s16): Likewise.  Fix return type.
+	(vqmovuns_s32): Likewise.
+	(vqmovund_s64): Likewise.
+
+2020-10-08  Alan Modra  <amodra@gmail.com>
+
+	Backported from master:
+	2020-10-01  Alan Modra  <amodra@gmail.com>
+
+	* config/rs6000/rs6000.c (rs6000_legitimize_address): Use
+	gen_int_mode for high part of address constant.
+
 2020-10-06  Alex Coplan  <alex.coplan@arm.com>
 
 	* config/arm/driver-arm.c (arm_cpu_table): Add neoverse-v1.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index df504552863..96085704552 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201008
+20201009
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e6a2cc50f8c..0d5a5215c8a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,23 @@
+2020-10-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-10-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/97150
+	* gcc.target/aarch64/pr97150.c: New test.
+
+2020-10-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-10-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/96313
+	* gcc.target/aarch64/pr96313.c: New test.
+	* gcc.target/aarch64/scalar_intrinsics.c (test_vqmovunh_s16):
+	Adjust return type.
+	(test_vqmovuns_s32): Likewise.
+	(test_vqmovund_s64): Likewise.
+
 2020-09-30  H.J. Lu  <hjl.tools@gmail.com>
 
 	Backported from master:
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 69f60a3ba85..3f7d2447afa 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,12 @@
+2020-10-08  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-10-07  Jonathan Wakely  <jwakely@redhat.com>
+
+	* include/bits/random.h (seed_seq(initializer_list<T>)): Rename
+	parameter to use reserved name.
+	* testsuite/17_intro/names.cc: Check "il".
+
 2020-09-22  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit 80218a1eb56bcfa7b338279ff8d677c2f8de6ecf
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Oct 10 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 96085704552..bca154ae9f3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201009
+20201010

commit 0657793704fb4e7c4fae4fdc445479b6f0cee564
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Oct 11 00:17:37 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index bca154ae9f3..d02c1f74829 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201010
+20201011

commit 8897e14141c46f3f740e898417f8b777b8ad4b09
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Oct 12 00:17:37 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d02c1f74829..02373369eab 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201011
+20201012

commit a0bc59d3b78d23b117840b05baefe14abcf0564a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Oct 13 00:17:41 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 02373369eab..4d019bc9672 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201012
+20201013

commit 5d3052a4755173f447cfcffa361086562033c8be
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Fri Oct 9 10:34:15 2020 +0100

    PR target/97349 AArch64: Incorrect types for some Neon vdupq_n_<...> intrinsics
    
    This patch fixes the PR by adjusting the input types of the intrinsic
    prototypes to the ones mandated by ACLE
    Turns out the tests in the testsuite were already using the correct
    ones, but implicit conversions hid the bug...
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            PR target/97349
            * config/aarch64/arm_neon.h (vdupq_n_p8, vdupq_n_p16,
            vdupq_n_p64, vdupq_n_s8, vdupq_n_s16, vdupq_n_u8, vdupq_n_u16):
            Fix argument type.
    
    gcc/testsuite/
            PR target/97349
            * gcc.target/aarch64/simd/pr97349.c: New test.
    
    (cherry picked from commit 8a3da2e6060ff0f61dae6aaada716e2c67f3d54f)
    (cherry picked from commit b9c1ca3e2fc84b40dc2ab70d12064e3d0eb8abdd)

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 2741b67b8d4..0216e583f0c 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -15746,7 +15746,7 @@ vdupq_n_f64 (float64_t __a)
 
 __extension__ extern __inline poly8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vdupq_n_p8 (uint32_t __a)
+vdupq_n_p8 (poly8_t __a)
 {
   return (poly8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
 		       __a, __a, __a, __a, __a, __a, __a, __a};
@@ -15754,21 +15754,21 @@ vdupq_n_p8 (uint32_t __a)
 
 __extension__ extern __inline poly16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vdupq_n_p16 (uint32_t __a)
+vdupq_n_p16 (poly16_t __a)
 {
   return (poly16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
 }
 
 __extension__ extern __inline poly64x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vdupq_n_p64 (uint64_t __a)
+vdupq_n_p64 (poly64_t __a)
 {
   return (poly64x2_t) {__a, __a};
 }
 
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vdupq_n_s8 (int32_t __a)
+vdupq_n_s8 (int8_t __a)
 {
   return (int8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
 		      __a, __a, __a, __a, __a, __a, __a, __a};
@@ -15776,7 +15776,7 @@ vdupq_n_s8 (int32_t __a)
 
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vdupq_n_s16 (int32_t __a)
+vdupq_n_s16 (int16_t __a)
 {
   return (int16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
 }
@@ -15797,7 +15797,7 @@ vdupq_n_s64 (int64_t __a)
 
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vdupq_n_u8 (uint32_t __a)
+vdupq_n_u8 (uint8_t __a)
 {
   return (uint8x16_t) {__a, __a, __a, __a, __a, __a, __a, __a,
 		       __a, __a, __a, __a, __a, __a, __a, __a};
@@ -15805,7 +15805,7 @@ vdupq_n_u8 (uint32_t __a)
 
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vdupq_n_u16 (uint32_t __a)
+vdupq_n_u16 (uint16_t __a)
 {
   return (uint16x8_t) {__a, __a, __a, __a, __a, __a, __a, __a};
 }
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr97349.c b/gcc/testsuite/gcc.target/aarch64/simd/pr97349.c
new file mode 100644
index 00000000000..026767a7243
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/pr97349.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+
+#include <arm_neon.h>
+
+poly16x8_t  (*fp0)(poly16_t) = vdupq_n_p16;
+poly64x2_t  (*fp1)(poly64_t) = vdupq_n_p64;
+poly8x16_t  (*fp2)(poly8_t)  = vdupq_n_p8;
+int16x8_t   (*fp3)(int16_t)  = vdupq_n_s16;
+int8x16_t   (*fp4)(int8_t)   = vdupq_n_s8;
+uint16x8_t  (*fp5)(uint16_t) = vdupq_n_u16;
+uint8x16_t  (*fp6)(uint8_t)  = vdupq_n_u8;
+

commit 66982057a960665229e053e1a72ca2bf47c25fab
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu Oct 8 15:20:23 2020 +0100

    AArch64: Add Neoverse N2 tuning model
    
    This is the GCC 8 patch for the Neoverse N2 tuning struct.
    It sets the AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC tune flag as well.
    
    Bootstrapped and tested on the branch.
    
    gcc/
            * config/aarch64/aarch64.c (neoversen2_tunings): Define.
            * config/aarch64/aarch64-cores.def (neoverse-n2): Use it.

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 29727fabc2a..dfb839c01cc 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -101,7 +101,7 @@ AARCH64_CORE("zeus", zeus, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL
 AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_SVE | AARCH64_FL_RNG, neoversev1, 0x41, 0xd40, -1)
 
 /* Armv8.5-A Architecture Processors.  */
-AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_RNG, cortexa72, 0x41, 0xd49, -1)
+AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_RNG, neoversen2, 0x41, 0xd49, -1)
 
 /* ARMv8-A big.LITTLE implementations.  */
 
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 3d218b6b951..72c11e35659 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -786,6 +786,32 @@ static const struct tune_params neoversev1_tunings =
   &generic_prefetch_tune
 };
 
+static const struct tune_params neoversen2_tunings =
+{
+  &cortexa57_extra_costs,
+  &generic_addrcost_table,
+  &cortexa57_regmove_cost,
+  &cortexa57_vector_cost,
+  &generic_branch_cost,
+  &generic_approx_modes,
+  4, /* memmov_cost  */
+  3, /* issue_rate  */
+  (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+   | AARCH64_FUSE_MOVK_MOVK), /* fusible_ops  */
+  16,	/* function_align.  */
+  4,	/* jump_align.  */
+  8,	/* loop_align.  */
+  2,	/* int_reassoc_width.  */
+  4,	/* fp_reassoc_width.  */
+  1,	/* vec_reassoc_width.  */
+  2,	/* min_div_recip_mul_sf.  */
+  2,	/* min_div_recip_mul_df.  */
+  0,	/* max_case_values.  */
+  tune_params::AUTOPREFETCHER_WEAK,	/* autoprefetcher_model.  */
+  (AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC),	/* tune_flags.  */
+  &generic_prefetch_tune
+};
+
 static const struct tune_params cortexa73_tunings =
 {
   &cortexa57_extra_costs,

commit 29da194a4575d91d27307c5899dac3e4ab91a18d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Oct 14 00:17:37 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index faef3adaada..78a2a2c895b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2020-10-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.c (neoversen2_tunings): Define.
+	* config/aarch64/aarch64-cores.def (neoverse-n2): Use it.
+
+2020-10-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-10-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/97349
+	* config/aarch64/arm_neon.h (vdupq_n_p8, vdupq_n_p16,
+	vdupq_n_p64, vdupq_n_s8, vdupq_n_s16, vdupq_n_u8, vdupq_n_u16):
+	Fix argument type.
+
 2020-10-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4d019bc9672..7516298d9d2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201013
+20201014
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0d5a5215c8a..94527525fe9 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-10-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2020-10-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/97349
+	* gcc.target/aarch64/simd/pr97349.c: New test.
+
 2020-10-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	Backported from master:

commit 5ea7a0ab434fd362cf3da56e2b78b61ed8e9799e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Oct 15 00:17:49 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7516298d9d2..630766919da 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201014
+20201015

commit 8af9b4e047f8c7254a10f0b23665ea3c4618bfd7
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Oct 16 00:17:44 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 630766919da..90be3bdbe8f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201015
+20201016

commit 4afba91a3186ab35e66cfabd47d06bca4183b98f
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Oct 17 00:17:46 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 90be3bdbe8f..b5f8af25539 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201016
+20201017

commit 34558681b17282a45d17671a6ea848306bc35728
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Oct 18 00:17:34 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b5f8af25539..49cebdf4a94 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201017
+20201018

commit 541b5595460d493f70bc02e9d8679f961f6749ec
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Oct 19 00:17:39 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 49cebdf4a94..d408c72ce93 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201018
+20201019

commit d64cc79d94dcd83032a500cae69cfcf50d2dce47
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Oct 20 00:17:42 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d408c72ce93..90bac5173df 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201019
+20201020

commit 59e503c1f450d1a55497c6dedf307713f38eea2f
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Oct 21 00:17:47 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 90bac5173df..8a26653d7f8 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201020
+20201021

commit 5c5e23cd5cadc92033aeafd5a1c64011ab0302ce
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Oct 22 08:29:49 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 8a26653d7f8..d3ccbf5b38e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201021
+20201022

commit 2819cdd8ff8e15ed5efb4095143cf531cf3e50f9
Author: Andreas Krebbel <krebbel@linux.ibm.com>
Date:   Thu Oct 22 12:24:22 2020 +0200

    Fix PR97439
    
    decimal_real_maxval misses to set the sign flag in the REAL_VALUE_TYPE.
    
    gcc/ChangeLog:
    
            PR rtl-optimization/97439
            * dfp.c (decimal_real_maxval): Set the sign flag in the
            generated number.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.dg/dfp/pr97439.c: New test.
    
    (cherry picked from commit e3f25eac67aee77af0b2038cd4d6cbd36d7f1030)

diff --git a/gcc/dfp.c b/gcc/dfp.c
index 26efdc51901..ee47c30b1f5 100644
--- a/gcc/dfp.c
+++ b/gcc/dfp.c
@@ -740,4 +740,6 @@ decimal_real_maxval (REAL_VALUE_TYPE *r, int sign, machine_mode mode)
   decimal_real_from_string (r, max);
   if (sign)
     decimal128SetSign ((decimal128 *) r->sig, 1);
+
+  r->sign = sign;
 }
diff --git a/gcc/testsuite/gcc.dg/dfp/pr97439.c b/gcc/testsuite/gcc.dg/dfp/pr97439.c
new file mode 100644
index 00000000000..7fcf834043c
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/dfp/pr97439.c
@@ -0,0 +1,27 @@
+// { dg-do run }
+// { dg-options "-O1" }
+
+static int
+foo(_Decimal128 x, _Decimal128 y)
+{
+  if (x > y)
+    return 1;
+
+  return 0;
+}
+
+int __attribute__((noinline))
+bar(_Decimal128 x)
+{
+  return foo (x, -1.0DL * __builtin_infd32());
+}
+
+int
+main (void)
+{
+  int res = bar (0.0DL);
+  if (res != 1)
+    __builtin_abort ();
+
+  return 0;
+}

commit fe7e1f2340efbdffd85366a7e0c622333816d41b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Oct 23 00:17:49 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 78a2a2c895b..49158b622ba 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2020-10-22  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	Backported from master:
+	2020-10-22  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	PR rtl-optimization/97439
+	* dfp.c (decimal_real_maxval): Set the sign flag in the
+	generated number.
+
 2020-10-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* config/aarch64/aarch64.c (neoversen2_tunings): Define.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d3ccbf5b38e..b3873063e3e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201022
+20201023
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 94527525fe9..d74fcf166cb 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-10-22  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	Backported from master:
+	2020-10-22  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+	* gcc.dg/dfp/pr97439.c: New test.
+
 2020-10-13  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	Backported from master:

commit 10f9a44f74fa7e1597fc2d9a5edf5592ec957d52
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Oct 24 00:17:43 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b3873063e3e..b858c4c782c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201023
+20201024

commit 98931867e61552f76af90eb5337a28ccedbd604b
Author: Harald Anlauf <anlauf@gmx.de>
Date:   Sun Oct 18 20:15:26 2020 +0200

    PR libfortran/97063 - Wrong result for vector (step size is negative) * matrix
    
    The MATMUL intrinsic provided a wrong result for rank-1 times rank-2 array
    when a negative stride was used for addressing the elements of the rank-1
    array, because a check on strides was erroneously placed before the check
    on the rank.  Interchange order of checks.
    
    libgfortran/ChangeLog:
    
            * m4/matmul_internal.m4: Move check for rank-1 times rank-2 before
            checks on strides for rank-2 times rank-2.
            * generated/matmul_c10.c: Regenerated.
            * generated/matmul_c16.c: Likewise.
            * generated/matmul_c4.c: Likewise.
            * generated/matmul_c8.c: Likewise.
            * generated/matmul_i1.c: Likewise.
            * generated/matmul_i16.c: Likewise.
            * generated/matmul_i2.c: Likewise.
            * generated/matmul_i4.c: Likewise.
            * generated/matmul_i8.c: Likewise.
            * generated/matmul_r10.c: Likewise.
            * generated/matmul_r16.c: Likewise.
            * generated/matmul_r4.c: Likewise.
            * generated/matmul_r8.c: Likewise.
            * generated/matmulavx128_c10.c: Likewise.
            * generated/matmulavx128_c16.c: Likewise.
            * generated/matmulavx128_c4.c: Likewise.
            * generated/matmulavx128_c8.c: Likewise.
            * generated/matmulavx128_i1.c: Likewise.
            * generated/matmulavx128_i16.c: Likewise.
            * generated/matmulavx128_i2.c: Likewise.
            * generated/matmulavx128_i4.c: Likewise.
            * generated/matmulavx128_i8.c: Likewise.
            * generated/matmulavx128_r10.c: Likewise.
            * generated/matmulavx128_r16.c: Likewise.
            * generated/matmulavx128_r4.c: Likewise.
            * generated/matmulavx128_r8.c: Likewise.
    
    gcc/testsuite/ChangeLog:
    
            * gfortran.dg/matmul_20.f90: New test.
    
    (cherry picked from commit cd6cd6aed195b4ec7d652e8b41d60b60e174304e)

diff --git a/gcc/testsuite/gfortran.dg/matmul_20.f90 b/gcc/testsuite/gfortran.dg/matmul_20.f90
new file mode 100644
index 00000000000..7a211a4974d
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/matmul_20.f90
@@ -0,0 +1,47 @@
+! { dg-do run }
+! PR97063 - Wrong result for vector (step size is negative) * matrix
+
+program p
+  implicit none
+  integer, parameter :: m = 3, k = 2*m, l = k-1, n = 4
+  integer :: i, j,  m1, m2, ms
+  integer :: ai(k), bi(k,n), ci(n), ci_ref(n), c1, c2
+  real    :: ar(k), br(k,n), cr(n), cr_ref(n)
+
+  ai(:)   = [(i,i=0,k-1)]
+  bi(:,:) = reshape ([(((5*i+j),i=0,k-1),j=0,n-1)],[k,n])
+
+  ! Parameters of subscript triplet
+  m1 = 1; m2 = l; ms =  2
+
+  ! Reference values for cross-checks: integer variant
+  c1 = dot_product (ai(m1:m2: ms), bi(m1:m2: ms,1))
+  c2 = dot_product (ai(m1:m2: ms), bi(m1:m2: ms,2))
+  ci_ref = matmul  (ai(m1:m2: ms), bi(m1:m2: ms,:))
+  ci     = matmul  (ai(m2:m1:-ms), bi(m2:m1:-ms,:))
+
+  if (ci_ref(1) /= c1 .or. ci_ref(2) /= c2) stop 1
+  if (any (ci   /= ci_ref)) stop 2
+
+  ! Real variant
+  ar = real (ai)
+  br = real (bi)
+  cr_ref = matmul  (ar(m1:m2: ms), br(m1:m2: ms,:))
+  cr     = matmul  (ar(m2:m1:-ms), br(m2:m1:-ms,:))
+
+  if (any (cr_ref /= real (ci_ref))) stop 3
+  if (any (cr     /=       cr_ref )) stop 4
+
+  ! Mixed variants
+  cr_ref = matmul  (ar(m1:m2: ms), bi(m1:m2: ms,:))
+  cr     = matmul  (ar(m2:m1:-ms), bi(m2:m1:-ms,:))
+
+  if (any (cr_ref /= real (ci_ref))) stop 5
+  if (any (cr     /=       cr_ref )) stop 6
+
+  cr_ref = matmul  (ai(m1:m2: ms), br(m1:m2: ms,:))
+  cr     = matmul  (ai(m2:m1:-ms), br(m2:m1:-ms,:))
+
+  if (any (cr_ref /= real (ci_ref))) stop 7
+  if (any (cr     /=       cr_ref )) stop 8
+end program
diff --git a/libgfortran/generated/matmul_c10.c b/libgfortran/generated/matmul_c10.c
index 462d71e23f5..3db1d37a9c7 100644
--- a/libgfortran/generated/matmul_c10.c
+++ b/libgfortran/generated/matmul_c10.c
@@ -579,20 +579,6 @@ matmul_c10_avx (gfc_array_c10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_10 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_c10_avx (gfc_array_c10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_10 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_c10_avx2 (gfc_array_c10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_10 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_c10_avx2 (gfc_array_c10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_10 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_c10_avx512f (gfc_array_c10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_10 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_c10_avx512f (gfc_array_c10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_10 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_c10_vanilla (gfc_array_c10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_10 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_c10_vanilla (gfc_array_c10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_10 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_c10 (gfc_array_c10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_10 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_c10 (gfc_array_c10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_10 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_c16.c b/libgfortran/generated/matmul_c16.c
index 2062739ce1f..16637b86bd3 100644
--- a/libgfortran/generated/matmul_c16.c
+++ b/libgfortran/generated/matmul_c16.c
@@ -579,20 +579,6 @@ matmul_c16_avx (gfc_array_c16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_16 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_c16_avx (gfc_array_c16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_16 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_c16_avx2 (gfc_array_c16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_16 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_c16_avx2 (gfc_array_c16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_16 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_c16_avx512f (gfc_array_c16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_16 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_c16_avx512f (gfc_array_c16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_16 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_c16_vanilla (gfc_array_c16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_16 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_c16_vanilla (gfc_array_c16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_16 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_c16 (gfc_array_c16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_16 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_c16 (gfc_array_c16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_16 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_c4.c b/libgfortran/generated/matmul_c4.c
index 91d193dca37..40a8c9ac87c 100644
--- a/libgfortran/generated/matmul_c4.c
+++ b/libgfortran/generated/matmul_c4.c
@@ -579,20 +579,6 @@ matmul_c4_avx (gfc_array_c4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_4 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_c4_avx (gfc_array_c4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_4 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_c4_avx2 (gfc_array_c4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_4 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_c4_avx2 (gfc_array_c4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_4 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_c4_avx512f (gfc_array_c4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_4 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_c4_avx512f (gfc_array_c4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_4 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_c4_vanilla (gfc_array_c4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_4 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_c4_vanilla (gfc_array_c4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_4 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_c4 (gfc_array_c4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_4 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_c4 (gfc_array_c4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_4 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_c8.c b/libgfortran/generated/matmul_c8.c
index 425af85d1bb..75c0479f8ed 100644
--- a/libgfortran/generated/matmul_c8.c
+++ b/libgfortran/generated/matmul_c8.c
@@ -579,20 +579,6 @@ matmul_c8_avx (gfc_array_c8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_8 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_c8_avx (gfc_array_c8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_8 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_c8_avx2 (gfc_array_c8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_8 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_c8_avx2 (gfc_array_c8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_8 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_c8_avx512f (gfc_array_c8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_8 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_c8_avx512f (gfc_array_c8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_8 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_c8_vanilla (gfc_array_c8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_8 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_c8_vanilla (gfc_array_c8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_8 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_c8 (gfc_array_c8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_8 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_c8 (gfc_array_c8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_8 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_i1.c b/libgfortran/generated/matmul_i1.c
index 0c9335d4322..2550c564041 100644
--- a/libgfortran/generated/matmul_i1.c
+++ b/libgfortran/generated/matmul_i1.c
@@ -579,20 +579,6 @@ matmul_i1_avx (gfc_array_i1 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_1 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_i1_avx (gfc_array_i1 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_1 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_i1_avx2 (gfc_array_i1 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_1 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_i1_avx2 (gfc_array_i1 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_1 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_i1_avx512f (gfc_array_i1 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_1 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_i1_avx512f (gfc_array_i1 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_1 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_i1_vanilla (gfc_array_i1 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_1 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_i1_vanilla (gfc_array_i1 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_1 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_i1 (gfc_array_i1 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_1 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_i1 (gfc_array_i1 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_1 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_i16.c b/libgfortran/generated/matmul_i16.c
index b9334b3278f..907aa28c381 100644
--- a/libgfortran/generated/matmul_i16.c
+++ b/libgfortran/generated/matmul_i16.c
@@ -579,20 +579,6 @@ matmul_i16_avx (gfc_array_i16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_16 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_i16_avx (gfc_array_i16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_16 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_i16_avx2 (gfc_array_i16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_16 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_i16_avx2 (gfc_array_i16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_16 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_i16_avx512f (gfc_array_i16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_16 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_i16_avx512f (gfc_array_i16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_16 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_i16_vanilla (gfc_array_i16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_16 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_i16_vanilla (gfc_array_i16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_16 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_i16 (gfc_array_i16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_16 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_i16 (gfc_array_i16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_16 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_i2.c b/libgfortran/generated/matmul_i2.c
index e4246e948df..f0a33ce60cf 100644
--- a/libgfortran/generated/matmul_i2.c
+++ b/libgfortran/generated/matmul_i2.c
@@ -579,20 +579,6 @@ matmul_i2_avx (gfc_array_i2 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_2 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_i2_avx (gfc_array_i2 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_2 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_i2_avx2 (gfc_array_i2 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_2 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_i2_avx2 (gfc_array_i2 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_2 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_i2_avx512f (gfc_array_i2 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_2 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_i2_avx512f (gfc_array_i2 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_2 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_i2_vanilla (gfc_array_i2 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_2 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_i2_vanilla (gfc_array_i2 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_2 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_i2 (gfc_array_i2 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_2 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_i2 (gfc_array_i2 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_2 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_i4.c b/libgfortran/generated/matmul_i4.c
index 78cf27c4fcd..b69d112db76 100644
--- a/libgfortran/generated/matmul_i4.c
+++ b/libgfortran/generated/matmul_i4.c
@@ -579,20 +579,6 @@ matmul_i4_avx (gfc_array_i4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_4 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_i4_avx (gfc_array_i4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_4 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_i4_avx2 (gfc_array_i4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_4 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_i4_avx2 (gfc_array_i4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_4 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_i4_avx512f (gfc_array_i4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_4 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_i4_avx512f (gfc_array_i4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_4 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_i4_vanilla (gfc_array_i4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_4 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_i4_vanilla (gfc_array_i4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_4 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_i4 (gfc_array_i4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_4 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_i4 (gfc_array_i4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_4 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_i8.c b/libgfortran/generated/matmul_i8.c
index cf8c401400d..3801561e02d 100644
--- a/libgfortran/generated/matmul_i8.c
+++ b/libgfortran/generated/matmul_i8.c
@@ -579,20 +579,6 @@ matmul_i8_avx (gfc_array_i8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_8 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_i8_avx (gfc_array_i8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_8 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_i8_avx2 (gfc_array_i8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_8 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_i8_avx2 (gfc_array_i8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_8 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_i8_avx512f (gfc_array_i8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_8 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_i8_avx512f (gfc_array_i8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_8 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_i8_vanilla (gfc_array_i8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_8 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_i8_vanilla (gfc_array_i8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_8 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_i8 (gfc_array_i8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_8 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_i8 (gfc_array_i8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_8 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_r10.c b/libgfortran/generated/matmul_r10.c
index e4309c80a6b..60740edde62 100644
--- a/libgfortran/generated/matmul_r10.c
+++ b/libgfortran/generated/matmul_r10.c
@@ -579,20 +579,6 @@ matmul_r10_avx (gfc_array_r10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_10 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_r10_avx (gfc_array_r10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_10 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_r10_avx2 (gfc_array_r10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_10 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_r10_avx2 (gfc_array_r10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_10 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_r10_avx512f (gfc_array_r10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_10 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_r10_avx512f (gfc_array_r10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_10 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_r10_vanilla (gfc_array_r10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_10 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_r10_vanilla (gfc_array_r10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_10 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_r10 (gfc_array_r10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_10 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_r10 (gfc_array_r10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_10 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_r16.c b/libgfortran/generated/matmul_r16.c
index 1ab554660d7..df199fb31cf 100644
--- a/libgfortran/generated/matmul_r16.c
+++ b/libgfortran/generated/matmul_r16.c
@@ -579,20 +579,6 @@ matmul_r16_avx (gfc_array_r16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_16 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_r16_avx (gfc_array_r16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_16 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_r16_avx2 (gfc_array_r16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_16 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_r16_avx2 (gfc_array_r16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_16 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_r16_avx512f (gfc_array_r16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_16 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_r16_avx512f (gfc_array_r16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_16 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_r16_vanilla (gfc_array_r16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_16 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_r16_vanilla (gfc_array_r16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_16 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_r16 (gfc_array_r16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_16 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_r16 (gfc_array_r16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_16 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_r4.c b/libgfortran/generated/matmul_r4.c
index 97dba9825b1..6aa156f525d 100644
--- a/libgfortran/generated/matmul_r4.c
+++ b/libgfortran/generated/matmul_r4.c
@@ -579,20 +579,6 @@ matmul_r4_avx (gfc_array_r4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_4 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_r4_avx (gfc_array_r4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_4 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_r4_avx2 (gfc_array_r4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_4 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_r4_avx2 (gfc_array_r4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_4 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_r4_avx512f (gfc_array_r4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_4 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_r4_avx512f (gfc_array_r4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_4 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_r4_vanilla (gfc_array_r4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_4 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_r4_vanilla (gfc_array_r4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_4 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_r4 (gfc_array_r4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_4 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_r4 (gfc_array_r4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_4 *restrict abase_x;
diff --git a/libgfortran/generated/matmul_r8.c b/libgfortran/generated/matmul_r8.c
index 5e4c9500260..03928c4cee9 100644
--- a/libgfortran/generated/matmul_r8.c
+++ b/libgfortran/generated/matmul_r8.c
@@ -579,20 +579,6 @@ matmul_r8_avx (gfc_array_r8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_8 *restrict bbase_y;
@@ -607,6 +593,20 @@ matmul_r8_avx (gfc_array_r8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_8 *restrict abase_x;
@@ -1136,20 +1136,6 @@ matmul_r8_avx2 (gfc_array_r8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_8 *restrict bbase_y;
@@ -1164,6 +1150,20 @@ matmul_r8_avx2 (gfc_array_r8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_8 *restrict abase_x;
@@ -1693,20 +1693,6 @@ matmul_r8_avx512f (gfc_array_r8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_8 *restrict bbase_y;
@@ -1721,6 +1707,20 @@ matmul_r8_avx512f (gfc_array_r8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_8 *restrict abase_x;
@@ -2264,20 +2264,6 @@ matmul_r8_vanilla (gfc_array_r8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_8 *restrict bbase_y;
@@ -2292,6 +2278,20 @@ matmul_r8_vanilla (gfc_array_r8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_8 *restrict abase_x;
@@ -2895,20 +2895,6 @@ matmul_r8 (gfc_array_r8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_8 *restrict bbase_y;
@@ -2923,6 +2909,20 @@ matmul_r8 (gfc_array_r8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_8 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_c10.c b/libgfortran/generated/matmulavx128_c10.c
index 5cb0f6ad6f3..9c11629f234 100644
--- a/libgfortran/generated/matmulavx128_c10.c
+++ b/libgfortran/generated/matmulavx128_c10.c
@@ -544,20 +544,6 @@ matmul_c10_avx128_fma3 (gfc_array_c10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_10 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_c10_avx128_fma3 (gfc_array_c10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_10 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_c10_avx128_fma4 (gfc_array_c10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_10 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_c10_avx128_fma4 (gfc_array_c10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_10 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_c16.c b/libgfortran/generated/matmulavx128_c16.c
index 66272fefaf9..5a3f3f52bf1 100644
--- a/libgfortran/generated/matmulavx128_c16.c
+++ b/libgfortran/generated/matmulavx128_c16.c
@@ -544,20 +544,6 @@ matmul_c16_avx128_fma3 (gfc_array_c16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_16 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_c16_avx128_fma3 (gfc_array_c16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_16 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_c16_avx128_fma4 (gfc_array_c16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_16 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_c16_avx128_fma4 (gfc_array_c16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_16 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_c4.c b/libgfortran/generated/matmulavx128_c4.c
index f6e06e2e88f..c12bae3fafe 100644
--- a/libgfortran/generated/matmulavx128_c4.c
+++ b/libgfortran/generated/matmulavx128_c4.c
@@ -544,20 +544,6 @@ matmul_c4_avx128_fma3 (gfc_array_c4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_4 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_c4_avx128_fma3 (gfc_array_c4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_4 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_c4_avx128_fma4 (gfc_array_c4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_4 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_c4_avx128_fma4 (gfc_array_c4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_4 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_c8.c b/libgfortran/generated/matmulavx128_c8.c
index accc69c4d1a..b011ca12b2a 100644
--- a/libgfortran/generated/matmulavx128_c8.c
+++ b/libgfortran/generated/matmulavx128_c8.c
@@ -544,20 +544,6 @@ matmul_c8_avx128_fma3 (gfc_array_c8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_8 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_c8_avx128_fma3 (gfc_array_c8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_8 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_c8_avx128_fma4 (gfc_array_c8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_COMPLEX_8 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_c8_avx128_fma4 (gfc_array_c8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_COMPLEX_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_COMPLEX_8 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_i1.c b/libgfortran/generated/matmulavx128_i1.c
index 48b15c8074a..025bf06b371 100644
--- a/libgfortran/generated/matmulavx128_i1.c
+++ b/libgfortran/generated/matmulavx128_i1.c
@@ -544,20 +544,6 @@ matmul_i1_avx128_fma3 (gfc_array_i1 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_1 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_i1_avx128_fma3 (gfc_array_i1 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_1 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_i1_avx128_fma4 (gfc_array_i1 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_1 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_i1_avx128_fma4 (gfc_array_i1 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_1)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_1 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_i16.c b/libgfortran/generated/matmulavx128_i16.c
index 319321eca49..9452245fab1 100644
--- a/libgfortran/generated/matmulavx128_i16.c
+++ b/libgfortran/generated/matmulavx128_i16.c
@@ -544,20 +544,6 @@ matmul_i16_avx128_fma3 (gfc_array_i16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_16 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_i16_avx128_fma3 (gfc_array_i16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_16 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_i16_avx128_fma4 (gfc_array_i16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_16 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_i16_avx128_fma4 (gfc_array_i16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_16 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_i2.c b/libgfortran/generated/matmulavx128_i2.c
index 4d8945b10a2..60929bc654a 100644
--- a/libgfortran/generated/matmulavx128_i2.c
+++ b/libgfortran/generated/matmulavx128_i2.c
@@ -544,20 +544,6 @@ matmul_i2_avx128_fma3 (gfc_array_i2 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_2 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_i2_avx128_fma3 (gfc_array_i2 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_2 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_i2_avx128_fma4 (gfc_array_i2 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_2 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_i2_avx128_fma4 (gfc_array_i2 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_2)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_2 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_i4.c b/libgfortran/generated/matmulavx128_i4.c
index acaa00a30bb..7e6dfcff2bc 100644
--- a/libgfortran/generated/matmulavx128_i4.c
+++ b/libgfortran/generated/matmulavx128_i4.c
@@ -544,20 +544,6 @@ matmul_i4_avx128_fma3 (gfc_array_i4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_4 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_i4_avx128_fma3 (gfc_array_i4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_4 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_i4_avx128_fma4 (gfc_array_i4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_4 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_i4_avx128_fma4 (gfc_array_i4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_4 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_i8.c b/libgfortran/generated/matmulavx128_i8.c
index 56e85167a3f..b6071e898b9 100644
--- a/libgfortran/generated/matmulavx128_i8.c
+++ b/libgfortran/generated/matmulavx128_i8.c
@@ -544,20 +544,6 @@ matmul_i8_avx128_fma3 (gfc_array_i8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_8 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_i8_avx128_fma3 (gfc_array_i8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_8 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_i8_avx128_fma4 (gfc_array_i8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_INTEGER_8 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_i8_avx128_fma4 (gfc_array_i8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_INTEGER_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_INTEGER_8 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_r10.c b/libgfortran/generated/matmulavx128_r10.c
index 880c9d921b2..3fabc362fb4 100644
--- a/libgfortran/generated/matmulavx128_r10.c
+++ b/libgfortran/generated/matmulavx128_r10.c
@@ -544,20 +544,6 @@ matmul_r10_avx128_fma3 (gfc_array_r10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_10 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_r10_avx128_fma3 (gfc_array_r10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_10 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_r10_avx128_fma4 (gfc_array_r10 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_10 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_r10_avx128_fma4 (gfc_array_r10 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_10)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_10 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_r16.c b/libgfortran/generated/matmulavx128_r16.c
index 328e251a3a1..b53ce280610 100644
--- a/libgfortran/generated/matmulavx128_r16.c
+++ b/libgfortran/generated/matmulavx128_r16.c
@@ -544,20 +544,6 @@ matmul_r16_avx128_fma3 (gfc_array_r16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_16 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_r16_avx128_fma3 (gfc_array_r16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_16 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_r16_avx128_fma4 (gfc_array_r16 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_16 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_r16_avx128_fma4 (gfc_array_r16 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_16)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_16 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_r4.c b/libgfortran/generated/matmulavx128_r4.c
index 013a1804a11..ac1e1a35e5a 100644
--- a/libgfortran/generated/matmulavx128_r4.c
+++ b/libgfortran/generated/matmulavx128_r4.c
@@ -544,20 +544,6 @@ matmul_r4_avx128_fma3 (gfc_array_r4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_4 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_r4_avx128_fma3 (gfc_array_r4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_4 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_r4_avx128_fma4 (gfc_array_r4 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_4 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_r4_avx128_fma4 (gfc_array_r4 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_4)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_4 *restrict abase_x;
diff --git a/libgfortran/generated/matmulavx128_r8.c b/libgfortran/generated/matmulavx128_r8.c
index 4da59f9e69c..416604af13b 100644
--- a/libgfortran/generated/matmulavx128_r8.c
+++ b/libgfortran/generated/matmulavx128_r8.c
@@ -544,20 +544,6 @@ matmul_r8_avx128_fma3 (gfc_array_r8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_8 *restrict bbase_y;
@@ -572,6 +558,20 @@ matmul_r8_avx128_fma3 (gfc_array_r8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_8 *restrict abase_x;
@@ -1102,20 +1102,6 @@ matmul_r8_avx128_fma4 (gfc_array_r8 * const restrict retarray,
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const GFC_REAL_8 *restrict bbase_y;
@@ -1130,6 +1116,20 @@ matmul_r8_avx128_fma4 (gfc_array_r8 * const restrict retarray,
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = (GFC_REAL_8)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const GFC_REAL_8 *restrict abase_x;
diff --git a/libgfortran/m4/matmul_internal.m4 b/libgfortran/m4/matmul_internal.m4
index 2020e8a50df..4c8237a66e6 100644
--- a/libgfortran/m4/matmul_internal.m4
+++ b/libgfortran/m4/matmul_internal.m4
@@ -495,20 +495,6 @@ sinclude(`matmul_asm_'rtype_code`.m4')dnl
 	    }
 	}
     }
-  else if (axstride < aystride)
-    {
-      for (y = 0; y < ycount; y++)
-	for (x = 0; x < xcount; x++)
-	  dest[x*rxstride + y*rystride] = ('rtype_name`)0;
-
-      for (y = 0; y < ycount; y++)
-	for (n = 0; n < count; n++)
-	  for (x = 0; x < xcount; x++)
-	    /* dest[x,y] += a[x,n] * b[n,y] */
-	    dest[x*rxstride + y*rystride] +=
-					abase[x*axstride + n*aystride] *
-					bbase[n*bxstride + y*bystride];
-    }
   else if (GFC_DESCRIPTOR_RANK (a) == 1)
     {
       const 'rtype_name` *restrict bbase_y;
@@ -523,6 +509,20 @@ sinclude(`matmul_asm_'rtype_code`.m4')dnl
 	  dest[y*rxstride] = s;
 	}
     }
+  else if (axstride < aystride)
+    {
+      for (y = 0; y < ycount; y++)
+	for (x = 0; x < xcount; x++)
+	  dest[x*rxstride + y*rystride] = ('rtype_name`)0;
+
+      for (y = 0; y < ycount; y++)
+	for (n = 0; n < count; n++)
+	  for (x = 0; x < xcount; x++)
+	    /* dest[x,y] += a[x,n] * b[n,y] */
+	    dest[x*rxstride + y*rystride] +=
+					abase[x*axstride + n*aystride] *
+					bbase[n*bxstride + y*bystride];
+    }
   else
     {
       const 'rtype_name` *restrict abase_x;

commit c70827788716a77bca0597de12119b88594ac56e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Oct 25 00:17:38 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b858c4c782c..49d6a92f23f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201024
+20201025
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d74fcf166cb..3ba29ef8c39 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-10-24  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-10-18  Harald Anlauf  <anlauf@gmx.de>
+
+	* gfortran.dg/matmul_20.f90: New test.
+
 2020-10-22  Andreas Krebbel  <krebbel@linux.ibm.com>
 
 	Backported from master:
diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog
index e3cd3692ca8..0a48927285c 100644
--- a/libgfortran/ChangeLog
+++ b/libgfortran/ChangeLog
@@ -1,3 +1,37 @@
+2020-10-24  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2020-10-18  Harald Anlauf  <anlauf@gmx.de>
+
+	* m4/matmul_internal.m4: Move check for rank-1 times rank-2 before
+	checks on strides for rank-2 times rank-2.
+	* generated/matmul_c10.c: Regenerated.
+	* generated/matmul_c16.c: Likewise.
+	* generated/matmul_c4.c: Likewise.
+	* generated/matmul_c8.c: Likewise.
+	* generated/matmul_i1.c: Likewise.
+	* generated/matmul_i16.c: Likewise.
+	* generated/matmul_i2.c: Likewise.
+	* generated/matmul_i4.c: Likewise.
+	* generated/matmul_i8.c: Likewise.
+	* generated/matmul_r10.c: Likewise.
+	* generated/matmul_r16.c: Likewise.
+	* generated/matmul_r4.c: Likewise.
+	* generated/matmul_r8.c: Likewise.
+	* generated/matmulavx128_c10.c: Likewise.
+	* generated/matmulavx128_c16.c: Likewise.
+	* generated/matmulavx128_c4.c: Likewise.
+	* generated/matmulavx128_c8.c: Likewise.
+	* generated/matmulavx128_i1.c: Likewise.
+	* generated/matmulavx128_i16.c: Likewise.
+	* generated/matmulavx128_i2.c: Likewise.
+	* generated/matmulavx128_i4.c: Likewise.
+	* generated/matmulavx128_i8.c: Likewise.
+	* generated/matmulavx128_r10.c: Likewise.
+	* generated/matmulavx128_r16.c: Likewise.
+	* generated/matmulavx128_r4.c: Likewise.
+	* generated/matmulavx128_r8.c: Likewise.
+
 2020-09-09  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:

commit 4b7395ba4a9282c685a4c0cdf89bcdafbd3feefb
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Oct 26 00:17:36 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 49d6a92f23f..8f5453ef1e3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201025
+20201026

commit 50765cc3255c5b7b57029346583bff15f8ad1a61
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Oct 27 00:17:38 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 8f5453ef1e3..86b2464d6bb 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201026
+20201027

commit 7b81cfaa565fec77be7a6faa42d40f54a53f73a7
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Oct 28 00:17:57 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 86b2464d6bb..52d576a34f9 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201027
+20201028

commit 2d327cb2bf9f5e9553700c7ecbb5c09e02ee5b4e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Oct 29 00:18:10 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 52d576a34f9..8559f6c8b74 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201028
+20201029

commit b0cb1f1fed535595660d03469fb922b2cd42ba4e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Oct 30 00:17:38 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 8559f6c8b74..d724ea40a76 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201029
+20201030

commit 3940a3ff2be0b445a5b24a222e83669e570f32a9
Author: Thomas Schwinge <thomas@codesourcery.com>
Date:   Thu Oct 29 10:29:19 2020 +0100

    libgomp testsuite: tell warning from error diagnostics, etc. [PR80219, PR85303]
    
    This changes makes 'dg-warning', 'dg-error', 'dg-bogus', 'dg-message' behave as
    expected, and also enables use of relative line numbers as well as 'dg-line'.
    
            libgomp/
            PR testsuite/80219
            PR testsuite/85303
            * testsuite/lib/libgomp.exp (libgomp_init): Set
            'gcc_warning_prefix', 'gcc_error_prefix'.
    
    (cherry picked from commit 528507fa0314c75d1105890e4781a475c8badd7c)

diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp
index ea3da2cb383..04302074732 100644
--- a/libgomp/testsuite/lib/libgomp.exp
+++ b/libgomp/testsuite/lib/libgomp.exp
@@ -248,6 +248,12 @@ proc libgomp_init { args } {
     if { $offload_additional_options != "" } {
 	lappend ALWAYS_CFLAGS "additional_flags=${offload_additional_options}"
     }
+
+    # Tell warning from error diagnostics.  This fits for C, C++, and Fortran.
+    global gcc_warning_prefix
+    set gcc_warning_prefix "\[Ww\]arning:"
+    global gcc_error_prefix
+    set gcc_error_prefix "(\[Ff\]atal )?\[Ee\]rror:"
 }
 
 #

commit 7f5d91750e9f9db62fb8c46810f7145954a4e0eb
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Nov 2 20:54:16 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d724ea40a76..f676795e9a5 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201030
+20201102
diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 9bc4ac32fdd..15b6418ff5a 100644
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,13 @@
+2020-11-02  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2020-11-02  Thomas Schwinge  <thomas@codesourcery.com>
+
+	PR testsuite/80219
+	PR testsuite/85303
+	* testsuite/lib/libgomp.exp (libgomp_init): Set
+	'gcc_warning_prefix', 'gcc_error_prefix'.
+
 2020-09-17  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:

commit 100e274ed8bdf38e60991e8de8a80f010f9088a3
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Nov 3 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f676795e9a5..70922553ee1 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201102
+20201103

commit 80b6f6cf6374a6541a7515d7bfef1a3506db2a3d
Author: Richard Biener <rguenther@suse.de>
Date:   Tue Nov 3 10:24:02 2020 +0100

    testsuite/97688 - fix check_vect () with __AVX2__
    
    This fixes the cpuid check to always specify a subleaf zero
    which is required to detect AVX2 and doesn't hurt for level one.
    Without this fix we get zero runtime coverage when -mavx2 is
    specified.
    
    2020-11-03  Richard Biener  <rguenther@suse.de>
    
            PR testsuite/97688
            * gcc.dg/vect/tree-vect.h (check_vect): Fix the x86 cpuid
            check to always specify subleaf zero.
    
    (cherry picked from commit 8414529156e0bca37647c440c71beeca1d04ac86)

diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h
index 69c93ac8092..eb890745a00 100644
--- a/gcc/testsuite/gcc.dg/vect/tree-vect.h
+++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h
@@ -52,7 +52,7 @@ check_vect (void)
     want_level = 1, want_d = bit_SSE2;
 # endif
 
-    if (!__get_cpuid (want_level, &a, &b, &c, &d)
+    if (!__get_cpuid_count (want_level, 0, &a, &b, &c, &d)
 	|| ((b & want_b) | (c & want_c) | (d & want_d)) == 0)
       exit (0);
   }

commit 1ed4f10a9d2955d65766f15e9925c7c638657378
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Nov 4 00:18:02 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 70922553ee1..f23c2c72098 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201103
+20201104
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3ba29ef8c39..de927d41834 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2020-11-03  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2020-11-03  Richard Biener  <rguenther@suse.de>
+
+	PR testsuite/97688
+	* gcc.dg/vect/tree-vect.h (check_vect): Fix the x86 cpuid
+	check to always specify subleaf zero.
+
 2020-10-24  Harald Anlauf  <anlauf@gmx.de>
 
 	Backported from master:

commit 5f94c963732ed54bc09f33ff38f789a1c208392b
Author: Martin Liska <mliska@suse.cz>
Date:   Wed Nov 4 10:21:40 2020 +0100

    Remove duplicite ChangeLog entry.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 49158b622ba..973329a6330 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -461,12 +461,6 @@
 	TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
 	fenv_var and new_fenv_var.
 
-2020-04-29  Richard Sandiford  <richard.sandiford@arm.com>
-
-	* config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
-	TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
-	fenv_var and new_fenv_var.
-
 2020-09-17  Segher Boessenkool  <segher@kernel.crashing.org>
 
 	Backported from master:

commit 6739ef0748ce47b937563aaa8098d9b3a19bb3b7
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Nov 5 00:17:52 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f23c2c72098..35d25ab2f20 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201104
+20201105

commit 6340340503bee78bcd10051930cd1ccf811b3f00
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Nov 6 00:17:49 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 35d25ab2f20..7096b2dbae9 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201105
+20201106

commit 217af6ff5d3c83eaff7fa9aba18c7cd57fdbc7a9
Author: Martin Liska <mliska@suse.cz>
Date:   Fri Nov 6 14:52:05 2020 +0100

    Sync gcc-changelog scripts.
    
    contrib/ChangeLog:
    
    2020-11-06  Martin Liska  <mliska@suse.cz>
    
            * gcc-changelog/git_commit.py: Sync.
            * gcc-changelog/git_email.py: Likewise.
            * gcc-changelog/git_repository.py: Likewise.
            * gcc-changelog/test_email.py: Likewise.
            * gcc-changelog/test_patches.txt: Likewise.
            * gcc-changelog/setup.cfg: New file.

diff --git a/contrib/gcc-changelog/git_commit.py b/contrib/gcc-changelog/git_commit.py
index 5a9cc4c7563..80ae0b2a77d 100755
--- a/contrib/gcc-changelog/git_commit.py
+++ b/contrib/gcc-changelog/git_commit.py
@@ -155,6 +155,8 @@ pr_regex = re.compile(r'\tPR (?P<component>[a-z+-]+\/)?([0-9]+)$')
 dr_regex = re.compile(r'\tDR ([0-9]+)$')
 star_prefix_regex = re.compile(r'\t\*(?P<spaces>\ *)(?P<content>.*)')
 end_of_location_regex = re.compile(r'[\[<(:]')
+item_empty_regex = re.compile(r'\t(\* \S+ )?\(\S+\):\s*$')
+item_parenthesis_regex = re.compile(r'\t(\*|\(\S+\):)')
 
 LINE_LIMIT = 100
 TAB_WIDTH = 8
@@ -421,7 +423,11 @@ class GitCommit:
                     continue
                 elif line.startswith(CHERRY_PICK_PREFIX):
                     commit = line[len(CHERRY_PICK_PREFIX):].rstrip(')')
-                    self.cherry_pick_commit = commit
+                    if self.cherry_pick_commit:
+                        self.errors.append(Error('multiple cherry pick lines',
+                                                 line))
+                    else:
+                        self.cherry_pick_commit = commit
                     continue
 
                 # ChangeLog name will be deduced later
@@ -459,6 +465,13 @@ class GitCommit:
                             msg = 'one space should follow asterisk'
                             self.errors.append(Error(msg, line))
                         else:
+                            content = m.group('content')
+                            parts = content.split(':')
+                            if len(parts) > 1:
+                                for needle in ('()', '[]', '<>'):
+                                    if ' ' + needle in parts[0]:
+                                        msg = f'empty group "{needle}" found'
+                                        self.errors.append(Error(msg, line))
                             last_entry.lines.append(line)
                     else:
                         if last_entry.is_empty:
@@ -483,9 +496,10 @@ class GitCommit:
     def check_for_empty_description(self):
         for entry in self.changelog_entries:
             for i, line in enumerate(entry.lines):
-                if (star_prefix_regex.match(line) and line.endswith(':') and
+                if (item_empty_regex.match(line) and
                     (i == len(entry.lines) - 1
-                     or star_prefix_regex.match(entry.lines[i + 1]))):
+                     or not entry.lines[i+1].strip()
+                     or item_parenthesis_regex.match(entry.lines[i+1]))):
                     msg = 'missing description of a change'
                     self.errors.append(Error(msg, line))
 
diff --git a/contrib/gcc-changelog/git_email.py b/contrib/gcc-changelog/git_email.py
index 014fdd1004b..5b53ca4a6a9 100755
--- a/contrib/gcc-changelog/git_email.py
+++ b/contrib/gcc-changelog/git_email.py
@@ -24,10 +24,11 @@ from dateutil.parser import parse
 
 from git_commit import GitCommit, GitInfo
 
-from unidiff import PatchSet
+from unidiff import PatchSet, PatchedFile
 
 DATE_PREFIX = 'Date: '
 FROM_PREFIX = 'From: '
+unidiff_supports_renaming = hasattr(PatchedFile(), 'is_rename')
 
 
 class GitEmail(GitCommit):
@@ -58,7 +59,7 @@ class GitEmail(GitCommit):
                 t = 'A'
             elif f.is_removed_file:
                 t = 'D'
-            elif f.is_rename:
+            elif unidiff_supports_renaming and f.is_rename:
                 # Consider that renamed files are two operations: the deletion
                 # of the original name and the addition of the new one.
                 modified_files.append((source, 'D'))
diff --git a/contrib/gcc-changelog/git_repository.py b/contrib/gcc-changelog/git_repository.py
index 90edc3ce3d8..8edcff91ad6 100755
--- a/contrib/gcc-changelog/git_repository.py
+++ b/contrib/gcc-changelog/git_repository.py
@@ -29,7 +29,7 @@ except ImportError:
 from git_commit import GitCommit, GitInfo
 
 
-def parse_git_revisions(repo_path, revisions, strict=False):
+def parse_git_revisions(repo_path, revisions, strict=True):
     repo = Repo(repo_path)
 
     def commit_to_info(commit):
diff --git a/contrib/gcc-changelog/setup.cfg b/contrib/gcc-changelog/setup.cfg
new file mode 100644
index 00000000000..9e4a0f6479c
--- /dev/null
+++ b/contrib/gcc-changelog/setup.cfg
@@ -0,0 +1,2 @@
+[tool:pytest]
+addopts = -vv --flake8
diff --git a/contrib/gcc-changelog/test_email.py b/contrib/gcc-changelog/test_email.py
index b6fbe6a5303..e38c3e52158 100755
--- a/contrib/gcc-changelog/test_email.py
+++ b/contrib/gcc-changelog/test_email.py
@@ -362,6 +362,25 @@ class TestGccChangelog(unittest.TestCase):
         assert '\t2020-06-11  Martin Liska  <mliska@suse.cz>' in entry
         assert '\t\t    Jakub Jelinek  <jakub@redhat.com>' in entry
 
+    def test_backport_double_cherry_pick(self):
+        email = self.from_patch_glob('double-cherry-pick.patch')
+        assert email.errors[0].message.startswith('multiple cherry pick lines')
+
     def test_square_and_lt_gt(self):
         email = self.from_patch_glob('0001-Check-for-more-missing')
         assert not email.errors
+
+    def test_empty_parenthesis(self):
+        email = self.from_patch_glob('0001-tree-optimization-97633-fix')
+        assert len(email.errors) == 1
+        assert email.errors[0].message == 'empty group "()" found'
+
+    def test_emptry_entry_desc(self):
+        email = self.from_patch_glob('0001-c-Set-CALL_FROM_NEW_OR')
+        assert len(email.errors) == 1
+        assert email.errors[0].message == 'missing description of a change'
+
+    def test_emptry_entry_desc_2(self):
+        email = self.from_patch_glob('0001-lto-fix-LTO-debug')
+        assert not email.errors
+        assert len(email.changelog_entries) == 1
diff --git a/contrib/gcc-changelog/test_patches.txt b/contrib/gcc-changelog/test_patches.txt
index 2bf5d1aefaa..37f49c851ec 100644
--- a/contrib/gcc-changelog/test_patches.txt
+++ b/contrib/gcc-changelog/test_patches.txt
@@ -3160,6 +3160,35 @@ index 823eb539993..4ec22162c12 100644
 -- 
 2.27.0
 
+=== double-cherry-pick.patch ===
+From e1d68582022cfa2b1dc76646724b397ba2739439 Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Thu, 11 Jun 2020 09:34:41 +0200
+Subject: [PATCH] asan: fix RTX emission for ilp32
+
+gcc/ChangeLog:
+
+	PR sanitizer/95634
+	* asan.c (asan_emit_stack_protection): Fix emission for ilp32
+	by using Pmode instead of ptr_mode.
+
+Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
+(cherry picked from commit 8cff672cb9a132d3d3158c2edfc9a64b55292b80)
+(cherry picked from commit 8cff672cb9a132d3d3158c2edfc9a64b55292b80)
+---
+ gcc/asan.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/asan.c b/gcc/asan.c
+index 823eb539993..4ec22162c12 100644
+--- a/gcc/asan.c
++++ b/gcc/asan.c
+@@ -1 +1,2 @@
+ 
++
+-- 
+2.27.0
+
 === 0001-Check-for-more-missing-math-decls-on-vxworks.patch ===
 From 0edfc1fd22405ee8e946101e44cd8edc0ee12047 Mon Sep 17 00:00:00 2001
 From: Douglas B Rupp <douglas.b.rupp@gmail.com>
@@ -3193,5 +3222,101 @@ index fe18288..313f84d 100644
  
 +
 -- 
+=== 0001-tree-optimization-97633-fix-SLP-scheduling-of-single.patch ===
+From c0bfd9672e19caf08e45afeb4277f848488ced2b Mon Sep 17 00:00:00 2001
+From: Richard Biener <rguenther@suse.de>
+Date: Fri, 30 Oct 2020 09:57:02 +0100
+Subject: [PATCH] tree-optimization/97633 - fix SLP scheduling of single-node
+ cycles
+
+This makes sure to update backedges in single-node cycles.
+
+2020-10-30  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/97633
+	* tree-vect-slp.c (): Update backedges in single-node cycles.
+	Optimize processing of externals.
+
+	* g++.dg/vect/slp-pr97636.cc: New testcase.
+	* gcc.dg/vect/bb-slp-pr97633.c: Likewise.
+---
+ gcc/testsuite/g++.dg/vect/slp-pr97636.cc   |  83 +++++++++++
+ gcc/testsuite/gcc.dg/vect/bb-slp-pr97633.c |  27 ++++
+ gcc/tree-vect-slp.c                        | 162 +++++++++++----------
+ 3 files changed, 198 insertions(+), 74 deletions(-)
+ create mode 100644 gcc/testsuite/g++.dg/vect/slp-pr97636.cc
+ create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr97633.c
+
+diff --git a/gcc/testsuite/g++.dg/vect/slp-pr97636.cc b/gcc/testsuite/g++.dg/vect/slp-pr97636.cc
+new file mode 100644
+index 00000000000..012342004f1
+--- /dev/null
++++ b/gcc/testsuite/g++.dg/vect/slp-pr97636.cc
+@@ -0,0 +1 @@
++
+diff --git a/gcc/tree-vect-slp.c b/gcc/tree-vect-slp.c
+index 5d69a98c2a9..714e50697bd 100644
+--- a/gcc/tree-vect-slp.c
++++ b/gcc/tree-vect-slp.c
+@@ -1 +1,2 @@
+ 
++
+-- 
+
 2.7.4
+=== 0001-c-Set-CALL_FROM_NEW_OR_DELETE_P-on-more-calls.patch ===
+From 4f4ced28826ece7b7b76649522ee2a9601a63b90 Mon Sep 17 00:00:00 2001
+From: Jason Merrill <jason@redhat.com>
+Date: Fri, 2 Oct 2020 09:00:49 +0200
+Subject: [PATCH] c++: Set CALL_FROM_NEW_OR_DELETE_P on more calls.
+
+We were failing to set the flag on a delete call in a new expression, in a
+deleting destructor, and in a coroutine.  Fixed by setting it in the
+function that builds the call.
+
+2020-10-02  Jason Merril  <jason@redhat.com>
+
+gcc/cp/ChangeLog:
+	* init.c (build_new_1, build_vec_delete_1, build_delete): Not here.
+	(build_delete):
+
+---
+ gcc/cp/init.c                  |  1 -
+ 1 files changed, 0 insertions(+), 1 deletions(-)
+
+diff --git a/gcc/cp/init.c b/gcc/cp/init.c
+index e84e985492d..00fff3f7327 100644
+--- a/gcc/cp/init.c
++++ b/gcc/cp/init.c
+@@ -3436,1 +3435,0 @@ build_new_1 (vec<tree, va_gc> **placement, tree type, tree nelts,
+-
+-- 
+2.25.1
+
+=== 0001-lto-fix-LTO-debug-sections-copying.patch ===
+From 190c04ba36d9c6c3dce41f12012aa97c6d7f22f5 Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Mon, 5 Oct 2020 18:03:08 +0200
+Subject: [PATCH] lto: fix LTO debug sections copying.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+libiberty/ChangeLog:
+
+	PR lto/97290
+	* simple-object-elf.c (simple_object_elf_copy_lto_debug_sections):
+	Use sh_link of a .symtab_shndx section.
+---
+ libiberty/simple-object-elf.c | 1 -
+ 1 file changed, 0 insertions(+), 1 deletions(-)
+
+diff --git a/libiberty/simple-object-elf.c b/libiberty/simple-object-elf.c
+index 7c9d492f6a4..37e73348cb7 100644
+--- a/libiberty/simple-object-elf.c
++++ b/libiberty/simple-object-elf.c
+@@ -1191,1 +1191,0 @@ simple_object_elf_copy_lto_debug_sections (simple_object_read *sobj,
+- 
+-- 
+2.25.1
 

commit 95181e74e430fd0edd5a1fa7b7d4472457fa840d
Author: Peter Bergner <bergner@linux.ibm.com>
Date:   Fri Nov 6 16:49:37 2020 -0600

    rs6000: Use the correct minimized testcase
    
    Use the correct minimized test case source rather than the large test
    source.
    
    gcc/testsuite/
            * gcc.target/powerpc/pr64505.c: Run everywhere.  Use correct minimized
            test case.
    
    (cherry picked from commit bd7ed0974fe634e0001a6132528a76d24b5e024f)

diff --git a/gcc/testsuite/gcc.target/powerpc/pr64505.c b/gcc/testsuite/gcc.target/powerpc/pr64505.c
index 8601f2d7e9f..42b961f3df5 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr64505.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr64505.c
@@ -1,231 +1,52 @@
-/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-do compile } */
 /* { dg-skip-if "" { powerpc*-*-aix* } } */
-/* { dg-options "-O2 -mpowerpc64" } */
+/* { dg-options "-w -O2 -mpowerpc64" } */
 
 /*
- * (below is inlined and simplified from previously included headers)
+ * (below is minimized test case)
  */
 
-struct fltcom_st {
-    short fltbuf[950];
-} fltcom_  __attribute__((common))  ;
-#define CM_PLIBOR (*(((double *)&fltcom_ + 1)))
-#define CM_QMRG (*(((double *)&fltcom_ + 2)))
+extern double pow(double x, double y);
+extern long func ();
+short global0, global1;
+static int i0, i1, i2, i3, i4, i5;
+double dbl, *array0, *array1;
 
-struct fltcom2_st {
-    short fltbuf2[56];
-} fltcom2_  __attribute__((common))  ;
-#define CM_FLPRV ((short *)&fltcom2_ + 17)
-#define CM_FLNXT ((short *)&fltcom2_ + 20)
-#define CM_FLCPN (*(((double *)&fltcom2_)))
-#define CM_FLCNT (*(((short *)&fltcom2_ + 12)))
-
-struct aidatcm_st {
-    double cm_aid, cm_ext, cm_basis;
-    short cm_aiday, cm_exday, cm_dperd, cm_aiexf, cm_aidex, cm_aiok,
-            cm_aigdo, cm_aildo, cm_prev[3], cm_next[3], cm_aid_pad[2];
-    double cm_rvgfact, cm_ai1st, cm_ai2nd;
-    int cm_aieurok;
-} aidatcm_  __attribute__((common))  ;
-#define CM_EXDAY aidatcm_.cm_exday
-#define CM_BASIS aidatcm_.cm_basis
-#define CM_PREV aidatcm_.cm_prev
-
-struct cshfcm_st {
-    short bufff[10862];
-} cshfcm_  __attribute__((common))  ;
-#define CM_FNUM (*(((short *)&cshfcm_ + 9038)))
-#define CM_FIFLX ((double *)&cshfcm_ + 1)
-#define CM_FEXTX ((double *)&cshfcm_ + 1201)
-#define CM_FSHDT ((short *)&cshfcm_ + 7230)
-
-struct calctsdb_st {
-    short calctsdbbuff[115];
-} calctsdb_  __attribute__((common))  ;
-#define CM_CTUP_GOOD_TO_GO (*(((short *)&calctsdb_ + 16)))
-#define CM_PAYMENT_FREQUENCY (*(((short *)&calctsdb_ + 61)))
-#define CM_DISCOUNTING_DAYTYP (*(((short *)&calctsdb_ + 59)))
-
-struct cf600cm_st {
-    short bufcf[14404];
-} cf600cm_  __attribute__((common)) ;
-#define CM_FLT_RFIXRATES ((double *)&cf600cm_ + 600)
-
-typedef struct { int id; int type; const char *name; } bregdb_bitinfo_t;
-
-int
-bregdb_eval_bbitcxt_bool_rv(const bregdb_bitinfo_t * const bbit,
-                            const int bbit_default,
-                            const void * const bregucxt);
-
-static const bregdb_bitinfo_t bbit_calc_dr_d33 =
-  { 160667, 5, "bbit_calc_dr_d33" };
-#define bbit_calc_dr_d33__value() \
-  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d33, 0, 0)
-static const bregdb_bitinfo_t bbit_calc_sx_b24 =
-  { 158854, 5, "bbit_calc_sx_b24" };
-#define bbit_calc_sx_b24__value() \
-  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_sx_b24, 0, 0)
-static const bregdb_bitinfo_t bbit_calc_dr_d36 =
-  { 161244, 5, "bbit_calc_dr_d36" };
-#define bbit_calc_dr_d36__value() \
-  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d36, 0, 0)
-static const bregdb_bitinfo_t bbit_calc_dr_d37 =
-  { 161315, 5, "bbit_calc_dr_d37" };
-#define bbit_calc_dr_d37__value() \
-  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d37, 0, 0)
-static const bregdb_bitinfo_t bbit_calc_dr_d47 =
-  { 163259, 5, "bbit_calc_dr_d47" };
-#define bbit_calc_dr_d47__value() \
-  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d47, 0, 0)
-static const bregdb_bitinfo_t bbit_calc_dr_d46 =
-  { 163239, 5, "bbit_calc_dr_d46" };
-#define bbit_calc_dr_d46__value() \
-  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d46, 0, 0)
-static const bregdb_bitinfo_t bbit_calc_dr_d62 =
-  { 166603, 5, "bbit_calc_dr_d62" };
-#define bbit_calc_dr_d62__value() \
-  bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d62, 0, 0)
-
-
-
-int dtyp_is_actact_(short *daytyp);
-double rnd_trunc_numb(double in, short num_digits, short rnd_or_trunc);
-void datetrn_(const short* dt, short* dt2);
-short difday_(short* daytyp_in, short* srtdti, short* enddti, short* ercode);
-
-
-double pow(double x, double y);
-
-
-/*
- * (above is inlined and simplified from previously included headers)
- */
-
-
-void calc_1566(
-  short  sCalcType,
-  short  sDayType,
-  short  sFreq,
-  short  asSettleDt[3],
-  short  asMtyDt[3],
-  short  asIssueDt[3],
-  short  asFCpnDt[3],
-  double dCpn,
-  short  *psNoPer,
-  double *pdExt,
-  double *pdAI,
-  double *pdAI2,
-  double *pdFCpn,
-  short  *psRcode)
+void
+pr64505 (short *arg0, double *arg1)
 {
-
-    short ercode = 0;
-    int isactact;
-    short days_to_next_cpn = 0;
-    const short discDaytype = CM_DISCOUNTING_DAYTYP;
-
-    if(bbit_calc_sx_b24__value())
-        isactact = (dtyp_is_actact_(&sDayType) != 0);
-    else
-        isactact = (sDayType == 1 || sDayType == 10);
-
-    short days_in_current_period = difday_(&sDayType,CM_FLPRV,CM_FLNXT,&ercode);
-    const short sfreq1 = (CM_CTUP_GOOD_TO_GO == 1 && CM_PAYMENT_FREQUENCY == 1);
-
-    for (int j = 0; j < CM_FNUM; j++) {
-
-        if(j == 0) {
-            days_to_next_cpn = difday_(&sDayType,asSettleDt,CM_FLNXT,&ercode);
-
-            if(isactact) {
-                CM_FIFLX[j] = CM_FLCPN / sFreq;
-                CM_FEXTX[j] = (double)days_to_next_cpn / (double)days_in_current_period;
-            }
-            else {
-                CM_FIFLX[j] = CM_FLCPN * days_in_current_period;
-                CM_FEXTX[j] = (double)days_to_next_cpn / (double)(1/sfreq1);
-            }
-
-            if(CM_FNUM == 1) {
-                CM_FEXTX[j] = (double)days_to_next_cpn / ((double)1/sfreq1);
-            }
-        }
-        else {
-
-            short days_from_settle, days_in_period;
-
-            if(bbit_calc_dr_d46__value()){
-             days_from_settle = difday_(&sDayType,asSettleDt,
-                                             &CM_FSHDT[j*3],&ercode);
-             days_in_period =  difday_(&sDayType,&CM_FSHDT[(j-1)*3],
-                                            &CM_FSHDT[j*3],&ercode);
-            }
-
-            double cpn_rate = CM_PLIBOR;
-
-            if(bbit_calc_dr_d62__value()) {
-              if(j < CM_FLCNT && CM_FLT_RFIXRATES[j] != 0) cpn_rate = CM_FLT_RFIXRATES[j];
-            }
-            else {
-              if(j < CM_FLCNT ) cpn_rate = CM_FLT_RFIXRATES[j];
-            }
-
-            if(bbit_calc_dr_d37__value()&& j >= CM_FLCNT && sCalcType == 1570) {
-                cpn_rate = CM_PLIBOR + CM_QMRG;
-
-                if(bbit_calc_dr_d36__value()){
-                double projected_rate = pow((1 + CM_PLIBOR/100.0),
-                                            (days_in_period)) - 1;
-
-                projected_rate = projected_rate + CM_QMRG/100.0 * days_in_period;
-                cpn_rate = 100 * projected_rate * (1/days_in_period);
-                }
-            }
-
-
-            if(isactact) {
-                CM_FIFLX[j] = cpn_rate / sFreq;
-                CM_FEXTX[j] = CM_FEXTX[j-1] + 1;
-
-                if(bbit_calc_dr_d46__value() && discDaytype != 0) {
-                    CM_FEXTX[j] = (double)days_from_settle / (double)(1/sfreq1);
-                }
-            }
-            else {
-                if(!bbit_calc_dr_d46__value()){
-                days_from_settle = difday_(&sDayType,asSettleDt,
-                                               &CM_FSHDT[j*3],&ercode);
-                days_in_period =  difday_(&sDayType,&CM_FSHDT[(j-1)*3],
-                                               &CM_FSHDT[j*3],&ercode);
-
-                }
-
-                CM_FIFLX[j] = cpn_rate * days_in_period;
-                CM_FEXTX[j] = (double)days_from_settle / (double)(1/sfreq1);
-            }
-
-        }
-
-        if(bbit_calc_dr_d33__value() && CM_CTUP_GOOD_TO_GO != 0) {
-            CM_FIFLX[j] = rnd_trunc_numb (CM_FIFLX[j], 0, 0);
-        }
-
+  int error = 0;
+  short num = func (&global1 + 15, &error);
+  for (int j = 0; j < array0[0]; j++)
+    {
+      if (j == 0)
+	{
+	  func (arg0, &global1 + 20, &error);
+	  array0[0] = num;
+	}
+      else
+	{
+	  double cr = (&dbl)[1];
+	  if (func (&i4))
+	    func (0, &(&array0)[j]);
+	  if (func (&i5))
+	    {
+	      if ((&global1)[12])
+		cr = array1[j];
+	    }
+	  if (func (&i2)
+	      && (&global1)[12])
+	    {
+	      if (func (&i1))
+	        pow ((&dbl)[1], 2);
+	    }
+	    array0[j] = cr;
+	}
+      if (func (&i0) && global0)
+        func (((short *) array0 + 1)[j]);
     }
-
-
-    short accrued_days = difday_(&sDayType,CM_FLPRV,asSettleDt,&ercode);
-
-    if(!bbit_calc_dr_d47__value()) {
-    if(isactact) {
-        *pdAI = (CM_FLCPN / sFreq)* accrued_days / ((double)days_in_current_period);
-    }
-    else{
-        *pdAI = (CM_FLCPN / sFreq)* accrued_days / ((double)1/sFreq);
-    }
-    }
-
-    CM_EXDAY = days_to_next_cpn;
-    CM_BASIS = days_in_current_period;
-    datetrn_(CM_FLPRV,CM_PREV);
+  short ad = func (&global1 + 15, 0);
+  if (func (&i3) && func ())
+    *arg1 = *((double *) &global1) * ad;
+  func (&global1 + 15);
 }

commit df2257f56401d7ac780d1434e0c3131384f9904b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Nov 7 00:17:57 2020 +0000

    Daily bump.

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index af24fca9886..c1239f86307 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,12 @@
+2020-11-06  Martin Liska  <mliska@suse.cz>
+
+	* gcc-changelog/git_commit.py: Sync.
+	* gcc-changelog/git_email.py: Likewise.
+	* gcc-changelog/git_repository.py: Likewise.
+	* gcc-changelog/test_email.py: Likewise.
+	* gcc-changelog/test_patches.txt: Likewise.
+	* gcc-changelog/setup.cfg: New file.
+
 2020-07-29  Martin Liska  <mliska@suse.cz>
 
 	* git-backport.py: fix how are ChangeLog paths combined.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7096b2dbae9..55bedf8dcf4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201106
+20201107
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index de927d41834..29aa2d5497c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2020-11-06  Peter Bergner  <bergner@linux.ibm.com>
+
+	Backported from master:
+	2020-11-06  Peter Bergner  <bergner@linux.ibm.com>
+
+	* gcc.target/powerpc/pr64505.c: Run everywhere.  Use correct minimized
+	test case.
+
 2020-11-03  Richard Biener  <rguenther@suse.de>
 
 	Backported from master:

commit a551a1443d6ebfae4d22309665eedd778787a038
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Nov 8 00:17:45 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 55bedf8dcf4..568c6178ca4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201107
+20201108

commit b69c40fc481fca42eeefe55331ac3d0a7490e4c7
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Nov 9 00:17:40 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 568c6178ca4..9938e11b47b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201108
+20201109

commit 749cfa1f150d1e0749feb7aed8f68b8d0294b03f
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Thu Nov 5 17:26:13 2020 +0000

    libstdc++: Use non-throwing increment in recursive_directory_iterator [PR 97731]
    
    As described in the PR, the recursive_directory_iterator constructor
    calls advance(ec), but ec is a pointer so it calls _Dir::advance(bool).
    The intention was to either call advance() or advance(*ec) depending
    whether the pointer is null or not.
    
    This fixes the bug and renames the parameter to ecptr to make similar
    mistakes less likely in future.
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/97731
            * src/filesystem/dir.cc (recursive_directory_iterator): Call the
            right overload of _Dir::advance.
            * testsuite/experimental/filesystem/iterators/97731.cc: New test.
    
    (cherry picked from commit 2f93a2a03a343a29f614a530d7657f1ed6347ed5)

diff --git a/libstdc++-v3/src/filesystem/dir.cc b/libstdc++-v3/src/filesystem/dir.cc
index 8b1b98dba9c..9db295dcb44 100644
--- a/libstdc++-v3/src/filesystem/dir.cc
+++ b/libstdc++-v3/src/filesystem/dir.cc
@@ -181,16 +181,16 @@ struct fs::recursive_directory_iterator::_Dir_stack : std::stack<_Dir>
 
 fs::recursive_directory_iterator::
 recursive_directory_iterator(const path& p, directory_options options,
-                             error_code* ec)
+                             error_code* ecptr)
 : _M_options(options), _M_pending(true)
 {
-  if (ec)
-    ec->clear();
   if (DIR* dirp = ::opendir(p.c_str()))
     {
+      if (ecptr)
+	ecptr->clear();
       auto sp = std::make_shared<_Dir_stack>();
       sp->push(_Dir{ dirp, p });
-      if (sp->top().advance(ec))
+      if (ecptr ? sp->top().advance(*ecptr) : sp->top().advance())
 	_M_dirs.swap(sp);
     }
   else
@@ -198,14 +198,18 @@ recursive_directory_iterator(const path& p, directory_options options,
       const int err = errno;
       if (err == EACCES
 	  && is_set(options, fs::directory_options::skip_permission_denied))
-	return;
+	{
+	  if (ecptr)
+	    ecptr->clear();
+	  return;
+	}
 
-      if (!ec)
+      if (!ecptr)
 	_GLIBCXX_THROW_OR_ABORT(filesystem_error(
 	      "recursive directory iterator cannot open directory", p,
 	      std::error_code(err, std::generic_category())));
 
-      ec->assign(err, std::generic_category());
+      ecptr->assign(err, std::generic_category());
     }
 }
 
diff --git a/libstdc++-v3/testsuite/experimental/filesystem/iterators/97731.cc b/libstdc++-v3/testsuite/experimental/filesystem/iterators/97731.cc
new file mode 100644
index 00000000000..c6a9d5663fe
--- /dev/null
+++ b/libstdc++-v3/testsuite/experimental/filesystem/iterators/97731.cc
@@ -0,0 +1,49 @@
+// Copyright (C) 2020 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-DUSE_FILESYSTEM_TS -lstdc++fs" }
+// { dg-do run { target c++11 } }
+// { dg-require-filesystem-ts "" }
+
+#include <experimental/filesystem>
+#include <cerrno>
+#include <testsuite_hooks.h>
+
+bool used_custom_readdir = false;
+
+extern "C" void* readdir(void*)
+{
+  used_custom_readdir = true;
+  errno = EIO;
+  return nullptr;
+}
+
+void
+test01()
+{
+  using std::experimental::filesystem::recursive_directory_iterator;
+  std::error_code ec;
+  recursive_directory_iterator it(".", ec);
+  if (used_custom_readdir)
+    VERIFY( ec.value() == EIO );
+}
+
+int
+main()
+{
+  test01();
+}

commit 390c069341b506f991a547188eeff434186ac423
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Nov 10 00:17:42 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 9938e11b47b..2cca29cf6c6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201109
+20201110
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 3f7d2447afa..abfc75d2b5e 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,13 @@
+2020-11-09  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-11-05  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/97731
+	* src/filesystem/dir.cc (recursive_directory_iterator): Call the
+	right overload of _Dir::advance.
+	* testsuite/experimental/filesystem/iterators/97731.cc: New test.
+
 2020-10-08  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit 336b7bc769973b89b345f898373972d1b9231ee0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Nov 11 00:17:49 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2cca29cf6c6..bb826fc6328 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201110
+20201111

commit 6f53dfa9acec588c3c7fb19ab10a286c190045fe
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Nov 12 00:17:51 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index bb826fc6328..95634e06f0d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201111
+20201112

commit 6a5765a9b92e33baec228d07731c27a359aac5af
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Nov 13 00:17:52 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 95634e06f0d..b84a76f5a25 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201112
+20201113

commit 2b89fe5836b8a1919f5e1273ae01e395c0f5ca91
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Nov 14 00:17:52 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b84a76f5a25..30ba5a060da 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201113
+20201114

commit b68b24c86d5875c2e89ca109f8e18dd36cecf097
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Nov 15 00:17:41 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 30ba5a060da..bd9040325d2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201114
+20201115

commit 5d185d740f3a2b878b9be9bfb39f95d181ff31c0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Nov 16 00:17:45 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index bd9040325d2..69155b9380a 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201115
+20201116

commit 7dbed9dead9002ee0cd4aa9c22b20942c6f13757
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Fri Aug 28 22:45:24 2020 +0100

    libstdc++: Fix std::gcd and std::lcm for unsigned integers [PR 92978]
    
    This fixes a bug with mixed signed and unsigned types, where converting
    a negative value to the unsigned result type alters the value. The
    solution is to obtain the absolute values of the arguments immediately
    and to perform the actual GCD or LCM algorithm on two arguments of the
    same type.
    
    In order to operate on the most negative number without overflow when
    taking its absolute, use an unsigned type for the result of the abs
    operation. For example, -INT_MIN will overflow, but -(unsigned)INT_MIN
    is (unsigned)INT_MAX+1U which is the correct value.
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/92978
            * include/std/numeric (__abs_integral): Replace with ...
            (__detail::__absu): New function template that returns an
            unsigned type, guaranteeing it can represent the most
            negative signed value.
            (__detail::__gcd, __detail::__lcm): Require arguments to
            be unsigned and therefore already non-negative.
            (gcd, lcm): Convert arguments to absolute value as unsigned
            type before calling __detail::__gcd or __detail::__lcm.
            * include/experimental/numeric (gcd, lcm): Likewise.
            * testsuite/26_numerics/gcd/gcd_neg.cc: Adjust expected
            errors.
            * testsuite/26_numerics/lcm/lcm_neg.cc: Likewise.
            * testsuite/26_numerics/gcd/92978.cc: New test.
            * testsuite/26_numerics/lcm/92978.cc: New test.
            * testsuite/experimental/numeric/92978.cc: New test.
    
    (cherry picked from commit 82db1a42e9254c9009bbf8ac01366da4d1ab6df5)

diff --git a/libstdc++-v3/include/experimental/numeric b/libstdc++-v3/include/experimental/numeric
index c80848d2ba8..71bfe61b208 100644
--- a/libstdc++-v3/include/experimental/numeric
+++ b/libstdc++-v3/include/experimental/numeric
@@ -53,15 +53,19 @@ inline namespace fundamentals_v2
   /// Greatest common divisor
   template<typename _Mn, typename _Nn>
     constexpr common_type_t<_Mn, _Nn>
-    gcd(_Mn __m, _Nn __n)
+    gcd(_Mn __m, _Nn __n) noexcept
     {
-      static_assert(is_integral_v<_Mn>, "gcd arguments are integers");
-      static_assert(is_integral_v<_Nn>, "gcd arguments are integers");
-      static_assert(!is_same_v<remove_cv_t<_Mn>, bool>,
-		    "gcd arguments are not bools");
-      static_assert(!is_same_v<remove_cv_t<_Nn>, bool>,
-		    "gcd arguments are not bools");
-      return std::__detail::__gcd(__m, __n);
+      static_assert(is_integral_v<_Mn>,
+	  "std::experimental::gcd arguments must be integers");
+      static_assert(is_integral_v<_Nn>,
+	  "std::experimental::gcd arguments must be integers");
+      static_assert(_Mn(2) != _Mn(1),
+	  "std::experimental::gcd arguments must not be bool");
+      static_assert(_Nn(2) != _Nn(1),
+	  "std::experimental::gcd arguments must not be bool");
+      using _Up = make_unsigned_t<common_type_t<_Mn, _Nn>>;
+      return std::__detail::__gcd(std::__detail::__absu<_Up>(__m),
+				  std::__detail::__absu<_Up>(__n));
     }
 
   /// Least common multiple
@@ -69,13 +73,17 @@ inline namespace fundamentals_v2
     constexpr common_type_t<_Mn, _Nn>
     lcm(_Mn __m, _Nn __n)
     {
-      static_assert(is_integral_v<_Mn>, "lcm arguments are integers");
-      static_assert(is_integral_v<_Nn>, "lcm arguments are integers");
-      static_assert(!is_same_v<remove_cv_t<_Mn>, bool>,
-		    "lcm arguments are not bools");
-      static_assert(!is_same_v<remove_cv_t<_Nn>, bool>,
-		    "lcm arguments are not bools");
-      return std::__detail::__lcm(__m, __n);
+      static_assert(is_integral_v<_Mn>,
+	  "std::experimental::lcm arguments must be integers");
+      static_assert(is_integral_v<_Nn>,
+	  "std::experimental::lcm arguments must be integers");
+      static_assert(_Mn(2) != _Mn(1),
+	  "std::experimental::lcm arguments must not be bool");
+      static_assert(_Nn(2) != _Nn(1),
+	  "std::experimental::lcm arguments must not be bool");
+      using _Up = make_unsigned_t<common_type_t<_Mn, _Nn>>;
+      return std::__detail::__lcm(std::__detail::__absu<_Up>(__m),
+				  std::__detail::__absu<_Up>(__n));
     }
 } // namespace fundamentals_v2
 } // namespace experimental
diff --git a/libstdc++-v3/include/std/numeric b/libstdc++-v3/include/std/numeric
index c093df18ecd..3597544ef9f 100644
--- a/libstdc++-v3/include/std/numeric
+++ b/libstdc++-v3/include/std/numeric
@@ -60,6 +60,7 @@
 #include <bits/c++config.h>
 #include <bits/stl_iterator_base_types.h>
 #include <bits/stl_numeric.h>
+#include <ext/numeric_traits.h>
 
 #ifdef _GLIBCXX_PARALLEL
 # include <parallel/numeric>
@@ -83,38 +84,38 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 
 namespace __detail
 {
-  // std::abs is not constexpr and doesn't support unsigned integers.
-  template<typename _Tp>
-    constexpr
-    enable_if_t<__and_<is_integral<_Tp>, is_signed<_Tp>>::value, _Tp>
-    __abs_integral(_Tp __val)
-    { return __val < 0 ? -__val : __val; }
-
-  template<typename _Tp>
-    constexpr
-    enable_if_t<__and_<is_integral<_Tp>, is_unsigned<_Tp>>::value, _Tp>
-    __abs_integral(_Tp __val)
-    { return __val; }
+  // std::abs is not constexpr, doesn't support unsigned integers,
+  // and std::abs(std::numeric_limits<T>::min()) is undefined.
+  template<typename _Up, typename _Tp>
+    constexpr _Up
+    __absu(_Tp __val)
+    {
+      static_assert(is_unsigned<_Up>::value, "result type must be unsigned");
+      static_assert(sizeof(_Up) >= sizeof(_Tp),
+	  "result type must be at least as wide as the input type");
+      return __val < 0 ? -(_Up)__val : (_Up)__val;
+    }
 
-  void __abs_integral(bool) = delete;
+  template<typename _Up> void __absu(bool) = delete;
 
-  template<typename _Mn, typename _Nn>
-    constexpr common_type_t<_Mn, _Nn>
-    __gcd(_Mn __m, _Nn __n)
+  // GCD implementation
+  template<typename _Tp>
+    constexpr _Tp
+    __gcd(_Tp __m, _Tp __n)
     {
-      return __m == 0 ? __detail::__abs_integral(__n)
-	: __n == 0 ? __detail::__abs_integral(__m)
-	: __detail::__gcd(__n, __m % __n);
+      static_assert(is_unsigned<_Tp>::value, "type must be unsigned");
+      return __m == 0 ? __n
+	: __n == 0 ? __m
+	: __detail::__gcd(__n, _Tp(__m % __n));
     }
 
-  /// Least common multiple
-  template<typename _Mn, typename _Nn>
-    constexpr common_type_t<_Mn, _Nn>
-    __lcm(_Mn __m, _Nn __n)
+  // LCM implementation
+  template<typename _Tp>
+    constexpr _Tp
+    __lcm(_Tp __m, _Tp __n)
     {
       return (__m != 0 && __n != 0)
-	? (__detail::__abs_integral(__m) / __detail::__gcd(__m, __n))
-	  * __detail::__abs_integral(__n)
+	? (__m / __detail::__gcd(__m, __n)) * __n
 	: 0;
     }
 } // namespace __detail
@@ -129,29 +130,29 @@ namespace __detail
   /// Greatest common divisor
   template<typename _Mn, typename _Nn>
     constexpr common_type_t<_Mn, _Nn>
-    gcd(_Mn __m, _Nn __n)
+    gcd(_Mn __m, _Nn __n) noexcept
     {
-      static_assert(is_integral_v<_Mn>, "gcd arguments are integers");
-      static_assert(is_integral_v<_Nn>, "gcd arguments are integers");
-      static_assert(!is_same_v<remove_cv_t<_Mn>, bool>,
-		    "gcd arguments are not bools");
-      static_assert(!is_same_v<remove_cv_t<_Nn>, bool>,
-		    "gcd arguments are not bools");
-      return __detail::__gcd(__m, __n);
+      static_assert(is_integral_v<_Mn>, "std::gcd arguments must be integers");
+      static_assert(is_integral_v<_Nn>, "std::gcd arguments must be integers");
+      static_assert(_Mn(2) != _Mn(1), "std::gcd arguments must not be bool");
+      static_assert(_Nn(2) != _Nn(1), "std::gcd arguments must not be bool");
+      using _Up = make_unsigned_t<common_type_t<_Mn, _Nn>>;
+      return __detail::__gcd(__detail::__absu<_Up>(__m),
+			     __detail::__absu<_Up>(__n));
     }
 
   /// Least common multiple
   template<typename _Mn, typename _Nn>
     constexpr common_type_t<_Mn, _Nn>
-    lcm(_Mn __m, _Nn __n)
+    lcm(_Mn __m, _Nn __n) noexcept
     {
-      static_assert(is_integral_v<_Mn>, "lcm arguments are integers");
-      static_assert(is_integral_v<_Nn>, "lcm arguments are integers");
-      static_assert(!is_same_v<remove_cv_t<_Mn>, bool>,
-		    "lcm arguments are not bools");
-      static_assert(!is_same_v<remove_cv_t<_Nn>, bool>,
-		    "lcm arguments are not bools");
-      return __detail::__lcm(__m, __n);
+      static_assert(is_integral_v<_Mn>, "std::lcm arguments must be integers");
+      static_assert(is_integral_v<_Nn>, "std::lcm arguments must be integers");
+      static_assert(_Mn(2) == 2, "std::lcm arguments must not be bool");
+      static_assert(_Nn(2) == 2, "std::lcm arguments must not be bool");
+      using _Up = make_unsigned_t<common_type_t<_Mn, _Nn>>;
+      return __detail::__lcm(__detail::__absu<_Up>(__m),
+			     __detail::__absu<_Up>(__n));
     }
 
 #endif // C++17
diff --git a/libstdc++-v3/testsuite/26_numerics/gcd/92978.cc b/libstdc++-v3/testsuite/26_numerics/gcd/92978.cc
new file mode 100644
index 00000000000..ddf7237df4c
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/gcd/92978.cc
@@ -0,0 +1,41 @@
+// Copyright (C) 2020 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-std=gnu++17" }
+// { dg-do compile { target c++17 } }
+
+#include <numeric>
+#include <limits.h>
+
+void
+test01()
+{
+  // PR libstdc++/92978
+  static_assert( std::gcd(-120, 10U) == 10 );
+  static_assert( std::gcd(120U, -10) == 10 );
+}
+
+void
+test02()
+{
+  // |INT_MIN| should not be undefined, as long as it fits in the result type.
+  static_assert( std::gcd(INT_MIN, 0LL) == 1LL+INT_MAX );
+  static_assert( std::gcd(0LL, INT_MIN) == 1LL+INT_MAX );
+  static_assert( std::gcd(INT_MIN, 0LL + INT_MIN) == 1LL + INT_MAX );
+  static_assert( std::gcd(INT_MIN, 1LL + INT_MAX) == 1LL + INT_MAX );
+  static_assert( std::gcd(SHRT_MIN, 1U + SHRT_MAX) == 1U + SHRT_MAX );
+}
diff --git a/libstdc++-v3/testsuite/26_numerics/gcd/gcd_neg.cc b/libstdc++-v3/testsuite/26_numerics/gcd/gcd_neg.cc
index 66a74ec20ce..44d6c0a2d7f 100644
--- a/libstdc++-v3/testsuite/26_numerics/gcd/gcd_neg.cc
+++ b/libstdc++-v3/testsuite/26_numerics/gcd/gcd_neg.cc
@@ -46,9 +46,9 @@ test01()
   std::gcd<const int&, const int&>(0.1, 0.1);   // { dg-error "from here" }
 }
 
-// { dg-error "integers" "" { target *-*-* } 134 }
-// { dg-error "integers" "" { target *-*-* } 135 }
-// { dg-error "not bools" "" { target *-*-* } 136 }
-// { dg-error "not bools" "" { target *-*-* } 138 }
+// { dg-error "must be integers" "" { target *-*-* } 135 }
+// { dg-error "must be integers" "" { target *-*-* } 136 }
+// { dg-error "must not be bool" "" { target *-*-* } 137 }
+// { dg-error "must not be bool" "" { target *-*-* } 138 }
 // { dg-prune-output "deleted function" }
-// { dg-prune-output "invalid operands" }
+// { dg-prune-output "incomplete type .*make_unsigned" }
diff --git a/libstdc++-v3/testsuite/26_numerics/lcm/92978.cc b/libstdc++-v3/testsuite/26_numerics/lcm/92978.cc
new file mode 100644
index 00000000000..f178e1e5a36
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/lcm/92978.cc
@@ -0,0 +1,28 @@
+// Copyright (C) 2020 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-options "-std=gnu++17" }
+// { dg-do compile { target c++17 } }
+
+#include <numeric>
+
+void
+test01()
+{
+  // PR libstdc++/92978
+  static_assert( std::lcm(-42, 21U) == 42U );
+}
diff --git a/libstdc++-v3/testsuite/26_numerics/lcm/lcm_neg.cc b/libstdc++-v3/testsuite/26_numerics/lcm/lcm_neg.cc
index 27b2028fd13..e98a305df08 100644
--- a/libstdc++-v3/testsuite/26_numerics/lcm/lcm_neg.cc
+++ b/libstdc++-v3/testsuite/26_numerics/lcm/lcm_neg.cc
@@ -46,9 +46,9 @@ test01()
   std::lcm<const int&, const int&>(0.1, 0.1);   // { dg-error "from here" }
 }
 
-// { dg-error "integers" "" { target *-*-* } 148 }
-// { dg-error "integers" "" { target *-*-* } 149 }
-// { dg-error "not bools" "" { target *-*-* } 150 }
-// { dg-error "not bools" "" { target *-*-* } 152 }
+// { dg-error "must be integers" "" { target *-*-* } 149 }
+// { dg-error "must be integers" "" { target *-*-* } 150 }
+// { dg-error "must not be bool" "" { target *-*-* } 151 }
+// { dg-error "must not be bool" "" { target *-*-* } 152 }
 // { dg-prune-output "deleted function" }
-// { dg-prune-output "invalid operands" }
+// { dg-prune-output "incomplete type .*make_unsigned" }
diff --git a/libstdc++-v3/testsuite/experimental/numeric/92978.cc b/libstdc++-v3/testsuite/experimental/numeric/92978.cc
new file mode 100644
index 00000000000..e2a4b1adefa
--- /dev/null
+++ b/libstdc++-v3/testsuite/experimental/numeric/92978.cc
@@ -0,0 +1,48 @@
+// Copyright (C) 2020 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// <http://www.gnu.org/licenses/>.
+
+// { dg-do compile { target c++14 } }
+
+#include <experimental/numeric>
+#include <limits.h>
+
+void
+test01()
+{
+  // PR libstdc++/92978
+  static_assert( std::experimental::gcd(-120, 10U) == 10,
+      "mixed signed/unsigned" );
+  static_assert( std::experimental::gcd(120U, -10) == 10,
+      "mixed signed/unsigned" );
+
+  static_assert( std::experimental::lcm(-42, 21U) == 42U );
+}
+
+void
+test02()
+{
+  static_assert( std::experimental::gcd(INT_MIN, 0LL) == 1LL+INT_MAX,
+      "|INT_MIN| should not be undefined as long as it fits in the result" );
+  static_assert( std::experimental::gcd(0LL, INT_MIN) == 1LL+INT_MAX,
+      "|INT_MIN| should not be undefined" );
+  static_assert( std::experimental::gcd(INT_MIN, 0LL + INT_MIN) == 1LL + INT_MAX,
+      "|INT_MIN| should not be undefined" );
+  static_assert( std::experimental::gcd(INT_MIN, 1LL + INT_MAX) == 1LL + INT_MAX,
+      "|INT_MIN| should not be undefined" );
+  static_assert( std::experimental::gcd(SHRT_MIN, 1U + SHRT_MAX) == 1U + SHRT_MAX,
+      "|SHRT_MIN| should not be undefined" );
+}

commit 3182e62d8c2fc4ffb082c272f568e9c5ccdb06f3
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Nov 17 00:17:43 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 69155b9380a..0ad54ab67bd 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201116
+20201117
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index abfc75d2b5e..2cb3a625d5b 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,25 @@
+2020-11-16  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-08-28  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/92978
+	* include/std/numeric (__abs_integral): Replace with ...
+	(__detail::__absu): New function template that returns an
+	unsigned type, guaranteeing it can represent the most
+	negative signed value.
+	(__detail::__gcd, __detail::__lcm): Require arguments to
+	be unsigned and therefore already non-negative.
+	(gcd, lcm): Convert arguments to absolute value as unsigned
+	type before calling __detail::__gcd or __detail::__lcm.
+	* include/experimental/numeric (gcd, lcm): Likewise.
+	* testsuite/26_numerics/gcd/gcd_neg.cc: Adjust expected
+	errors.
+	* testsuite/26_numerics/lcm/lcm_neg.cc: Likewise.
+	* testsuite/26_numerics/gcd/92978.cc: New test.
+	* testsuite/26_numerics/lcm/92978.cc: New test.
+	* testsuite/experimental/numeric/92978.cc: New test.
+
 2020-11-09  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit ff3bb57646fb49090ce84b05bda5003b8f33fc07
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Tue Nov 17 12:53:08 2020 +0000

    AArch64: Fix overflow in memcopy expansion on aarch64.
    
    This a partial backport for 0f801e0b6cc9f67c9a8983127e23161f6025c5b6 which fixes
    a truncation error for the inline memcopy on AArch64 on GCC-8.
    
    gcc/ChangeLog:
    
            PR target/97535
            * config/aarch64/aarch64.c (aarch64_expand_movme): Use
            unsigned HOST_WIDE_INT.
    
    gcc/testsuite/ChangeLog:
    
            PR target/97535
            * gcc.target/aarch64/pr97535.c: New test.

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 72c11e35659..8faadabc996 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -15968,7 +15968,7 @@ aarch64_copy_one_block_and_progress_pointers (rtx *src, rtx *dst,
 bool
 aarch64_expand_movmem (rtx *operands)
 {
-  unsigned int n;
+  unsigned HOST_WIDE_INT n;
   rtx dst = operands[0];
   rtx src = operands[1];
   rtx base;
diff --git a/gcc/testsuite/gcc.target/aarch64/pr97535.c b/gcc/testsuite/gcc.target/aarch64/pr97535.c
new file mode 100644
index 00000000000..55586c6e5c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr97535.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! ilp32 } } } */
+
+#include <string.h>
+
+#define SIZE 0xFF00000000
+
+extern char raw_buffer[SIZE];
+
+void setRaw(const void *raw)
+{
+        memcpy(raw_buffer, raw, SIZE);
+}
+
+/* At any optimization level this should be a function call
+   and not inlined.  */
+/* { dg-final { scan-assembler "bl\tmemcpy" } } */

commit 3ee527923b1ce92c6b16c587d072720a6c813c95
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Tue Nov 17 18:16:45 2020 +0000

    aarch64: Clear canary value after stack_protect_test [PR96191]
    
    The stack_protect_test patterns were leaving the canary value in the
    temporary register, meaning that it was often still in registers on
    return from the function.  An attacker might therefore have been
    able to use it to defeat stack-smash protection for a later function.
    
    gcc/
            PR target/96191
            * config/aarch64/aarch64.md (stack_protect_test_<mode>): Set the
            CC register directly, instead of a GPR.  Replace the original GPR
            destination with an extra scratch register.  Zero out operand 3
            after use.
            (stack_protect_test): Update accordingly.
    
    gcc/testsuite/
            PR target/96191
            * gcc.target/aarch64/stack-protector-1.c: New test.
            * gcc.target/aarch64/stack-protector-2.c: Likewise.
    
    (cherry picked from commit fe1a26429038d7cd17abc53f96a6f3e2639b605f)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 9fc555c4006..ea1319c56a4 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -5995,35 +5995,30 @@
    (match_operand 2)]
   ""
 {
-  rtx result;
   machine_mode mode = GET_MODE (operands[0]);
 
-  result = gen_reg_rtx(mode);
-
   emit_insn ((mode == DImode
-	      ? gen_stack_protect_test_di
-	      : gen_stack_protect_test_si) (result,
-					    operands[0],
-					    operands[1]));
-
-  if (mode == DImode)
-    emit_jump_insn (gen_cbranchdi4 (gen_rtx_EQ (VOIDmode, result, const0_rtx),
-				    result, const0_rtx, operands[2]));
-  else
-    emit_jump_insn (gen_cbranchsi4 (gen_rtx_EQ (VOIDmode, result, const0_rtx),
-				    result, const0_rtx, operands[2]));
+	     ? gen_stack_protect_test_di
+	     : gen_stack_protect_test_si) (operands[0], operands[1]));
+
+  rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
+  emit_jump_insn (gen_condjump (gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx),
+				cc_reg, operands[2]));
   DONE;
 })
 
+;; DO NOT SPLIT THIS PATTERN.  It is important for security reasons that the
+;; canary value does not live beyond the end of this sequence.
 (define_insn "stack_protect_test_<mode>"
-  [(set (match_operand:PTR 0 "register_operand" "=r")
-	(unspec:PTR [(match_operand:PTR 1 "memory_operand" "m")
-		     (match_operand:PTR 2 "memory_operand" "m")]
-	 UNSPEC_SP_TEST))
+  [(set (reg:CC CC_REGNUM)
+	(unspec:CC [(match_operand:PTR 0 "memory_operand" "m")
+		    (match_operand:PTR 1 "memory_operand" "m")]
+		   UNSPEC_SP_TEST))
+   (clobber (match_scratch:PTR 2 "=&r"))
    (clobber (match_scratch:PTR 3 "=&r"))]
   ""
-  "ldr\t%<w>3, %1\;ldr\t%<w>0, %2\;eor\t%<w>0, %<w>3, %<w>0"
-  [(set_attr "length" "12")
+  "ldr\t%<w>2, %0\;ldr\t%<w>3, %1\;subs\t%<w>2, %<w>2, %<w>3\;mov\t%3, 0"
+  [(set_attr "length" "16")
    (set_attr "type" "multiple")])
 
 ;; Write Floating-point Control Register.
diff --git a/gcc/testsuite/gcc.target/aarch64/stack-protector-1.c b/gcc/testsuite/gcc.target/aarch64/stack-protector-1.c
new file mode 100644
index 00000000000..73e83bc413f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/stack-protector-1.c
@@ -0,0 +1,89 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fstack_protector } */
+/* { dg-options "-fstack-protector-all -O2" } */
+
+extern volatile long *stack_chk_guard_ptr;
+
+volatile long *
+get_ptr (void)
+{
+  return stack_chk_guard_ptr;
+}
+
+void __attribute__ ((noipa))
+f (void)
+{
+  volatile int x;
+  x = 1;
+  x += 1;
+}
+
+#define CHECK(REG) "\tcmp\tx0, " #REG "\n\tbeq\t1f\n"
+
+asm (
+"	.pushsection .data\n"
+"	.align	3\n"
+"	.globl	stack_chk_guard_ptr\n"
+"stack_chk_guard_ptr:\n"
+#if __ILP32__
+"	.word	__stack_chk_guard\n"
+#else
+"	.xword	__stack_chk_guard\n"
+#endif
+"	.weak	__stack_chk_guard\n"
+"__stack_chk_guard:\n"
+"	.word	0xdead4321\n"
+"	.word	0xbeef8765\n"
+"	.text\n"
+"	.globl	main\n"
+"	.type	main, %function\n"
+"main:\n"
+"	bl	get_ptr\n"
+"	str	x0, [sp, #-16]!\n"
+"	bl	f\n"
+"	str	x0, [sp, #8]\n"
+"	ldr	x0, [sp]\n"
+#if __ILP32__
+"	ldr     w0, [x0]\n"
+#else
+"	ldr     x0, [x0]\n"
+#endif
+	CHECK (x1)
+	CHECK (x2)
+	CHECK (x3)
+	CHECK (x4)
+	CHECK (x5)
+	CHECK (x6)
+	CHECK (x7)
+	CHECK (x8)
+	CHECK (x9)
+	CHECK (x10)
+	CHECK (x11)
+	CHECK (x12)
+	CHECK (x13)
+	CHECK (x14)
+	CHECK (x15)
+	CHECK (x16)
+	CHECK (x17)
+	CHECK (x18)
+	CHECK (x19)
+	CHECK (x20)
+	CHECK (x21)
+	CHECK (x22)
+	CHECK (x23)
+	CHECK (x24)
+	CHECK (x25)
+	CHECK (x26)
+	CHECK (x27)
+	CHECK (x28)
+	CHECK (x29)
+	CHECK (x30)
+"	ldr	x1, [sp]\n"
+	CHECK (x1)
+"	mov	x0, #0\n"
+"	b	exit\n"
+"1:\n"
+"	b	abort\n"
+"	.size	main, .-main\n"
+"	.popsection"
+);
diff --git a/gcc/testsuite/gcc.target/aarch64/stack-protector-2.c b/gcc/testsuite/gcc.target/aarch64/stack-protector-2.c
new file mode 100644
index 00000000000..266c36fdbc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/stack-protector-2.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fstack_protector } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-fstack-protector-all -O2 -fpic" } */
+
+#include "stack-protector-1.c"

commit 44337fbf592ba8498a5e614515d42c2beba3dcc8
Author: Sebastian Pop <spop@amazon.com>
Date:   Tue Nov 17 16:00:51 2020 +0000

    add --with-tune configure flag
    
    fixes a configure error on Arm64 when passing --with-tune=... to configure:
    ```
    This target does not support --with-tune.
    Valid --with options are: abi cpu arch
    ```
    The missing flag sets target tuning to a different value than generic tuning.
    
    gcc/
            * config.gcc: Add --with-tune to AArch64 configure flags.
    
    (cherry picked from commit 04dedd18141ccf42e59f7f5f0abc3b86dd63bdb9)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 47cfce25dee..4c4c09b6445 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3703,9 +3703,8 @@ fi
 supported_defaults=
 case "${target}" in
 	aarch64*-*-*)
-		supported_defaults="abi cpu arch"
-		for which in cpu arch; do
-
+		supported_defaults="abi cpu arch tune"
+		for which in cpu arch tune; do
 			eval "val=\$with_$which"
 			base_val=`echo $val | sed -e 's/\+.*//'`
 			ext_val=`echo $val | sed -e 's/[a-z0-9.-]\+//'`

commit 87fd84e59dcd9f0b2270e19015e7fa632de151e0
Author: Sebastian Pop <spop@amazon.com>
Date:   Tue Nov 17 18:56:15 2020 +0000

    add --with-{cpu,arch,tune}-{32,64} as alias flags for --with-{cpu,arch,tune}
    
    gcc/
            * config.gcc: add configure flags --with-{cpu,arch,tune}-{32,64}
            as alias flags for --with-{cpu,arch,tune} on AArch64.
            * doc/install.texi: Document new flags for aarch64.
    
    (cherry picked from commit 61ef34c503443dadc0744c5150256b90d138db0a)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 4c4c09b6445..dcd1c503cee 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3703,7 +3703,25 @@ fi
 supported_defaults=
 case "${target}" in
 	aarch64*-*-*)
-		supported_defaults="abi cpu arch tune"
+		supported_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64"
+		if test x$with_cpu_64 != x && test x$with_cpu = x; then
+			with_cpu=$with_cpu_64
+		fi
+		if test x$with_cpu_32 != x && test x$with_cpu = x; then
+			with_cpu=$with_cpu_32
+		fi
+		if test x$with_arch_64 != x && test x$with_arch = x; then
+			with_arch=$with_arch_64
+		fi
+		if test x$with_arch_32 != x && test x$with_arch = x; then
+			with_arch=$with_arch_32
+		fi
+		if test x$with_tune_64 != x && test x$with_tune = x; then
+			with_tune=$with_tune_64
+		fi
+		if test x$with_tune_32 != x && test x$with_tune = x; then
+			with_tune=$with_tune_32
+		fi
 		for which in cpu arch tune; do
 			eval "val=\$with_$which"
 			base_val=`echo $val | sed -e 's/\+.*//'`
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 686191f8409..1571447aa2b 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1263,7 +1263,7 @@ Specify which cpu variant the compiler should generate code for by default.
 This option is only supported on some targets, including ARC, ARM, i386, M68k,
 PowerPC, and SPARC@.  It is mandatory for ARC@.  The @option{--with-cpu-32} and
 @option{--with-cpu-64} options specify separate default CPUs for
-32-bit and 64-bit modes; these options are only supported for i386,
+32-bit and 64-bit modes; these options are only supported for aarch64, i386,
 x86-64, PowerPC, and SPARC@.
 
 @item --with-schedule=@var{cpu}

commit ba0caa157c91c7a63993b274ea0c6b33218069cc
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Nov 18 00:17:54 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 973329a6330..cc8cfe41cac 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,37 @@
+2020-11-17  Sebastian Pop  <spop@amazon.com>
+
+	Backported from master:
+	2020-11-17  Sebastian Pop  <spop@amazon.com>
+
+	* config.gcc: add configure flags --with-{cpu,arch,tune}-{32,64}
+	as alias flags for --with-{cpu,arch,tune} on AArch64.
+	* doc/install.texi: Document new flags for aarch64.
+
+2020-11-17  Sebastian Pop  <spop@amazon.com>
+
+	Backported from master:
+	2020-11-17  Sebastian Pop  <spop@amazon.com>
+
+	* config.gcc: Add --with-tune to AArch64 configure flags.
+
+2020-11-17  Richard Sandiford  <richard.sandiford@arm.com>
+
+	Backported from master:
+	2020-08-05  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/96191
+	* config/aarch64/aarch64.md (stack_protect_test_<mode>): Set the
+	CC register directly, instead of a GPR.  Replace the original GPR
+	destination with an extra scratch register.  Zero out operand 3
+	after use.
+	(stack_protect_test): Update accordingly.
+
+2020-11-17  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/97535
+	* config/aarch64/aarch64.c (aarch64_expand_movme): Use
+	unsigned HOST_WIDE_INT.
+
 2020-10-22  Andreas Krebbel  <krebbel@linux.ibm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0ad54ab67bd..6ee7c2ae987 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201117
+20201118
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 29aa2d5497c..2b9e0da5d7c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2020-11-17  Richard Sandiford  <richard.sandiford@arm.com>
+
+	Backported from master:
+	2020-08-05  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/96191
+	* gcc.target/aarch64/stack-protector-1.c: New test.
+	* gcc.target/aarch64/stack-protector-2.c: Likewise.
+
+2020-11-17  Tamar Christina  <tamar.christina@arm.com>
+
+	PR target/97535
+	* gcc.target/aarch64/pr97535.c: New test.
+
 2020-11-06  Peter Bergner  <bergner@linux.ibm.com>
 
 	Backported from master:

commit f80afc3259680115d7fc090713c54c1bf43aca34
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Nov 19 00:17:50 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6ee7c2ae987..f5efa497de1 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201118
+20201119

commit 78fb37bdf9dc18b715fcd31d2443569a9ff2618a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Nov 20 00:17:55 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f5efa497de1..e732e26b1c7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201119
+20201120

commit 53c17956412c0c3854f9f202a59c4923b0a13a83
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Nov 21 00:17:48 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e732e26b1c7..1867e9391c3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201120
+20201121

commit 2e7de78bda34c4373ede147c5464012aa2a2f0e8
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Nov 22 00:17:42 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 1867e9391c3..091f0200bdd 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201121
+20201122

commit 4e676ee9fb8c030f84de26889bd0162bf5df6a58
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Nov 23 00:17:39 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 091f0200bdd..62b5bb21775 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201122
+20201123

commit 7642c1e7cf6c2f318145a08b570ee73d1506a84c
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Nov 24 00:18:01 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 62b5bb21775..b33fafcefbd 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201123
+20201124

commit a2bdff4f24d9065791e6d8820004772b9fe0c4c1
Author: Jason Merrill <jason@redhat.com>
Date:   Wed Jun 3 23:50:06 2020 -0400

    c++: Fix FE devirt with diamond inheritance [PR95158]
    
    This started breaking in GCC 8 because of the fix for PR15272; after that
    change, we (correctly) remember the lookup from template parsing time that
    found Base::foo through the non-dependent MiddleB base, and so we overlook
    the overrider in MiddleA.  But given that, the devirtualization condition
    from the fix for PR59031 is insufficient; we know that d has to be a
    Derived, and we found Base::foo in Base, but forcing a non-virtual call
    gets the wrong function.
    
    Fixed by removing the PR59031 code, and instead looking up the overrider in
    BINFO_VIRTUALS.
    
    gcc/cp/ChangeLog:
    
            PR c++/95158
            * class.c (lookup_vfn_in_binfo): New.
            * call.c (build_over_call): Use it.
            (build_new_method_call_1): Don't set LOOKUP_NONVIRTUAL.
            * cp-tree.h (resolves_to_fixed_type_p): Add default argument.
            (lookup_vfn_in_binfo): Declare.
    
    gcc/testsuite/ChangeLog:
    
            PR c++/95158
            * g++.dg/template/virtual5.C: New test.

diff --git a/gcc/cp/call.c b/gcc/cp/call.c
index 22de5c70425..196eeafe8e8 100644
--- a/gcc/cp/call.c
+++ b/gcc/cp/call.c
@@ -7905,6 +7905,15 @@ build_over_call (struct z_candidate *cand, int flags, tsubst_flags_t complain)
 	  || CLASSTYPE_FINAL (TYPE_METHOD_BASETYPE (TREE_TYPE (fn))))
 	flags |= LOOKUP_NONVIRTUAL;
 
+      /* If we know the dynamic type of the object, look up the final overrider
+	 in the BINFO.  */
+      if (DECL_VINDEX (fn) && (flags & LOOKUP_NONVIRTUAL) == 0
+	  && resolves_to_fixed_type_p (arg))
+	{
+	  fn = lookup_vfn_in_binfo (DECL_VINDEX (fn), cand->conversion_path);
+	  flags |= LOOKUP_NONVIRTUAL;
+	}
+
       /* [class.mfct.nonstatic]: If a nonstatic member function of a class
 	 X is called for an object that is not of type X, or of a type
 	 derived from X, the behavior is undefined.
@@ -9387,17 +9396,6 @@ build_new_method_call_1 (tree instance, tree fns, vec<tree, va_gc> **args,
 
 	  if (call != error_mark_node)
 	    {
-	      /* Optimize away vtable lookup if we know that this
-		 function can't be overridden.  We need to check if
-		 the context and the type where we found fn are the same,
-		 actually FN might be defined in a different class
-		 type because of a using-declaration. In this case, we
-		 do not want to perform a non-virtual call.  */
-	      if (DECL_VINDEX (fn) && ! (flags & LOOKUP_NONVIRTUAL)
-		  && same_type_ignoring_top_level_qualifiers_p
-		  (DECL_CONTEXT (fn), BINFO_TYPE (binfo))
-		  && resolves_to_fixed_type_p (instance, 0))
-		flags |= LOOKUP_NONVIRTUAL;
               if (explicit_targs)
                 flags |= LOOKUP_EXPLICIT_TMPL_ARGS;
 	      /* Now we know what function is being called.  */
diff --git a/gcc/cp/class.c b/gcc/cp/class.c
index 07ce48917f6..b06aa6faedf 100644
--- a/gcc/cp/class.c
+++ b/gcc/cp/class.c
@@ -2395,6 +2395,20 @@ get_vcall_index (tree fn, tree type)
   gcc_unreachable ();
 }
 
+/* Given a DECL_VINDEX of a virtual function found in BINFO, return the final
+   overrider at that index in the vtable.  This should only be used when we
+   know that BINFO is correct for the dynamic type of the object.  */
+
+tree
+lookup_vfn_in_binfo (tree idx, tree binfo)
+{
+  int ix = tree_to_shwi (idx);
+  if (TARGET_VTABLE_USES_DESCRIPTORS)
+    ix /= MAX (TARGET_VTABLE_USES_DESCRIPTORS, 1);
+  tree virtuals = BINFO_VIRTUALS (binfo);
+  return TREE_VALUE (chain_index (ix, virtuals));
+}
+
 /* Update an entry in the vtable for BINFO, which is in the hierarchy
    dominated by T.  FN is the old function; VIRTUALS points to the
    corresponding position in the new BINFO_VIRTUALS list.  IX is the index
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 964b8b7ecb8..1456c8ef5f2 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -6144,7 +6144,7 @@ extern tree outermost_open_class		(void);
 extern tree current_nonlambda_class_type	(void);
 extern tree finish_struct			(tree, tree);
 extern void finish_struct_1			(tree);
-extern int resolves_to_fixed_type_p		(tree, int *);
+extern int resolves_to_fixed_type_p		(tree, int * = NULL);
 extern void init_class_processing		(void);
 extern int is_empty_class			(tree);
 extern bool is_really_empty_class		(tree);
@@ -6158,6 +6158,7 @@ extern void pop_lang_context			(void);
 extern tree instantiate_type			(tree, tree, tsubst_flags_t);
 extern void build_self_reference		(void);
 extern int same_signature_p			(const_tree, const_tree);
+extern tree lookup_vfn_in_binfo			(tree, tree);
 extern void maybe_add_class_template_decl_list	(tree, tree, int);
 extern void unreverse_member_declarations	(tree);
 extern void invalidate_class_lookup_cache	(void);
diff --git a/gcc/testsuite/g++.dg/template/virtual5.C b/gcc/testsuite/g++.dg/template/virtual5.C
new file mode 100644
index 00000000000..4d9044579ca
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/virtual5.C
@@ -0,0 +1,31 @@
+// PR c++/95158
+// { dg-do run }
+
+class Base {
+    public:
+        virtual void foo()=0;
+};
+
+template <typename T>
+class MiddleA : virtual public Base {
+    public:
+        virtual void foo() {}
+};
+
+class MiddleB : virtual public Base {};
+
+template <typename T>
+class Derived : public MiddleA<T>, public MiddleB {
+    public:
+        void bar()
+        {
+	  Derived d;
+	  d.foo();
+        }
+};
+
+int main()
+{
+  Derived<void> a;
+  a.bar(); // Instantiate the template
+}

commit ca8325441a6bb06292db9f165607d4e395f46c4b
Author: Jason Merrill <jason@redhat.com>
Date:   Fri Nov 20 15:20:45 2020 -0500

    dwarf2: ICE with local class in unused function [PR97918]
    
    Here, since we only mention bar<B>, we never emit debug information for it.
    But we do emit debug information for H<J>::h, so we need to refer to the
    debug info for bar<B>::J even though there is no bar<B>.  We deal with this
    sort of thing in dwarf2out with the limbo_die_list; parentless dies like J
    get attached to the CU at EOF.  But here, we were flushing the limbo list,
    then generating the template argument DIE for H<J> that refers to J, which
    adds J to the limbo list, too late to be flushed.  So let's flush a little
    later.
    
    gcc/ChangeLog:
    
            PR c++/97918
            * dwarf2out.c (dwarf2out_early_finish): flush_limbo_die_list
            after gen_scheduled_generic_parms_dies.
    
    gcc/testsuite/ChangeLog:
    
            PR c++/97918
            * g++.dg/debug/localclass2.C: New test.

diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index 467de650394..b1dd03cf0ba 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -31928,13 +31928,13 @@ dwarf2out_early_finish (const char *filename)
      emit full debugging info for them.  */
   retry_incomplete_types ();
 
+  gen_scheduled_generic_parms_dies ();
+  gen_remaining_tmpl_value_param_die_attribute ();
+
   /* The point here is to flush out the limbo list so that it is empty
      and we don't need to stream it for LTO.  */
   flush_limbo_die_list ();
 
-  gen_scheduled_generic_parms_dies ();
-  gen_remaining_tmpl_value_param_die_attribute ();
-
   /* Add DW_AT_linkage_name for all deferred DIEs.  */
   for (limbo_die_node *node = deferred_asm_name; node; node = node->next)
     {
diff --git a/gcc/testsuite/g++.dg/debug/localclass2.C b/gcc/testsuite/g++.dg/debug/localclass2.C
new file mode 100644
index 00000000000..9897eec5d2d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/debug/localclass2.C
@@ -0,0 +1,24 @@
+// PR c++/97918
+// { dg-do compile { target c++11 } }
+// { dg-require-effective-target lto }
+// { dg-additional-options "-g -O -flto" }
+
+namespace { class A {}; }
+class B {};
+template <typename T> struct H {
+  constexpr static unsigned h = 0;
+};
+
+template <typename T> A bar ()
+{
+  struct J {
+    static void foo();
+  };
+  H<J>();
+  return A ();
+}
+
+void fn ()
+{
+  bar<B>;			// only mentions the function
+}

commit b49f17753ce6cc915e699fad2c4b458572dbea7c
Author: Martin Liska <mliska@suse.cz>
Date:   Wed Nov 25 07:56:57 2020 +0100

    changelog: fix parsing of a revert commit
    
    contrib/ChangeLog:
    
            * gcc-changelog/git_commit.py: Use revert_regex instead
            of string prefix.  Convert sets to literals.

diff --git a/contrib/gcc-changelog/git_commit.py b/contrib/gcc-changelog/git_commit.py
index 80ae0b2a77d..5f856660bb3 100755
--- a/contrib/gcc-changelog/git_commit.py
+++ b/contrib/gcc-changelog/git_commit.py
@@ -19,7 +19,7 @@
 import os
 import re
 
-changelog_locations = set([
+changelog_locations = {
     'config',
     'contrib',
     'contrib/header-tools',
@@ -72,9 +72,9 @@ changelog_locations = set([
     'libvtv',
     'lto-plugin',
     'maintainer-scripts',
-    'zlib'])
+    'zlib'}
 
-bug_components = set([
+bug_components = {
     'ada',
     'analyzer',
     'boehm-gc',
@@ -123,9 +123,9 @@ bug_components = set([
     'testsuite',
     'translation',
     'tree-optimization',
-    'web'])
+    'web'}
 
-ignored_prefixes = [
+ignored_prefixes = {
     'gcc/d/dmd/',
     'gcc/go/gofrontend/',
     'gcc/testsuite/gdc.test/',
@@ -134,18 +134,18 @@ ignored_prefixes = [
     'libphobos/libdruntime/',
     'libphobos/src/',
     'libsanitizer/',
-    ]
+    }
 
-wildcard_prefixes = [
+wildcard_prefixes = {
     'gcc/testsuite/',
     'libstdc++-v3/doc/html/'
-    ]
+    }
 
-misc_files = [
+misc_files = {
     'gcc/DATESTAMP',
     'gcc/BASE-VER',
     'gcc/DEV-PHASE'
-    ]
+    }
 
 author_line_regex = \
         re.compile(r'^(?P<datetime>\d{4}-\d{2}-\d{2})\ {2}(?P<name>.*  <.*>)')
@@ -157,12 +157,12 @@ star_prefix_regex = re.compile(r'\t\*(?P<spaces>\ *)(?P<content>.*)')
 end_of_location_regex = re.compile(r'[\[<(:]')
 item_empty_regex = re.compile(r'\t(\* \S+ )?\(\S+\):\s*$')
 item_parenthesis_regex = re.compile(r'\t(\*|\(\S+\):)')
+revert_regex = re.compile(r'This reverts commit (?P<hash>\w+).$')
 
 LINE_LIMIT = 100
 TAB_WIDTH = 8
 CO_AUTHORED_BY_PREFIX = 'co-authored-by: '
 CHERRY_PICK_PREFIX = '(cherry picked from commit '
-REVERT_PREFIX = 'This reverts commit '
 
 REVIEW_PREFIXES = ('reviewed-by: ', 'reviewed-on: ', 'signed-off-by: ',
                    'acked-by: ', 'tested-by: ', 'reported-by: ',
@@ -274,8 +274,9 @@ class GitCommit:
 
         # Identify first if the commit is a Revert commit
         for line in self.info.lines:
-            if line.startswith(REVERT_PREFIX):
-                self.revert_commit = line[len(REVERT_PREFIX):].rstrip('.')
+            m = revert_regex.match(line)
+            if m:
+                self.revert_commit = m.group('hash')
                 break
         if self.revert_commit:
             self.info = self.commit_to_info_hook(self.revert_commit)

commit 3e7d58bc1271ce3f0c67eabba52e8241e150fb47
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Nov 25 09:35:18 2020 +0000

    Daily bump.

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index c1239f86307..991500df3e2 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,8 @@
+2020-11-25  Martin Liska  <mliska@suse.cz>
+
+	* gcc-changelog/git_commit.py: Use revert_regex instead
+	of string prefix.  Convert sets to literals.
+
 2020-11-06  Martin Liska  <mliska@suse.cz>
 
 	* gcc-changelog/git_commit.py: Sync.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cc8cfe41cac..c4e3b6aea40 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-11-24  Jason Merrill  <jason@redhat.com>
+
+	PR c++/97918
+	* dwarf2out.c (dwarf2out_early_finish): flush_limbo_die_list
+	after gen_scheduled_generic_parms_dies.
+
 2020-11-17  Sebastian Pop  <spop@amazon.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b33fafcefbd..a2b688586c3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201124
+20201125
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index d2396105afa..d0dd8bd8f0e 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,12 @@
+2020-11-24  Jason Merrill  <jason@redhat.com>
+
+	PR c++/95158
+	* class.c (lookup_vfn_in_binfo): New.
+	* call.c (build_over_call): Use it.
+	(build_new_method_call_1): Don't set LOOKUP_NONVIRTUAL.
+	* cp-tree.h (resolves_to_fixed_type_p): Add default argument.
+	(lookup_vfn_in_binfo): Declare.
+
 2020-09-17  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2b9e0da5d7c..33cb936e2db 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2020-11-24  Jason Merrill  <jason@redhat.com>
+
+	PR c++/97918
+	* g++.dg/debug/localclass2.C: New test.
+
+2020-11-24  Jason Merrill  <jason@redhat.com>
+
+	PR c++/95158
+	* g++.dg/template/virtual5.C: New test.
+
 2020-11-17  Richard Sandiford  <richard.sandiford@arm.com>
 
 	Backported from master:

commit d4fcc365700f94fd15c67b30a3051aeabbb767bc
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Tue Jun 2 16:44:41 2020 +0100

    aarch64: fix return address access with pac [PR94891][PR94791]
    
    This is a big hammer fix for __builtin_return_address (PR target/94891)
    returning signed addresses (sometimes, depending on wether lr happens
    to be signed or not at the time of call which depends on optimizations),
    and similarly -pg may pass signed return address to _mcount
    (PR target/94791).
    
    At the time of return address expansion we don't know if it's signed or
    not so it is done unconditionally.
    
    2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
    
    gcc/ChangeLog:
    
            PR target/94891
            PR target/94791
            * config/aarch64/aarch64-protos.h (aarch64_return_addr_rtx): Declare.
            * config/aarch64/aarch64.c (aarch64_return_addr_rtx): New.
            (aarch64_return_addr): Use aarch64_return_addr_rtx.
            * config/aarch64/aarch64.h (PROFILE_HOOK): Likewise.
    
    (cherry picked from commit 463a54e5d4956143f81c1f23b91cbd2d93855741)

diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index 0f1dc75a27f..ba0c5a55f4d 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -427,6 +427,7 @@ int aarch64_vec_fpconst_pow_of_2 (rtx);
 rtx aarch64_eh_return_handler_rtx (void);
 rtx aarch64_mask_from_zextract_ops (rtx, rtx);
 const char *aarch64_output_move_struct (rtx *operands);
+rtx aarch64_return_addr_rtx (void);
 rtx aarch64_return_addr (int, rtx);
 rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT);
 bool aarch64_simd_mem_operand_p (rtx);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 8faadabc996..f8ee68ad9ef 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -7624,6 +7624,24 @@ aarch64_initial_elimination_offset (unsigned from, unsigned to)
   return cfun->machine->frame.frame_size;
 }
 
+
+/* Get return address without mangling.  */
+
+rtx
+aarch64_return_addr_rtx (void)
+{
+  rtx val = get_hard_reg_initial_val (Pmode, LR_REGNUM);
+  /* Note: aarch64_return_address_signing_enabled only
+     works after cfun->machine->frame.laid_out is set,
+     so here we don't know if the return address will
+     be signed or not.  */
+  rtx lr = gen_rtx_REG (Pmode, LR_REGNUM);
+  emit_move_insn (lr, val);
+  emit_insn (GEN_FCN (CODE_FOR_xpaclri) ());
+  return lr;
+}
+
+
 /* Implement RETURN_ADDR_RTX.  We do not support moving back to a
    previous frame.  */
 
@@ -7632,7 +7650,7 @@ aarch64_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
 {
   if (count != 0)
     return const0_rtx;
-  return get_hard_reg_initial_val (Pmode, LR_REGNUM);
+  return aarch64_return_addr_rtx ();
 }
 
 
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 42d61b94c9c..b0b1d423817 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -929,7 +929,7 @@ typedef struct
 #define PROFILE_HOOK(LABEL)						\
   {									\
     rtx fun, lr;							\
-    lr = get_hard_reg_initial_val (Pmode, LR_REGNUM);			\
+    lr = aarch64_return_addr_rtx ();					\
     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);			\
     emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode);		\
   }

commit de7352725acf209ebb3e4c647cd35e176062231a
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Thu Jun 4 13:42:16 2020 +0100

    aarch64: fix __builtin_eh_return with pac-ret [PR94891]
    
    Currently __builtin_eh_return takes a signed return address, which can
    cause ABI and API issues: 1) pointer representation problems if the
    address is passed around before eh return, 2) the source code needs
    pac-ret specific changes and needs to know if pac-ret is used in the
    current frame, 3) signed address may not be representible as void *
    (with ilp32 abi).
    
    Using address signing to protect eh return is ineffective because the
    instruction sequence in the unwinder that starts from the address
    signing and ends with a ret can be used as a return to anywhere gadget.
    Using indirect branch istead of ret with bti j landing pads at the
    target can reduce the potential of such gadget, which also implies
    that __builtin_eh_return should not take a signed address.
    
    This is a big hammer fix to the ABI and API issues: it turns pac-ret
    off for the caller completely (not just on the eh return path).  To
    harden the caller against ROP attacks, it should use indirect branch
    instead of ret, this is not attempted so the patch remains small and
    backportable.
    
    2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
    
    gcc/ChangeLog:
    
            PR target/94891
            * config/aarch64/aarch64.c (aarch64_return_address_signing_enabled):
            Disable return address signing if __builtin_eh_return is used.
    
    gcc/testsuite/ChangeLog:
    
            PR target/94891
            * gcc.target/aarch64/return_address_sign_1.c: Update test.
    
    (cherry picked from commit 2bc95be3bb8c8138e2e87c1c11c84bfede989d61)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index f8ee68ad9ef..e8e73b8ea92 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4446,6 +4446,17 @@ aarch64_return_address_signing_enabled (void)
   /* This function should only be called after frame laid out.   */
   gcc_assert (cfun->machine->frame.laid_out);
 
+  /* Turn return address signing off in any function that uses
+     __builtin_eh_return.  The address passed to __builtin_eh_return
+     is not signed so either it has to be signed (with original sp)
+     or the code path that uses it has to avoid authenticating it.
+     Currently eh return introduces a return to anywhere gadget, no
+     matter what we do here since it uses ret with user provided
+     address. An ideal fix for that is to use indirect branch which
+     can be protected with BTI j (to some extent).  */
+  if (crtl->calls_eh_return)
+    return false;
+
   /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
      if it's LR is pushed onto stack.  */
   return (aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL
diff --git a/gcc/testsuite/gcc.target/aarch64/return_address_sign_1.c b/gcc/testsuite/gcc.target/aarch64/return_address_sign_1.c
index f87c3d28d1e..50cb08fb36c 100644
--- a/gcc/testsuite/gcc.target/aarch64/return_address_sign_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/return_address_sign_1.c
@@ -41,12 +41,12 @@ func3 (int a, int b, int c)
 void __attribute__ ((target ("arch=armv8.3-a")))
 func4 (long offset, void *handler, int *ptr, int imm1, int imm2)
 {
-  /* paciasp */
+  /* no paciasp */
   *ptr = imm1 + foo (imm1) + imm2;
   __builtin_eh_return (offset, handler);
-  /* autiasp */
+  /* no autiasp */
   return;
 }
 
-/* { dg-final { scan-assembler-times "autiasp" 4 } } */
-/* { dg-final { scan-assembler-times "paciasp" 4 } } */
+/* { dg-final { scan-assembler-times "autiasp" 3 } } */
+/* { dg-final { scan-assembler-times "paciasp" 3 } } */

commit d5f58a0287d2bc4c0a84bf63cade069744ce3185
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Thu Jun 4 09:33:35 2020 +0100

    libgcc: fix the handling of return address mangling [PR94891]
    
    Mangling, currently only used on AArch64 for return address signing,
    is an internal representation that should not be exposed via
    
      __builtin_return_address return value,
      __builtin_eh_return handler argument,
      _Unwind_DebugHook handler argument.
    
    Note that a mangled address might not even fit into a void *, e.g.
    with AArch64 ilp32 ABI the return address is stored as 64bit, so
    the mangled return address cannot be accessed via _Unwind_GetPtr.
    
    This patch changes the unwinder hooks as follows:
    
    MD_POST_EXTRACT_ROOT_ADDR is removed: root address comes from
    __builtin_return_address which is not mangled.
    
    MD_POST_EXTRACT_FRAME_ADDR is renamed to MD_DEMANGLE_RETURN_ADDR,
    it now operates on _Unwind_Word instead of void *, so the hook
    should work when return address signing is enabled on AArch64 ilp32.
    (But for that __builtin_aarch64_autia1716 should be fixed to operate
    on 64bit input instead of a void *.)
    
    MD_POST_FROB_EH_HANDLER_ADDR is removed: it is the responsibility of
    __builtin_eh_return to do the mangling if necessary.
    
    2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
    
    libgcc/ChangeLog:
    
            PR target/94891
            * config/aarch64/aarch64-unwind.h (MD_POST_EXTRACT_ROOT_ADDR): Remove.
            (MD_POST_FROB_EH_HANDLER_ADDR): Remove.
            (MD_POST_EXTRACT_FRAME_ADDR): Rename to ...
            (MD_DEMANGLE_RETURN_ADDR): This.
            (aarch64_post_extract_frame_addr): Rename to ...
            (aarch64_demangle_return_addr): This.
            (aarch64_post_frob_eh_handler_addr): Remove.
            * unwind-dw2.c (uw_update_context): Demangle return address.
            (uw_frob_return_addr): Remove.
    
    (cherry picked from commit b097c7a27fb0796b2653a1d003cbf6b7a69d8961)

diff --git a/libgcc/config/aarch64/aarch64-unwind.h b/libgcc/config/aarch64/aarch64-unwind.h
index f3b4cfa3b8c..c219d679807 100644
--- a/libgcc/config/aarch64/aarch64-unwind.h
+++ b/libgcc/config/aarch64/aarch64-unwind.h
@@ -27,22 +27,20 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 
 #define DWARF_REGNUM_AARCH64_RA_STATE 34
 
-#define MD_POST_EXTRACT_ROOT_ADDR(addr)  __builtin_aarch64_xpaclri (addr)
-#define MD_POST_EXTRACT_FRAME_ADDR(context, fs, addr) \
-  aarch64_post_extract_frame_addr (context, fs, addr)
-#define MD_POST_FROB_EH_HANDLER_ADDR(current, target, addr) \
-  aarch64_post_frob_eh_handler_addr (current, target, addr)
+#define MD_DEMANGLE_RETURN_ADDR(context, fs, addr) \
+  aarch64_demangle_return_addr (context, fs, addr)
 #define MD_FROB_UPDATE_CONTEXT(context, fs) \
   aarch64_frob_update_context (context, fs)
 
-/* Do AArch64 private extraction on ADDR based on context info CONTEXT and
-   unwind frame info FS.  If ADDR is signed, we do address authentication on it
-   using CFA of current frame.  */
+/* Do AArch64 private extraction on ADDR_WORD based on context info CONTEXT and
+   unwind frame info FS.  If ADDR_WORD is signed, we do address authentication
+   on it using CFA of current frame.  */
 
 static inline void *
-aarch64_post_extract_frame_addr (struct _Unwind_Context *context,
-				 _Unwind_FrameState *fs, void *addr)
+aarch64_demangle_return_addr (struct _Unwind_Context *context,
+			      _Unwind_FrameState *fs, _Unwind_Word addr_word)
 {
+  void *addr = (void *)addr_word;
   if (fs->regs.reg[DWARF_REGNUM_AARCH64_RA_STATE].loc.offset & 0x1)
     {
       _Unwind_Word salt = (_Unwind_Word) context->cfa;
@@ -52,23 +50,6 @@ aarch64_post_extract_frame_addr (struct _Unwind_Context *context,
     return addr;
 }
 
-/* Do AArch64 private frob on exception handler's address HANDLER_ADDR before
-   installing it into current context CURRENT.  TARGET is currently not used.
-   We need to sign exception handler's address if CURRENT itself is signed.  */
-
-static inline void *
-aarch64_post_frob_eh_handler_addr (struct _Unwind_Context *current,
-				   struct _Unwind_Context *target
-				   ATTRIBUTE_UNUSED,
-				   void *handler_addr)
-{
-  if (current->flags & RA_A_SIGNED_BIT)
-    return __builtin_aarch64_pacia1716 (handler_addr,
-					(_Unwind_Word) current->cfa);
-  else
-    return handler_addr;
-}
-
 /* Do AArch64 private initialization on CONTEXT based on frame info FS.  Mark
    CONTEXT as return address signed if bit 0 of DWARF_REGNUM_AARCH64_RA_STATE is
    set.  */
diff --git a/libgcc/unwind-dw2.c b/libgcc/unwind-dw2.c
index 952288ed5cb..b2e1c526732 100644
--- a/libgcc/unwind-dw2.c
+++ b/libgcc/unwind-dw2.c
@@ -1532,11 +1532,14 @@ uw_update_context (struct _Unwind_Context *context, _Unwind_FrameState *fs)
     {
       /* Compute the return address now, since the return address column
 	 can change from frame to frame.  */
-      context->ra = __builtin_extract_return_addr
-	(_Unwind_GetPtr (context, fs->retaddr_column));
-#ifdef MD_POST_EXTRACT_FRAME_ADDR
-      context->ra = MD_POST_EXTRACT_FRAME_ADDR (context, fs, context->ra);
+      void *ret_addr;
+#ifdef MD_DEMANGLE_RETURN_ADDR
+      _Unwind_Word ra = _Unwind_GetGR (context, fs->retaddr_column);
+      ret_addr = MD_DEMANGLE_RETURN_ADDR (context, fs, ra);
+#else
+      ret_addr = _Unwind_GetPtr (context, fs->retaddr_column);
 #endif
+      context->ra = __builtin_extract_return_addr (ret_addr);
     }
 }
 
@@ -1571,9 +1574,6 @@ uw_init_context_1 (struct _Unwind_Context *context,
 		   void *outer_cfa, void *outer_ra)
 {
   void *ra = __builtin_extract_return_addr (__builtin_return_address (0));
-#ifdef MD_POST_EXTRACT_ROOT_ADDR
-  ra = MD_POST_EXTRACT_ROOT_ADDR (ra);
-#endif
   _Unwind_FrameState fs;
   _Unwind_SpTmp sp_slot;
   _Unwind_Reason_Code code;
@@ -1610,9 +1610,6 @@ uw_init_context_1 (struct _Unwind_Context *context,
      initialization context, then we can't see it in the given
      call frame data.  So have the initialization context tell us.  */
   context->ra = __builtin_extract_return_addr (outer_ra);
-#ifdef MD_POST_EXTRACT_ROOT_ADDR
-  context->ra = MD_POST_EXTRACT_ROOT_ADDR (context->ra);
-#endif
 }
 
 static void _Unwind_DebugHook (void *, void *)
@@ -1635,21 +1632,6 @@ _Unwind_DebugHook (void *cfa __attribute__ ((__unused__)),
 #endif
 }
 
-/* Frob exception handler's address kept in TARGET before installing into
-   CURRENT context.  */
-
-static inline void *
-uw_frob_return_addr (struct _Unwind_Context *current
-		     __attribute__ ((__unused__)),
-		     struct _Unwind_Context *target)
-{
-  void *ret_addr = __builtin_frob_return_addr (target->ra);
-#ifdef MD_POST_FROB_EH_HANDLER_ADDR
-  ret_addr = MD_POST_FROB_EH_HANDLER_ADDR (current, target, ret_addr);
-#endif
-  return ret_addr;
-}
-
 /* Install TARGET into CURRENT so that we can return to it.  This is a
    macro because __builtin_eh_return must be invoked in the context of
    our caller.  FRAMES is a number of frames to be unwind.
@@ -1661,7 +1643,7 @@ uw_frob_return_addr (struct _Unwind_Context *current
   do									\
     {									\
       long offset = uw_install_context_1 ((CURRENT), (TARGET));		\
-      void *handler = uw_frob_return_addr ((CURRENT), (TARGET));	\
+      void *handler = __builtin_frob_return_addr ((TARGET)->ra);	\
       _Unwind_DebugHook ((TARGET)->cfa, handler);			\
       _Unwind_Frames_Extra (FRAMES);					\
       __builtin_eh_return (offset, handler);				\

commit 74bffa9a325f7360dc9d105c2fc5719fe45164d3
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Thu May 28 10:28:30 2020 +0100

    doc: Clarify __builtin_return_address [PR94891]
    
    The expected semantics and valid usage of __builtin_return_address is
    not clear since it exposes implementation internals that are normally
    not meaningful to portable c code.
    
    This documentation change tries to clarify the semantics in case the
    return address is stored in a mangled form. This affects AArch64 when
    pointer authentication is used for the return address signing (i.e.
    -mbranch-protection=pac-ret).
    
    2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
    
    gcc/ChangeLog:
    
            PR target/94891
            * doc/extend.texi: Update the text for  __builtin_return_address.
    
    (cherry picked from commit 6a391e06f953c3390b14020d8cacb6d55f81b2b9)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 08cc1fdddfc..7984606b948 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -10179,18 +10179,31 @@ The @var{level} argument must be a constant integer.
 
 On some machines it may be impossible to determine the return address of
 any function other than the current one; in such cases, or when the top
-of the stack has been reached, this function returns @code{0} or a
-random value.  In addition, @code{__builtin_frame_address} may be used
+of the stack has been reached, this function returns an unspecified
+value.  In addition, @code{__builtin_frame_address} may be used
 to determine if the top of the stack has been reached.
 
 Additional post-processing of the returned value may be needed, see
 @code{__builtin_extract_return_addr}.
 
+The stored representation of the return address in memory may be different
+from the address returned by @code{__builtin_return_address}.  For example,
+on AArch64 the stored address may be mangled with return address signing
+whereas the address returned by @code{__builtin_return_address} is not.
+
 Calling this function with a nonzero argument can have unpredictable
 effects, including crashing the calling program.  As a result, calls
 that are considered unsafe are diagnosed when the @option{-Wframe-address}
 option is in effect.  Such calls should only be made in debugging
 situations.
+
+On targets where code addresses are representable as @code{void *},
+@smallexample
+void *addr = __builtin_extract_return_addr (__builtin_return_address (0));
+@end smallexample
+gives the code address where the current function would return.  For example,
+such an address may be used with @code{dladdr} or other interfaces that work
+with code addresses.
 @end deftypefn
 
 @deftypefn {Built-in Function} {void *} __builtin_extract_return_addr (void *@var{addr})

commit 1dbf117ce5df08e3303f89c0af9e601b2cbd6163
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Thu Jul 2 16:11:04 2020 +0100

    aarch64: Add missing ACLE support for PAC-RET
    
    Define the __ARM_FEATURE_PAC_DEFAULT feature test
    macro when PAC-RET branch protection is enabled.
    
    2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add
            __ARM_FEATURE_PAC_DEFAULT support.
    
    (cherry picked from commit a1faa8e2470b33e92f6274804bf7941fbb6e2d38)

diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index fbcf1d95338..0c9cb2e4bfc 100644
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -159,6 +159,15 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
 
   aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile);
 
+  cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT");
+  if (aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE)
+    {
+      int v = 1;
+      if (aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL)
+	v |= 4;
+      builtin_define_with_int_value ("__ARM_FEATURE_PAC_DEFAULT", v);
+    }
+
   /* Not for ACLE, but required to keep "float.h" correct if we switch
      target between implementations that do or do not support ARMv8.2-A
      16-bit floating-point extensions.  */

commit b4a3e26c329f63c9953f4c4e3141c562bf91ce93
Author: Thomas Schwinge <thomas@codesourcery.com>
Date:   Wed Nov 25 13:03:52 2020 +0100

    Fix templatized C++ OpenACC 'cache' directive ICEs
    
    This has been broken forever, whoops...
    
            gcc/cp/
            * pt.c (tsubst_omp_clauses): Handle 'OMP_CLAUSE__CACHE_'.
            (tsubst_expr): Handle 'OACC_CACHE'.
            gcc/testsuite/
            * c-c++-common/goacc/cache-1.c: Update.
            * c-c++-common/goacc/cache-2.c: Likewise.
            * g++.dg/goacc/cache-1.C: New.
            * g++.dg/goacc/cache-2.C: Likewise.
            libgomp/
            * testsuite/libgomp.oacc-c++/cache-1.C: New.
            * testsuite/libgomp.oacc-c-c++-common/cache-1.c: Update.
    
    (cherry picked from commit 0cab70604cfda30bc64351b39493ef884ff7ba10)

diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index 2d38310f1fb..063b18c1f45 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -16130,6 +16130,7 @@ tsubst_omp_clauses (tree clauses, enum c_omp_region_type ort,
 	case OMP_CLAUSE_FROM:
 	case OMP_CLAUSE_TO:
 	case OMP_CLAUSE_MAP:
+	case OMP_CLAUSE__CACHE_:
 	case OMP_CLAUSE_USE_DEVICE_PTR:
 	case OMP_CLAUSE_IS_DEVICE_PTR:
 	  OMP_CLAUSE_DECL (nc)
@@ -17369,6 +17370,7 @@ tsubst_expr (tree t, tree args, tsubst_flags_t complain, tree in_decl,
       add_stmt (t);
       break;
 
+    case OACC_CACHE:
     case OACC_ENTER_DATA:
     case OACC_EXIT_DATA:
     case OACC_UPDATE:
diff --git a/gcc/testsuite/c-c++-common/goacc/cache-1.c b/gcc/testsuite/c-c++-common/goacc/cache-1.c
index 1d4759e738c..242f3c612fd 100644
--- a/gcc/testsuite/c-c++-common/goacc/cache-1.c
+++ b/gcc/testsuite/c-c++-common/goacc/cache-1.c
@@ -1,9 +1,15 @@
-/* OpenACC cache directive: valid usage.  */
-/* For execution testing, this file is "#include"d from
-   libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c.  */
+/* OpenACC 'cache' directive: valid usage.  */
 
-int
-main (int argc, char **argv)
+/* See also corresponding C++ variant: '../../g++.dg/goacc/cache-1.C'.  */
+
+/* For execution testing, this file is '#include'd from
+   '../../../../libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c'.  */
+
+#ifdef TEMPLATIZE
+template <int N>
+#endif
+static void
+test ()
 {
 #define N   2
     int a[N], b[N];
@@ -61,6 +67,4 @@ main (int argc, char **argv)
         if (a[i] != b[i])
             __builtin_abort ();
     }
-
-    return 0;
 }
diff --git a/gcc/testsuite/c-c++-common/goacc/cache-2.c b/gcc/testsuite/c-c++-common/goacc/cache-2.c
index d1181d1b6e7..80b925e5112 100644
--- a/gcc/testsuite/c-c++-common/goacc/cache-2.c
+++ b/gcc/testsuite/c-c++-common/goacc/cache-2.c
@@ -1,7 +1,9 @@
-/* OpenACC cache directive: invalid usage.  */
+/* OpenACC 'cache' directive: invalid usage.  */
 
-int
-main (int argc, char **argv)
+/* See also corresponding C++ variant: '../../g++.dg/goacc/cache-2.C'.  */
+
+static void
+test ()
 {
 #define N   2
     int a[N], b[N];
@@ -52,6 +54,4 @@ main (int argc, char **argv)
         if (a[i] != b[i])
             __builtin_abort ();
     }
-
-    return 0;
 }
diff --git a/gcc/testsuite/g++.dg/goacc/cache-1.C b/gcc/testsuite/g++.dg/goacc/cache-1.C
new file mode 100644
index 00000000000..a8d5ab32016
--- /dev/null
+++ b/gcc/testsuite/g++.dg/goacc/cache-1.C
@@ -0,0 +1,15 @@
+/* OpenACC 'cache' directive: valid usage.  */
+
+/* See also corresponding C/C++ variant '../../c-c++-common/goacc/cache-1.c'.  */
+
+/* For execution testing, this file is '#include'd from
+   '../../../../libgomp/testsuite/libgomp.oacc-c++/cache-1.C'.  */
+
+#define TEMPLATIZE
+#include "../../c-c++-common/goacc/cache-1.c"
+
+static void
+instantiate ()
+{
+  &test<0>;
+}
diff --git a/gcc/testsuite/g++.dg/goacc/cache-2.C b/gcc/testsuite/g++.dg/goacc/cache-2.C
new file mode 100644
index 00000000000..ef0b8a9e76f
--- /dev/null
+++ b/gcc/testsuite/g++.dg/goacc/cache-2.C
@@ -0,0 +1,64 @@
+/* OpenACC 'cache' directive: invalid usage.  */
+
+/* See also corresponding C/C++ variant '../../c-c++-common/goacc/cache-2.c'.  */
+
+template <int N>
+static void
+test ()
+{
+#define N   2
+    int a[N], b[N];
+    int i;
+
+    for (i = 0; i < N; i++)
+    {
+        a[i] = 3;
+        b[i] = 0;
+    }
+
+#pragma acc parallel copyin (a[0:N]) copyout (b[0:N])
+{
+    int ii;
+
+    for (ii = 0; ii < N; ii++)
+    {
+        const int idx = ii;
+        int n = 1;
+        const int len = n;
+
+#pragma acc cache /* { dg-error "expected '\\\(' before end of line" } */
+#pragma acc cache a[0:N] /* { dg-error "expected '\\\(' before 'a'" } */
+	/* { dg-bogus "expected end of line before 'a'" "" { xfail c++ } .-1 } */
+#pragma acc cache (a) /* { dg-error "expected '\\\['" } */
+#pragma acc cache ( /* { dg-error "expected (identifier|unqualified-id) before end of line" } */
+#pragma acc cache () /* { dg-error "expected (identifier|unqualified-id) before '\\\)' token" } */
+#pragma acc cache (,) /* { dg-error "expected (identifier|unqualified-id) before '(,|\\\))' token" } */
+#pragma acc cache (a[0:N] /* { dg-error "expected '\\\)' before end of line" } */
+#pragma acc cache (a[0:N],) /* { dg-error "expected (identifier|unqualified-id) before '(,|\\\))' token" "" { xfail c } } */
+#pragma acc cache (a[0:N]) copyin (a[0:N]) /* { dg-error "expected end of line before 'copyin'" } */
+#pragma acc cache () /* { dg-error "expected (identifier|unqualified-id) before '\\\)' token" } */
+#pragma acc cache (a[0:N] b[0:N]) /* { dg-error "expected '\\\)' before 'b'" } */
+#pragma acc cache (a[0:N] b[0:N}) /* { dg-error "expected '\\\)' before 'b'" } */
+	/* { dg-bogus "expected end of line before '\\\}' token" "" { xfail c++ } .-1 } */
+#pragma acc cache (a[0:N] /* { dg-error "expected '\\\)' before end of line" } */
+#pragma acc cache (a[0:N]) ( /* { dg-error "expected end of line before '\\(' token" } */
+#pragma acc cache (a[0:N]) ii /* { dg-error "expected end of line before 'ii'" } */
+#pragma acc cache (a[0:N] ii) /* { dg-error "expected '\\)' before 'ii'" } */
+
+        b[ii] = a[ii];
+    }
+}
+
+
+    for (i = 0; i < N; i++)
+    {
+        if (a[i] != b[i])
+            __builtin_abort ();
+    }
+}
+
+static void
+instantiate ()
+{
+  &test<0>;
+}
diff --git a/libgomp/testsuite/libgomp.oacc-c++/cache-1.C b/libgomp/testsuite/libgomp.oacc-c++/cache-1.C
new file mode 100644
index 00000000000..fcb1f84eef9
--- /dev/null
+++ b/libgomp/testsuite/libgomp.oacc-c++/cache-1.C
@@ -0,0 +1,13 @@
+/* OpenACC 'cache' directive.  */
+
+/* See also corresponding C/C++ variant '../libgomp.oacc-c-c++-common/cache-1.c'.  */
+
+#include "../../../gcc/testsuite/g++.dg/goacc/cache-1.C"
+
+int
+main (int argc, char *argv[])
+{
+  test<0> ();
+
+  return 0;
+}
diff --git a/libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c b/libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c
index 16aaed5df70..c0dddb3c4f3 100644
--- a/libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c
+++ b/libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c
@@ -1,3 +1,13 @@
-/* OpenACC cache directive.  */
+/* OpenACC 'cache' directive.  */
+
+/* See also corresponding C++ variant '../libgomp.oacc-c++/cache-1.C'.  */
 
 #include "../../../gcc/testsuite/c-c++-common/goacc/cache-1.c"
+
+int
+main (int argc, char *argv[])
+{
+  test ();
+
+  return 0;
+}

commit e7e0360147d973e7634f16bfec265cd4cc937e1c
Author: Thomas Schwinge <thomas@codesourcery.com>
Date:   Wed Nov 25 11:41:45 2020 +0100

    Add 'g++.dg/gomp/map-{1,2}.C'
    
            gcc/testsuite/
            * g++.dg/gomp/map-1.C: New.
            * g++.dg/gomp/map-2.C: Likewise.
            * c-c++-common/gomp/map-1.c: Adjust.
            * c-c++-common/gomp/map-2.c: Likewise.
    
    (cherry picked from commit 1049e5408fa343b5bf0a6380212a8ec8dfe2b6fc)

diff --git a/gcc/testsuite/c-c++-common/gomp/map-1.c b/gcc/testsuite/c-c++-common/gomp/map-1.c
index 5dad7d6a9aa..cd026f1243f 100644
--- a/gcc/testsuite/c-c++-common/gomp/map-1.c
+++ b/gcc/testsuite/c-c++-common/gomp/map-1.c
@@ -1,5 +1,6 @@
-/* { dg-do compile } */
-/* { dg-options "-fopenmp" } */
+/* Test 'map' clause diagnostics.  */
+
+/* See also corresponding C++ variant: '../../g++.dg/gomp/map-1.C'.  */
 
 extern int a[][10], a2[][10];
 int b[10], c[10][2], d[10], e[10], f[10];
diff --git a/gcc/testsuite/c-c++-common/gomp/map-2.c b/gcc/testsuite/c-c++-common/gomp/map-2.c
index 101f4047b85..cd69f6b9a57 100644
--- a/gcc/testsuite/c-c++-common/gomp/map-2.c
+++ b/gcc/testsuite/c-c++-common/gomp/map-2.c
@@ -1,5 +1,6 @@
-/* { dg-do compile } */
-/* { dg-options "-fopenmp" } */
+/* Test 'map' clause diagnostics.  */
+
+/* See also corresponding C++ variant: '../../g++.dg/gomp/map-2.C'.  */
 
 void
 foo (int *p, int (*q)[10], int r[10], int s[10][10])
diff --git a/gcc/testsuite/g++.dg/gomp/map-1.C b/gcc/testsuite/g++.dg/gomp/map-1.C
new file mode 100644
index 00000000000..107b59ee87a
--- /dev/null
+++ b/gcc/testsuite/g++.dg/gomp/map-1.C
@@ -0,0 +1,117 @@
+/* Test 'map' clause diagnostics.  */
+
+/* See also corresponding C/C++ variant: '../../c-c++-common/gomp/map-1.c'.  */
+
+extern int a[][10], a2[][10];
+int b[10], c[10][2], d[10], e[10], f[10];
+int b2[10], c2[10][2], d2[10], e2[10], f2[10];
+int k[10], l[10], m[10], n[10], o;
+int *p;
+int **q;
+int r[4][4][4][4][4];
+extern struct s s1;
+extern struct s s2[1]; /* { dg-error "array type has incomplete element type" "" { target c } } */
+int t[10];
+#pragma omp threadprivate (t)
+#pragma omp declare target
+void bar (int *);
+#pragma omp end declare target
+
+template <int N>
+void
+foo (int g[3][10], int h[4][8], int i[2][10], int j[][9],
+     int g2[3][10], int h2[4][8], int i2[2][10], int j2[][9])
+{
+  #pragma omp target map(to: bar[2:5]) /* { dg-error "is not a variable" } */
+    ;
+  #pragma omp target map(from: t[2:5]) /* { dg-error "is threadprivate variable" } */
+    ;
+  #pragma omp target map(tofrom: k[0.5:]) /* { dg-error "low bound \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma omp target map(from: l[:7.5f]) /* { dg-error "length \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma omp target map(to: m[p:]) /* { dg-error "low bound \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma omp target map(tofrom: n[:p]) /* { dg-error "length \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma omp target map(to: o[2:5]) /* { dg-error "does not have pointer or array type" } */
+    ;
+  #pragma omp target map(alloc: s1) /* { dg-error "'s1' does not have a mappable type in 'map' clause" } */
+    ;
+  #pragma omp target map(alloc: s2) /* { dg-error "'s2' does not have a mappable type in 'map' clause" } */
+    ;
+  #pragma omp target map(to: a[:][:]) /* { dg-error "array type length expression must be specified" } */
+    bar (&a[0][0]); /* { dg-error "referenced in target region does not have a mappable type" "TODO" { xfail *-*-* } } */
+  #pragma omp target map(tofrom: b[-1:]) /* { dg-error "negative low bound in array section" } */
+    bar (b);
+  #pragma omp target map(tofrom: c[:-3][:]) /* { dg-error "negative length in array section" } */
+    bar (&c[0][0]);
+  #pragma omp target map(from: d[11:]) /* { dg-error "low bound \[^\n\r]* above array section size" } */
+    bar (d);
+  #pragma omp target map(to: e[:11]) /* { dg-error "length \[^\n\r]* above array section size" } */
+    bar (e);
+  #pragma omp target map(to: f[1:10]) /* { dg-error "high bound \[^\n\r]* above array section size" } */
+    bar (f);
+  #pragma omp target map(from: g[:][0:10]) /* { dg-error "for pointer type length expression must be specified" } */
+    bar (&g[0][0]);
+  #pragma omp target map(from: h[2:1][-1:]) /* { dg-error "negative low bound in array section" } */
+    bar (&h[0][0]);
+  #pragma omp target map(tofrom: h[:1][:-3]) /* { dg-error "negative length in array section" } */
+    bar (&h[0][0]);
+  #pragma omp target map(i[:1][11:]) /* { dg-error "low bound \[^\n\r]* above array section size" } */
+    bar (&i[0][0]);
+  #pragma omp target map(from: j[3:1][:10]) /* { dg-error "length \[^\n\r]* above array section size" } */
+    bar (&j[0][0]);
+  #pragma omp target map(to: j[30:1][5:5]) /* { dg-error "high bound \[^\n\r]* above array section size" } */
+    bar (&j[0][0]);
+  #pragma omp target map(to: a2[:1][2:4])
+    bar (&a2[0][0]);
+  #pragma omp target map(a2[3:5][:])
+    bar (&a2[0][0]);
+  #pragma omp target map(to: a2[3:5][:10])
+    bar (&a2[0][0]);
+  #pragma omp target map(tofrom: b2[0:])
+    bar (b2);
+  #pragma omp target map(tofrom: c2[:3][:])
+    bar (&c2[0][0]);
+  #pragma omp target map(from: d2[9:])
+    bar (d2);
+  #pragma omp target map(to: e2[:10])
+    bar (e2);
+  #pragma omp target map(to: f2[1:9])
+    bar (f2);
+  #pragma omp target map(g2[:1][2:4])
+    bar (&g2[0][0]);
+  #pragma omp target map(from: h2[2:2][0:])
+    bar (&h2[0][0]);
+  #pragma omp target map(tofrom: h2[:1][:3])
+    bar (&h2[0][0]);
+  #pragma omp target map(to: i2[:1][9:])
+    bar (&i2[0][0]);
+  #pragma omp target map(from: j2[3:4][:9])
+    bar (&j2[0][0]);
+  #pragma omp target map(to: j2[30:1][5:4])
+    bar (&j2[0][0]);
+  #pragma omp target map(q[1:2])
+    ;
+  #pragma omp target map(tofrom: q[3:5][:10]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma omp target map(r[3:][2:1][1:2])
+    ;
+  #pragma omp target map(r[3:][2:1][1:2][:][0:4])
+    ;
+  #pragma omp target map(r[3:][2:1][1:2][1:][0:4]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma omp target map(r[3:][2:1][1:2][:3][0:4]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma omp target map(r[3:][2:1][1:2][:][1:]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma omp target map(r[3:][2:1][1:2][:][:3]) /* { dg-error "array section is not contiguous" } */
+    ;
+}
+
+static void
+instantiate ()
+{
+  &foo<0>;
+}
diff --git a/gcc/testsuite/g++.dg/gomp/map-2.C b/gcc/testsuite/g++.dg/gomp/map-2.C
new file mode 100644
index 00000000000..10eaaa948b8
--- /dev/null
+++ b/gcc/testsuite/g++.dg/gomp/map-2.C
@@ -0,0 +1,52 @@
+/* Test 'map' clause diagnostics.  */
+
+/* See also corresponding C/C++ variant: '../../c-c++-common/gomp/map-2.c'.  */
+
+template <int N>
+void
+foo (int *p, int (*q)[10], int r[10], int s[10][10])
+{
+  int a[10], b[10][10];
+  #pragma omp target map (tofrom: p[-1:2])
+  ;
+  #pragma omp target map (tofrom: q[-1:2][0:10])
+  ;
+  #pragma omp target map (tofrom: q[-1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma omp target map (tofrom: r[-1:2])
+  ;
+  #pragma omp target map (tofrom: s[-1:2][:])
+  ;
+  #pragma omp target map (tofrom: s[-1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma omp target map (tofrom: a[-1:2])	 /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma omp target map (tofrom: b[-1:2][0:])	 /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma omp target map (tofrom: b[1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma omp target map (tofrom: p[2:-3])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma omp target map (tofrom: q[2:-3][:])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma omp target map (tofrom: q[2:3][0:-1])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma omp target map (tofrom: r[2:-5])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma omp target map (tofrom: s[2:-5][:])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma omp target map (tofrom: s[2:5][0:-4])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma omp target map (tofrom: a[2:-5])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma omp target map (tofrom: b[2:-5][0:10]) /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma omp target map (tofrom: b[2:5][0:-4]) /* { dg-error "negative length in array section in" } */
+  ;
+}
+
+static void
+instantiate ()
+{
+  &foo<0>;
+}

commit c71a85f4804d9d5d4f3d70fb46a066f4ab3ae3d0
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Nov 26 00:18:01 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c4e3b6aea40..8e10b0d4d80 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,40 @@
+2020-11-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	Backported from master:
+	2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add
+	__ARM_FEATURE_PAC_DEFAULT support.
+
+2020-11-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	Backported from master:
+	2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	PR target/94891
+	* doc/extend.texi: Update the text for  __builtin_return_address.
+
+2020-11-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	Backported from master:
+	2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	PR target/94891
+	* config/aarch64/aarch64.c (aarch64_return_address_signing_enabled):
+	Disable return address signing if __builtin_eh_return is used.
+
+2020-11-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	Backported from master:
+	2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	PR target/94891
+	PR target/94791
+	* config/aarch64/aarch64-protos.h (aarch64_return_addr_rtx): Declare.
+	* config/aarch64/aarch64.c (aarch64_return_addr_rtx): New.
+	(aarch64_return_addr): Use aarch64_return_addr_rtx.
+	* config/aarch64/aarch64.h (PROFILE_HOOK): Likewise.
+
 2020-11-24  Jason Merrill  <jason@redhat.com>
 
 	PR c++/97918
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a2b688586c3..2c90f2149a7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201125
+20201126
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index d0dd8bd8f0e..da4713806e2 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,11 @@
+2020-11-25  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2020-11-25  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* pt.c (tsubst_omp_clauses): Handle 'OMP_CLAUSE__CACHE_'.
+	(tsubst_expr): Handle 'OACC_CACHE'.
+
 2020-11-24  Jason Merrill  <jason@redhat.com>
 
 	PR c++/95158
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 33cb936e2db..dd345346389 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,31 @@
+2020-11-25  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2020-11-25  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* g++.dg/gomp/map-1.C: New.
+	* g++.dg/gomp/map-2.C: Likewise.
+	* c-c++-common/gomp/map-1.c: Adjust.
+	* c-c++-common/gomp/map-2.c: Likewise.
+
+2020-11-25  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2020-11-25  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* c-c++-common/goacc/cache-1.c: Update.
+	* c-c++-common/goacc/cache-2.c: Likewise.
+	* g++.dg/goacc/cache-1.C: New.
+	* g++.dg/goacc/cache-2.C: Likewise.
+
+2020-11-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	Backported from master:
+	2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	PR target/94891
+	* gcc.target/aarch64/return_address_sign_1.c: Update test.
+
 2020-11-24  Jason Merrill  <jason@redhat.com>
 
 	PR c++/97918
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index dda054d0d4f..483ccd2c9e2 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,19 @@
+2020-11-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	Backported from master:
+	2020-07-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	PR target/94891
+	* config/aarch64/aarch64-unwind.h (MD_POST_EXTRACT_ROOT_ADDR): Remove.
+	(MD_POST_FROB_EH_HANDLER_ADDR): Remove.
+	(MD_POST_EXTRACT_FRAME_ADDR): Rename to ...
+	(MD_DEMANGLE_RETURN_ADDR): This.
+	(aarch64_post_extract_frame_addr): Rename to ...
+	(aarch64_demangle_return_addr): This.
+	(aarch64_post_frob_eh_handler_addr): Remove.
+	* unwind-dw2.c (uw_update_context): Demangle return address.
+	(uw_frob_return_addr): Remove.
+
 2020-08-07  Jakub Jelinek  <jakub@redhat.com>
 
 	Backported from master:
diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 15b6418ff5a..e464ec8fde5 100644
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,11 @@
+2020-11-25  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2020-11-25  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* testsuite/libgomp.oacc-c++/cache-1.C: New.
+	* testsuite/libgomp.oacc-c-c++-common/cache-1.c: Update.
+
 2020-11-02  Thomas Schwinge  <thomas@codesourcery.com>
 
 	Backported from master:

commit 23ec71d91e3044108a557dace573d3e60ff1c07e
Author: Thomas Schwinge <thomas@codesourcery.com>
Date:   Wed Nov 25 20:36:55 2020 +0100

    Don't create location wrapper nodes within OpenACC clauses (testsuite changes only)
    
    This fixes a GCC 11, 10, 9 regression introduced by commit
    dfd7fdca2ac17d8b823a16700525824ca312ade0 (Subversion r267272) "C++: more
    location wrapper nodes (PR c++/43064, PR c++/43486)".  But: this isn't
    intending to blame David, because back then, the problem hasn't been visible in
    the testsuite (or else I'm sure would've been addressed right away) because of
    our all dear friend: missing testsuite coverage.  Thus, for GCC 8, I'm likewise
    enhancing the testsuite, without the C++ front end code changes.
    
    I actually had presumed that there may be an issue for OpenACC:
    <http://mid.mail-archive.com/874lb9qr2u.fsf@euler.schwinge.homeip.net>, so here
    we are, two years (and many "wasted" hours...) later...
    
            gcc/testsuite/
            * c-c++-common/goacc/cache-3-1.c: New.
            * c-c++-common/goacc/cache-3-2.c: Likewise.
            * c-c++-common/goacc/data-clause-1.c: Likewise.
            * c-c++-common/goacc/data-clause-2.c: Likewise.
            * c-c++-common/gomp/map-1.c: Adjust.
            * c-c++-common/gomp/map-2.c: Likewise.
            * g++.dg/goacc/cache-3-1.C: New.
            * g++.dg/goacc/cache-3-2.C: Likewise.
            * g++.dg/goacc/data-clause-1.C: Likewise.
            * g++.dg/goacc/data-clause-2.C: Likewise.
            * g++.dg/gomp/map-1.C: Adjust.
            * g++.dg/gomp/map-2.C: Likewise.
    
    Reported-by: Sandra Loosemore <sandra@codesourcery.com>
    (cherry picked from commit c0c7270cc4efd896fe99f8ad5409dbef089a407f (testsuite changes only))

diff --git a/gcc/testsuite/c-c++-common/goacc/cache-3-1.c b/gcc/testsuite/c-c++-common/goacc/cache-3-1.c
new file mode 100644
index 00000000000..155de689dfa
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/goacc/cache-3-1.c
@@ -0,0 +1,116 @@
+/* Test 'cache' directive diagnostics.  */
+
+/* See also corresponding C++ variant: '../../g++.dg/goacc/cache-3-1.C'.  */
+
+/* See also corresponding C/C++ data clause variant: 'data-clause-1.c'.  */
+
+/* { dg-additional-options "-fopenmp" } for '#pragma omp threadprivate'.  */
+
+/* The current implementation doesn't restrict where a 'cache' directive may
+   appear, so we don't make any special arrangements.  */
+
+extern int a[][10], a2[][10];
+int b[10], c[10][2], d[10], e[10], f[10];
+int b2[10], c2[10][2], d2[10], e2[10], f2[10];
+int k[10], l[10], m[10], n[10], o;
+int *p;
+int **q;
+int r[4][4][4][4][4];
+extern struct s s1;
+extern struct s s2[1]; /* { dg-error "array type has incomplete element type" "" { target c } } */
+int t[10];
+#pragma omp threadprivate (t)
+#pragma acc routine
+void bar (int *);
+
+void
+foo (int g[3][10], int h[4][8], int i[2][10], int j[][9],
+     int g2[3][10], int h2[4][8], int i2[2][10], int j2[][9])
+{
+  #pragma acc cache(bar[2:5]) /* { dg-error "is not a variable" } */
+    ;
+  #pragma acc cache(t[2:5]) /* { dg-error "is threadprivate variable" } */
+    ;
+  #pragma acc cache(k[0.5:]) /* { dg-error "low bound \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc cache(l[:7.5f]) /* { dg-error "length \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc cache(m[p:]) /* { dg-error "low bound \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc cache(n[:p]) /* { dg-error "length \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc cache(o[2:5]) /* { dg-error "does not have pointer or array type" } */
+    ;
+  #pragma acc cache(s1) /* { dg-error "expected '\\\['" } */
+    ;
+  #pragma acc cache(s2) /* { dg-error "expected '\\\['" } */
+    ;
+  #pragma acc cache(a[:][:]) /* { dg-error "array type length expression must be specified" } */
+    bar (&a[0][0]); /* { dg-bogus "referenced in target region does not have a mappable type" } */
+  #pragma acc cache(b[-1:]) /* { dg-error "negative low bound in array section" } */
+    bar (b);
+  #pragma acc cache(c[:-3][:]) /* { dg-error "negative length in array section" } */
+    bar (&c[0][0]);
+  #pragma acc cache(d[11:]) /* { dg-error "low bound \[^\n\r]* above array section size" } */
+    bar (d);
+  #pragma acc cache(e[:11]) /* { dg-error "length \[^\n\r]* above array section size" } */
+    bar (e);
+  #pragma acc cache(f[1:10]) /* { dg-error "high bound \[^\n\r]* above array section size" } */
+    bar (f);
+  #pragma acc cache(g[:][0:10]) /* { dg-error "for pointer type length expression must be specified" } */
+    bar (&g[0][0]);
+  #pragma acc cache(h[2:1][-1:]) /* { dg-error "negative low bound in array section" } */
+    bar (&h[0][0]);
+  #pragma acc cache(h[:1][:-3]) /* { dg-error "negative length in array section" } */
+    bar (&h[0][0]);
+  #pragma acc cache(i[:1][11:]) /* { dg-error "low bound \[^\n\r]* above array section size" } */
+    bar (&i[0][0]);
+  #pragma acc cache(j[3:1][:10]) /* { dg-error "length \[^\n\r]* above array section size" } */
+    bar (&j[0][0]);
+  #pragma acc cache(j[30:1][5:5]) /* { dg-error "high bound \[^\n\r]* above array section size" } */
+    bar (&j[0][0]);
+  #pragma acc cache(a2[:1][2:4])
+    bar (&a2[0][0]);
+  #pragma acc cache(a2[3:5][:])
+    bar (&a2[0][0]);
+  #pragma acc cache(a2[3:5][:10])
+    bar (&a2[0][0]);
+  #pragma acc cache(b2[0:])
+    bar (b2);
+  #pragma acc cache(c2[:3][:])
+    bar (&c2[0][0]);
+  #pragma acc cache(d2[9:])
+    bar (d2);
+  #pragma acc cache(e2[:10])
+    bar (e2);
+  #pragma acc cache(f2[1:9])
+    bar (f2);
+  #pragma acc cache(g2[:1][2:4])
+    bar (&g2[0][0]);
+  #pragma acc cache(h2[2:2][0:])
+    bar (&h2[0][0]);
+  #pragma acc cache(h2[:1][:3])
+    bar (&h2[0][0]);
+  #pragma acc cache(i2[:1][9:])
+    bar (&i2[0][0]);
+  #pragma acc cache(j2[3:4][:9])
+    bar (&j2[0][0]);
+  #pragma acc cache(j2[30:1][5:4])
+    bar (&j2[0][0]);
+  #pragma acc cache(q[1:2])
+    ;
+  #pragma acc cache(q[3:5][:10]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc cache(r[3:][2:1][1:2])
+    ;
+  #pragma acc cache(r[3:][2:1][1:2][:][0:4])
+    ;
+  #pragma acc cache(r[3:][2:1][1:2][1:][0:4]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc cache(r[3:][2:1][1:2][:3][0:4]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc cache(r[3:][2:1][1:2][:][1:]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc cache(r[3:][2:1][1:2][:][:3]) /* { dg-error "array section is not contiguous" } */
+    ;
+}
diff --git a/gcc/testsuite/c-c++-common/goacc/cache-3-2.c b/gcc/testsuite/c-c++-common/goacc/cache-3-2.c
new file mode 100644
index 00000000000..ea5222e7d0c
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/goacc/cache-3-2.c
@@ -0,0 +1,50 @@
+/* Test 'cache' directive diagnostics.  */
+
+/* See also corresponding C++ variant: '../../g++.dg/goacc/cache-3-2.C'.  */
+
+/* See also corresponding C/C++ data clause variant: 'data-clause-2.c'.  */
+
+/* The current implementation doesn't restrict where a 'cache' directive may
+   appear, so we don't make any special arrangements.  */
+
+void
+foo (int *p, int (*q)[10], int r[10], int s[10][10])
+{
+  int a[10], b[10][10];
+  #pragma acc cache (p[-1:2])
+  ;
+  #pragma acc cache (q[-1:2][0:10])
+  ;
+  #pragma acc cache (q[-1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc cache (r[-1:2])
+  ;
+  #pragma acc cache (s[-1:2][:])
+  ;
+  #pragma acc cache (s[-1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc cache (a[-1:2])	 /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc cache (b[-1:2][0:])	 /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc cache (b[1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc cache (p[2:-3])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (q[2:-3][:])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (q[2:3][0:-1])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (r[2:-5])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (s[2:-5][:])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (s[2:5][0:-4])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (a[2:-5])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (b[2:-5][0:10]) /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (b[2:5][0:-4]) /* { dg-error "negative length in array section in" } */
+  ;
+}
diff --git a/gcc/testsuite/c-c++-common/goacc/data-clause-1.c b/gcc/testsuite/c-c++-common/goacc/data-clause-1.c
new file mode 100644
index 00000000000..20f822cbb99
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/goacc/data-clause-1.c
@@ -0,0 +1,115 @@
+/* Test data clause diagnostics.  */
+
+/* See also corresponding OpenACC C++ variant: '../../g++.dg/goacc/data-clause-1.C'.  */
+
+/* See also corresponding OpenACC 'cache' directive variant: 'cache-3-1.c'.  */
+
+/* See also corresponding OpenMP variant: '../gomp/map-1.c'.  */
+
+/* { dg-additional-options "-fopenmp" } for '#pragma omp threadprivate'.  */
+
+extern int a[][10], a2[][10];
+int b[10], c[10][2], d[10], e[10], f[10];
+int b2[10], c2[10][2], d2[10], e2[10], f2[10];
+int k[10], l[10], m[10], n[10], o;
+int *p;
+int **q;
+int r[4][4][4][4][4];
+extern struct s s1;
+extern struct s s2[1]; /* { dg-error "array type has incomplete element type" "" { target c } } */
+int t[10];
+#pragma omp threadprivate (t)
+#pragma acc routine
+void bar (int *);
+
+void
+foo (int g[3][10], int h[4][8], int i[2][10], int j[][9],
+     int g2[3][10], int h2[4][8], int i2[2][10], int j2[][9])
+{
+  #pragma acc parallel copyin(bar[2:5]) /* { dg-error "is not a variable" } */
+    ;
+  #pragma acc parallel copyout(t[2:5]) /* { dg-error "is threadprivate variable" } */
+    ;
+  #pragma acc parallel copy(k[0.5:]) /* { dg-error "low bound \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc parallel copyout(l[:7.5f]) /* { dg-error "length \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc parallel copyin(m[p:]) /* { dg-error "low bound \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc parallel copy(n[:p]) /* { dg-error "length \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc parallel copyin(o[2:5]) /* { dg-error "does not have pointer or array type" } */
+    ;
+  #pragma acc parallel create(s1) /* { dg-error "'s1' does not have a mappable type in 'map' clause" } */
+    ;
+  #pragma acc parallel create(s2) /* { dg-error "'s2' does not have a mappable type in 'map' clause" } */
+    ;
+  #pragma acc parallel copyin(a[:][:]) /* { dg-error "array type length expression must be specified" } */
+    bar (&a[0][0]); /* { dg-error "referenced in target region does not have a mappable type" } */
+  #pragma acc parallel copy(b[-1:]) /* { dg-error "negative low bound in array section" } */
+    bar (b);
+  #pragma acc parallel copy(c[:-3][:]) /* { dg-error "negative length in array section" } */
+    bar (&c[0][0]);
+  #pragma acc parallel copyout(d[11:]) /* { dg-error "low bound \[^\n\r]* above array section size" } */
+    bar (d);
+  #pragma acc parallel copyin(e[:11]) /* { dg-error "length \[^\n\r]* above array section size" } */
+    bar (e);
+  #pragma acc parallel copyin(f[1:10]) /* { dg-error "high bound \[^\n\r]* above array section size" } */
+    bar (f);
+  #pragma acc parallel copyout(g[:][0:10]) /* { dg-error "for pointer type length expression must be specified" } */
+    bar (&g[0][0]);
+  #pragma acc parallel copyout(h[2:1][-1:]) /* { dg-error "negative low bound in array section" } */
+    bar (&h[0][0]);
+  #pragma acc parallel copy(h[:1][:-3]) /* { dg-error "negative length in array section" } */
+    bar (&h[0][0]);
+  #pragma acc parallel copy(i[:1][11:]) /* { dg-error "low bound \[^\n\r]* above array section size" } */
+    bar (&i[0][0]);
+  #pragma acc parallel copyout(j[3:1][:10]) /* { dg-error "length \[^\n\r]* above array section size" } */
+    bar (&j[0][0]);
+  #pragma acc parallel copyin(j[30:1][5:5]) /* { dg-error "high bound \[^\n\r]* above array section size" } */
+    bar (&j[0][0]);
+  #pragma acc parallel copyin(a2[:1][2:4])
+    bar (&a2[0][0]);
+  #pragma acc parallel copy(a2[3:5][:])
+    bar (&a2[0][0]);
+  #pragma acc parallel copyin(a2[3:5][:10])
+    bar (&a2[0][0]);
+  #pragma acc parallel copy(b2[0:])
+    bar (b2);
+  #pragma acc parallel copy(c2[:3][:])
+    bar (&c2[0][0]);
+  #pragma acc parallel copyout(d2[9:])
+    bar (d2);
+  #pragma acc parallel copyin(e2[:10])
+    bar (e2);
+  #pragma acc parallel copyin(f2[1:9])
+    bar (f2);
+  #pragma acc parallel copy(g2[:1][2:4])
+    bar (&g2[0][0]);
+  #pragma acc parallel copyout(h2[2:2][0:])
+    bar (&h2[0][0]);
+  #pragma acc parallel copy(h2[:1][:3])
+    bar (&h2[0][0]);
+  #pragma acc parallel copyin(i2[:1][9:])
+    bar (&i2[0][0]);
+  #pragma acc parallel copyout(j2[3:4][:9])
+    bar (&j2[0][0]);
+  #pragma acc parallel copyin(j2[30:1][5:4])
+    bar (&j2[0][0]);
+  #pragma acc parallel copy(q[1:2])
+    ;
+  #pragma acc parallel copy(q[3:5][:10]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2])
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2][:][0:4])
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2][1:][0:4]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2][:3][0:4]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2][:][1:]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2][:][:3]) /* { dg-error "array section is not contiguous" } */
+    ;
+}
diff --git a/gcc/testsuite/c-c++-common/goacc/data-clause-2.c b/gcc/testsuite/c-c++-common/goacc/data-clause-2.c
new file mode 100644
index 00000000000..d4603b016dd
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/goacc/data-clause-2.c
@@ -0,0 +1,49 @@
+/* Test data clause diagnostics.  */
+
+/* See also corresponding OpenACC C++ variant: '../../g++.dg/goacc/data-clause-2.C'.  */
+
+/* See also corresponding OpenACC 'cache' directive variant: 'cache-3-2.c'.  */
+
+/* See also corresponding OpenMP variant: '../gomp/map-2.c'.  */
+
+void
+foo (int *p, int (*q)[10], int r[10], int s[10][10])
+{
+  int a[10], b[10][10];
+  #pragma acc parallel copy (p[-1:2])
+  ;
+  #pragma acc parallel copy (q[-1:2][0:10])
+  ;
+  #pragma acc parallel copy (q[-1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc parallel copy (r[-1:2])
+  ;
+  #pragma acc parallel copy (s[-1:2][:])
+  ;
+  #pragma acc parallel copy (s[-1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc parallel copy (a[-1:2])	 /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc parallel copy (b[-1:2][0:])	 /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc parallel copy (b[1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc parallel copy (p[2:-3])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (q[2:-3][:])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (q[2:3][0:-1])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (r[2:-5])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (s[2:-5][:])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (s[2:5][0:-4])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (a[2:-5])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (b[2:-5][0:10]) /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (b[2:5][0:-4]) /* { dg-error "negative length in array section in" } */
+  ;
+}
diff --git a/gcc/testsuite/c-c++-common/gomp/map-1.c b/gcc/testsuite/c-c++-common/gomp/map-1.c
index cd026f1243f..a8549bc49d9 100644
--- a/gcc/testsuite/c-c++-common/gomp/map-1.c
+++ b/gcc/testsuite/c-c++-common/gomp/map-1.c
@@ -1,6 +1,8 @@
 /* Test 'map' clause diagnostics.  */
 
-/* See also corresponding C++ variant: '../../g++.dg/gomp/map-1.C'.  */
+/* See also corresponding OpenMP C++ variant: '../../g++.dg/gomp/map-1.C'.  */
+
+/* See also corresponding OpenACC variant: '../goacc/data-clause-1.c'.  */
 
 extern int a[][10], a2[][10];
 int b[10], c[10][2], d[10], e[10], f[10];
diff --git a/gcc/testsuite/c-c++-common/gomp/map-2.c b/gcc/testsuite/c-c++-common/gomp/map-2.c
index cd69f6b9a57..01fb4be869d 100644
--- a/gcc/testsuite/c-c++-common/gomp/map-2.c
+++ b/gcc/testsuite/c-c++-common/gomp/map-2.c
@@ -1,6 +1,8 @@
 /* Test 'map' clause diagnostics.  */
 
-/* See also corresponding C++ variant: '../../g++.dg/gomp/map-2.C'.  */
+/* See also corresponding OpenMP C++ variant: '../../g++.dg/gomp/map-2.C'.  */
+
+/* See also corresponding OpenACC variant: '../goacc/data-clause-2.c'.  */
 
 void
 foo (int *p, int (*q)[10], int r[10], int s[10][10])
diff --git a/gcc/testsuite/g++.dg/goacc/cache-3-1.C b/gcc/testsuite/g++.dg/goacc/cache-3-1.C
new file mode 100644
index 00000000000..d543db60a9d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/goacc/cache-3-1.C
@@ -0,0 +1,123 @@
+/* Test 'cache' directive diagnostics.  */
+
+/* See also corresponding C/C++ variant: '../../c-c++-common/goacc/cache-3-1.c'.  */
+
+/* See also corresponding C++ data clause variant: 'data-clause-1.C'.  */
+
+/* { dg-additional-options "-fopenmp" } for '#pragma omp threadprivate'.  */
+
+/* The current implementation doesn't restrict where a 'cache' directive may
+   appear, so we don't make any special arrangements.  */
+
+extern int a[][10], a2[][10];
+int b[10], c[10][2], d[10], e[10], f[10];
+int b2[10], c2[10][2], d2[10], e2[10], f2[10];
+int k[10], l[10], m[10], n[10], o;
+int *p;
+int **q;
+int r[4][4][4][4][4];
+extern struct s s1;
+extern struct s s2[1]; /* { dg-error "array type has incomplete element type" "" { target c } } */
+int t[10];
+#pragma omp threadprivate (t)
+#pragma acc routine
+void bar (int *);
+
+template <int N>
+void
+foo (int g[3][10], int h[4][8], int i[2][10], int j[][9],
+     int g2[3][10], int h2[4][8], int i2[2][10], int j2[][9])
+{
+  #pragma acc cache(bar[2:5]) /* { dg-error "is not a variable" } */
+    ;
+  #pragma acc cache(t[2:5]) /* { dg-error "is threadprivate variable" } */
+    ;
+  #pragma acc cache(k[0.5:]) /* { dg-error "low bound \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc cache(l[:7.5f]) /* { dg-error "length \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc cache(m[p:]) /* { dg-error "low bound \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc cache(n[:p]) /* { dg-error "length \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc cache(o[2:5]) /* { dg-error "does not have pointer or array type" } */
+    ;
+  #pragma acc cache(s1) /* { dg-error "expected '\\\['" } */
+    ;
+  #pragma acc cache(s2) /* { dg-error "expected '\\\['" } */
+    ;
+  #pragma acc cache(a[:][:]) /* { dg-error "array type length expression must be specified" } */
+    bar (&a[0][0]);
+  #pragma acc cache(b[-1:]) /* { dg-error "negative low bound in array section" } */
+    bar (b);
+  #pragma acc cache(c[:-3][:]) /* { dg-error "negative length in array section" } */
+    bar (&c[0][0]);
+  #pragma acc cache(d[11:]) /* { dg-error "low bound \[^\n\r]* above array section size" } */
+    bar (d);
+  #pragma acc cache(e[:11]) /* { dg-error "length \[^\n\r]* above array section size" } */
+    bar (e);
+  #pragma acc cache(f[1:10]) /* { dg-error "high bound \[^\n\r]* above array section size" } */
+    bar (f);
+  #pragma acc cache(g[:][0:10]) /* { dg-error "for pointer type length expression must be specified" } */
+    bar (&g[0][0]);
+  #pragma acc cache(h[2:1][-1:]) /* { dg-error "negative low bound in array section" } */
+    bar (&h[0][0]);
+  #pragma acc cache(h[:1][:-3]) /* { dg-error "negative length in array section" } */
+    bar (&h[0][0]);
+  #pragma acc cache(i[:1][11:]) /* { dg-error "low bound \[^\n\r]* above array section size" } */
+    bar (&i[0][0]);
+  #pragma acc cache(j[3:1][:10]) /* { dg-error "length \[^\n\r]* above array section size" } */
+    bar (&j[0][0]);
+  #pragma acc cache(j[30:1][5:5]) /* { dg-error "high bound \[^\n\r]* above array section size" } */
+    bar (&j[0][0]);
+  #pragma acc cache(a2[:1][2:4])
+    bar (&a2[0][0]);
+  #pragma acc cache(a2[3:5][:])
+    bar (&a2[0][0]);
+  #pragma acc cache(a2[3:5][:10])
+    bar (&a2[0][0]);
+  #pragma acc cache(b2[0:])
+    bar (b2);
+  #pragma acc cache(c2[:3][:])
+    bar (&c2[0][0]);
+  #pragma acc cache(d2[9:])
+    bar (d2);
+  #pragma acc cache(e2[:10])
+    bar (e2);
+  #pragma acc cache(f2[1:9])
+    bar (f2);
+  #pragma acc cache(g2[:1][2:4])
+    bar (&g2[0][0]);
+  #pragma acc cache(h2[2:2][0:])
+    bar (&h2[0][0]);
+  #pragma acc cache(h2[:1][:3])
+    bar (&h2[0][0]);
+  #pragma acc cache(i2[:1][9:])
+    bar (&i2[0][0]);
+  #pragma acc cache(j2[3:4][:9])
+    bar (&j2[0][0]);
+  #pragma acc cache(j2[30:1][5:4])
+    bar (&j2[0][0]);
+  #pragma acc cache(q[1:2])
+    ;
+  #pragma acc cache(q[3:5][:10]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc cache(r[3:][2:1][1:2])
+    ;
+  #pragma acc cache(r[3:][2:1][1:2][:][0:4])
+    ;
+  #pragma acc cache(r[3:][2:1][1:2][1:][0:4]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc cache(r[3:][2:1][1:2][:3][0:4]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc cache(r[3:][2:1][1:2][:][1:]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc cache(r[3:][2:1][1:2][:][:3]) /* { dg-error "array section is not contiguous" } */
+    ;
+}
+
+static void
+instantiate ()
+{
+  &foo<0>;
+}
diff --git a/gcc/testsuite/g++.dg/goacc/cache-3-2.C b/gcc/testsuite/g++.dg/goacc/cache-3-2.C
new file mode 100644
index 00000000000..5561e176a56
--- /dev/null
+++ b/gcc/testsuite/g++.dg/goacc/cache-3-2.C
@@ -0,0 +1,57 @@
+/* Test 'cache' directive diagnostics.  */
+
+/* See also corresponding C/C++ variant: '../../c-c++-common/goacc/cache-3-2.c'.  */
+
+/* See also corresponding C++ data clause variant: 'data-clause-2.C'.  */
+
+/* The current implementation doesn't restrict where a 'cache' directive may
+   appear, so we don't make any special arrangements.  */
+
+template <int N>
+void
+foo (int *p, int (*q)[10], int r[10], int s[10][10])
+{
+  int a[10], b[10][10];
+  #pragma acc cache (p[-1:2])
+  ;
+  #pragma acc cache (q[-1:2][0:10])
+  ;
+  #pragma acc cache (q[-1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc cache (r[-1:2])
+  ;
+  #pragma acc cache (s[-1:2][:])
+  ;
+  #pragma acc cache (s[-1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc cache (a[-1:2])	 /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc cache (b[-1:2][0:])	 /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc cache (b[1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc cache (p[2:-3])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (q[2:-3][:])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (q[2:3][0:-1])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (r[2:-5])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (s[2:-5][:])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (s[2:5][0:-4])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (a[2:-5])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (b[2:-5][0:10]) /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc cache (b[2:5][0:-4]) /* { dg-error "negative length in array section in" } */
+  ;
+}
+
+static void
+instantiate ()
+{
+  &foo<0>;
+}
diff --git a/gcc/testsuite/g++.dg/goacc/data-clause-1.C b/gcc/testsuite/g++.dg/goacc/data-clause-1.C
new file mode 100644
index 00000000000..3de3834efae
--- /dev/null
+++ b/gcc/testsuite/g++.dg/goacc/data-clause-1.C
@@ -0,0 +1,122 @@
+/* Test data clause diagnostics.  */
+
+/* See also corresponding OpenACC C/C++ variant: '../../c-c++-common/goacc/data-clause-1.c'.  */
+
+/* See also corresponding OpenACC 'cache' directive variant: 'cache-3-1.C'.  */
+
+/* See also corresponding OpenMP variant: '../gomp/map-1.C'.  */
+
+/* { dg-additional-options "-fopenmp" } for '#pragma omp threadprivate'.  */
+
+extern int a[][10], a2[][10];
+int b[10], c[10][2], d[10], e[10], f[10];
+int b2[10], c2[10][2], d2[10], e2[10], f2[10];
+int k[10], l[10], m[10], n[10], o;
+int *p;
+int **q;
+int r[4][4][4][4][4];
+extern struct s s1;
+extern struct s s2[1]; /* { dg-error "array type has incomplete element type" "" { target c } } */
+int t[10];
+#pragma omp threadprivate (t)
+#pragma acc routine
+void bar (int *);
+
+template <int N>
+void
+foo (int g[3][10], int h[4][8], int i[2][10], int j[][9],
+     int g2[3][10], int h2[4][8], int i2[2][10], int j2[][9])
+{
+  #pragma acc parallel copyin(bar[2:5]) /* { dg-error "is not a variable" } */
+    ;
+  #pragma acc parallel copyout(t[2:5]) /* { dg-error "is threadprivate variable" } */
+    ;
+  #pragma acc parallel copy(k[0.5:]) /* { dg-error "low bound \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc parallel copyout(l[:7.5f]) /* { dg-error "length \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc parallel copyin(m[p:]) /* { dg-error "low bound \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc parallel copy(n[:p]) /* { dg-error "length \[^\n\r]* of array section does not have integral type" } */
+    ;
+  #pragma acc parallel copyin(o[2:5]) /* { dg-error "does not have pointer or array type" } */
+    ;
+  #pragma acc parallel create(s1) /* { dg-error "'s1' does not have a mappable type in 'map' clause" } */
+    ;
+  #pragma acc parallel create(s2) /* { dg-error "'s2' does not have a mappable type in 'map' clause" } */
+    ;
+  #pragma acc parallel copyin(a[:][:]) /* { dg-error "array type length expression must be specified" } */
+    bar (&a[0][0]); /* { dg-error "referenced in target region does not have a mappable type" "PR97996" { xfail *-*-* } } */
+  #pragma acc parallel copy(b[-1:]) /* { dg-error "negative low bound in array section" } */
+    bar (b);
+  #pragma acc parallel copy(c[:-3][:]) /* { dg-error "negative length in array section" } */
+    bar (&c[0][0]);
+  #pragma acc parallel copyout(d[11:]) /* { dg-error "low bound \[^\n\r]* above array section size" } */
+    bar (d);
+  #pragma acc parallel copyin(e[:11]) /* { dg-error "length \[^\n\r]* above array section size" } */
+    bar (e);
+  #pragma acc parallel copyin(f[1:10]) /* { dg-error "high bound \[^\n\r]* above array section size" } */
+    bar (f);
+  #pragma acc parallel copyout(g[:][0:10]) /* { dg-error "for pointer type length expression must be specified" } */
+    bar (&g[0][0]);
+  #pragma acc parallel copyout(h[2:1][-1:]) /* { dg-error "negative low bound in array section" } */
+    bar (&h[0][0]);
+  #pragma acc parallel copy(h[:1][:-3]) /* { dg-error "negative length in array section" } */
+    bar (&h[0][0]);
+  #pragma acc parallel copy(i[:1][11:]) /* { dg-error "low bound \[^\n\r]* above array section size" } */
+    bar (&i[0][0]);
+  #pragma acc parallel copyout(j[3:1][:10]) /* { dg-error "length \[^\n\r]* above array section size" } */
+    bar (&j[0][0]);
+  #pragma acc parallel copyin(j[30:1][5:5]) /* { dg-error "high bound \[^\n\r]* above array section size" } */
+    bar (&j[0][0]);
+  #pragma acc parallel copyin(a2[:1][2:4])
+    bar (&a2[0][0]);
+  #pragma acc parallel copy(a2[3:5][:])
+    bar (&a2[0][0]);
+  #pragma acc parallel copyin(a2[3:5][:10])
+    bar (&a2[0][0]);
+  #pragma acc parallel copy(b2[0:])
+    bar (b2);
+  #pragma acc parallel copy(c2[:3][:])
+    bar (&c2[0][0]);
+  #pragma acc parallel copyout(d2[9:])
+    bar (d2);
+  #pragma acc parallel copyin(e2[:10])
+    bar (e2);
+  #pragma acc parallel copyin(f2[1:9])
+    bar (f2);
+  #pragma acc parallel copy(g2[:1][2:4])
+    bar (&g2[0][0]);
+  #pragma acc parallel copyout(h2[2:2][0:])
+    bar (&h2[0][0]);
+  #pragma acc parallel copy(h2[:1][:3])
+    bar (&h2[0][0]);
+  #pragma acc parallel copyin(i2[:1][9:])
+    bar (&i2[0][0]);
+  #pragma acc parallel copyout(j2[3:4][:9])
+    bar (&j2[0][0]);
+  #pragma acc parallel copyin(j2[30:1][5:4])
+    bar (&j2[0][0]);
+  #pragma acc parallel copy(q[1:2])
+    ;
+  #pragma acc parallel copy(q[3:5][:10]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2])
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2][:][0:4])
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2][1:][0:4]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2][:3][0:4]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2][:][1:]) /* { dg-error "array section is not contiguous" } */
+    ;
+  #pragma acc parallel copy(r[3:][2:1][1:2][:][:3]) /* { dg-error "array section is not contiguous" } */
+    ;
+}
+
+static void
+instantiate ()
+{
+  &foo<0>;
+}
diff --git a/gcc/testsuite/g++.dg/goacc/data-clause-2.C b/gcc/testsuite/g++.dg/goacc/data-clause-2.C
new file mode 100644
index 00000000000..57d1823aede
--- /dev/null
+++ b/gcc/testsuite/g++.dg/goacc/data-clause-2.C
@@ -0,0 +1,56 @@
+/* Test data clause diagnostics.  */
+
+/* See also corresponding OpenACC C/C++ variant: '../../c-c++-common/goacc/data-clause-2.c'.  */
+
+/* See also corresponding OpenACC 'cache' directive variant: 'cache-3-2.C'.  */
+
+/* See also corresponding OpenMP variant: '../gomp/map-2.C'.  */
+
+template <int N>
+void
+foo (int *p, int (*q)[10], int r[10], int s[10][10])
+{
+  int a[10], b[10][10];
+  #pragma acc parallel copy (p[-1:2])
+  ;
+  #pragma acc parallel copy (q[-1:2][0:10])
+  ;
+  #pragma acc parallel copy (q[-1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc parallel copy (r[-1:2])
+  ;
+  #pragma acc parallel copy (s[-1:2][:])
+  ;
+  #pragma acc parallel copy (s[-1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc parallel copy (a[-1:2])	 /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc parallel copy (b[-1:2][0:])	 /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc parallel copy (b[1:2][-2:10]) /* { dg-error "negative low bound in array section in" } */
+  ;
+  #pragma acc parallel copy (p[2:-3])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (q[2:-3][:])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (q[2:3][0:-1])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (r[2:-5])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (s[2:-5][:])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (s[2:5][0:-4])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (a[2:-5])	 /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (b[2:-5][0:10]) /* { dg-error "negative length in array section in" } */
+  ;
+  #pragma acc parallel copy (b[2:5][0:-4]) /* { dg-error "negative length in array section in" } */
+  ;
+}
+
+static void
+instantiate ()
+{
+  &foo<0>;
+}
diff --git a/gcc/testsuite/g++.dg/gomp/map-1.C b/gcc/testsuite/g++.dg/gomp/map-1.C
index 107b59ee87a..c314d55a621 100644
--- a/gcc/testsuite/g++.dg/gomp/map-1.C
+++ b/gcc/testsuite/g++.dg/gomp/map-1.C
@@ -1,6 +1,8 @@
 /* Test 'map' clause diagnostics.  */
 
-/* See also corresponding C/C++ variant: '../../c-c++-common/gomp/map-1.c'.  */
+/* See also corresponding OpenMP C/C++ variant: '../../c-c++-common/gomp/map-1.c'.  */
+
+/* See also corresponding OpenACC variant: '../goacc/data-clause-1.C'.  */
 
 extern int a[][10], a2[][10];
 int b[10], c[10][2], d[10], e[10], f[10];
@@ -41,7 +43,7 @@ foo (int g[3][10], int h[4][8], int i[2][10], int j[][9],
   #pragma omp target map(alloc: s2) /* { dg-error "'s2' does not have a mappable type in 'map' clause" } */
     ;
   #pragma omp target map(to: a[:][:]) /* { dg-error "array type length expression must be specified" } */
-    bar (&a[0][0]); /* { dg-error "referenced in target region does not have a mappable type" "TODO" { xfail *-*-* } } */
+    bar (&a[0][0]); /* { dg-error "referenced in target region does not have a mappable type" "PR97996" { xfail *-*-* } } */
   #pragma omp target map(tofrom: b[-1:]) /* { dg-error "negative low bound in array section" } */
     bar (b);
   #pragma omp target map(tofrom: c[:-3][:]) /* { dg-error "negative length in array section" } */
diff --git a/gcc/testsuite/g++.dg/gomp/map-2.C b/gcc/testsuite/g++.dg/gomp/map-2.C
index 10eaaa948b8..bbe26061fe3 100644
--- a/gcc/testsuite/g++.dg/gomp/map-2.C
+++ b/gcc/testsuite/g++.dg/gomp/map-2.C
@@ -1,6 +1,8 @@
 /* Test 'map' clause diagnostics.  */
 
-/* See also corresponding C/C++ variant: '../../c-c++-common/gomp/map-2.c'.  */
+/* See also corresponding OpenMP C/C++ variant: '../../c-c++-common/gomp/map-2.c'.  */
+
+/* See also corresponding OpenACC variant: '../goacc/data-clause-2.C'.  */
 
 template <int N>
 void

commit c6145860aac6acfeed2a98fe7532dd2cd0ffab2b
Author: Jonathan Wakely <jwakely@redhat.com>
Date:   Thu Nov 26 11:25:55 2020 +0000

    libstdc++: Fix undefined FILE* operations in test
    
    We only need to check that the constructor doesn't clear errno, so
    there's no need to use an invalid FILE* for that.
    
    libstdc++-v3/ChangeLog:
    
            PR libstdc++/98001
            * testsuite/ext/stdio_filebuf/char/79820.cc: Do not pass invalid
            FILE* to constructor.
    
    (cherry picked from commit 2762cb1df686fc1ebcee23c7c4f0f6e8bf5a6abc)

diff --git a/libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc b/libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc
index c2af0a63c36..4aee84d9165 100644
--- a/libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc
+++ b/libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc
@@ -26,10 +26,11 @@ void
 test01()
 {
   FILE* f = std::fopen("79820.txt", "w");
-  std::fclose(f);
   errno = 127;
   __gnu_cxx::stdio_filebuf<char> b(f, std::ios::out, BUFSIZ);
   VERIFY(errno == 127); // PR libstdc++/79820
+  b.close();
+  std::fclose(f);
 }
 
 int

commit c2be82c5cbb0e7647f93e2ab8855d44777a811a2
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Nov 27 12:47:25 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2c90f2149a7..5476fe043d6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201126
+20201127
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index dd345346389..997a21c6752 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2020-11-26  Thomas Schwinge  <thomas@codesourcery.com>
+
+	Backported from master:
+	2020-11-26  Thomas Schwinge  <thomas@codesourcery.com>
+
+	* c-c++-common/goacc/cache-3-1.c: New.
+	* c-c++-common/goacc/cache-3-2.c: Likewise.
+	* c-c++-common/goacc/data-clause-1.c: Likewise.
+	* c-c++-common/goacc/data-clause-2.c: Likewise.
+	* c-c++-common/gomp/map-1.c: Adjust.
+	* c-c++-common/gomp/map-2.c: Likewise.
+	* g++.dg/goacc/cache-3-1.C: New.
+	* g++.dg/goacc/cache-3-2.C: Likewise.
+	* g++.dg/goacc/data-clause-1.C: Likewise.
+	* g++.dg/goacc/data-clause-2.C: Likewise.
+	* g++.dg/gomp/map-1.C: Adjust.
+	* g++.dg/gomp/map-2.C: Likewise.
+
 2020-11-25  Thomas Schwinge  <thomas@codesourcery.com>
 
 	Backported from master:
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 2cb3a625d5b..b5d7eda945b 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,12 @@
+2020-11-26  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2020-11-26  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/98001
+	* testsuite/ext/stdio_filebuf/char/79820.cc: Do not pass invalid
+	FILE* to constructor.
+
 2020-11-16  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backported from master:

commit 5cf8eddf938553d9a7dbc3f57115d8d7b1d530ba
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Nov 28 00:17:55 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 5476fe043d6..b79287fabff 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201127
+20201128

commit b68aa8c9eec1e355b4b2b00a33779f5838e8e190
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Nov 29 00:17:39 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b79287fabff..2504b485b3e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201128
+20201129

commit c715a3659873b5f6b449493f54a29c26d06dfd1c
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Nov 30 00:17:44 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2504b485b3e..ab33186e4b4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201129
+20201130

commit 3a936a9ecddef58ad5b6ee11697c3f791b942708
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Mon Nov 30 10:47:54 2020 +0000

    Backport of the patch for PR target/91816
    
    This is a patch for an issue where the compiler was generating a
    conditional branch in Thumb2, which was too far for b{cond} to handle.
    
    This backport also includes the subsequent fixes to the test in this
    patch.
    
    gcc/ChangeLog
    
            PR target/91816
            * config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
            * config/arm/arm.c (arm_gen_far_branch): New function
            arm_gen_far_branch.
            * config/arm/arm.md: Update b<cond> for Thumb2 range checks.
    
    gcc/testsuite/ChangeLog
    
            PR target/91816
            * gcc.target/arm/pr91816.c: New test.

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 9d0acde7a39..87e01e35221 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -553,4 +553,6 @@ void arm_parse_option_features (sbitmap, const cpu_arch_option *,
 
 void arm_initialize_isa (sbitmap, const enum isa_feature *);
 
+const char * arm_gen_far_branch (rtx *, int, const char * , const char *);
+
 #endif /* ! GCC_ARM_PROTOS_H */
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index f990ca11bcb..eefe3d99548 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -31629,6 +31629,39 @@ arm_constant_alignment (const_tree exp, HOST_WIDE_INT align)
   return align;
 }
 
+/* Generate code to enable conditional branches in functions over 1 MiB.
+   Parameters are:
+     operands: is the operands list of the asm insn (see arm_cond_branch or
+       arm_cond_branch_reversed).
+     pos_label: is an index into the operands array where operands[pos_label] is
+       the asm label of the final jump destination.
+     dest: is a string which is used to generate the asm label of the intermediate
+       destination
+   branch_format: is a string denoting the intermediate branch format, e.g.
+     "beq", "bne", etc.  */
+
+const char *
+arm_gen_far_branch (rtx * operands, int pos_label, const char * dest,
+		    const char * branch_format)
+{
+  rtx_code_label * tmp_label = gen_label_rtx ();
+  char label_buf[256];
+  char buffer[128];
+  ASM_GENERATE_INTERNAL_LABEL (label_buf, dest , \
+			CODE_LABEL_NUMBER (tmp_label));
+  const char *label_ptr = arm_strip_name_encoding (label_buf);
+  rtx dest_label = operands[pos_label];
+  operands[pos_label] = tmp_label;
+
+  snprintf (buffer, sizeof (buffer), "%s%s", branch_format , label_ptr);
+  output_asm_insn (buffer, operands);
+
+  snprintf (buffer, sizeof (buffer), "b\t%%l0%d\n%s:", pos_label, label_ptr);
+  operands[pos_label] = dest_label;
+  output_asm_insn (buffer, operands);
+  return "";
+}
+
 #if CHECKING_P
 namespace selftest {
 
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 6d6b37719e0..81c96658d95 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -7187,9 +7187,15 @@
 ;; And for backward branches we have 
 ;;   (neg_range - neg_base_offs + pc_offs) = (neg_range - (-2 or -4) + 4).
 ;;
+;; In 16-bit Thumb these ranges are:
 ;; For a 'b'       pos_range = 2046, neg_range = -2048 giving (-2040->2048).
 ;; For a 'b<cond>' pos_range = 254,  neg_range = -256  giving (-250 ->256).
 
+;; In 32-bit Thumb these ranges are:
+;; For a 'b'       +/- 16MB is not checked for.
+;; For a 'b<cond>' pos_range = 1048574,  neg_range = -1048576  giving
+;; (-1048568 -> 1048576).
+
 (define_expand "cbranchsi4"
   [(set (pc) (if_then_else
 	      (match_operator 0 "expandable_comparison_operator"
@@ -7444,23 +7450,50 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   "TARGET_32BIT"
-  "*
-  if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
+  {
+    if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
     {
       arm_ccfsm_state += 2;
-      return \"\";
+      return "";
     }
-  return \"b%d1\\t%l0\";
-  "
+    switch (get_attr_length (insn))
+      {
+	case 2: /* Thumb2 16-bit b{cond}.  */
+	case 4: /* Thumb2 32-bit b{cond} or A32 b{cond}.  */
+	  return "b%d1\t%l0";
+	  break;
+
+	/* Thumb2 b{cond} out of range.  Use 16-bit b{cond} and
+	   unconditional branch b.  */
+	default: return arm_gen_far_branch (operands, 0, "Lbcond", "b%D1\t");
+      }
+  }
   [(set_attr "conds" "use")
    (set_attr "type" "branch")
    (set (attr "length")
-	(if_then_else
-	   (and (match_test "TARGET_THUMB2")
-		(and (ge (minus (match_dup 0) (pc)) (const_int -250))
-		     (le (minus (match_dup 0) (pc)) (const_int 256))))
-	   (const_int 2)
-	   (const_int 4)))]
+    (if_then_else (match_test "!TARGET_THUMB2")
+
+      ;;Target is not Thumb2, therefore is A32.  Generate b{cond}.
+      (const_int 4)
+
+      ;; Check if target is within 16-bit Thumb2 b{cond} range.
+      (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -250))
+		         (le (minus (match_dup 0) (pc)) (const_int 256)))
+
+	;; Target is Thumb2, within narrow range.
+	;; Generate b{cond}.
+	(const_int 2)
+
+	;; Check if target is within 32-bit Thumb2 b{cond} range.
+	(if_then_else (and (ge (minus (match_dup 0) (pc))(const_int -1048568))
+			   (le (minus (match_dup 0) (pc)) (const_int 1048576)))
+
+	  ;; Target is Thumb2, within wide range.
+	  ;; Generate b{cond}
+	  (const_int 4)
+	  ;; Target is Thumb2, out of range.
+	  ;; Generate narrow b{cond} and unconditional branch b.
+	  (const_int 6)))))]
 )
 
 (define_insn "*arm_cond_branch_reversed"
@@ -7470,23 +7503,50 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   "TARGET_32BIT"
-  "*
-  if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
-    {
-      arm_ccfsm_state += 2;
-      return \"\";
-    }
-  return \"b%D1\\t%l0\";
-  "
-  [(set_attr "conds" "use")
+  {
+    if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
+      {
+	arm_ccfsm_state += 2;
+	return "";
+      }
+    switch (get_attr_length (insn))
+      {
+	case 2: /* Thumb2 16-bit b{cond}.  */
+	case 4: /* Thumb2 32-bit b{cond} or A32 b{cond}.  */
+	  return "b%D1\t%l0";
+	  break;
+
+	/* Thumb2 b{cond} out of range.  Use 16-bit b{cond} and
+	   unconditional branch b.  */
+	default: return arm_gen_far_branch (operands, 0, "Lbcond", "b%d1\t");
+      }
+  }
+[(set_attr "conds" "use")
    (set_attr "type" "branch")
    (set (attr "length")
-	(if_then_else
-	   (and (match_test "TARGET_THUMB2")
-		(and (ge (minus (match_dup 0) (pc)) (const_int -250))
-		     (le (minus (match_dup 0) (pc)) (const_int 256))))
-	   (const_int 2)
-	   (const_int 4)))]
+    (if_then_else (match_test "!TARGET_THUMB2")
+
+      ;;Target is not Thumb2, therefore is A32.  Generate b{cond}.
+      (const_int 4)
+
+      ;; Check if target is within 16-bit Thumb2 b{cond} range.
+      (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -250))
+			 (le (minus (match_dup 0) (pc)) (const_int 256)))
+
+	;; Target is Thumb2, within narrow range.
+	;; Generate b{cond}.
+	(const_int 2)
+
+	;; Check if target is within 32-bit Thumb2 b{cond} range.
+	(if_then_else (and (ge (minus (match_dup 0) (pc))(const_int -1048568))
+			   (le (minus (match_dup 0) (pc)) (const_int 1048576)))
+
+	  ;; Target is Thumb2, within wide range.
+	  ;; Generate b{cond}.
+	  (const_int 4)
+	  ;; Target is Thumb2, out of range.
+	  ;; Generate narrow b{cond} and unconditional branch b.
+	  (const_int 6)))))]
 )
 
 
diff --git a/gcc/testsuite/gcc.target/arm/pr91816.c b/gcc/testsuite/gcc.target/arm/pr91816.c
new file mode 100644
index 00000000000..f1269141690
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr91816.c
@@ -0,0 +1,64 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-additional-options "-mthumb" }  */
+/* { dg-timeout-factor 4.0 } */
+
+int printf(const char *, ...);
+
+#define HW0	printf("Hello World!\n");
+#define HW1	HW0 HW0 HW0 HW0 HW0 HW0 HW0 HW0 HW0 HW0
+#define HW2	HW1 HW1 HW1 HW1 HW1 HW1 HW1 HW1 HW1 HW1
+#define HW3	HW2 HW2 HW2 HW2 HW2 HW2 HW2 HW2 HW2 HW2
+#define HW4	HW3 HW3 HW3 HW3 HW3 HW3 HW3 HW3 HW3 HW3
+#define HW5	HW4 HW4 HW4 HW4 HW4 HW4 HW4 HW4 HW4 HW4
+#define HW6	HW5 HW5
+
+__attribute__((noinline,noclone)) void f1 (int a)
+{
+  if (a) { HW0 }
+}
+
+__attribute__((noinline,noclone)) void f2 (int a)
+{
+  if (a) { HW3 }
+}
+
+
+__attribute__((noinline,noclone)) void f3 (int a)
+{
+  if (a) { HW6 }
+}
+
+__attribute__((noinline,noclone)) void f4 (int a)
+{
+  if (a == 1) { HW0 }
+}
+
+__attribute__((noinline,noclone)) void f5 (int a)
+{
+  if (a == 1) { HW3 }
+}
+
+
+__attribute__((noinline,noclone)) void f6 (int a)
+{
+  if (a == 1) { HW6 }
+}
+
+
+int main(void)
+{
+	f1(0);
+	f2(0);
+	f3(0);
+	f4(0);
+	f5(0);
+	f6(0);
+	return 0;
+}
+
+
+/* { dg-final { scan-assembler-times "beq\\t.L\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "beq\\t.Lbcond\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "bne\\t.L\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "bne\\t.Lbcond\[0-9\]" 1 } } */

commit 1631094a3eb4d1b1eb8b04db6f3b9ba6a5b645eb
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Dec 1 00:17:55 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8e10b0d4d80..1e505c6aff5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-11-30  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/91816
+	* config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
+	* config/arm/arm.c (arm_gen_far_branch): New function
+	arm_gen_far_branch.
+	* config/arm/arm.md: Update b<cond> for Thumb2 range checks.
+
 2020-11-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 
 	Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ab33186e4b4..91326ab1d8f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201130
+20201201
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 997a21c6752..a9622cc559f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-11-30  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/91816
+	* gcc.target/arm/pr91816.c: New test.
+
 2020-11-26  Thomas Schwinge  <thomas@codesourcery.com>
 
 	Backported from master:

commit 46384dc73076d945c9222b3f0850a9aa3e694eda
Author: Richard Biener <rguenther@suse.de>
Date:   Mon Oct 26 10:10:46 2020 +0100

    middle-end/97554 - avoid overflow in alloc size compute
    
    This avoids overflow in the allocation size computations in
    sbitmap_vector_alloc when the result exceeds 2GB.
    
    2020-10-26  Richard Biener  <rguenther@suse.de>
    
            PR middle-end/97554
            * sbitmap.c (sbitmap_vector_alloc): Use size_t for byte
            quantities to avoid overflow.
    
    (cherry picked from commit 50f9e1f4d458e36d306b2449c689e45492847f68)

diff --git a/gcc/sbitmap.c b/gcc/sbitmap.c
index 967868ad118..6dacdd0ef6b 100644
--- a/gcc/sbitmap.c
+++ b/gcc/sbitmap.c
@@ -139,7 +139,8 @@ sbitmap_realloc (sbitmap src, unsigned int n_elms)
 sbitmap *
 sbitmap_vector_alloc (unsigned int n_vecs, unsigned int n_elms)
 {
-  unsigned int i, bytes, offset, elm_bytes, size, amt, vector_bytes;
+  unsigned int i, size;
+  size_t amt, bytes, vector_bytes, elm_bytes, offset;
   sbitmap *bitmap_vector;
 
   size = SBITMAP_SET_SIZE (n_elms);

commit 427fe143a43ba13497759e1482ce683deed9a00b
Author: Richard Biener <rguenther@suse.de>
Date:   Thu Nov 26 10:07:06 2020 +0100

    testsuite/98002 - fix gcc.dg/strncmp-2.c
    
    This makes sure not to free() memory we have mprotected to PROT_NONE
    by calling mprotect again with PROT_READ|PROT_WRITE.  This avoids
    crashing the allocator when in debug mode.
    
    2020-11-16  Richard Biener  <rguenther@suse.de>
    
            PR testsuite/98002
            * gcc.dg/strncmp-2.c: Call mprotect again before free.
    
    (cherry picked from commit 5b3a8fad18324cd38c221bdb0ae2b690fc82ede0)

diff --git a/gcc/testsuite/gcc.dg/strncmp-2.c b/gcc/testsuite/gcc.dg/strncmp-2.c
index f5555ba4081..40a4f501448 100644
--- a/gcc/testsuite/gcc.dg/strncmp-2.c
+++ b/gcc/testsuite/gcc.dg/strncmp-2.c
@@ -40,6 +40,7 @@ static void test_driver_strncmp (void (test_strncmp)(const char *, const char *,
     e = lib_memcmp(buf1,p2,sz);
     (*test_memcmp)(buf1,p2,e);
   }
+  mprotect (buf2+pgsz,pgsz,PROT_READ|PROT_WRITE);
   free(buf2);
 }
 

commit 3d0da0bc398054f2c37f09b13ccf7e2e2ef63b22
Author: Richard Biener <rguenther@suse.de>
Date:   Fri May 15 09:38:54 2020 +0200

    tree-optimization/95133 - avoid abnormal edges in path splitting
    
    When path splitting tries to detect a CFG diamond make sure it
    is composed of normal (non-EH, not abnormal) edges.  Otherwise
    CFG manipulation later may fail.
    
    2020-05-15  Richard Biener  <rguenther@suse.de>
    
            PR tree-optimization/95133
            * gimple-ssa-split-paths.c
            (find_block_to_duplicate_for_splitting_paths): Check for
            normal edges.
    
            * gcc.dg/pr95133.c: New testcase.
    
    (cherry picked from commit aaf1ee48316f9b414b11c17e298198925d816595)

diff --git a/gcc/gimple-ssa-split-paths.c b/gcc/gimple-ssa-split-paths.c
index a8515119ce5..caf8f94808b 100644
--- a/gcc/gimple-ssa-split-paths.c
+++ b/gcc/gimple-ssa-split-paths.c
@@ -68,8 +68,14 @@ find_block_to_duplicate_for_splitting_paths (basic_block latch)
 	 region.  Verify that it is.
 
 	 First, verify that BB has two predecessors (each arm of the
-	 IF-THEN-ELSE) and two successors (the latch and exit).  */
-      if (EDGE_COUNT (bb->preds) == 2 && EDGE_COUNT (bb->succs) == 2)
+	 IF-THEN-ELSE) and two successors (the latch and exit) and that
+	 all edges are normal.  */
+      if (EDGE_COUNT (bb->preds) == 2
+	  && !(EDGE_PRED (bb, 0)->flags & EDGE_COMPLEX)
+	  && !(EDGE_PRED (bb, 1)->flags & EDGE_COMPLEX)
+	  && EDGE_COUNT (bb->succs) == 2
+	  && !(EDGE_SUCC (bb, 0)->flags & EDGE_COMPLEX)
+	  && !(EDGE_SUCC (bb, 1)->flags & EDGE_COMPLEX))
 	{
 	  /* Now verify that BB's immediate dominator ends in a
 	     conditional as well.  */
diff --git a/gcc/testsuite/gcc.dg/pr95133.c b/gcc/testsuite/gcc.dg/pr95133.c
new file mode 100644
index 00000000000..523decaf90e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr95133.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+extern int a[16];
+void f (int *ip, int x)
+{
+  int *xp = a;
+  for (int i=0; i<8; ++i)
+  {
+    base: if (x) return;
+  }
+  *xp++ = *ip;
+  goto *(&&base + *ip);
+}

commit 70ac96884811b6971b44a7ffa94d637f612e6cc4
Author: Richard Biener <rguenther@suse.de>
Date:   Wed May 6 10:23:15 2020 +0200

    middle-end/94964 - avoid EH loop entry with CP_SIMPLE_PREHEADERS
    
    Loop optimizers expect to be able to insert on the preheader
    edge w/o splitting it thus avoid ending up with a preheader
    that enters the loop via an EH edge (or an abnormal edge).
    
    2020-05-06  Richard Biener  <rguenther@suse.de>
    
            PR middle-end/94964
            * cfgloopmanip.c (create_preheader): Require non-complex
            preheader edge for CP_SIMPLE_PREHEADERS.
    
    (cherry picked from commit 6fc00b41e764219e2c88d8892d7c701c0d292a17)

diff --git a/gcc/cfgloopmanip.c b/gcc/cfgloopmanip.c
index 4b300f20428..6be59c348ec 100644
--- a/gcc/cfgloopmanip.c
+++ b/gcc/cfgloopmanip.c
@@ -1500,9 +1500,10 @@ create_preheader (struct loop *loop, int flags)
       else
         {
           /* If we want simple preheaders, also force the preheader to have
-             just a single successor.  */
+	     just a single successor and a normal edge.  */
           if ((flags & CP_SIMPLE_PREHEADERS)
-              && !single_succ_p (single_entry->src))
+	      && ((single_entry->flags & EDGE_COMPLEX)
+		  || !single_succ_p (single_entry->src)))
             need_forwarder_block = true;
           /* If we want fallthru preheaders, also create forwarder block when
              preheader ends with a jump or has predecessors from loop.  */

commit 1cd95acac5a521937b205ace0db3f1a042561dd8
Author: Richard Biener <rguenther@suse.de>
Date:   Tue May 5 13:09:50 2020 +0200

    ipa/94947 - fix test for externally visible variables for IPA PTA
    
    This fixes lack of an escape point of externally declared variables.
    
    2020-05-05  Richard Biener  <rguenther@suse.de>
    
            PR ipa/94947
            * tree-ssa-structalias.c (ipa_pta_execute): Use
            varpool_node::externally_visible_p ().
            (refered_from_nonlocal_var): Likewise.
    
            * gcc.dg/torture/pr94947-1.c: New testcase.
            * gcc.dg/torture/pr94947-2.c: Likewise.
    
    (cherry picked from commit f9b5db750bc7fbba69fee93564907f7da1bca35f)

diff --git a/gcc/testsuite/gcc.dg/torture/pr94947-1.c b/gcc/testsuite/gcc.dg/torture/pr94947-1.c
new file mode 100644
index 00000000000..ab8b488c6fc
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr94947-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-additional-sources "pr94947-2.c" } */
+/* { dg-additional-options "-fipa-pta -flto-partition=1to1" } */
+
+extern void abort ();
+extern void baz ();
+extern void (*baz_call)();
+static int *p;
+
+static void foo ()
+{
+  if (*p != 1)
+    abort ();
+}
+
+int main()
+{
+  int x = 1;
+  p = &x;
+  baz_call = foo;
+  baz ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/torture/pr94947-2.c b/gcc/testsuite/gcc.dg/torture/pr94947-2.c
new file mode 100644
index 00000000000..670dd61c1e9
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr94947-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+
+void (*baz_call)();
+void baz ()
+{
+  baz_call ();
+}
diff --git a/gcc/tree-ssa-structalias.c b/gcc/tree-ssa-structalias.c
index b02f57cc949..9bb6fbb00cf 100644
--- a/gcc/tree-ssa-structalias.c
+++ b/gcc/tree-ssa-structalias.c
@@ -7905,7 +7905,7 @@ refered_from_nonlocal_var (struct varpool_node *node, void *data)
 {
   bool *nonlocal_p = (bool *)data;
   *nonlocal_p |= (node->used_from_other_partition
-		  || node->externally_visible
+		  || node->externally_visible_p ()
 		  || node->force_output);
   return false;
 }
@@ -7994,8 +7994,8 @@ ipa_pta_execute (void)
 
       /* For the purpose of IPA PTA unit-local globals are not
          escape points.  */
-      bool nonlocal_p = (var->used_from_other_partition
-			 || var->externally_visible
+      bool nonlocal_p = (var->externally_visible_p ()
+			 || var->used_from_other_partition
 			 || var->force_output);
       var->call_for_symbol_and_aliases (refered_from_nonlocal_var,
 					&nonlocal_p, true);

commit 3114be1ceb750f323a13dad0a419a7622bd71fbe
Author: Richard Biener <rguenther@suse.de>
Date:   Thu May 7 14:06:02 2020 +0200

    ipa/94947 - avoid using externally_visible_p ()
    
    externally_visible_p wasn't the correct predicate to use (even if it
    worked), instead we should use DECL_EXTERNAL || TREE_PUBLIC.
    
    2020-05-07  Richard Biener  <rguenther@suse.de>
    
            PR ipa/94947
            * tree-ssa-structalias.c (refered_from_nonlocal_fn): Use
            DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible.
            (refered_from_nonlocal_var): Likewise.
            (ipa_pta_execute): Likewise.
    
    (cherry picked from commit b9250b3cb91b667cd67943e0fac94bf39ac089a8)

diff --git a/gcc/tree-ssa-structalias.c b/gcc/tree-ssa-structalias.c
index 9bb6fbb00cf..91f20ee4b1f 100644
--- a/gcc/tree-ssa-structalias.c
+++ b/gcc/tree-ssa-structalias.c
@@ -7893,7 +7893,8 @@ refered_from_nonlocal_fn (struct cgraph_node *node, void *data)
 {
   bool *nonlocal_p = (bool *)data;
   *nonlocal_p |= (node->used_from_other_partition
-		  || node->externally_visible
+		  || DECL_EXTERNAL (node->decl)
+		  || TREE_PUBLIC (node->decl)
 		  || node->force_output
 		  || lookup_attribute ("noipa", DECL_ATTRIBUTES (node->decl)));
   return false;
@@ -7905,7 +7906,8 @@ refered_from_nonlocal_var (struct varpool_node *node, void *data)
 {
   bool *nonlocal_p = (bool *)data;
   *nonlocal_p |= (node->used_from_other_partition
-		  || node->externally_visible_p ()
+		  || DECL_EXTERNAL (node->decl)
+		  || TREE_PUBLIC (node->decl)
 		  || node->force_output);
   return false;
 }
@@ -7954,7 +7956,8 @@ ipa_pta_execute (void)
 	 For local functions we see all callers and thus do not need initial
 	 constraints for parameters.  */
       bool nonlocal_p = (node->used_from_other_partition
-			 || node->externally_visible
+			 || DECL_EXTERNAL (node->decl)
+			 || TREE_PUBLIC (node->decl)
 			 || node->force_output
 			 || lookup_attribute ("noipa",
 					      DECL_ATTRIBUTES (node->decl)));
@@ -7994,7 +7997,8 @@ ipa_pta_execute (void)
 
       /* For the purpose of IPA PTA unit-local globals are not
          escape points.  */
-      bool nonlocal_p = (var->externally_visible_p ()
+      bool nonlocal_p = (DECL_EXTERNAL (var->decl)
+			 || TREE_PUBLIC (var->decl)
 			 || var->used_from_other_partition
 			 || var->force_output);
       var->call_for_symbol_and_aliases (refered_from_nonlocal_var,

commit e03bdd99101a6191679969535de02aa18f9a5b11
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Dec 2 00:18:00 2020 +0000

    Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1e505c6aff5..d29cbab0c2d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,52 @@
+2020-12-01  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2020-05-07  Richard Biener  <rguenther@suse.de>
+
+	PR ipa/94947
+	* tree-ssa-structalias.c (refered_from_nonlocal_fn): Use
+	DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible.
+	(refered_from_nonlocal_var): Likewise.
+	(ipa_pta_execute): Likewise.
+
+2020-12-01  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2020-05-05  Richard Biener  <rguenther@suse.de>
+
+	PR ipa/94947
+	* tree-ssa-structalias.c (ipa_pta_execute): Use
+	varpool_node::externally_visible_p ().
+	(refered_from_nonlocal_var): Likewise.
+
+2020-12-01  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2020-05-06  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/94964
+	* cfgloopmanip.c (create_preheader): Require non-complex
+	preheader edge for CP_SIMPLE_PREHEADERS.
+
+2020-12-01  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2020-05-15  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/95133
+	* gimple-ssa-split-paths.c
+	(find_block_to_duplicate_for_splitting_paths): Check for
+	normal edges.
+
+2020-12-01  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2020-10-26  Richard Biener  <rguenther@suse.de>
+
+	PR middle-end/97554
+	* sbitmap.c (sbitmap_vector_alloc): Use size_t for byte
+	quantities to avoid overflow.
+
 2020-11-30  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 
 	PR target/91816
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 91326ab1d8f..ddafb1c0f90 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201201
+20201202
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a9622cc559f..f7eca03744d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,28 @@
+2020-12-01  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2020-05-05  Richard Biener  <rguenther@suse.de>
+
+	PR ipa/94947
+	* gcc.dg/torture/pr94947-1.c: New testcase.
+	* gcc.dg/torture/pr94947-2.c: Likewise.
+
+2020-12-01  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2020-05-15  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/95133
+	* gcc.dg/pr95133.c: New testcase.
+
+2020-12-01  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2020-11-26  Richard Biener  <rguenther@suse.de>
+
+	PR testsuite/98002
+	* gcc.dg/strncmp-2.c: Call mprotect again before free.
+
 2020-11-30  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 
 	PR target/91816

commit 3d20f125b49d6f55eb889902c2b37de3b174caee
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Dec 3 00:18:09 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ddafb1c0f90..81e21c81a48 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201202
+20201203

commit a61486017fa128439d07893afa837b00ff42b5e1
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Fri Dec 4 00:17:53 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 81e21c81a48..3fac2aa9f61 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201203
+20201204

commit e0d562a3b4fcbd8e7a525a3cef2afd7b4988f7ff
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Dec 5 00:17:56 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3fac2aa9f61..e4face1d0a8 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201204
+20201205

commit 25d661a55a6aa18f448756272f5af2f5a5ff40c4
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sun Dec 6 00:18:04 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e4face1d0a8..4cbdc7e3660 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201205
+20201206

commit 77019f860e1d9eee9c8b68c4f2690df831c0d7f3
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Dec 7 00:17:39 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4cbdc7e3660..a4de7b0fbad 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201206
+20201207

commit 833c99a8b09f07d5499861daba92e20783744724
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Dec 8 00:18:07 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a4de7b0fbad..0793ecd0c80 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201207
+20201208

commit fab88d42ed2f2c8f013689aae7b55d08da538837
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Dec 9 00:18:10 2020 +0000

    Daily bump.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0793ecd0c80..c8f34b85e95 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201208
+20201209
